c3dhall4.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef C3DHALL4_H
#define C3DHALL4_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
#include "drv_analog_in.h"
 
#define C3DHALL4_REG_0                      0x00
#define C3DHALL4_REG_1                      0x01
#define C3DHALL4_REG_2                      0x02
#define C3DHALL4_REG_3                      0x03
#define C3DHALL4_REG_4                      0x04
#define C3DHALL4_REG_5                      0x05
#define C3DHALL4_REG_6                      0x06
#define C3DHALL4_REG_7                      0x07
#define C3DHALL4_REG_PWM_CTRL               0x08
#define C3DHALL4_REG_CHANNEL_CTRL           0x09
#define C3DHALL4_REG_OSC_TRIM               0x0A
#define C3DHALL4_REG_THRES_X                0x0B
#define C3DHALL4_REG_THRES_Z                0x0C
#define C3DHALL4_REG_THRES_Y                0x0D
#define C3DHALL4_REG_G_CTRL_X               0x0E
#define C3DHALL4_REG_G_CTRL_Z               0x0F
#define C3DHALL4_REG_G_CTRL_Y               0x10
#define C3DHALL4_REG_DAC_X                  0x11
#define C3DHALL4_REG_DAC_Z                  0x12
#define C3DHALL4_REG_DAC_Y                  0x13
#define C3DHALL4_REG_SENS_X                 0x14
#define C3DHALL4_REG_SENS_Z                 0x15
#define C3DHALL4_REG_SENS_Y                 0x16
#define C3DHALL4_REG_SENS_TC_X              0x17
#define C3DHALL4_REG_SENS_TC_Z              0x18
#define C3DHALL4_REG_SENS_TC_Y              0x19
#define C3DHALL4_REG_OFFSET_X               0x1A
#define C3DHALL4_REG_OFFSET_Z               0x1B
#define C3DHALL4_REG_OFFSET_Y               0x1C
#define C3DHALL4_REG_OFFSET_TC_X            0x1D
#define C3DHALL4_REG_OFFSET_TC_Z            0x1E
#define C3DHALL4_REG_OFFSET_TC_Y            0x1F
#define C3DHALL4_REG_STATUS                 0x3F
#define C3DHALL4_REG_ADC_DATAXL             0x40
#define C3DHALL4_REG_ADC_DATAXH             0x41
#define C3DHALL4_REG_ADC_DATAZL             0x42
#define C3DHALL4_REG_ADC_DATAZH             0x43
#define C3DHALL4_REG_ADC_DATAYL             0x44
#define C3DHALL4_REG_ADC_DATAYH             0x45
#define C3DHALL4_REG_ADC_DATATL             0x46
#define C3DHALL4_REG_ADC_DATATH             0x47
 
#define C3DHALL4_EREG_0                     0x00
#define C3DHALL4_EREG_1                     0x01
#define C3DHALL4_EREG_2                     0x02
#define C3DHALL4_EREG_3                     0x03
#define C3DHALL4_EREG_4                     0x04
#define C3DHALL4_EREG_5                     0x05
#define C3DHALL4_EREG_6                     0x06
#define C3DHALL4_EREG_7                     0x07
#define C3DHALL4_EREG_PWM_CTRL              0x08
#define C3DHALL4_EREG_CHANNEL_CTRL          0x09
#define C3DHALL4_EREG_OSC_TRIM              0x0A
#define C3DHALL4_EREG_THRES_Y               0x0B
#define C3DHALL4_EREG_THRES_X               0x0C
#define C3DHALL4_EREG_THRES_Z               0x0D
#define C3DHALL4_EREG_GAIN_SEL              0x0E
#define C3DHALL4_EREG_DAC_Y_G0              0x40
#define C3DHALL4_EREG_DAC_X_G0              0x41
#define C3DHALL4_EREG_DAC_Z_G0              0x42
#define C3DHALL4_EREG_SENS_Y_G0             0x43
#define C3DHALL4_EREG_SENS_X_G0             0x44
#define C3DHALL4_EREG_SENS_Z_G0             0x45
#define C3DHALL4_EREG_SENS_TC_Y_G0          0x46
#define C3DHALL4_EREG_SENS_TC_X_G0          0x47
#define C3DHALL4_EREG_SENS_TC_Z_G0          0x48
#define C3DHALL4_EREG_OFFSET_Y_G0           0x49
#define C3DHALL4_EREG_OFFSET_X_G0           0x4A
#define C3DHALL4_EREG_OFFSET_Z_G0           0x4B
#define C3DHALL4_EREG_OFFSET_TC_Y_G0        0x4C
#define C3DHALL4_EREG_OFFSET_TC_X_G0        0x4D
#define C3DHALL4_EREG_OFFSET_TC_Z_G0        0x4E
#define C3DHALL4_EREG_DAC_Y_G1              0x50
#define C3DHALL4_EREG_DAC_X_G1              0x51
#define C3DHALL4_EREG_DAC_Z_G1              0x52
#define C3DHALL4_EREG_SENS_Y_G1             0x53
#define C3DHALL4_EREG_SENS_X_G1             0x54
#define C3DHALL4_EREG_SENS_Z_G1             0x55
#define C3DHALL4_EREG_SENS_TC_Y_G1          0x56
#define C3DHALL4_EREG_SENS_TC_X_G1          0x57
#define C3DHALL4_EREG_SENS_TC_Z_G1          0x58
#define C3DHALL4_EREG_OFFSET_Y_G1           0x59
#define C3DHALL4_EREG_OFFSET_X_G1           0x5A
#define C3DHALL4_EREG_OFFSET_Z_G1           0x5B
#define C3DHALL4_EREG_OFFSET_TC_Y_G1        0x5C
#define C3DHALL4_EREG_OFFSET_TC_X_G1        0x5D
#define C3DHALL4_EREG_OFFSET_TC_Z_G1        0x5E
#define C3DHALL4_EREG_DAC_Y_G2              0x60
#define C3DHALL4_EREG_DAC_X_G2              0x61
#define C3DHALL4_EREG_DAC_Z_G2              0x62
#define C3DHALL4_EREG_SENS_Y_G2             0x63
#define C3DHALL4_EREG_SENS_X_G2             0x64
#define C3DHALL4_EREG_SENS_Z_G2             0x65
#define C3DHALL4_EREG_SENS_TC_Y_G2          0x66
#define C3DHALL4_EREG_SENS_TC_X_G2          0x67
#define C3DHALL4_EREG_SENS_TC_Z_G2          0x68
#define C3DHALL4_EREG_OFFSET_Y_G2           0x69
#define C3DHALL4_EREG_OFFSET_X_G2           0x6A
#define C3DHALL4_EREG_OFFSET_Z_G2           0x6B
#define C3DHALL4_EREG_OFFSET_TC_Y_G2        0x6C
#define C3DHALL4_EREG_OFFSET_TC_X_G2        0x6D
#define C3DHALL4_EREG_OFFSET_TC_Z_G2        0x6E
#define C3DHALL4_EREG_DAC_Y_G3              0x70
#define C3DHALL4_EREG_DAC_X_G3              0x71
#define C3DHALL4_EREG_DAC_Z_G3              0x72
#define C3DHALL4_EREG_SENS_Y_G3             0x73
#define C3DHALL4_EREG_SENS_X_G3             0x74
#define C3DHALL4_EREG_SENS_Z_G3             0x75
#define C3DHALL4_EREG_SENS_TC_Y_G3          0x76
#define C3DHALL4_EREG_SENS_TC_X_G3          0x77
#define C3DHALL4_EREG_SENS_TC_Z_G3          0x78
#define C3DHALL4_EREG_OFFSET_Y_G3           0x79
#define C3DHALL4_EREG_OFFSET_X_G3           0x7A
#define C3DHALL4_EREG_OFFSET_Z_G3           0x7B
#define C3DHALL4_EREG_OFFSET_TC_Y_G3        0x7C
#define C3DHALL4_EREG_OFFSET_TC_X_G3        0x7D
#define C3DHALL4_EREG_OFFSET_TC_Z_G3        0x7E
#define C3DHALL4_EREG_KEY                   0xFE
#define C3DHALL4_EREG_CHECKSUM              0xFF
 
 // c3dhall4_reg
 
#define C3DHALL4_CMD_REG_WRITE              0x00
#define C3DHALL4_CMD_REG_READ               0x80
#define C3DHALL4_CMD_EREG_WRITE             0x01
#define C3DHALL4_CMD_EREG_READ              0x81
#define C3DHALL4_CMD_SPECIAL_KEY            0xA5
 
#define C3DHALL4_ADC_VREF_3V3               3.3f
#define C3DHALL4_ADC_VREF_5V                5.0f
 
#define C3DHALL4_RANGE_20                   0x00
#define C3DHALL4_RANGE_40                   0x01
#define C3DHALL4_RANGE_350                  0x02
#define C3DHALL4_RANGE_3000                 0x03
#define C3DHALL4_RANGE_MASK                 0x03
#define C3DHALL4_SENS_RANGE_3000            6.0f
#define C3DHALL4_SENS_RANGE_350             60.0f
#define C3DHALL4_SENS_RANGE_40              550.0f
#define C3DHALL4_SENS_RANGE_20              1000.0f
#define C3DHALL4_SENS_TEMPERATURE           168.0f
#define C3DHALL4_OFFSET_XYZ                 32768
#define C3DHALL4_OFFSET_TEMPERATURE         19913
 
#define C3DHALL4_SET_DATA_SAMPLE_EDGE       SET_SPI_DATA_SAMPLE_EDGE
#define C3DHALL4_SET_DATA_SAMPLE_MIDDLE     SET_SPI_DATA_SAMPLE_MIDDLE
 
 // c3dhall4_set
 
#define C3DHALL4_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.tan  = MIKROBUS( mikrobus, MIKROBUS_AN );
 
 // c3dhall4_map
 // c3dhall4
 
typedef struct
{
    spi_master_t spi;           
    analog_in_t  adc;           
    pin_name_t   chip_select;   
    float        x_sens;        
    float        y_sens;        
    float        z_sens;        
} c3dhall4_t;
 
typedef struct
{
    pin_name_t miso;            
    pin_name_t mosi;            
    pin_name_t sck;             
    pin_name_t cs;              
    pin_name_t tan;             
    uint32_t                          spi_speed;    
    spi_master_mode_t                 spi_mode;     
    spi_master_chip_select_polarity_t cs_polarity;  
    analog_in_resolution_t resolution;  
    float                  vref;        
} c3dhall4_cfg_t;
 
typedef struct
{
    uint8_t status;             
    float x_data;               
    float y_data;               
    float z_data;               
    float chip_temp;            
} c3dhall4_data_t;
 
typedef enum
{
    C3DHALL4_OK = 0,
    C3DHALL4_ERROR = -1
 
} c3dhall4_return_value_t;
 
void c3dhall4_cfg_setup ( c3dhall4_cfg_t *cfg );
 
err_t c3dhall4_init ( c3dhall4_t *ctx, c3dhall4_cfg_t *cfg );
 
err_t c3dhall4_default_cfg ( c3dhall4_t *ctx );
 
err_t c3dhall4_reg_write ( c3dhall4_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t c3dhall4_reg_read ( c3dhall4_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t c3dhall4_eeprom_write ( c3dhall4_t *ctx, uint8_t address, uint8_t data_in );
 
err_t c3dhall4_eeprom_read ( c3dhall4_t *ctx, uint8_t address, uint8_t *data_out );
 
err_t c3dhall4_eeprom_update_cksum ( c3dhall4_t *ctx );
 
err_t c3dhall4_read_an_pin_value ( c3dhall4_t *ctx, uint16_t *data_out );
 
err_t c3dhall4_read_an_pin_voltage ( c3dhall4_t *ctx, float *data_out );
 
err_t c3dhall4_read_data ( c3dhall4_t *ctx, c3dhall4_data_t *data_out );
 
#ifdef __cplusplus
}
#endif
#endif // C3DHALL4_H
 
 // c3dhall4
 
// ------------------------------------------------------------------------ END