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c6dofimu12 2.0.0.0
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| #define C6DOFIMU12_REG_ACC_CONF_ADDR 0x40 |
| #define C6DOFIMU12_REG_ACC_OFF_COMP_0_ADDR 0X71 |
| #define C6DOFIMU12_REG_ACC_SELF_TEST_ADDR 0X6D |
| #define C6DOFIMU12_REG_ACC_X_LSB_ADDR 0x0C |
| #define C6DOFIMU12_REG_AUX_CONF_ADDR 0x44 |
| #define C6DOFIMU12_REG_AUX_DEV_ID_ADDR 0x4B |
| #define C6DOFIMU12_REG_AUX_IF_CONF_ADDR 0x4C |
| #define C6DOFIMU12_REG_AUX_RD_ADDR 0x4D |
| #define C6DOFIMU12_REG_AUX_WR_ADDR 0x4E |
| #define C6DOFIMU12_REG_AUX_WR_DATA_ADDR 0x4F |
| #define C6DOFIMU12_REG_AUX_X_LSB_ADDR 0x04 |
| #define C6DOFIMU12_REG_CHIP_ID_ADDR 0x00 |
| #define C6DOFIMU12_REG_CMD_REG_ADDR 0x7E |
| #define C6DOFIMU12_REG_ERROR 0x02 |
| #define C6DOFIMU12_REG_EVENT_ADDR 0x1B |
| #define C6DOFIMU12_REG_FEAT_PAGE_ADDR 0x2F |
| #define C6DOFIMU12_REG_FEATURES_REG_ADDR 0x30 |
| #define C6DOFIMU12_REG_FIFO_CONFIG_0_ADDR 0X48 |
| #define C6DOFIMU12_REG_FIFO_CONFIG_1_ADDR 0X49 |
| #define C6DOFIMU12_REG_FIFO_DATA_ADDR 0X26 |
| #define C6DOFIMU12_REG_FIFO_DOWNS_ADDR 0X45 |
| #define C6DOFIMU12_REG_FIFO_LENGTH_0_ADDR 0X24 |
| #define C6DOFIMU12_REG_FIFO_WTM_0_ADDR 0X46 |
| #define C6DOFIMU12_REG_FIFO_WTM_1_ADDR 0X47 |
| #define C6DOFIMU12_REG_GYR_CAS_GPIO0_ADDR 0x1E |
| #define C6DOFIMU12_REG_GYR_CONF_ADDR 0x42 |
| #define C6DOFIMU12_REG_GYR_CRT_CONF_ADDR 0X69 |
| #define C6DOFIMU12_REG_GYR_OFF_COMP_3_ADDR 0X74 |
| #define C6DOFIMU12_REG_GYR_OFF_COMP_6_ADDR 0X77 |
| #define C6DOFIMU12_REG_GYR_SELF_TEST_AXES_ADDR 0x6E |
| #define C6DOFIMU12_REG_GYR_USR_GAIN_0_ADDR 0X78 |
| #define C6DOFIMU12_REG_GYR_X_LSB_ADDR 0x12 |
| #define C6DOFIMU12_REG_IF_CONF_ADDR 0X6B |
| #define C6DOFIMU12_REG_INIT_ADDR_0 0x5B |
| #define C6DOFIMU12_REG_INIT_ADDR_1 0x5C |
| #define C6DOFIMU12_REG_INIT_CTRL_ADDR 0x59 |
| #define C6DOFIMU12_REG_INIT_DATA_ADDR 0x5E |
| #define C6DOFIMU12_REG_INT1_IO_CTRL_ADDR 0x53 |
| #define C6DOFIMU12_REG_INT1_MAP_FEAT_ADDR 0x56 |
| #define C6DOFIMU12_REG_INT2_IO_CTRL_ADDR 0x54 |
| #define C6DOFIMU12_REG_INT2_MAP_FEAT_ADDR 0x57 |
| #define C6DOFIMU12_REG_INT_MAP_DATA_ADDR 0x58 |
| #define C6DOFIMU12_REG_INT_STATUS_0_ADDR 0x1C |
| #define C6DOFIMU12_REG_INT_STATUS_1_ADDR 0x1D |
| #define C6DOFIMU12_REG_INTERNAL_STATUS_ADDR 0x21 |
| #define C6DOFIMU12_REG_NV_CONF_ADDR 0x70 |
| #define C6DOFIMU12_REG_NVM_CONF_ADDR 0x6A |
| #define C6DOFIMU12_REG_PWR_CONF_ADDR 0x7C |
| #define C6DOFIMU12_REG_PWR_CTRL_ADDR 0x7D |
| #define C6DOFIMU12_REG_SC_OUT_0_ADDR 0x1E |
| #define C6DOFIMU12_REG_SELF_TEST_MEMS_ADDR 0X6F |
| #define C6DOFIMU12_REG_STATUS_ADDR 0x03 |
| #define C6DOFIMU12_REG_SYNC_COMMAND_ADDR 0x1E |