i2cmux5.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef I2CMUX5_H
#define I2CMUX5_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_i2c_master.h"
 
#define I2CMUX5_REGISTER_0                           0x00
#define I2CMUX5_REGISTER_1                           0x01
#define I2CMUX5_REGISTER_2                           0x02
#define I2CMUX5_REGISTER_3                           0x03
 
 // i2cmux5_reg
 
#define I2CMUX5_SET_REG_0_US_BUS_DISCONNECTED        0x00
#define I2CMUX5_SET_REG_0_US_BUS_CONNECTED           0x80
#define I2CMUX5_SET_REG_0_ALERT1_STATE_LOW           0x00
#define I2CMUX5_SET_REG_0_ALERT1_STATE_HIGH          0x40
#define I2CMUX5_SET_REG_0_ALERT2_STATE_LOW           0x00
#define I2CMUX5_SET_REG_0_ALERT2_STATE_HIGH          0x20
#define I2CMUX5_SET_REG_0_ALERT3_STATE_LOW           0x00
#define I2CMUX5_SET_REG_0_ALERT3_STATE_HIGH          0x10
#define I2CMUX5_SET_REG_0_ALERT4_STATE_LOW           0x00
#define I2CMUX5_SET_REG_0_ALERT5_STATE_HIGH          0x08
#define I2CMUX5_SET_REG_0_ATTEMPT_CONN_FAILED        0x00
#define I2CMUX5_SET_REG_0_ATTEMPT_CONN_OK            0x04
#define I2CMUX5_SET_REG_0_NO_LATCHED_TIMEOUT         0x00
#define I2CMUX5_SET_REG_0_LATCHED_TIMEOUT            0x02
#define I2CMUX5_SET_REG_0_NO_TIMEOUT_OCCURRING       0x00
#define I2CMUX5_SET_REG_0_TIMEOUT_OCCURRING          0x01
 
 
#define I2CMUX5_SET_REG_1_URTAC_INACTIVE             0x00
#define I2CMUX5_SET_REG_1_URTAC_ACTIVE               0x80
#define I2CMUX5_SET_REG_1_DRTAC_INACTIVE             0x00
#define I2CMUX5_SET_REG_1_DRTAC_ACTIVE               0x40
#define I2CMUX5_SET_REG_1_GPIO_1_LOW                 0x00
#define I2CMUX5_SET_REG_1_GPIO_1_HIGH                0x20
#define I2CMUX5_SET_REG_1_GPIO_2_LOW                 0x00
#define I2CMUX5_SET_REG_1_GPIO_2_HIGH                0x10
 
#define I2CMUX5_SET_REG_2_CFG_GPIO_1_OUTPUT          0x00
#define I2CMUX5_SET_REG_2_CFG_GPIO_1_INPUT           0x80
#define I2CMUX5_SET_REG_2_CFG_GPIO_2_OUTPUT          0x00
#define I2CMUX5_SET_REG_2_CFG_GPIO_2_INPUT           0x40
#define I2CMUX5_SET_REG_2_BUS_LOGIC_STATE_BITS       0x00
#define I2CMUX5_SET_REG_2_CONN_RGL_LOGIC_STATE       0x20
#define I2CMUX5_SET_REG_2_CFG_GPIO_1_OD_PULL_DOWN    0x00
#define I2CMUX5_SET_REG_2_CFG_GPIO_1_PUSH_PULL       0x10
#define I2CMUX5_SET_REG_2_CFG_GPIO_2_OD_PULL_DOWN    0x00
#define I2CMUX5_SET_REG_2_CFG_GPIO_2_PUSH_PULL       0x08
#define I2CMUX5_SET_REG_2_MASS_WRITE_DISABLE         0x00
#define I2CMUX5_SET_REG_2_MASS_WRITE_ENABLE          0x04
#define I2CMUX5_SET_REG_2_TIMEOUT_DISABLED           0x00
#define I2CMUX5_SET_REG_2_TIMEOUT_MODE_30_MS         0x01
#define I2CMUX5_SET_REG_2_TIMEOUT_MODE_15_MS         0x02
#define I2CMUX5_SET_REG_2_TIMEOUT_MODE_7_5_MS        0x03
 
#define I2CMUX5_SET_REG_3_BUS_1_SWITCH_OPEN          0x00
#define I2CMUX5_SET_REG_3_BUS_1_SWITCH_CLOSED        0x80
#define I2CMUX5_SET_REG_3_BUS_2_SWITCH_OPEN          0x00
#define I2CMUX5_SET_REG_3_BUS_2_SWITCH_CLOSED        0x40
#define I2CMUX5_SET_REG_3_BUS_3_SWITCH_OPEN          0x00
#define I2CMUX5_SET_REG_3_BUS_3_SWITCH_CLOSED        0x20
#define I2CMUX5_SET_REG_3_BUS_4_SWITCH_OPEN          0x00
#define I2CMUX5_SET_REG_3_BUS_4_SWITCH_CLOSED        0x10
 
#define I2CMUX5_CH_SEL_ERROR                         0xFF
 
#define I2CMUX5_SET_DEV_ADDR                         0x44
 
#define I2CMUX5_SET_6DOF_IMU_9_ADDR                  0x69
#define I2CMUX5_SET_6DOF_IMU_11_ADDR                 0x0E
#define I2CMUX5_SET_RTC_10_ADDR                      0x68
#define I2CMUX5_SET_ACCEL_10_ADDR                    0x18
 
 // i2cmux5_set
 
#define I2CMUX5_CH_1                                 0x01
#define I2CMUX5_CH_2                                 0x02
#define I2CMUX5_CH_3                                 0x03
#define I2CMUX5_CH_4                                 0x04
 
 // sel_ch
 
#define I2CMUX5_PIN_STATE_LOW                    0
#define I2CMUX5_PIN_STATE_HIGH                   1
 
 
 // pin_state
 
#define I2CMUX5_MAP_MIKROBUS( cfg, mikrobus )      \
    cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL );  \
    cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA );  \
    cfg.en = MIKROBUS( mikrobus, MIKROBUS_CS );    \
    cfg.ready = MIKROBUS( mikrobus, MIKROBUS_AN ); \
    cfg.alert = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // i2cmux5_map
 // i2cmux5
 
typedef struct
{
    // Output pins
 
    digital_out_t  en;         
    // Input pins
 
    digital_in_t  ready;       
    digital_in_t  alert;       
    // Modules
 
    i2c_master_t i2c;          
    // I2C slave address
 
    uint8_t slave_address;     
} i2cmux5_t;
 
typedef struct
{
    pin_name_t  scl;        
    pin_name_t  sda;        
    pin_name_t  en;         
    pin_name_t  ready;      
    pin_name_t  alert;      
    uint32_t  i2c_speed;    
    uint8_t   i2c_address;  
} i2cmux5_cfg_t;
 
void i2cmux5_cfg_setup ( i2cmux5_cfg_t *cfg );
 
err_t i2cmux5_init ( i2cmux5_t *ctx, i2cmux5_cfg_t *cfg );
 
void i2cmux5_default_cfg ( i2cmux5_t *ctx );
 
void i2cmux5_hw_reset ( i2cmux5_t *ctx );
 
void i2cmux5_dev_enable ( i2cmux5_t *ctx );
 
uint8_t i2cmux5_check_rdy ( i2cmux5_t *ctx );
 
uint8_t i2cmux5_check_alert ( i2cmux5_t *ctx );
 
err_t i2cmux5_generic_write ( i2cmux5_t *ctx, uint8_t reg, uint8_t *tx_buf, uint8_t tx_len );
 
err_t i2cmux5_generic_read ( i2cmux5_t *ctx, uint8_t reg, uint8_t *rx_buf, uint8_t rx_len );
 
uint8_t i2cmux5_check_ch_alert ( i2cmux5_t *ctx, uint8_t n_channel );
 
void i2cmux5_channel_write_byte ( i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg, uint8_t tx_data );
 
uint8_t i2cmux5_channel_read_byte ( i2cmux5_t *ctx, uint8_t sel_ch, uint8_t ch_slave_addr, uint8_t reg );
 
#ifdef __cplusplus
}
#endif
#endif // I2CMUX5_H
 
 // i2cmux5
 
// ------------------------------------------------------------------------ END