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#define | PIXI_MAP_MIKROBUS(cfg, mikrobus) |
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#define | PIXI_RETVAL uint8_t |
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#define | PIXI_INIT_ERROR 0xFF |
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#define | READ_OP 0 |
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#define | WRITE_OP 1 |
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#define | PIXI_ERR 1 |
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#define | PIXI_OK 0 |
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#define | PIXI_REG_DEVICE_ID 0x00 |
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#define | PIXI_REG_INTERRUPT 0x01 |
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#define | PIXI_REG_ADC_DATA_STATUS 0x02 |
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#define | PIXI_REG_OVERCURRENT_STATUS 0x04 |
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#define | PIXI_REG_GPI_STATUS 0x06 |
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#define | PIXI_REG_INT_TEMP 0x08 |
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#define | PIXI_REG_EXT_TEMP_1 0x09 |
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#define | PIXI_REG_EXT_TEMP_2 0x0A |
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#define | PIXI_REG_GPI_DATA 0x0B |
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#define | PIXI_REG_ADC_DATA_BASE 0x40 |
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#define | PIXI_REG_GPO_DATA 0x0D |
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#define | PIXI_REG_DEVICE_CONTROL 0x10 |
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#define | PIXI_REG_INTERRUPT_MASK 0x11 |
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#define | PIXI_REG_GPI_IRQMODE 0x12 |
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#define | PIXI_REG_DAC_PRESET_1 0x16 |
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#define | PIXI_REG_DAC_PRESET_2 0x17 |
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#define | PIXI_REG_TEMP_MONITOR_CONFIG 0x18 |
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#define | PIXI_REG_TEMP_IN_THRES_HIGH 0x19 |
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#define | PIXI_REG_TEMP_IN_THRES_LOW 0x1A |
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#define | PIXI_REG_TEMP_EXT_1_THRES_HIGH 0x1B |
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#define | PIXI_REG_TEMP_EXT_1_THRES_LOW 0x1C |
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#define | PIXI_REG_TEMP_EXT_2_THRES_HIGH 0x1D |
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#define | PIXI_REG_TEMP_EXT_2_THRES_LOW 0x1E |
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#define | PIXI_REG_PORT_CONFIG_BASE 0x20 |
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#define | PIXI_REG_DAC_DATA_BASE 0x60 |
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#define | PIXI_CTL_ADCCTL_IDLE 0x0000 |
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#define | PIXI_CTL_ADCCTL_SINGLESWEEP 0x0001 |
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#define | PIXI_CTL_ADCCTL_SINGLECONV 0x0002 |
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#define | PIXI_CTL_ADCCTL_CONTSWEEP 0x0003 |
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#define | PIXI_CTL_DACCTL_SEQUPDATE 0x0000 |
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#define | PIXI_CTL_DACCTL_IMMUPDATE 0x0001 << 2 |
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#define | PIXI_CTL_DACCTL_USEPRST_1 0x0002 << 2 |
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#define | PIXI_CTL_DACCTL_USEPRST_2 0x0003 << 2 |
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#define | PIXI_CTL_ADCCONV_200KSPS 0x0000 |
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#define | PIXI_CTL_ADCCONV_250KSPS 0x0001 << 4 |
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#define | PIXI_CTL_ADCCONV_333KSPS 0x0002 << 4 |
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#define | PIXI_CTL_ADCCONV_400KSPS 0x0003 << 4 |
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#define | PIXI_CTL_DACREF_INTREF 0x0001 << 6 |
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#define | PIXI_CTL_THSHDN_ENABLE 0x0001 << 7 |
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#define | PIXI_CTL_TMPCTL_INT 0x0001 << 8 |
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#define | PIXI_CTL_TMPCTL_EXT_1 0x0002 << 8 |
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#define | PIXI_CTL_TMPCTL_EXT_2 0x0004 << 8 |
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#define | PIXI_CTL_TMPPER_EXTENDED 0x0001 << 11 |
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#define | PIXI_CTL_RS_CANCEL_ENABLE 0x0001 << 12 |
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#define | PIXI_CTL_LPEN_LOWPOWER 0x0001 << 13 |
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#define | PIXI_CTL_BRST_CONTEX_INC 0x0001 << 14 |
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#define | PIXI_CTL_RESET 0x0001 << 15 |
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#define | PIXI_IMASK_ADCFLAG 0x0001 |
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#define | PIXI_IMASK_ADCDR 0x0002 |
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#define | PIXI_IMASK_ADCDM 0x0004 |
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#define | PIXI_IMASK_GPIDR 0x0008 |
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#define | PIXI_IMASK_GPIDM 0x0010 |
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#define | PIXI_IMASK_DACOI 0x0020 |
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#define | PIXI_IMASK_TMPINT 6 |
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#define | PIXI_IMASK_TMPEXT1 9 |
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#define | PIXI_IMASK_TMPEXT2 12 |
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#define | PIXI_IMASK_VMON 0x8000 |
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#define | PIXI_TMPMON_INT_4_SMP 0x0000 |
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#define | PIXI_TMPMOD_INT_8_SMP 0x0001 |
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#define | PIXI_TMPMON_INT_16_SMP 0x0002 |
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#define | PIXI_TMPMON_INT_32_SMP 0x0003 |
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#define | PIXI_TMPMON_EXT1_4_SMP 0x0000 |
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#define | PIXI_TMPMOD_EXT1_8_SMP 0x0001 << 2 |
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#define | PIXI_TMPMON_EXT1_16_SMP 0x0002 << 2 |
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#define | PIXI_TMPMON_EXT1_32_SMP 0x0003 << 2 |
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#define | PIXI_TMPMON_EXT2_4_SMP 0x0000 |
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#define | PIXI_TMPMOD_EXT2_8_SMP 0x0001 << 4 |
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#define | PIXI_TMPMON_EXT2_16_SMP 0x0002 << 4 |
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#define | PIXI_TMPMON_EXT2_32_SMP 0x0003 << 4 |
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#define | PIXI_PORT_CFG_CFG_ASSOCIATED 0 |
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#define | PIXI_PORT_CFG_CFG_SAMPLES_1 0x0000 << 5 |
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#define | PIXI_PORT_CFG_CFG_SAMPLES_2 0x0001 << 5 |
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#define | PIXI_PORT_CFG_CFG_SAMPLES_4 0x0002 << 5 |
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#define | PIXI_PORT_CFG_CFG_SAMPLES_8 0x0003 << 5 |
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#define | PIXI_PORT_CFG_CFG_SAMPLES_16 0x0004 << 5 |
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#define | PIXI_PORT_CFG_CFG_SAMPLES_32 0x0005 << 5 |
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#define | PIXI_PORT_CFG_CFG_SAMPLES_64 0x0006 << 5 |
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#define | PIXI_PORT_CFG_CFG_SAMPLES_128 0x0007 << 5 |
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#define | PIXI_PORT_CFG_CFG_RANGE_N 0x0000 << 8 |
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#define | PIXI_PORT_CFG_CFG_RANGE_1 0x0001 << 8 |
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#define | PIXI_PORT_CFG_CFG_RANGE_2 0x0002 << 8 |
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#define | PIXI_PORT_CFG_CFG_RANGE_3 0x0003 << 8 |
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#define | PIXI_PORT_CFG_CFG_RANGE_4 0x0004 << 8 |
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#define | PIXI_PORT_CFG_CFG_RANGE_5 0x0005 << 8 |
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#define | PIXI_PORT_CFG_CFG_RANGE_6 0x0006 << 8 |
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#define | PIXI_PORT_CFG_CFG_RANGE_7 0x0007 << 8 |
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#define | PIXI_PORT_CFG_MODE_0 0x0000 << 12 |
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#define | PIXI_PORT_CFG_MODE_1 0x0001 << 12 |
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#define | PIXI_PORT_CFG_MODE_2 0x0002 << 12 |
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#define | PIXI_PORT_CFG_MODE_3 0x0003 << 12 |
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#define | PIXI_PORT_CFG_MODE_4 0x0004 << 12 |
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#define | PIXI_PORT_CFG_MODE_5 0x0005 << 12 |
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#define | PIXI_PORT_CFG_MODE_6 0x0006 << 12 |
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#define | PIXI_PORT_CFG_MODE_7 0x0007 << 12 |
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#define | PIXI_PORT_CFG_MODE_8 0x0008 << 12 |
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#define | PIXI_PORT_CFG_MODE_9 0x0009 << 12 |
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#define | PIXI_PORT_CFG_MODE_10 0x000A << 12 |
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#define | PIXI_PORT_CFG_MODE_11 0x000B << 12 |
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#define | PIXI_PORT_CFG_MODE_12 0x000C << 12 |
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