|
#define | SILENTSTEP3_REG_DRVCTRL 0x00 |
| Silent Step 3 register list.
|
|
#define | SILENTSTEP3_REG_CHOPCONF 0x04 |
|
#define | SILENTSTEP3_REG_SMARTEN 0x05 |
|
#define | SILENTSTEP3_REG_SGCSCONF 0x06 |
|
#define | SILENTSTEP3_REG_DRVCONF 0x07 |
|
#define | SILENTSTEP3_DRVCTRL_1_PHA_MASK 0x20000ul |
| Silent Step 3 DRVCTRL (SDOFF=1) register setting.
|
|
#define | SILENTSTEP3_DRVCTRL_1_CA_MASK 0x1FE00ul |
|
#define | SILENTSTEP3_DRVCTRL_1_PHB_MASK 0x00100ul |
|
#define | SILENTSTEP3_DRVCTRL_1_CB_MASK 0x000FFul |
|
#define | SILENTSTEP3_DRVCTRL_0_INTPOL_MASK 0x00200ul |
| Silent Step 3 DRVCTRL (SDOFF=0) register setting.
|
|
#define | SILENTSTEP3_DRVCTRL_0_DEDGE_MASK 0x00100ul |
|
#define | SILENTSTEP3_DRVCTRL_0_MRES_256 0x00000ul |
|
#define | SILENTSTEP3_DRVCTRL_0_MRES_128 0x00001ul |
|
#define | SILENTSTEP3_DRVCTRL_0_MRES_64 0x00002ul |
|
#define | SILENTSTEP3_DRVCTRL_0_MRES_32 0x00003ul |
|
#define | SILENTSTEP3_DRVCTRL_0_MRES_16 0x00004ul |
|
#define | SILENTSTEP3_DRVCTRL_0_MRES_8 0x00005ul |
|
#define | SILENTSTEP3_DRVCTRL_0_MRES_4 0x00006ul |
|
#define | SILENTSTEP3_DRVCTRL_0_MRES_2 0x00007ul |
|
#define | SILENTSTEP3_DRVCTRL_0_MRES_1 0x00008ul |
|
#define | SILENTSTEP3_DRVCTRL_0_MRES_MASK 0x0000Ful |
|
#define | SILENTSTEP3_CHOPCONF_TBL_16 0x00000ul |
| Silent Step 3 CHOPCONF register setting.
|
|
#define | SILENTSTEP3_CHOPCONF_TBL_24 0x08000ul |
|
#define | SILENTSTEP3_CHOPCONF_TBL_32 0x10000ul |
|
#define | SILENTSTEP3_CHOPCONF_TBL_54 0x18000ul |
|
#define | SILENTSTEP3_CHOPCONF_TBL_MASK 0x18000ul |
|
#define | SILENTSTEP3_CHOPCONF_CHM_STANDARD 0x00000ul |
|
#define | SILENTSTEP3_CHOPCONF_CHM_FAST 0x04000ul |
|
#define | SILENTSTEP3_CHOPCONF_CHM_MASK 0x04000ul |
|
#define | SILENTSTEP3_CHOPCONF_RNDTF_DISABLE 0x00000ul |
|
#define | SILENTSTEP3_CHOPCONF_RNDTF_ENABLE 0x02000ul |
|
#define | SILENTSTEP3_CHOPCONF_RNDTF_MASK 0x02000ul |
|
#define | SILENTSTEP3_CHOPCONF_HDEC_16 0x00000ul |
|
#define | SILENTSTEP3_CHOPCONF_HDEC_32 0x00800ul |
|
#define | SILENTSTEP3_CHOPCONF_HDEC_48 0x01000ul |
|
#define | SILENTSTEP3_CHOPCONF_HDEC_64 0x01800ul |
|
#define | SILENTSTEP3_CHOPCONF_HDEC_MASK 0x01800ul |
|
#define | SILENTSTEP3_CHOPCONF_HEND_0 0x00180ul |
|
#define | SILENTSTEP3_CHOPCONF_HEND_MASK 0x00780ul |
|
#define | SILENTSTEP3_CHOPCONF_HSTRT_4 0x00030ul |
|
#define | SILENTSTEP3_CHOPCONF_HSTRT_MASK 0x00070ul |
|
#define | SILENTSTEP3_CHOPCONF_TOFF_4 0x00004ul |
|
#define | SILENTSTEP3_CHOPCONF_TOFF_MASK 0x0000Ful |
|
#define | SILENTSTEP3_SMARTEN_SEIMIN_HALF_CS 0x00000ul |
| Silent Step 3 SMARTEN register setting.
|
|
#define | SILENTSTEP3_SMARTEN_SEIMIN_QUARTER_CS 0x08000ul |
|
#define | SILENTSTEP3_SMARTEN_SEIMIN_MASK 0x08000ul |
|
#define | SILENTSTEP3_SMARTEN_SEDN_32 0x00000ul |
|
#define | SILENTSTEP3_SMARTEN_SEDN_8 0x02000ul |
|
#define | SILENTSTEP3_SMARTEN_SEDN_2 0x04000ul |
|
#define | SILENTSTEP3_SMARTEN_SEDN_1 0x06000ul |
|
#define | SILENTSTEP3_SMARTEN_SEDN_MASK 0x06000ul |
|
#define | SILENTSTEP3_SMARTEN_SEMAX_2 0x00200ul |
|
#define | SILENTSTEP3_SMARTEN_SEMAX_MASK 0x00F00ul |
|
#define | SILENTSTEP3_SMARTEN_SEUP_1 0x00000ul |
|
#define | SILENTSTEP3_SMARTEN_SEUP_2 0x00020ul |
|
#define | SILENTSTEP3_SMARTEN_SEUP_4 0x00040ul |
|
#define | SILENTSTEP3_SMARTEN_SEUP_8 0x00060ul |
|
#define | SILENTSTEP3_SMARTEN_SEUP_MASK 0x00060ul |
|
#define | SILENTSTEP3_SMARTEN_SEMIN_2 0x00002ul |
|
#define | SILENTSTEP3_SMARTEN_SEMIN_MASK 0x0000Ful |
|
#define | SILENTSTEP3_SGCSCONF_SFILT_STANDARD 0x00000ul |
| Silent Step 3 SGCSCONF register setting.
|
|
#define | SILENTSTEP3_SGCSCONF_SFILT_FILTERED 0x10000ul |
|
#define | SILENTSTEP3_SGCSCONF_SFILT_MASK 0x10000ul |
|
#define | SILENTSTEP3_SGCSCONF_SGT_0 0x00000ul |
|
#define | SILENTSTEP3_SGCSCONF_SGT_MASK 0x07F00ul |
|
#define | SILENTSTEP3_SGCSCONF_CS_2_OF_32 0x00002ul |
|
#define | SILENTSTEP3_SGCSCONF_CS_MASK 0x0001Ful |
|
#define | SILENTSTEP3_DRVCONF_TST_MASK 0x10000ul |
| Silent Step 3 DRVCONF register setting.
|
|
#define | SILENTSTEP3_DRVCONF_SLPH_MIN 0x00000ul |
|
#define | SILENTSTEP3_DRVCONF_SLPH_MIN_TEMP 0x04000ul |
|
#define | SILENTSTEP3_DRVCONF_SLPH_MED_TEMP 0x08000ul |
|
#define | SILENTSTEP3_DRVCONF_SLPH_MAX 0x0C000ul |
|
#define | SILENTSTEP3_DRVCONF_SLPH_MASK 0x0C000ul |
|
#define | SILENTSTEP3_DRVCONF_SLPL_MIN 0x00000ul |
|
#define | SILENTSTEP3_DRVCONF_SLPL_MIN_TEMP 0x01000ul |
|
#define | SILENTSTEP3_DRVCONF_SLPL_MED_TEMP 0x02000ul |
|
#define | SILENTSTEP3_DRVCONF_SLPL_MAX 0x03000ul |
|
#define | SILENTSTEP3_DRVCONF_SLPL_MASK 0x03000ul |
|
#define | SILENTSTEP3_DRVCONF_DISS2G_ENABLE 0x00000ul |
|
#define | SILENTSTEP3_DRVCONF_DISS2G_DISABLE 0x00400ul |
|
#define | SILENTSTEP3_DRVCONF_DISS2G_MASK 0x00400ul |
|
#define | SILENTSTEP3_DRVCONF_TS2G_3_2US 0x00000ul |
|
#define | SILENTSTEP3_DRVCONF_TS2G_1_6US 0x00100ul |
|
#define | SILENTSTEP3_DRVCONF_TS2G_1_2US 0x00200ul |
|
#define | SILENTSTEP3_DRVCONF_TS2G_0_8US 0x00300ul |
|
#define | SILENTSTEP3_DRVCONF_TS2G_MASK 0x00300ul |
|
#define | SILENTSTEP3_DRVCONF_SDOFF_0 0x00000ul |
|
#define | SILENTSTEP3_DRVCONF_SDOFF_1 0x00080ul |
|
#define | SILENTSTEP3_DRVCONF_SDOFF_MASK 0x00080ul |
|
#define | SILENTSTEP3_DRVCONF_VSENSE_305MV 0x00000ul |
|
#define | SILENTSTEP3_DRVCONF_VSENSE_165MV 0x00040ul |
|
#define | SILENTSTEP3_DRVCONF_VSENSE_MASK 0x00040ul |
|
#define | SILENTSTEP3_DRVCONF_RDSEL_MSTEP 0x00000ul |
|
#define | SILENTSTEP3_DRVCONF_RDSEL_SG_LEVEL 0x00010ul |
|
#define | SILENTSTEP3_DRVCONF_RDSEL_SG_CS_LEVEL 0x00020ul |
|
#define | SILENTSTEP3_DRVCONF_RDSEL_MASK 0x00030ul |
|
#define | SILENTSTEP3_PIN_STATE_LOW 0 |
| Silent Step 3 pin logic state setting.
|
|
#define | SILENTSTEP3_PIN_STATE_HIGH 1 |
|
#define | SILENTSTEP3_DIR_CCW 0 |
| Silent Step 3 direction setting.
|
|
#define | SILENTSTEP3_DIR_CW 1 |
|
#define | SILENTSTEP3_MODE_FULL_STEP 8 |
| Silent Step 3 step resolution setting.
|
|
#define | SILENTSTEP3_MODE_HALF_STEP 7 |
|
#define | SILENTSTEP3_MODE_QUARTER_STEP 6 |
|
#define | SILENTSTEP3_MODE_1_OVER_8_STEP 5 |
|
#define | SILENTSTEP3_MODE_1_OVER_16_STEP 4 |
|
#define | SILENTSTEP3_MODE_1_OVER_32_STEP 3 |
|
#define | SILENTSTEP3_MODE_1_OVER_64_STEP 2 |
|
#define | SILENTSTEP3_MODE_1_OVER_128_STEP 1 |
|
#define | SILENTSTEP3_MODE_1_OVER_256_STEP 0 |
|
#define | SILENTSTEP3_SPEED_VERY_SLOW 0 |
| Silent Step 3 device speed settings.
|
|
#define | SILENTSTEP3_SPEED_SLOW 1 |
|
#define | SILENTSTEP3_SPEED_MEDIUM 2 |
|
#define | SILENTSTEP3_SPEED_FAST 3 |
|
#define | SILENTSTEP3_SPEED_VERY_FAST 4 |
|
#define | SILENTSTEP3_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
| Data sample selection.
|
|
#define | SILENTSTEP3_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
|
#define | SILENTSTEP3_MAP_MIKROBUS(cfg, mikrobus) |
| MikroBUS pin mapping.
|
|