tdc2.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish,distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef TDC2_H
#define TDC2_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
 
#define TDC2_REG_CFG0                       0x00
#define TDC2_REG_CFG1                       0x01
#define TDC2_REG_CFG2                       0x02
#define TDC2_REG_CFG3                       0x03
#define TDC2_REG_CFG4                       0x04
#define TDC2_REG_CFG5                       0x05
#define TDC2_REG_CFG6                       0x06
#define TDC2_REG_CFG7                       0x07
#define TDC2_REG_CFG8                       0x08
#define TDC2_REG_CFG9                       0x09
#define TDC2_REG_CFG10                      0x0A
#define TDC2_REG_CFG11                      0x0B
#define TDC2_REG_CFG12                      0x0C
#define TDC2_REG_CFG13                      0x0D
#define TDC2_REG_CFG14                      0x0E
#define TDC2_REG_CFG15                      0x0F
#define TDC2_REG_CFG16                      0x10
 
#define TDC2_REG_INDEX_CH1_BYTE3            0x08
#define TDC2_REG_INDEX_CH1_BYTE2            0x09
#define TDC2_REG_INDEX_CH1_BYTE1            0x0A
#define TDC2_REG_STOP_CH1_BYTE3             0x0B
#define TDC2_REG_STOP_CH1_BYTE2             0x0C
#define TDC2_REG_STOP_CH1_BYTE1             0x0D
#define TDC2_REG_INDEX_CH2_BYTE3            0x0E
#define TDC2_REG_INDEX_CH2_BYTE2            0x0F
#define TDC2_REG_INDEX_CH2_BYTE1            0x10
#define TDC2_REG_STOP_CH2_BYTE3             0x11
#define TDC2_REG_STOP_CH2_BYTE2             0x12
#define TDC2_REG_STOP_CH2_BYTE1             0x13
#define TDC2_REG_INDEX_CH3_BYTE3            0x14
#define TDC2_REG_INDEX_CH3_BYTE2            0x15
#define TDC2_REG_INDEX_CH3_BYTE1            0x16
#define TDC2_REG_STOP_CH3_BYTE3             0x17
#define TDC2_REG_STOP_CH3_BYTE2             0x18
#define TDC2_REG_STOP_CH3_BYTE1             0x19
#define TDC2_REG_INDEX_CH4_BYTE3            0x1A
#define TDC2_REG_INDEX_CH4_BYTE2            0x1B
#define TDC2_REG_INDEX_CH4_BYTE1            0x1C
#define TDC2_REG_STOP_CH4_BYTE3             0x1D
#define TDC2_REG_STOP_CH4_BYTE2             0x1E
#define TDC2_REG_STOP_CH4_BYTE1             0x1F
 
 // tdc2_reg
 
#define TDC2_SPIOPC_POWER                   0x30
#define TDC2_SPIOPC_INIT                    0x18
#define TDC2_SPIOPC_WRITE_CONFIG            0x80
#define TDC2_SPIOPC_READ_CONFIG             0x40
#define TDC2_SPIOPC_READ_RESULTS            0x60
#define TDC2_SPIOPC_READ_RESULTS            0x60
 
#define TDC2_ENABLE_STOP1_PIN               0x01
#define TDC2_DISABLE_STOP1_PIN              0x00
#define TDC2_ENABLE_STOP2_PIN               0x02
#define TDC2_DISABLE_STOP2_PIN              0x00
#define TDC2_ENABLE_STOP3_PIN               0x04
#define TDC2_DISABLE_STOP3_PIN              0x00
#define TDC2_ENABLE_STOP4_PIN               0x08
#define TDC2_DISABLE_STOP4_PIN              0x00
#define TDC2_ENABLE_REFCLK_PIN              0x10
#define TDC2_DISABLE_REFCLK_PIN             0x00
#define TDC2_ENABLE_DISABLE_PIN             0x40
#define TDC2_DISABLE_DISABLE_PIN            0x00
#define TDC2_ENABLE_RSTINDX_PIN             0x80
#define TDC2_DISABLE_RSTINDX_PIN            0x00
 
#define TDC2_HIT_ENABLE_STOP1               0x01
#define TDC2_HIT_DISABLE_STOP1              0x00
#define TDC2_HIT_ENABLE_STOP2               0x02
#define TDC2_HIT_DISABLE_STOP2              0x00
#define TDC2_HIT_ENABLE_STOP3               0x04
#define TDC2_HIT_DISABLE_STOP3              0x00
#define TDC2_HIT_ENABLE_STOP4               0x08
#define TDC2_HIT_DISABLE_STOP4              0x00
#define TDC2_CHANNEL_COMBINE_NORMAL         0x00
#define TDC2_CHANNEL_COMBINE_PULSE_DISTANCE 0x10
#define TDC2_CHANNEL_COMBINE_PULSE_WIDTH    0x20
#define TDC2_HIGH_RESOLUTION_OFF            0x00
#define TDC2_HIGH_RESOLUTION_X2             0x40
#define TDC2_HIGH_RESOLUTION_X4             0x80
 
#define TDC2_FIFO_COMMON_READ_OFF           0x00
#define TDC2_FIFO_COMMON_READ_ON            0x40
#define TDC2_FIFO_BLOCKWISE_READ_OFF        0x00
#define TDC2_FIFO_BLOCKWISE_READ_ON         0x80
 
#define TDC2_CFG6_FIXED_VALUE               0xC0
#define TDC2_CFG8_FIXED_VALUE               0xA1
#define TDC2_CFG9_FIXED_VALUE               0x13
#define TDC2_CFG10_FIXED_VALUE              0x00
#define TDC2_CFG11_FIXED_VALUE              0x0A
#define TDC2_CFG12_FIXED_VALUE              0xCC
#define TDC2_CFG13_FIXED_VALUE              0x05
#define TDC2_CFG14_FIXED_VALUE              0xF1
#define TDC2_CFG15_FIXED_VALUE              0x7D
#define TDC2_CFG16_FIXED_VALUE              0x04
 
#define TDC2_CFG7_FIXED_VALUE               0x23
#define TDC2_REFERENCE_CLOCK_INTERNAL       0x80
#define TDC2_REFERENCE_CLOCK_EXTERNAL       0x00
 
#define TDC2_1pS_RESOLUTION                 125000
#define TDC2_5pS_RESOLUTION                 62500
#define TDC2_10pS_RESOLUTION                12500
 
#define TDC2_uS_TO_mS                       1000000
 
#define TDC2_SET_DATA_SAMPLE_EDGE      SET_SPI_DATA_SAMPLE_EDGE
#define TDC2_SET_DATA_SAMPLE_MIDDLE    SET_SPI_DATA_SAMPLE_MIDDLE
 
 // tdc2_set
 
#define TDC2_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.rir  = MIKROBUS( mikrobus, MIKROBUS_AN ); \
    cfg.rst  = MIKROBUS( mikrobus, MIKROBUS_RST ); \
    cfg.dis = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
    cfg.int_pin = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // tdc2_map
 // tdc2
 
typedef struct
{
    // Output pins
    digital_out_t rir;      
    digital_out_t rst;      
    digital_out_t dis;      
    // Input pins
    digital_in_t int_pin;   
    // Modules
    spi_master_t spi;                  
    pin_name_t   chip_select;          
} tdc2_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t miso;            
    pin_name_t mosi;            
    pin_name_t sck;             
    pin_name_t cs;              
    // Additional gpio pins
    pin_name_t rir;             
    pin_name_t rst;             
    pin_name_t dis;             
    pin_name_t int_pin;         
    // static variable
    uint32_t                          spi_speed;    
    spi_master_mode_t                 spi_mode;     
    spi_master_chip_select_polarity_t cs_polarity;  
} tdc2_cfg_t;
 
typedef enum
{
    TDC2_OK = 0,
    TDC2_ERROR = -1
 
} tdc2_return_value_t;
 
void tdc2_cfg_setup ( tdc2_cfg_t *cfg );
 
err_t tdc2_init ( tdc2_t *ctx, tdc2_cfg_t *cfg );
 
err_t tdc2_default_cfg ( tdc2_t *ctx );
 
err_t tdc2_generic_write ( tdc2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t tdc2_generic_read ( tdc2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t tdc2_write_config ( tdc2_t *ctx, uint8_t reg, uint8_t *data_in, uint8_t len );
 
err_t tdc2_read_config ( tdc2_t *ctx, uint8_t reg, uint8_t *data_out, uint8_t len );
 
err_t tdc2_read_results( tdc2_t *ctx, uint8_t reg, uint32_t *reference_index, uint32_t *stop_result );
 
err_t tdc2_send_command ( tdc2_t *ctx, uint8_t command );
 
err_t tdc2_sw_reset ( tdc2_t *ctx );
 
err_t tdc2_start_measuring ( tdc2_t *ctx );
 
err_t tdc2_set_resolution ( tdc2_t *ctx, uint32_t resolution );
 
err_t tdc2_get_resolution ( tdc2_t *ctx, uint32_t *resolution );
 
void tdc2_reset_index ( tdc2_t *ctx );
 
void tdc2_disable_stop_channels ( tdc2_t *ctx );
 
void tdc2_enable_stop_channels ( tdc2_t *ctx );
 
uint8_t tdc2_get_int_state ( tdc2_t *ctx );
 
err_t tdc2_get_time_between_stops ( tdc2_t *ctx, uint32_t stop_result1, uint32_t reference_index1, 
                                    uint32_t stop_result2, uint32_t reference_index2, 
                                    uint32_t *time_in_us );
 
#ifdef __cplusplus
}
#endif
#endif // TDC2_H
 
 // tdc2
 
// ------------------------------------------------------------------------ END