ultrasonic5.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
 
#ifndef ULTRASONIC5_H
#define ULTRASONIC5_H
 
#ifdef __cplusplus
extern "C"{
#endif
 
#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"
#include "drv_analog_in.h"
#include "drv_pwm.h"
 
#define ULTRASONIC5_REG_BPF_CONFIG_1                0x10
#define ULTRASONIC5_REG_BPF_CONFIG_2                0x11
#define ULTRASONIC5_REG_DEV_CTRL_1                  0x12
#define ULTRASONIC5_REG_DEV_CTRL_2                  0x13
#define ULTRASONIC5_REG_DEV_CTRL_3                  0x14
#define ULTRASONIC5_REG_VDRV_CTRL                   0x16
#define ULTRASONIC5_REG_ECHO_INT_CONFIG             0x17
#define ULTRASONIC5_REG_ZC_CONFIG                   0x18
#define ULTRASONIC5_REG_BURST_PULSE                 0x1A
#define ULTRASONIC5_REG_TOF_CONFIG                  0x1B
#define ULTRASONIC5_REG_DEV_STAT                    0x1C
#define ULTRASONIC5_REG_DEVICE_ID                   0x1D
#define ULTRASONIC5_REG_REV_ID                      0x1E
 
 // ultrasonic5_reg
 
#define ULTRASONIC5_BPF_CONFIG_1_FC_TRIM_FRC        0x80
#define ULTRASONIC5_BPF_CONFIG_1_BYPASS             0x40
#define ULTRASONIC5_BPF_CONFIG_1_HPF_FREQ_MASK      0x3F
#define ULTRASONIC5_BPF_CONFIG_1_RESET              0x00
 
#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_4            0x00
#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_5            0x10
#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_2            0x20
#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_3            0x30
#define ULTRASONIC5_BPF_CONFIG_2_Q_SEL_MASK         0x30
#define ULTRASONIC5_BPF_CONFIG_2_FC_TRIM_MASK       0x0F
#define ULTRASONIC5_BPF_CONFIG_2_RESET              0x00
 
#define ULTRASONIC5_DEV_CTRL_1_LOGAMP_FRC           0x80
#define ULTRASONIC5_DEV_CTRL_1_LOGAMP_SLP_ADJ_MASK  0x70
#define ULTRASONIC5_DEV_CTRL_1_LOGAMP_INT_ADJ_MASK  0x0F
#define ULTRASONIC5_DEV_CTRL_1_RESET                0x00
 
#define ULTRASONIC5_DEV_CTRL_2_LOGAMP_DIS_FIRST     0x80
#define ULTRASONIC5_DEV_CTRL_2_LOGAMP_DIS_LAST      0x40
#define ULTRASONIC5_DEV_CTRL_2_VOUT_SCALE_SEL_5V    0x04
#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_15V         0x00
#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_10V         0x01
#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_20V         0x02
#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_12_5V       0x03
#define ULTRASONIC5_DEV_CTRL_2_LNA_GAIN_MASK        0x03
#define ULTRASONIC5_DEV_CTRL_2_RESET                0x00
 
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_64US  0x00
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_48US  0x04
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_32US  0x08
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_24US  0x0C
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_16US  0x10
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_8US   0x14
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_4US   0x18
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_DIS   0x1C
#define ULTRASONIC5_DEV_CTRL_3_DRV_PLS_FLT_DT_MASK  0x1C
#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_0            0x00
#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_1            0x01
#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_2            0x02
#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_3            0x03
#define ULTRASONIC5_DEV_CTRL_3_IO_MODE_MASK         0x03
#define ULTRASONIC5_DEV_CTRL_3_RESET                0x00
 
#define ULTRASONIC5_VDRV_CTRL_DIS_VDRV_REG_LSTN     0x40
#define ULTRASONIC5_VDRV_CTRL_VDRV_HI_Z             0x20
#define ULTRASONIC5_VDRV_CTRL_VDRV_CURR_LVL_20MA    0x10
#define ULTRASONIC5_VDRV_CTRL_VDRV_VOLT_LVL_5V      0x00
#define ULTRASONIC5_VDRV_CTRL_VDRV_VOLT_LVL_MASK    0x0F
#define ULTRASONIC5_VDRV_CTRL_RESET                 0x20
 
#define ULTRASONIC5_ECHO_INT_CONFIG_CMP_EN          0x10
#define ULTRASONIC5_ECHO_INT_CONFIG_THR_SEL_MASK    0x0F
#define ULTRASONIC5_ECHO_INT_CONFIG_RESET           0x07
 
#define ULTRASONIC5_ZC_CONFIG_CMP_EN                0x80
#define ULTRASONIC5_ZC_CONFIG_EN_ECHO_INT           0x40
#define ULTRASONIC5_ZC_CONFIG_CMP_IN_SEL            0x20
#define ULTRASONIC5_ZC_CONFIG_CMP_STG_SEL_MASK      0x18
#define ULTRASONIC5_ZC_CONFIG_CMP_HYST_MASK         0x07
#define ULTRASONIC5_ZC_CONFIG_RESET                 0x14
 
#define ULTRASONIC5_BURST_PULSE_HALF_BRG_MODE       0x80
#define ULTRASONIC5_BURST_PULSE_PRE_DRIVER_MODE     0x40
#define ULTRASONIC5_BURST_PULSE_BURST_PULSE_16      0x0F
#define ULTRASONIC5_BURST_PULSE_BURST_PULSE_MASK    0x3F
#define ULTRASONIC5_BURST_PULSE_RESET               0x00
 
#define ULTRASONIC5_TOF_CONFIG_SLEEP_MODE_EN        0x80
#define ULTRASONIC5_TOF_CONFIG_STDBY_MODE_EN        0x40
#define ULTRASONIC5_TOF_CONFIG_VDRV_TRIGGER         0x02
#define ULTRASONIC5_TOF_CONFIG_CMD_TRIGGER          0x01
#define ULTRASONIC5_TOF_CONFIG_RESET                0x00
 
#define ULTRASONIC5_DEF_FREQ                        40000
#define ULTRASONIC5_DEF_DYTY                        0.5f
 
#define ULTRASONIC5_DEVICE_ID                       0xB9
 
#define ULTRASONIC5_ODD_PARITY                      0x01
 
#define ULTRASONIC5_SET_DATA_SAMPLE_EDGE            SET_SPI_DATA_SAMPLE_EDGE
#define ULTRASONIC5_SET_DATA_SAMPLE_MIDDLE          SET_SPI_DATA_SAMPLE_MIDDLE
 
 // ultrasonic5_set
 
#define ULTRASONIC5_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.an   = MIKROBUS( mikrobus, MIKROBUS_AN ); \
    cfg.io1  = MIKROBUS( mikrobus, MIKROBUS_RST ); \
    cfg.io2  = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
    cfg.out4 = MIKROBUS( mikrobus, MIKROBUS_INT )
 
 // ultrasonic5_map
 // ultrasonic5
 
typedef struct
{
    // Output pins
    digital_out_t io1;              
    // Input pins
    digital_in_t  out4;             
    // Modules
    spi_master_t  spi;              
    analog_in_t   adc;              
    pwm_t         pwm;              
    // ctx variable
    uint32_t      pwm_freq;         
    pin_name_t    chip_select;      
} ultrasonic5_t;
 
typedef struct
{
    // Communication gpio pins
    pin_name_t miso;                
    pin_name_t mosi;                
    pin_name_t sck;                 
    pin_name_t cs;                  
    pin_name_t an;                  
    pin_name_t io2;                 
    // Additional gpio pins
    pin_name_t io1;                 
    pin_name_t out4;                
    uint32_t                          spi_speed;    
    spi_master_mode_t                 spi_mode;     
    spi_master_chip_select_polarity_t cs_polarity;  
    analog_in_resolution_t resolution;  
    float                  vref;        
    uint32_t dev_pwm_freq;          
} ultrasonic5_cfg_t;
 
typedef enum
{
    ULTRASONIC5_OK = 0,
    ULTRASONIC5_ERROR = -1
 
} ultrasonic5_return_value_t;
 
void ultrasonic5_cfg_setup ( ultrasonic5_cfg_t *cfg );
 
err_t ultrasonic5_init ( ultrasonic5_t *ctx, ultrasonic5_cfg_t *cfg );
 
err_t ultrasonic5_default_cfg ( ultrasonic5_t *ctx );
 
err_t ultrasonic5_write_register ( ultrasonic5_t *ctx, uint8_t reg, uint8_t data_in );
 
err_t ultrasonic5_read_register ( ultrasonic5_t *ctx, uint8_t reg, uint8_t *data_out );
 
err_t ultrasonic5_check_communication ( ultrasonic5_t *ctx );
 
void ultrasonic5_set_io1_pin ( ultrasonic5_t *ctx );
 
void ultrasonic5_clear_io1_pin ( ultrasonic5_t *ctx );
 
uint8_t ultrasonic5_get_out4_pin ( ultrasonic5_t *ctx );
 
err_t ultrasonic5_read_an_pin_value ( ultrasonic5_t *ctx, uint16_t *data_out );
 
err_t ultrasonic5_read_an_pin_voltage ( ultrasonic5_t *ctx, float *data_out );
 
err_t ultrasonic5_set_duty_cycle ( ultrasonic5_t *ctx, float duty_cycle );
 
err_t ultrasonic5_pwm_stop ( ultrasonic5_t *ctx );
 
err_t ultrasonic5_pwm_start ( ultrasonic5_t *ctx );
 
#ifdef __cplusplus
}
#endif
#endif // ULTRASONIC5_H
 
 // ultrasonic5
 
// ------------------------------------------------------------------------ END