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#define | ADC4_MAP_MIKROBUS(cfg, mikrobus) |
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#define | ADC4_RETVAL uint8_t |
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#define | ADC4_OK 0x00 |
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#define | ADC4_INIT_ERROR 0xFF |
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#define | ADC4_RESOLUTION 8388607 |
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#define | ADC4_VREF_4000MV 4.096 |
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#define | ADC4_VREF_2500MV 2.5 |
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#define | ADC4_STATUS_REG 0x00 |
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#define | ADC4_MODE_REG 0x01 |
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#define | ADC4_IFACE_MODE_REG 0x02 |
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#define | ADC4_CHECK_REG 0x03 |
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#define | ADC4_DATA_REG 0x04 |
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#define | ADC4_GPIO_CONFIG_REG 0x06 |
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#define | ADC4_ID_REG 0x07 |
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#define | ADC4_SETUP_CONFIGURATION_REG 0x20 |
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#define | ADC4_CH_REG_BASE 0x10 |
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#define | ADC4_CON_REG_BASE 0x20 |
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#define | ADC4_FILCON_REG_BASE 0x28 |
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#define | ADC4_OFFSET_REG_BASE 0x30 |
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#define | ADC4_GAIN_REG_BASE 0x38 |
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#define | ADC4_STATUS_RDY 0x80 |
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#define | ADC4_STATUS_ERR 0x40 |
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#define | ADC4_STATUS_CRC_ERR 0x20 |
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#define | ADC4_STATUS_REG_ERR 0x10 |
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#define | ADC4_STATUS_CH_ACTIVE 0x0F |
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#define | ADC4_MODE_INT_REF_AND_SING_CYC_EN 0xA000 |
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#define | ADC4_MODE_INT_REF_EN 0x8000 |
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#define | ADC4_MODE_HIDE_RELAY_DIS 0x4000 |
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#define | ADC4_MODE_SING_CYC_EN 0x2000 |
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#define | ADC4_MODE_DELAY_0 0x0000 |
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#define | ADC4_MODE_DELAY_4 0x0100 |
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#define | ADC4_MODE_DELAY_16 0x0200 |
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#define | ADC4_MODE_DELAY_40 0x0300 |
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#define | ADC4_MODE_DELAY_100 0x0400 |
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#define | ADC4_MODE_DELAY_200 0x0500 |
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#define | ADC4_MODE_DELAY_500 0x0600 |
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#define | ADC4_MODE_DELAY_1000 0x0700 |
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#define | ADC4_MODE_CONTINUOUS 0x0000 |
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#define | ADC4_MODE_SINGLE 0x0010 |
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#define | ADC4_MODE_STBY 0x0020 |
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#define | ADC4_MODE_POWER_DOWN 0x0030 |
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#define | ADC4_MODE_INTERNAL_OFFSET 0x0040 |
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#define | ADC4_MODE_SYSTEM_OFFSET 0x0060 |
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#define | ADC4_MODE_GAIN_OFFSET 0x0070 |
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#define | ADC4_MODE_CLK_INTOSC 0x0000 |
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#define | ADC4_MODE_CLK_INTOSC_XT2 0x0002 |
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#define | ADC4_MODE_CLK_EXTOSC_XT2 0x0004 |
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#define | ADC4_MODE_CLK_EXTOSC 0x0006 |
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#define | ADC4_IFACE_MODE_ALTSYNC_EN 0x1000 |
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#define | ADC4_IFACE_MODE_IOSTREN_EN 0x0800 |
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#define | ADC4_IFACE_MODE_DOUTRES_EN 0x0100 |
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#define | ADC4_IFACE_MODE_CONTRD_EN 0x0080 |
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#define | ADC4_IFACE_MODE_DATASTA_EN 0x0040 |
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#define | ADC4_IFACE_MODE_REGCHK_EN 0x0020 |
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#define | ADC4_IFACE_MODE_CRC_DIS 0x0000 |
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#define | ADC4_IFACE_MODE_CRC_RD_EN 0x0002 |
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#define | ADC4_IFACE_MODE_CRC_RW_EN 0x0004 |
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#define | ADC4_CFG_PDSW 0x4000 |
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#define | ADC4_CFG_OP_EN2_3 0x2000 |
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#define | ADC4_CFG_MUX_IO 0x1000 |
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#define | ADC4_CFG_SYNC_EN 0x0800 |
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#define | ADC4_CFG_ERR_DISABLE 0x0000 |
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#define | ADC4_CFG_ERR_INPUT 0x0400 |
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#define | ADC4_CFG_ERR_OPENDRAIN 0x0200 |
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#define | ADC4_CFG_ERR_OUTPUT 0x0600 |
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#define | ADC4_CFG_ERR_DAT 0x0010 |
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#define | ADC4_CH_EN 0x8000 |
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#define | ADC4_CH_SETUP_0 0x0001 << 12 |
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#define | ADC4_CH_SETUP_1 0x0002 << 12 |
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#define | ADC4_CH_SETUP_2 0x0003 << 12 |
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#define | ADC4_CH_SETUP_3 0x0004 << 12 |
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#define | ADC4_CH_SETUP_4 0x0005 << 12 |
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#define | ADC4_CH_SETUP_5 0x0006 << 12 |
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#define | ADC4_CH_SETUP_6 0x0007 << 12 |
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#define | ADC4_CH_SETUP_7 0x0008 << 12 |
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#define | ADC4_CH_AINPOS_0 0x0000 << 5 |
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#define | ADC4_CH_AINPOS_1 0x0001 << 5 |
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#define | ADC4_CH_AINPOS_2 0x0002 << 5 |
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#define | ADC4_CH_AINPOS_3 0x0003 << 5 |
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#define | ADC4_CH_AINPOS_4 0x0004 << 5 |
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#define | ADC4_CH_AINPOS_5 0x0005 << 5 |
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#define | ADC4_CH_AINPOS_6 0x0006 << 5 |
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#define | ADC4_CH_AINPOS_7 0x0007 << 5 |
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#define | ADC4_CH_AINPOS_8 0x0008 << 5 |
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#define | ADC4_CH_AINPOS_9 0x0009 << 5 |
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#define | ADC4_CH_AINPOS_10 0x000A << 5 |
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#define | ADC4_CH_AINPOS_11 0x000B << 5 |
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#define | ADC4_CH_AINPOS_12 0x000C << 5 |
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#define | ADC4_CH_AINPOS_13 0x000D << 5 |
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#define | ADC4_CH_AINPOS_14 0x000E << 5 |
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#define | ADC4_CH_AINPOS_15 0x000F << 5 |
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#define | ADC4_CH_AINPOS_16 0x0010 << 5 |
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#define | ADC4_CH_AINPOS_TEMP_P 0x0011 << 5 |
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#define | ADC4_CH_AINPOS_TEMP_N 0x0012 << 5 |
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#define | ADC4_CH_AINPOS_AV_P 0x0013 << 5 |
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#define | ADC4_CH_AINPOS_AV_N 0x0014 << 5 |
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#define | ADC4_CH_AINPOS_REF_P 0x0015 << 5 |
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#define | ADC4_CH_AINPOS_REF_N 0x0016 << 5 |
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#define | ADC4_CH_AINNEG_0 0x0000 |
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#define | ADC4_CH_AINNEG_1 0x0001 |
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#define | ADC4_CH_AINNEG_2 0x0002 |
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#define | ADC4_CH_AINNEG_3 0x0003 |
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#define | ADC4_CH_AINNEG_4 0x0004 |
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#define | ADC4_CH_AINNEG_5 0x0005 |
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#define | ADC4_CH_AINNEG_6 0x0006 |
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#define | ADC4_CH_AINNEG_7 0x0007 |
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#define | ADC4_CH_AINNEG_8 0x0008 |
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#define | ADC4_CH_AINNEG_9 0x0009 |
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#define | ADC4_CH_AINNEG_10 0x000A |
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#define | ADC4_CH_AINNEG_11 0x000B |
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#define | ADC4_CH_AINNEG_12 0x000C |
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#define | ADC4_CH_AINNEG_13 0x000D |
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#define | ADC4_CH_AINNEG_14 0x000E |
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#define | ADC4_CH_AINNEG_15 0x000F |
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#define | ADC4_CH_AINNEG_16 0x0010 |
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#define | ADC4_CH_AINNEG_TEMP_P 0x0011 |
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#define | ADC4_CH_AINNEG_TEMP_N 0x0012 |
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#define | ADC4_CH_AINNEG_AV_P 0x0013 |
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#define | ADC4_CH_AINNEG_AV_N 0x0014 |
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#define | ADC4_CH_AINNEG_REF_P 0x0015 |
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#define | ADC4_CH_AINNEG_REF_N 0x0016 |
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#define | ADC4_CON_UNIPOL 0x0000 |
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#define | ADC4_CON_BIPOL 0x0001 << 12 |
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#define | ADC4_CON_REFBUF_P_EN 0x0001 << 11 |
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#define | ADC4_CON_REFBUF_N_EN 0x0001 << 10 |
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#define | ADC4_CON_AINBUF_P_EN 0x0001 << 9 |
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#define | ADC4_CON_AINBUF_N_EN 0x0001 << 8 |
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#define | ADC4_CON_BURNOUT_EN 0x0001 << 7 |
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#define | ADC4_CON_EXTREF 0x0000 |
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#define | ADC4_CON_EXTREF_SUPP 0x0001 << 4 |
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#define | ADC4_CON_EXTREF_INT 0x0002 << 4 |
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#define | ADC4_CON_EXTREF_AV 0x0003 << 4 |
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#define | ADC4_FILCON_SINC_MAP0 0x8000 |
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#define | ADC4_FILCON_ENHFILEN 0x0001 << 11 |
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#define | ADC4_FILCON_ENHFIL_SET1 0x0002 << 8 |
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#define | ADC4_FILCON_EHFFIL_SET2 0x0003 << 8 |
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#define | ADC4_FILCON_ENHFIL_SET3 0x0005 << 8 |
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#define | ADC4_FILCON_ENHFIL_SET4 0x0006 << 8 |
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#define | ADC4_FILCON_ORD_SINC5 0x0000 |
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#define | ADC4_FILCON_ORD_SINC3 0x0003 << 5 |
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#define | ADC4_FILCON_ODR_250000 0x0000 |
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#define | ADC4_FILCON_ODR_125000 0x0001 |
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#define | ADC4_FILCON_ODR_62500 0x0002 |
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#define | ADC4_FILCON_ODR_50000 0x0003 |
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#define | ADC4_FILCON_ODR_31250 0x0004 |
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#define | ADC4_FILCON_ODR_25000 0x0005 |
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#define | ADC4_FILCON_ODR_15625 0x0006 |
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#define | ADC4_FILCON_ODR_10000 0x0007 |
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#define | ADC4_FILCON_ODR_5000 0x0008 |
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#define | ADC4_FILCON_ODR_2500 0x0009 |
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#define | ADC4_FILCON_ODR_1000 0x000A |
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#define | ADC4_FILCON_ODR_500 0x000B |
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#define | ADC4_FILCON_ODR_397_5 0x000C |
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#define | ADC4_FILCON_ODR_200 0x000D |
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#define | ADC4_FILCON_ODR_100 0x000E |
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#define | ADC4_FILCON_ODR_59_92 0x000F |
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#define | ADC4_FILCON_ODR_49_96 0x0010 |
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#define | ADC4_FILCON_ODR_20 0x0011 |
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#define | ADC4_FILCON_ODR_16_66 0x0012 |
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#define | ADC4_FILCON_ODR_10 0x0013 |
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#define | ADC4_FILCON_ODR_5 0x0014 |
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