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#define | C3DHALL10_REG_DEVICE_CONFIG 0x00 |
| 3D Hall 10 register list.
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#define | C3DHALL10_REG_SENSOR_CONFIG 0x01 |
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#define | C3DHALL10_REG_SYSTEM_CONFIG 0x02 |
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#define | C3DHALL10_REG_ALERT_CONFIG 0x03 |
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#define | C3DHALL10_REG_X_THRX_CONFIG 0x04 |
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#define | C3DHALL10_REG_Y_THRX_CONFIG 0x05 |
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#define | C3DHALL10_REG_Z_THRX_CONFIG 0x06 |
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#define | C3DHALL10_REG_T_THRX_CONFIG 0x07 |
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#define | C3DHALL10_REG_CONV_STATUS 0x08 |
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#define | C3DHALL10_REG_X_CH_RESULT 0x09 |
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#define | C3DHALL10_REG_Y_CH_RESULT 0x0A |
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#define | C3DHALL10_REG_Z_CH_RESULT 0x0B |
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#define | C3DHALL10_REG_TEMP_RESULT 0x0C |
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#define | C3DHALL10_REG_AFE_STATUS 0x0D |
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#define | C3DHALL10_REG_SYS_STATUS 0x0E |
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#define | C3DHALL10_REG_TEST_CONFIG 0x0F |
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#define | C3DHALL10_REG_OSC_MONITOR 0x10 |
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#define | C3DHALL10_REG_MAG_GAIN_CONFIG 0x11 |
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#define | C3DHALL10_REG_MAG_OFFSET_CONFIG 0x12 |
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#define | C3DHALL10_REG_ANGLE_RESULT 0x13 |
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#define | C3DHALL10_REG_MAGNITUDE_RESULT 0x14 |
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#define | C3DHALL10_CONV_AVG_1X 0x0000 |
| 3D Hall 10 device config register settings.
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#define | C3DHALL10_CONV_AVG_2X 0x1000 |
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#define | C3DHALL10_CONV_AVG_4X 0x2000 |
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#define | C3DHALL10_CONV_AVG_8X 0x3000 |
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#define | C3DHALL10_CONV_AVG_16X 0x4000 |
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#define | C3DHALL10_CONV_AVG_32X 0x5000 |
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#define | C3DHALL10_CONV_AVG_BIT_MASK 0x7000 |
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#define | C3DHALL10_MAG_TEMPCO_0 0x0000 |
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#define | C3DHALL10_MAG_TEMPCO_0p12 0x0100 |
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#define | C3DHALL10_MAG_TEMPCO_0p03 0x0200 |
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#define | C3DHALL10_MAG_TEMPCO_0p2 0x0300 |
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#define | C3DHALL10_MAG_TEMPCO_BIT_MASK 0x0300 |
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#define | C3DHALL10_OPERATING_MODE_CONFIG 0x0000 |
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#define | C3DHALL10_OPERATING_MODE_STANDBY 0x0010 |
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#define | C3DHALL10_OPERATING_MODE_MEASURE 0x0020 |
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#define | C3DHALL10_OPERATING_MODE_TRIGGER 0x0030 |
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#define | C3DHALL10_OPERATING_MODE_DUTY_CYCLED 0x0040 |
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#define | C3DHALL10_OPERATING_MODE_SLEEP 0x0050 |
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#define | C3DHALL10_OPERATING_MODE_DEEP_SLEEP 0x0060 |
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#define | C3DHALL10_OPERATING_MODE_BIT_MASK 0x0070 |
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#define | C3DHALL10_T_CH_EN_DISABLE 0x0000 |
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#define | C3DHALL10_T_CH_EN_ENABLE 0x0008 |
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#define | C3DHALL10_T_CH_EN_BIT_MASK 0x0008 |
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#define | C3DHALL10_T_RATE_PER_CONV_AVG 0x0000 |
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#define | C3DHALL10_T_RATE_ONCE_PER_CONV 0x0004 |
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#define | C3DHALL10_T_RATE_BIT_MASK 0x0004 |
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#define | C3DHALL10_T_HLT_EN_DISABLE 0x0000 |
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#define | C3DHALL10_T_HLT_EN_ENABLE 0x0002 |
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#define | C3DHALL10_T_HLT_EN_BIT_MASK 0x0002 |
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#define | C3DHALL10_ANGLE_EN_NO_ANGLE 0x0000 |
| 3D Hall 10 sensor config register settings.
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#define | C3DHALL10_ANGLE_EN_XY_ANGLE 0x4000 |
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#define | C3DHALL10_ANGLE_EN_YZ_ANGLE 0x8000 |
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#define | C3DHALL10_ANGLE_EN_XZ_ANGLE 0xC000 |
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#define | C3DHALL10_ANGLE_EN_BIT_MASK 0xC000 |
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#define | C3DHALL10_SLEEPTIME_1MS 0x0000 |
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#define | C3DHALL10_SLEEPTIME_5MS 0x0400 |
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#define | C3DHALL10_SLEEPTIME_10MS 0x0800 |
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#define | C3DHALL10_SLEEPTIME_15MS 0x0C00 |
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#define | C3DHALL10_SLEEPTIME_20MS 0x1000 |
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#define | C3DHALL10_SLEEPTIME_30MS 0x1400 |
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#define | C3DHALL10_SLEEPTIME_50MS 0x1800 |
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#define | C3DHALL10_SLEEPTIME_100MS 0x1C00 |
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#define | C3DHALL10_SLEEPTIME_500MS 0x2000 |
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#define | C3DHALL10_SLEEPTIME_1000MS 0x2400 |
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#define | C3DHALL10_SLEEPTIME_BIT_MASK 0x3C00 |
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#define | C3DHALL10_MAG_CH_EN_DISABLE 0x0000 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_X 0x0040 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_Y 0x0080 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_XY 0x00C0 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_Z 0x0100 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_ZX 0x0140 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_YZ 0x0180 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_XYZ 0x01C0 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_XYX 0x0200 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_YXY 0x0240 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_YZY 0x0280 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_ZYZ 0x02C0 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_ZXZ 0x0300 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_XZX 0x0340 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_XYZYX 0x0380 |
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#define | C3DHALL10_MAG_CH_EN_ENABLE_XYZZYX 0x03C0 |
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#define | C3DHALL10_MAG_CH_EN_BIT_MASK 0x03C0 |
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#define | C3DHALL10_Z_RANGE_50mT 0x0000 |
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#define | C3DHALL10_Z_RANGE_25mT 0x0010 |
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#define | C3DHALL10_Z_RANGE_100mT 0x0020 |
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#define | C3DHALL10_Z_RANGE_BIT_MASK 0x0030 |
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#define | C3DHALL10_Y_RANGE_50mT 0x0000 |
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#define | C3DHALL10_Y_RANGE_25mT 0x0004 |
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#define | C3DHALL10_Y_RANGE_100mT 0x0008 |
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#define | C3DHALL10_Y_RANGE_BIT_MASK 0x000C |
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#define | C3DHALL10_X_RANGE_50mT 0x0000 |
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#define | C3DHALL10_X_RANGE_25mT 0x0001 |
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#define | C3DHALL10_X_RANGE_100mT 0x0002 |
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#define | C3DHALL10_X_RANGE_BIT_MASK 0x0003 |
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#define | C3DHALL10_DIAG_SEL_ALL_DP_DIAG_ALL 0x0000 |
| 3D Hall 10 system config register settings.
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#define | C3DHALL10_DIAG_SEL_EN_DP_ONLY_DIAG_ALL 0x1000 |
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#define | C3DHALL10_DIAG_SEL_ALL_DP_DIAG_SEQ 0x2000 |
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#define | C3DHALL10_DIAG_SEL_EN_DP_ONLY_DIAG_SEQ 0x3000 |
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#define | C3DHALL10_DIAG_SEL_BIT_MASK 0x3000 |
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#define | C3DHALL10_TRIGGER_MODE_SPI_CMD 0x0000 |
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#define | C3DHALL10_TRIGGER_MODE_CS_PULSE 0x0200 |
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#define | C3DHALL10_TRIGGER_MODE_ALERT_PULSE 0x0400 |
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#define | C3DHALL10_TRIGGER_MODE_BIT_MASK 0x0600 |
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#define | C3DHALL10_DATA_TYPE_32BIT_REG 0x0000 |
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#define | C3DHALL10_DATA_TYPE_12BIT_XY_DATA 0x0040 |
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#define | C3DHALL10_DATA_TYPE_12BIT_XZ_DATA 0x0080 |
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#define | C3DHALL10_DATA_TYPE_12BIT_ZY_DATA 0x00C0 |
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#define | C3DHALL10_DATA_TYPE_12BIT_XT_DATA 0x0100 |
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#define | C3DHALL10_DATA_TYPE_12BIT_YT_DATA 0x0140 |
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#define | C3DHALL10_DATA_TYPE_12BIT_ZT_DATA 0x0180 |
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#define | C3DHALL10_DATA_TYPE_12BIT_AM_DATA 0x01C0 |
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#define | C3DHALL10_DATA_TYPE_BIT_MASK 0x01C0 |
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#define | C3DHALL10_DIAG_EN_DISABLE 0x0000 |
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#define | C3DHALL10_DIAG_EN_ENABLE 0x0020 |
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#define | C3DHALL10_DIAG_EN_BIT_MASK 0x0020 |
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#define | C3DHALL10_Z_HLT_EN_DISABLE 0x0000 |
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#define | C3DHALL10_Z_HLT_EN_ENABLE 0x0004 |
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#define | C3DHALL10_Z_HLT_EN_BIT_MASK 0x0004 |
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#define | C3DHALL10_Y_HLT_EN_DISABLE 0x0000 |
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#define | C3DHALL10_Y_HLT_EN_ENABLE 0x0002 |
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#define | C3DHALL10_Y_HLT_EN_BIT_MASK 0x0002 |
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#define | C3DHALL10_X_HLT_EN_DISABLE 0x0000 |
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#define | C3DHALL10_X_HLT_EN_ENABLE 0x0001 |
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#define | C3DHALL10_X_HLT_EN_BIT_MASK 0x0001 |
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#define | C3DHALL10_ALERT_LATCH_DISABLE 0x0000 |
| 3D Hall 10 alert config register settings.
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#define | C3DHALL10_ALERT_LATCH_ENABLE 0x2000 |
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#define | C3DHALL10_ALERT_LATCH_BIT_MASK 0x2000 |
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#define | C3DHALL10_ALERT_MODE_INTERRUPT 0x0000 |
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#define | C3DHALL10_ALERT_MODE_SWITCH 0x1000 |
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#define | C3DHALL10_ALERT_MODE_BIT_MASK 0x1000 |
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#define | C3DHALL10_STATUS_ALRT_AFE_SYS_NO_ASSERT 0x0000 |
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#define | C3DHALL10_STATUS_ALRT_AFE_SYS_ASSERT 0x0800 |
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#define | C3DHALL10_STATUS_ALRT_BIT_MASK 0x0800 |
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#define | C3DHALL10_RSLT_ALRT_NO_CONV_COMPLETE 0x0000 |
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#define | C3DHALL10_RSLT_ALRT_CONV_COMPLETE 0x0100 |
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#define | C3DHALL10_RSLT_ALRT_BIT_MASK 0x0100 |
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#define | C3DHALL10_THRX_COUNT_1_CONV 0x0000 |
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#define | C3DHALL10_THRX_COUNT_2_CONV 0x0010 |
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#define | C3DHALL10_THRX_COUNT_3_CONV 0x0020 |
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#define | C3DHALL10_THRX_COUNT_4_CONV 0x0030 |
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#define | C3DHALL10_THRX_COUNT_BIT_MASK 0x0030 |
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#define | C3DHALL10_T_THRX_ALRT_NO_CROSSED 0x0000 |
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#define | C3DHALL10_T_THRX_ALRT_CROSSED 0x0008 |
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#define | C3DHALL10_T_THRX_ALRT_BIT_MASK 0x0008 |
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#define | C3DHALL10_Z_THRX_ALRT_NO_CROSSED 0x0000 |
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#define | C3DHALL10_Z_THRX_ALRT_CROSSED 0x0004 |
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#define | C3DHALL10_Z_THRX_ALRT_BIT_MASK 0x0004 |
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#define | C3DHALL10_Y_THRX_ALRT_NO_CROSSED 0x0000 |
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#define | C3DHALL10_Y_THRX_ALRT_CROSSED 0x0002 |
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#define | C3DHALL10_Y_THRX_ALRT_BIT_MASK 0x0002 |
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#define | C3DHALL10_X_THRX_ALRT_NO_CROSSED 0x0000 |
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#define | C3DHALL10_X_THRX_ALRT_CROSSED 0x0001 |
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#define | C3DHALL10_X_THRX_ALRT_BIT_MASK 0x0001 |
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#define | C3DHALL10_GAIN_SELECTION_NO_AXIS 0x0000 |
| 3D Hall 10 mag gain config register settings.
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#define | C3DHALL10_GAIN_SELECTION_X_AXIS 0x4000 |
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#define | C3DHALL10_GAIN_SELECTION_Y_AXIS 0x8000 |
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#define | C3DHALL10_GAIN_SELECTION_Z_AXIS 0xC000 |
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#define | C3DHALL10_GAIN_SELECTION_BIT_MASK 0xC000 |
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#define | C3DHALL10_GAIN_VALUE_BIT_MASK 0x07FF |
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#define | C3DHALL10_CONV_STATUS_RDY 0x2000 |
| 3D Hall 10 conv status register settings.
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#define | C3DHALL10_CONV_STATUS_A 0x1000 |
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#define | C3DHALL10_CONV_STATUS_T 0x0800 |
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#define | C3DHALL10_CONV_STATUS_Z 0x0400 |
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#define | C3DHALL10_CONV_STATUS_Y 0x0200 |
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#define | C3DHALL10_CONV_STATUS_X 0x0100 |
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#define | C3DHALL10_CONV_STATUS_SET_COUNT 0x0070 |
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#define | C3DHALL10_CONV_STATUS_ALRT_STATUS 0x0003 |
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#define | C3DHALL10_ANGLE_RESOLUTION 16.0 |
| 3D Hall 10 calculation values.
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#define | C3DHALL10_TEMP_SENS_T0 25.0 |
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#define | C3DHALL10_TEMP_ADC_T0 17522 |
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#define | C3DHALL10_TEMP_ADC_RESOLUTION 60.0 |
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#define | C3DHALL10_XYZ_RESOLUTION 32768.0 |
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#define | C3DHALL10_SPI_READ_MASK 0x80 |
| 3D Hall 10 SPI read/write bit mask.
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#define | C3DHALL10_SPI_WRITE_MASK 0x7F |
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#define | C3DHALL10_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
| Data sample selection.
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#define | C3DHALL10_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
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#define | C3DHALL10_MAP_MIKROBUS(cfg, mikrobus) |
| MikroBUS pin mapping.
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