accel5/html/accel5_8h_source.html

/*

 * MikroSDK - MikroE Software Development Kit

 * Copyright (c) 2019, MikroElektronika - www.mikroe.com

 * All rights reserved.

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

 * SOFTWARE.

 */


// ----------------------------------------------------------------------------


#ifndef ACCEL5_H

#define ACCEL5_H


#ifdef PREINIT_SUPPORTED

#include "preinit.h"

#endif


#ifdef MikroCCoreVersion

    #if MikroCCoreVersion >= 1

        #include "delays.h"

    #endif

#endif


#include "drv_digital_out.h"

#include "drv_digital_in.h"

#include "drv_i2c_master.h"


// -------------------------------------------------------------- PUBLIC MACROS


#define ACCEL5_MAP_MIKROBUS( cfg, mikrobus ) \

  cfg.scl = MIKROBUS( mikrobus, MIKROBUS_SCL ); \

  cfg.sda = MIKROBUS( mikrobus, MIKROBUS_SDA ); \

  cfg.it2 = MIKROBUS( mikrobus, MIKROBUS_PWM ); \

  cfg.it1 = MIKROBUS( mikrobus, MIKROBUS_INT );


#define ACCEL5_OK            0

#define ACCEL5_INIT_ERROR  (-1)

#define ACCEL5_CHIP_ID  0x90

#define ACCEL5_REG_CHIP_ID             0x00

#define ACCEL5_REG_ERR_REG             0x02

#define ACCEL5_REG_STATUS              0x03

#define ACCEL5_REG_ACC_X_LSB           0x04

#define ACCEL5_REG_ACC_X_MSB           0x05

#define ACCEL5_REG_ACC_Y_LSB           0x06

#define ACCEL5_REG_ACC_Y_MSB           0x07

#define ACCEL5_REG_ACC_Z_LSB           0x08

#define ACCEL5_REG_ACC_Z_MSB           0x09

#define ACCEL5_REG_SENSOR_TIME_0       0x0A

#define ACCEL5_REG_SENSOR_TIME_1       0x0B

#define ACCEL5_REG_SENSOR_TIME_2       0x0C

#define ACCEL5_REG_EVENT               0x0D

#define ACCEL5_REG_INT_STATUS_0        0x0E

#define ACCEL5_REG_INT_STATUS_1        0x0F

#define ACCEL5_REG_INT_STATUS_2        0x10

#define ACCEL5_REG_TEMPERATURE         0x11

#define ACCEL5_REG_FIFO_LENGTH_0       0x12

#define ACCEL5_REG_FIFO_LENGTH_1       0x13

#define ACCEL5_REG_FIFO_DATA           0x14

#define ACCEL5_REG_STEP_CNT_0          0x15

#define ACCEL5_REG_STEP_CNT_1          0x16

#define ACCEL5_REG_STEP_CNT_2          0x17

#define ACCEL5_REG_STEP_STATUS         0x18

#define ACCEL5_REG_ACC_CONGIG_0        0x19

#define ACCEL5_REG_ACC_CONGIG_1        0x1A

#define ACCEL5_REG_ACC_CONGIG_2        0x1B

#define ACCEL5_REG_INT_CONFIG_0        0x1F

#define ACCEL5_REG_INT_CONFIG_1        0x20

#define ACCEL5_REG_INT1_MAP            0x21

#define ACCEL5_REG_INT2_MAP            0x22

#define ACCEL5_REG_INT12_MAP           0x23

#define ACCEL5_REG_INT12_IO_CTRL       0x24

#define ACCEL5_REG_FIFO_CONFIG_0       0x26

#define ACCEL5_REG_FIFO_CONFIG_1       0x27

#define ACCEL5_REG_FIFO_CONFIG_2       0x28

#define ACCEL5_REG_FIFO_PWR_CONFIG     0x29

#define ACCEL5_REG_AUTO_LOW_POW_0      0x2A

#define ACCEL5_REG_AUTO_LOW_POW_1      0x2B

#define ACCEL5_REG_AUTO_WAKEUP_0       0x2C

#define ACCEL5_REG_AUTO_WAKEUP_1       0x2D

#define ACCEL5_REG_WAKEUP_CONFIG_0     0x2F

#define ACCEL5_REG_WAKEUP_CONFIG_1     0x30

#define ACCEL5_REG_WAKEUP_CONFIG_2     0x31

#define ACCEL5_REG_WAKEUP_CONFIG_3     0x32

#define ACCEL5_REG_WAKEUP_CONFIG_4     0x33

#define ACCEL5_REG_ORIENTCH_CONFIG_0   0x35

#define ACCEL5_REG_ORIENTCH_CONFIG_1   0x36

#define ACCEL5_REG_ORIENTCH_CONFIG_2   0x37

#define ACCEL5_REG_ORIENTCH_CONFIG_3   0x38

#define ACCEL5_REG_ORIENTCH_CONFIG_4   0x39

#define ACCEL5_REG_ORIENTCH_CONFIG_5   0x3A

#define ACCEL5_REG_ORIENTCH_CONFIG_6   0x3B

#define ACCEL5_REG_ORIENTCH_CONFIG_7   0x3C

#define ACCEL5_REG_ORIENTCH_CONFIG_8   0x3D

#define ACCEL5_REG_ORIENTCH_CONFIG_9   0x3E

#define ACCEL5_REG_GEN1_INT_CONFIG_0   0x3F

#define ACCEL5_REG_GEN1_INT_CONFIG_1   0x40

#define ACCEL5_REG_GEN1_INT_CONFIG_2   0x41

#define ACCEL5_REG_GEN1_INT_CONFIG_3   0x42

#define ACCEL5_REG_GEN1_INT_CONFIG_31  0x43

#define ACCEL5_REG_GEN1_INT_CONFIG_4   0x44

#define ACCEL5_REG_GEN1_INT_CONFIG_5   0x45

#define ACCEL5_REG_GEN1_INT_CONFIG_6   0x46

#define ACCEL5_REG_GEN1_INT_CONFIG_7   0x47

#define ACCEL5_REG_GEN1_INT_CONFIG_8   0x48

#define ACCEL5_REG_GEN1_INT_CONFIG_9   0x49

#define ACCEL5_REG_GEN2_INT_CONFIG_0   0x4A

#define ACCEL5_REG_GEN2_INT_CONFIG_1   0x4B

#define ACCEL5_REG_GEN2_INT_CONFIG_2   0x4C

#define ACCEL5_REG_GEN2_INT_CONFIG_3   0x4D

#define ACCEL5_REG_GEN2_INT_CONFIG_31  0x4E

#define ACCEL5_REG_GEN2_INT_CONFIG_4   0x4F

#define ACCEL5_REG_GEN2_INT_CONFIG_5   0x50

#define ACCEL5_REG_GEN2_INT_CONFIG_6   0x51

#define ACCEL5_REG_GEN2_INT_CONFIG_7   0x52

#define ACCEL5_REG_GEN2_INT_CONFIG_8   0x53

#define ACCEL5_REG_GEN2_INT_CONFIG_9   0x54

#define ACCEL5_REG_ACTCH_CONFIG_0      0x55

#define ACCEL5_REG_ACTCH_CONFIG_1      0x56

#define ACCEL5_REG_TAP_CONFIG_0        0x57

#define ACCEL5_REG_TAP_CONFIG_1        0x58

#define ACCEL5_REG_STEP_CNT_CONFIG_0   0x59

#define ACCEL5_REG_STEP_CNT_CONFIG_1   0x5A

#define ACCEL5_REG_STEP_CNT_CONFIG_2   0x5B

#define ACCEL5_REG_STEP_CNT_CONFIG_3   0x5C

#define ACCEL5_REG_STEP_CNT_CONFIG_4   0x5D

#define ACCEL5_REG_STEP_CNT_CONFIG_5   0x5E

#define ACCEL5_REG_STEP_CNT_CONFIG_6   0x5F

#define ACCEL5_REG_STEP_CNT_CONFIG_7   0x60

#define ACCEL5_REG_STEP_CNT_CONFIG_8   0x61

#define ACCEL5_REG_STEP_CNT_CONFIG_9   0x62

#define ACCEL5_REG_STEP_CNT_CONFIG_10  0x63

#define ACCEL5_REG_STEP_CNT_CONFIG_11  0x64

#define ACCEL5_REG_STEP_CNT_CONFIG_12  0x65

#define ACCEL5_REG_STEP_CNT_CONFIG_13  0x66

#define ACCEL5_REG_STEP_CNT_CONFIG_14  0x67

#define ACCEL5_REG_STEP_CNT_CONFIG_15  0x68

#define ACCEL5_REG_STEP_CNT_CONFIG_16  0x69

#define ACCEL5_REG_STEP_CNT_CONFIG_17  0x6A

#define ACCEL5_REG_STEP_CNT_CONFIG_18  0x6B

#define ACCEL5_REG_STEP_CNT_CONFIG_19  0x6C

#define ACCEL5_REG_STEP_CNT_CONFIG_20  0x6D

#define ACCEL5_REG_STEP_CNT_CONFIG_21  0x6E

#define ACCEL5_REG_STEP_CNT_CONFIG_22  0x6F

#define ACCEL5_REG_STEP_CNT_CONFIG_23  0x70

#define ACCEL5_REG_STEP_CNT_CONFIG_24  0x71

#define ACCEL5_REG_IF_CONFIG           0x7C

#define ACCEL5_REG_SELF_TEST           0x7D

#define ACCEL5_REG_CMD                 0x7E

#define ACCEL5_ERROR_CMD               0x02

#define  ACCEL5_STATUS_DATA_RDY_START            0x80

#define  ACCEL5_STATUS_RDY_CMD                   0x10

#define  ACCEL5_STATUS_NORMAL_MODE               0x04

#define  ACCEL5_STATUS_LOW_POWER_MODE            0x02

#define  ACCEL5_STATUS_SLEEP_MODE                0x04

#define  ACCEL5_STATUS_INT_ACTIVE_TRIGGERED      0x01

#define  ACCEL5_STATUS_INT_ACTIVE_NOT_TRIGGERED  0x00

#define ACCEL5_EVENT_POR_DETECTED       0x01

#define ACCEL5_INT_STATUS_0_DATA_RDY_STATUS       0x80

#define ACCEL5_INT_STATUS_0_FIFO_WATERMARK        0x40

#define ACCEL5_INT_STATUS_0_FIFO_FULL             0x20

#define ACCEL5_INT_STATUS_0_IENG_OVERRUN_STATUS   0x10

#define ACCEL5_INT_STATUS_0_GEN2_INT_STATUS       0x08

#define ACCEL5_INT_STATUS_0_GEN1_INT_STATUS       0x04

#define ACCEL5_INT_STATUS_0_ORIENTCH_INT_STATUS   0x02

#define ACCEL5_INT_STATUS_0_WAKEUP_INT_STATUS     0x01

#define ACCEL5_INT_STATUS_1_IENG_OVERRUN_STATUS   0x10

#define ACCEL5_INT_STATUS_1_DOUBLE_TAP            0x08

#define ACCEL5_INT_STATUS_1_SINGLE_TAP            0x04

#define ACCEL5_INT_STATUS_1_STEP_NO_SET           0x00

#define ACCEL5_INT_STATUS_1_STEP_SET              0x01

#define ACCEL5_INT_STATUS_1_STEP_DETECT           0x02

#define ACCEL5_INT_STATUS_1_STEP_NO_USED          0x03

#define ACCEL5_INT_STATUS_2_IENG_OVERRUN_STATUS   0x10

#define ACCEL5_INT_STATUS_2_ACTCH_Z_INIT_STATUS   0x04

#define ACCEL5_INT_STATUS_2_ACTCH_Y_INIT_STATUS   0x02

#define ACCEL5_INT_STATUS_2_ACTCH_X_INIT_STATUS   0x01

#define ACCEL5_STEP_STATUS_WALKING                0x01

#define ACCEL5_STEP_STATUS_RUNNING                0x02

#define ACCEL5_STEP_STATUS_NO_WALK_RUN            0x00

#define ACCEL5_CFG_0_FILT1_BW_LOW_0_2X_ODR        0x80

#define ACCEL5_CFG_0_FILT1_BW_HIGH_0_4X_ODR       0x00

#define ACCEL5_CFG_0_SLEEP_MODE                   0x00

#define ACCEL5_CFG_0_LOW_POWER_MODE               0x01

#define ACCEL5_CFG_0_NORMAL_MODE                  0x02

#define ACCEL5_CFG_1_ACC_RANGE_2g                 0x00

#define ACCEL5_CFG_1_ACC_RANGE_4g                 0x40

#define ACCEL5_CFG_1_ACC_RANGE_8g                 0x80

#define ACCEL5_CFG_1_ACC_RANGE_16g                0xC0

#define ACCEL5_CFG_1_OSR_LOW_POWER                0x00

#define ACCEL5_CFG_1_OSR_HIGH_POWER               0x30

#define ACCEL5_CFG_1_ODR_12p5_5                   0x00

#define ACCEL5_CFG_1_ODR_12p5_4                   0x01

#define ACCEL5_CFG_1_ODR_12p5_3                   0x02

#define ACCEL5_CFG_1_ODR_12p5_2                   0x03

#define ACCEL5_CFG_1_ODR_12p5_1                   0x04

#define ACCEL5_CFG_1_ODR_12p5                     0x05

#define ACCEL5_CFG_1_ODR_25                       0x06

#define ACCEL5_CFG_1_ODR_50                       0x07

#define ACCEL5_CFG_1_ODR_100                      0x08

#define ACCEL5_CFG_1_ODR_200                      0x09

#define ACCEL5_CFG_1_ODR_400                      0x0A

#define ACCEL5_CFG_1_ODR_800                      0x0B

#define ACCEL5_CFG_1_ODR_800_1                    0x0C

#define ACCEL5_CFG_1_ODR_800_2                    0x0D

#define ACCEL5_CFG_1_ODR_800_3                    0x0E

#define ACCEL5_CFG_1_ODR_800_4                    0x0F

#define ACCEL5_CFG_2_DATA_SCR_ACC_FILT_1          0x00

#define ACCEL5_CFG_2_DATA_SCR_ACC_FILT_2          0x04

#define ACCEL5_CFG_2_DATA_SCR_ACC_FILT_LP         0x08

#define ACCEL5_INT_CFG_0_DATA_RDY                 0x80

#define ACCEL5_INT_CFG_0_FIFO_WATERMARK           0x40

#define ACCEL5_INT_CFG_0_FIFO_FULL                0x20

#define ACCEL5_INT_CFG_0_GEN2_INT_STATUS          0x08

#define ACCEL5_INT_CFG_0_GEN1_INT_STATUS          0x04

#define ACCEL5_INT_CFG_0_ORIENTCH_INT             0x02

#define ACCEL5_INT_CFG_1_LATCH_MODE_NOLATCH    0x00

#define ACCEL5_INT_CFG_1_LATCH_MODE_LATCHING   0x80

#define ACCEL5_INT_CFG_1_ACTCH_INT_ENABLE      0x10

#define ACCEL5_INT_CFG_1_DOUBLE_TAP_ENABLE     0x08

#define ACCEL5_INT_CFG_1_SINGLE_TAP_ENABLE     0x04

#define ACCEL5_INT_CFG_1_STEP_INT_ENABLE       0x01

#define ACCEL5_INT1_MAP_DATA_RDY_STATUS        0x80

#define ACCEL5_INT1_MAP_FIFO_WATERMARK         0x40

#define ACCEL5_INT1_MAP_FIFO_FULL              0x20

#define ACCEL5_INT1_MAP_IENG_OVERRUN_STATUS    0x10

#define ACCEL5_INT1_MAP_GEN2_INT_STATUS        0x08

#define ACCEL5_INT1_MAP_GEN1_INT_STATUS        0x04

#define ACCEL5_INT1_MAP_ORIENTCH_INT_STATUS    0x02

#define ACCEL5_INT1_MAP_WAKEUP_INT_STATUS      0x01

#define ACCEL5_INT2_MAP_DATA_RDY_STATUS        0x80

#define ACCEL5_INT2_MAP_FIFO_WATERMARK         0x40

#define ACCEL5_INT2_MAP_FIFO_FULL              0x20

#define ACCEL5_INT2_MAP_IENG_OVERRUN_STATUS    0x10

#define ACCEL5_INT2_MAP_GEN2_INT_STATUS        0x08

#define ACCEL5_INT2_MAP_GEN1_INT_STATUS        0x04

#define ACCEL5_INT2_MAP_ORIENTCH_INT_STATUS    0x02

#define ACCEL5_INT2_MAP_WAKEUP_INT_STATUS      0x01

#define ACCEL5_INT12_MAP_ACTCH_INT2   0x80

#define ACCEL5_INT12_MAP_TAP_INT2     0x40

#define ACCEL5_INT12_MAP_STEP_INT2    0x10

#define ACCEL5_INT12_MAP_ACTCH_INT1   0x08

#define ACCEL5_INT12_MAP_TAP_INT1     0x04

#define ACCEL5_INT12_MAP_STEP_INT1    0x01

#define ACCEL5_INT12_CTRL_INT2_OPEN_DRAIN     0x40

#define ACCEL5_INT12_CTRL_INT1_OPEN_DRAIN     0x04

#define ACCEL5_INT12_CTRL_INT2_HIGH_ACTIVE    0x20

#define ACCEL5_INT12_CTRL_INT1_HIGH_ACTIVE    0x02

#define ACCEL5_FIFO_CFG0_Z_AXIS_ENABLE        0x80

#define ACCEL5_FIFO_CFG0_Y_AXIS_ENABLE        0x40

#define ACCEL5_FIFO_CFG0_X_AXIS_ENABLE        0x20

#define ACCEL5_FIFO_CFG0_8bit_ENABLE          0x10

#define ACCEL5_FIFO_CFG0_DATA_SRC_ENABLE      0x08

#define ACCEL5_FIFO_CFG0_TIME_ENABLE          0x04

#define ACCEL5_FIFO_CFG0_STOP_NO_FULL_ENABLE  0x02

#define ACCEL5_FIFO_CFG0_AUTO_FLUSH_ENABLE    0x01

#define ACCEL5_FIFO_AUTO_IP_TIMEOUT_0         0x00

#define ACCEL5_FIFO_AUTO_IP_TIMEOUT_1         0x04

#define ACCEL5_FIFO_AUTO_IP_TIMEOUT_2         0x08

#define ACCEL5_FIFO_AUTO_IP_TIMEOUT_3         0x0C

#define ACCEL5_FIFO_AUTO_TRIG_GEN1_INT        0x02

#define ACCEL5_FIFO_AUTO_TRIG_DATA_RDY        0x01

#define ACCEL5_WAKEUP_TIMEOUT_ENABLE          0x04

#define ACCEL5_WAKEUP_ENABLE                  0x02

#define ACCEL5_WAKEUP_Z_AXIS_ENABLE           0x80

#define ACCEL5_WAKEUP_Y_AXIS_ENABLE           0x40

#define ACCEL5_WAKEUP_X_AXIS_ENABLE           0x20

#define ACCEL5_WAKEUP_NUMBER_OF_SIMPLE        0x10

#define ACCEL5_WAKEUP_REFU_MANUAL             0x00

#define ACCEL5_WAKEUP_REFU_ONETIME            0x01

#define ACCEL5_WAKEUP_REFU_EVERYTIME          0x02

#define ACCEL5_ORIENT_Z_AXIS_ENABLE           0x80

#define ACCEL5_ORIENT_Y_AXIS_ENABLE           0x40

#define ACCEL5_ORIENT_X_AXIS_ENABLE           0x20

#define ACCEL5_ORIENT_DATA_SRC_ENABLE         0x10

#define ACCEL5_ORIENT_REFU_MANUAL             0x00

#define ACCEL5_ORIENT_REFU_ONETIME_2          0x04

#define ACCEL5_ORIENT_REFU_ONETIME_IP         0x08

#define ACCEL5_ORIENT_STABILITY_INACTIVE      0x00

#define ACCEL5_ORIENT_STABILITY_ENABLED_1     0x01

#define ACCEL5_ORIENT_STABILITY_ENABLED_2     0x02

#define ACCEL5_GEN1_CFG0_ACT_Z_ENABLE         0x80

#define ACCEL5_GEN1_CFG0_ACT_Y_ENABLE         0x40

#define ACCEL5_GEN1_CFG0_ACT_X_ENABLE         0x20

#define ACCEL5_GEN1_CFG0_DATA_ENABLE          0x10

#define ACCEL5_GEN1_CFG0_REFU_MANUAL          0x00

#define ACCEL5_GEN1_CFG0_REFU_ONETIME         0x04

#define ACCEL5_GEN1_CFG0_REFU_EVERYTIME       0x08

#define ACCEL5_GEN1_CFG0_HYST_24mg            0x01

#define ACCEL5_GEN1_CFG0_HYST_48mg            0x02

#define ACCEL5_GEN1_CFG0_HYST_96mg            0x03

#define ACCEL5_GEN1_CFG0_HYST_NO_ACTIVE       0x00

#define ACCEL5_GEN1_CFG1_CRITERION_SEL_ACTIVE      0x20

#define ACCEL5_GEN1_CFG1_CRITERION_SEL_INACTIVE    0x00

#define ACCEL5_GEN1_CFG1_COMB_SEL_AND              0x10

#define ACCEL5_GEN1_CFG1_COMB_SEL_OR               0x00

#define ACCEL5_GEN2_CFG0_ACT_Z_ENABLE              0x80

#define ACCEL5_GEN2_CFG0_ACT_Y_ENABLE              0x40

#define ACCEL5_GEN2_CFG0_ACT_X_ENABLE              0x20

#define ACCEL5_GEN2_CFG0_DATA_ENABLE               0x10

#define ACCEL5_GEN2_CFG0_REFU_MANUAL               0x00

#define ACCEL5_GEN2_CFG0_REFU_ONETIME              0x04

#define ACCEL5_GEN2_CFG0_REFU_EVERYTIME            0x08

#define ACCEL5_GEN2_CFG0_HYST_24mg                 0x01

#define ACCEL5_GEN2_CFG0_HYST_48mg                 0x02

#define ACCEL5_GEN2_CFG0_HYST_96mg                 0x03

#define ACCEL5_GEN2_CFG0_HYST_NO_ACTIVE            0x00

#define ACCEL5_GEN2_CFG1_CRITERION_SEL_ACTIVE      0x20

#define ACCEL5_GEN2_CFG1_CRITERION_SEL_INACTIVE    0x00

#define ACCEL5_GEN2_CFG1_COMB_SEL_AND              0x10

#define ACCEL5_GEN2_CFG1_COMB_SEL_OR               0x00

#define ACCEL5_ACTCH_CFG0_Z_AXIS_ENABLE            0x80

#define ACCEL5_ACTCH_CFG0_Y_AXIS_ENABLE            0x40

#define ACCEL5_ACTCH_CFG0_X_AXIS_ENABLE            0x20

#define ACCEL5_ACTCH_CFG0_DATA_ENABLE              0x10

#define ACCEL5_ACTCH_CFG0_NPTS_POINT_32            0x00

#define ACCEL5_ACTCH_CFG0_NPTS_POINT_64            0x01

#define ACCEL5_ACTCH_CFG0_NPTS_POINT_128           0x02

#define ACCEL5_ACTCH_CFG0_NPTS_POINT_256           0x03

#define ACCEL5_ACTCH_CFG0_NPTS_POINT_512           0x04

#define ACCEL5_TAP_CFG0_USE_Z_AXIS                 0x00

#define ACCEL5_TAP_CFG0_USE_Y_AXIS                 0x01

#define ACCEL5_TAP_CFG0_USE_X_AXIS                 0x02

#define ACCEL5_TAP_CFG0_TAP_SEL_HIGH               0x00

#define ACCEL5_TAP_CFG0_TAP_SEL_LOW                0x10

#define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_4          0x00

#define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_8          0x10

#define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_12         0x20

#define ACCEL5_TAP_CFG1_QUIET_DT_SAMPLE_16         0x30

#define ACCEL5_TAP_CFG1_QUIET_SAMPLE_60            0x00

#define ACCEL5_TAP_CFG1_QUIET_SAMPLE_80            0x04

#define ACCEL5_TAP_CFG1_QUIET_SAMPLE_100           0x08

#define ACCEL5_TAP_CFG1_QUIET_SAMPLE_120           0x0C

#define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_6           0x00

#define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_9           0x01

#define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_12          0x02

#define ACCEL5_TAP_CFG1_TICS_TH_SAMPLE_18          0x03

#define ACCEL5_IF_CONFIG_SPI_4_WIRE                0x00

#define ACCEL5_IF_CONFIG_SPI_3_WIRE                0x01

#define ACCEL5_TEST_SIGN_ENABLE                    0x08

#define ACCEL5_TEST_Z_AXIS_ENABLE                  0x04

#define ACCEL5_TEST_Y_AXIS_ENABLE                  0x02

#define ACCEL5_TEST_X_AXIS_ENABLE                  0x01

#define ACCEL5_CMD_FIFO_FLUSH                      0xB0

#define ACCEL5_CMD_STEP_CNT_CLEAR                  0xB1

#define ACCEL5_CMD_SOFTWARE_RESET                  0xB6

#define ACCEL5_X_AXIS                              0x04

#define ACCEL5_Y_AXIS                              0x06

#define ACCEL5_Z_AXIS                              0x08

#define DEVICE_ERROR                               0x01

#define DEVICE_OK                                  0x00

 // End group macro

// --------------------------------------------------------------- PUBLIC TYPES


typedef struct

{


    // Input pins


    digital_in_t it2;

    digital_in_t it1;


    // Modules


    i2c_master_t i2c;


    // ctx variable


    uint8_t slave_address;


} accel5_t;


typedef struct

{

    // Communication gpio pins


    pin_name_t scl;

    pin_name_t sda;


    // Additional gpio pins


    pin_name_t it2;

    pin_name_t it1;


    // static variable


    uint32_t i2c_speed;

    uint8_t i2c_address;


} accel5_cfg_t;


 // End types group


// ----------------------------------------------- PUBLIC FUNCTION DECLARATIONS


#ifdef __cplusplus

extern "C"{

#endif


void accel5_cfg_setup ( accel5_cfg_t *cfg );


err_t accel5_init ( accel5_t *ctx, accel5_cfg_t *cfg );


err_t accel5_generic_write ( accel5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );


err_t accel5_generic_read ( accel5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len );


void accel5_default_cfg ( accel5_t *ctx, uint8_t mode, uint8_t range );


void accel5_write_byte ( accel5_t *ctx, uint8_t reg, uint8_t reg_data );


uint8_t accel5_read_byte ( accel5_t *ctx, uint8_t reg );


uint16_t accel5_read_data ( accel5_t *ctx, uint8_t reg );


int16_t accel5_get_axis ( accel5_t *ctx, uint8_t axis );


uint32_t accel5_sensor_time ( accel5_t *ctx );


float accel5_get_temperature ( accel5_t *ctx );


void accel5_soft_reset ( accel5_t *ctx );


#ifdef __cplusplus

}

#endif

#endif  // ACCEL5_H


 // End public_function group

 // End click Driver group


// ------------------------------------------------------------------------ END

accel5_default_cfg
void accel5_default_cfg(accel5_t *ctx, uint8_t mode, uint8_t range)
Click Default Configuration function..

accel5_sensor_time
uint32_t accel5_sensor_time(accel5_t *ctx)
Functions for initialize the chip.

accel5_init
err_t accel5_init(accel5_t *ctx, accel5_cfg_t *cfg)
Initialization function.

accel5_get_axis
int16_t accel5_get_axis(accel5_t *ctx, uint8_t axis)
Functions for read axis data.

accel5_generic_read
err_t accel5_generic_read(accel5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic read function.

accel5_read_data
uint16_t accel5_read_data(accel5_t *ctx, uint8_t reg)
Functions for read data from register.

accel5_read_byte
uint8_t accel5_read_byte(accel5_t *ctx, uint8_t reg)
Functions for read byte from register.

accel5_get_temperature
float accel5_get_temperature(accel5_t *ctx)
Functions for read temperature.

accel5_write_byte
void accel5_write_byte(accel5_t *ctx, uint8_t reg, uint8_t reg_data)
Functions for write one byte in register.

accel5_cfg_setup
void accel5_cfg_setup(accel5_cfg_t *cfg)
Config Object Initialization function.

accel5_generic_write
err_t accel5_generic_write(accel5_t *ctx, uint8_t reg, uint8_t *data_buf, uint8_t len)
Generic write function.

accel5_soft_reset
void accel5_soft_reset(accel5_t *ctx)
Functions for software reset.

accel5_cfg_t
Click configuration structure definition.
Definition accel5.h:632

accel5_cfg_t::it2
pin_name_t it2
Definition accel5.h:640

accel5_cfg_t::i2c_speed
uint32_t i2c_speed
Definition accel5.h:645

accel5_cfg_t::it1
pin_name_t it1
Definition accel5.h:641

accel5_cfg_t::scl
pin_name_t scl
Definition accel5.h:635

accel5_cfg_t::sda
pin_name_t sda
Definition accel5.h:636

accel5_cfg_t::i2c_address
uint8_t i2c_address
Definition accel5.h:646

accel5_t
Click ctx object definition.
Definition accel5.h:611

accel5_t::it2
digital_in_t it2
Definition accel5.h:615

accel5_t::i2c
i2c_master_t i2c
Definition accel5.h:620

accel5_t::slave_address
uint8_t slave_address
Definition accel5.h:624

accel5_t::it1
digital_in_t it1
Definition accel5.h:616