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#define | C9DOF2_MAP_MIKROBUS(cfg, mikrobus) |
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#define | C9DOF2_RETVAL uint8_t |
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#define | C9DOF2_OK 0x00 |
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#define | C9DOF2_INIT_ERROR 0xFF |
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#define | C9DOF2_AK09916_ADR 0x0C |
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#define | C9DOF2_WHO_AM_I_AK09916 0x01 |
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#define | C9DOF2_AK09916_ST1 0x10 |
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#define | C9DOF2_AK09916_XOUT_L 0x11 |
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#define | C9DOF2_AK09916_XOUT_H 0x12 |
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#define | C9DOF2_AK09916_YOUT_L 0x13 |
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#define | C9DOF2_AK09916_YOUT_H 0x14 |
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#define | C9DOF2_AK09916_ZOUT_L 0x15 |
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#define | C9DOF2_AK09916_ZOUT_H 0x16 |
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#define | C9DOF2_AK09916_ST2 0x18 |
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#define | C9DOF2_AK09916_CNTL 0x30 |
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#define | C9DOF2_AK09916_CNTL2 0x31 |
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#define | C9DOF2_WHO_AM_I_ICM20948 0x00 |
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#define | C9DOF2_USER_CTRL 0x03 |
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#define | C9DOF2_LP_CCFG 0x05 |
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#define | C9DOF2_PWR_MGMT_1 0x06 |
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#define | C9DOF2_PWR_MGMT_2 0x07 |
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#define | C9DOF2_INT_PIN_CFG 0x0F |
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#define | C9DOF2_INT_EN 0x10 |
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#define | C9DOF2_INT_EN_1 0x11 |
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#define | C9DOF2_INT_EN_2 0x12 |
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#define | C9DOF2_INT_EN_3 0x13 |
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#define | C9DOF2_I2C_MST_STAT 0x17 |
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#define | C9DOF2_INT_STAT 0x19 |
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#define | C9DOF2_INT_STAT_1 0x1A |
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#define | C9DOF2_INT_STAT_2 0x1B |
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#define | C9DOF2_INT_STAT_3 0x1C |
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#define | C9DOF2_DELAY_TIMEH 0x28 |
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#define | C9DOF2_DELAY_TIMEL 0x29 |
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#define | C9DOF2_ACCEL_XOUT_H 0x2D |
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#define | C9DOF2_ACCEL_XOUT_L 0x2E |
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#define | C9DOF2_ACCEL_YOUT_H 0x2F |
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#define | C9DOF2_ACCEL_YOUT_L 0x30 |
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#define | C9DOF2_ACCEL_ZOUT_H 0x31 |
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#define | C9DOF2_ACCEL_ZOUT_L 0x32 |
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#define | C9DOF2_GYRO_XOUT_H 0x33 |
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#define | C9DOF2_GYRO_XOUT_L 0x34 |
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#define | C9DOF2_GYRO_YOUT_H 0x35 |
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#define | C9DOF2_GYRO_YOUT_L 0x36 |
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#define | C9DOF2_GYRO_ZOUT_H 0x37 |
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#define | C9DOF2_GYRO_ZOUT_L 0x38 |
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#define | C9DOF2_TEMP_OUT_H 0x39 |
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#define | C9DOF2_TEMP_OUT_L 0x3A |
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#define | C9DOF2_EXT_SENS_DATA_00 0x3B |
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#define | C9DOF2_EXT_SENS_DATA_01 0x3C |
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#define | C9DOF2_EXT_SENS_DATA_02 0x3D |
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#define | C9DOF2_EXT_SENS_DATA_03 0x3E |
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#define | C9DOF2_EXT_SENS_DATA_04 0x3F |
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#define | C9DOF2_EXT_SENS_DATA_05 0x40 |
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#define | C9DOF2_EXT_SENS_DATA_06 0x41 |
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#define | C9DOF2_EXT_SENS_DATA_07 0x42 |
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#define | C9DOF2_EXT_SENS_DATA_08 0x43 |
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#define | C9DOF2_EXT_SENS_DATA_09 0x44 |
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#define | C9DOF2_EXT_SENS_DATA_10 0x45 |
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#define | C9DOF2_EXT_SENS_DATA_11 0x46 |
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#define | C9DOF2_EXT_SENS_DATA_12 0x47 |
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#define | C9DOF2_EXT_SENS_DATA_13 0x48 |
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#define | C9DOF2_EXT_SENS_DATA_14 0x49 |
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#define | C9DOF2_EXT_SENS_DATA_15 0x4A |
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#define | C9DOF2_EXT_SENS_DATA_16 0x4B |
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#define | C9DOF2_EXT_SENS_DATA_17 0x4C |
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#define | C9DOF2_EXT_SENS_DATA_18 0x4D |
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#define | C9DOF2_EXT_SENS_DATA_19 0x4E |
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#define | C9DOF2_EXT_SENS_DATA_20 0x4F |
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#define | C9DOF2_EXT_SENS_DATA_21 0x50 |
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#define | C9DOF2_EXT_SENS_DATA_22 0x51 |
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#define | C9DOF2_EXT_SENS_DATA_23 0x52 |
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#define | C9DOF2_FIFO_EN_1 0x66 |
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#define | C9DOF2_FIFO_EN_2 0x67 |
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#define | C9DOF2_FIFO_RST 0x68 |
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#define | C9DOF2_FIFO_MODE 0x69 |
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#define | C9DOF2_FIFO_CNT_H 0x70 |
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#define | C9DOF2_FIFO_CNT_L 0x71 |
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#define | C9DOF2_FIFO_R_W 0x72 |
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#define | C9DOF2_DATA_RDY_STAT 0x74 |
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#define | C9DOF2_FIFO_CFG 0x76 |
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#define | C9DOF2_REG_BANK_SEL 0x7F |
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#define | C9DOF2_SELF_TEST_X_GYRO 0x02 |
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#define | C9DOF2_SELF_TEST_Y_GYRO 0x03 |
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#define | C9DOF2_SELF_TEST_Z_GYRO 0x04 |
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#define | C9DOF2_SELF_TEST_X_ACCEL 0x0E |
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#define | C9DOF2_SELF_TEST_Y_ACCEL 0x0F |
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#define | C9DOF2_SELF_TEST_Z_ACCEL 0x10 |
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#define | C9DOF2_XA_OFFSET_H 0x14 |
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#define | C9DOF2_XA_OFFSET_L 0x15 |
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#define | C9DOF2_YA_OFFSET_H 0x17 |
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#define | C9DOF2_YA_OFFSET_L 0x18 |
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#define | C9DOF2_ZA_OFFSET_H 0x1A |
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#define | C9DOF2_ZA_OFFSET_L 0x1B |
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#define | C9DOF2_TIMEBASE_CORREC_PLL 0x28 |
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#define | C9DOF2_GYRO_SMPLRT_DIV 0x00 |
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#define | C9DOF2_GYRO_CFG_1 0x01 |
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#define | C9DOF2_GYRO_CFG_2 0x02 |
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#define | C9DOF2_XG_OFFSET_H 0x03 |
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#define | C9DOF2_XG_OFFSET_L 0x04 |
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#define | C9DOF2_YG_OFFSET_H 0x05 |
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#define | C9DOF2_YG_OFFSET_L 0x06 |
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#define | C9DOF2_ZG_OFFSET_H 0x07 |
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#define | C9DOF2_ZG_OFFSET_L 0x08 |
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#define | C9DOF2_ODR_ALIGN_EN 0x09 |
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#define | C9DOF2_ACCEL_SMPLRT_DIV_1 0x10 |
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#define | C9DOF2_ACCEL_SMPLRT_DIV_2 0x11 |
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#define | C9DOF2_ACCEL_INTEL_CTRL 0x12 |
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#define | C9DOF2_ACCEL_WOM_THR 0x13 |
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#define | C9DOF2_ACCEL_CFG 0x14 |
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#define | C9DOF2_ACCEL_CFG_2 0x15 |
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#define | C9DOF2_FSYNC_CFG 0x52 |
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#define | C9DOF2_TEMP_CFG 0x53 |
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#define | C9DOF2_MOD_CTRL_USR 0x54 |
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#define | C9DOF2_I2C_MST_ODR_CFG 0x00 |
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#define | C9DOF2_I2C_MST_CTRL 0x01 |
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#define | C9DOF2_I2C_MST_DELAY_CTRL 0x02 |
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#define | C9DOF2_I2C_SLV0_ADR 0x03 |
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#define | C9DOF2_I2C_SLV0_REG 0x04 |
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#define | C9DOF2_I2C_SLV0_CTRL 0x05 |
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#define | C9DOF2_I2C_SLV0_DO 0x06 |
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#define | C9DOF2_I2C_SLV1_ADR 0x07 |
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#define | C9DOF2_I2C_SLV1_REG 0x08 |
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#define | C9DOF2_I2C_SLV1_CTRL 0x09 |
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#define | C9DOF2_I2C_SLV1_DO 0x0A |
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#define | C9DOF2_I2C_SLV2_ADR 0x0B |
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#define | C9DOF2_I2C_SLV2_REG 0x0C |
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#define | C9DOF2_I2C_SLV2_CTRL 0x0D |
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#define | C9DOF2_I2C_SLV2_DO 0x0E |
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#define | C9DOF2_I2C_SLV3_ADR 0x0F |
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#define | C9DOF2_I2C_SLV3_REG 0x10 |
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#define | C9DOF2_I2C_SLV3_CTRL 0x11 |
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#define | C9DOF2_I2C_SLV3_DO 0x12 |
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#define | C9DOF2_I2C_SLV4_ADR 0x13 |
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#define | C9DOF2_I2C_SLV4_REG 0x14 |
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#define | C9DOF2_I2C_SLV4_CTRL 0x15 |
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#define | C9DOF2_I2C_SLV4_DO 0x16 |
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#define | C9DOF2_I2C_SLV4_DI 0x17 |
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#define | C9DOF2_REG_BANK_0 0x00 |
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#define | C9DOF2_REG_BANK_1 0x10 |
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#define | C9DOF2_REG_BANK_2 0x20 |
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#define | C9DOF2_REG_BANK_3 0x30 |
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#define | C9DOF2_USER_CTL_DMP_EN 0x80 |
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#define | C9DOF2_USER_CTL_FIFO_EN 0x40 |
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#define | C9DOF2_USER_CTL_I2C_MST_EN 0x20 |
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#define | C9DOF2_USER_CTL_I2C_IF_DIS 0x10 |
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#define | C9DOF2_USER_CTL_DMP_RST 0x08 |
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#define | C9DOF2_USER_CTL_SRAM_RST 0x04 |
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#define | C9DOF2_USER_CTL_I2C_MST_RST 0x02 |
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#define | C9DOF2_LP_CFG_I2C_MST_CYC 0x80 |
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#define | C9DOF2_LP_CFG_ACCEL_CYC 0x40 |
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#define | C9DOF2_LP_CFG_GYRO_CYC 0x20 |
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#define | C9DOF2_PWR_MGMT_1_DEV_RST 0x80 |
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#define | C9DOF2_PWR_MGMT_1_SLP 0x40 |
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#define | C9DOF2_PWR_MGMT_1_LP_EN 0x20 |
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#define | C9DOF2_PWR_MGMT_1_TEMP_DIS 0x08 |
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#define | C9DOF2_PWR_MGMT_1_CLKSEL_7 0x07 |
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#define | C9DOF2_PWR_MGMT_1_CLKSEL_6 0x06 |
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#define | C9DOF2_PWR_MGMT_1_CLKSEL_5 0x05 |
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#define | C9DOF2_PWR_MGMT_1_CLKSEL_4 0x04 |
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#define | C9DOF2_PWR_MGMT_1_CLKSEL_3 0x03 |
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#define | C9DOF2_PWR_MGMT_1_CLKSEL_2 0x02 |
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#define | C9DOF2_PWR_MGMT_1_CLKSEL_1 0x01 |
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#define | C9DOF2_PWR_MGMT_1_CLKSEL_0 0x00 |
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#define | C9DOF2_PWR_MGMT_2_DIS_XA 0x20 |
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#define | C9DOF2_PWR_MGMT_2_DIS_YA 0x10 |
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#define | C9DOF2_PWR_MGMT_2_DIS_ZA 0x08 |
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#define | C9DOF2_PWR_MGMT_2_DIS_XG 0x04 |
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#define | C9DOF2_PWR_MGMT_2_DIS_YG 0x02 |
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#define | C9DOF2_PWR_MGMT_2_DIS_ZG 0x01 |
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#define | C9DOF2_INT_PIN_CFG_ACTL 0x80 |
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#define | C9DOF2_INT_PIN_CFG_OPEN 0x40 |
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#define | C9DOF2_INT_PIN_CFG_LATCH_INT_EN 0x20 |
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#define | C9DOF2_INT_PIN_CFG_INT_ANYRD_2CLR 0x10 |
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#define | C9DOF2_INT_PIN_CFG_ACTL_FSYNC 0x08 |
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#define | C9DOF2_INT_PIN_CFG_FSYNC_INT_MODE_EN 0x04 |
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#define | C9DOF2_INT_PIN_CFG_BYPASS_EN 0x02 |
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#define | C9DOF2_INT_ENABLE_REG_WOF_EN 0x80 |
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#define | C9DOF2_INT_ENABLE_WOM_INT_EN 0x08 |
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#define | C9DOF2_INT_ENABLE_PLL_RDY_EN 0x04 |
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#define | C9DOF2_INT_ENABLE_FIFO_OVF_EN 0x10 |
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#define | C9DOF2_INT_ENABLE_DMP_INT1_EN 0x04 |
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#define | C9DOF2_INT_ENABLE_I2C_MST_INT_EN 0x01 |
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#define | C9DOF2_INT_EN_1_RAW_DATA_0_RDY_EN 0x01 |
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#define | C9DOF2_INT_EN_2_FIFO_OVERFLOW_EN 0x1F |
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#define | C9DOF2_INT_ENABLE_3_FIFO_WM_EN 0x1F |
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#define | C9DOF2_I2C_MST_STAT_PASS_THROUGH 0x80 |
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#define | C9DOF2_I2C_MST_STAT_I2C_SLV4_DONE 0x40 |
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#define | C9DOF2_I2C_MST_STAT_I2C_LOST_ARB 0x20 |
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#define | C9DOF2_I2C_MST_STAT_I2C_SLV4_NACK 0x10 |
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#define | C9DOF2_I2C_MST_STAT_I2C_SLV3_NACK 0x08 |
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#define | C9DOF2_I2C_MST_STAT_I2C_SLV2_NACK 0x04 |
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#define | C9DOF2_I2C_MST_STAT_I2C_SLV1_NACK 0x02 |
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#define | C9DOF2_I2C_MST_STAT_I2C_SLV0_NACK 0x01 |
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#define | C9DOF2_INT_STAT_WOM_INT 0x80 |
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#define | C9DOF2_INT_STAT_PLL_RDY_INT 0x40 |
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#define | C9DOF2_INT_STAT_DMP_INT1 0x20 |
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#define | C9DOF2_INT_STAT_I2C_MST_INT 0x10 |
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#define | C9DOF2_INT_STAT_1_RAW_DATA_0_RDY_EN 0x01 |
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#define | C9DOF2_INT_STAT_2_FIFO_OWF_EN 0x1F |
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#define | C9DOF2_INT_STAT_3_FIFO_WM_EN 0x1F |
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#define | C9DOF2_FIFO_EN_1_SLV_3_FIFO_EN 0x08 |
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#define | C9DOF2_FIFO_EN_1_SLV_2_FIFO_EN 0x04 |
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#define | C9DOF2_FIFO_EN_1_SLV_1_FIFO_EN 0x02 |
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#define | C9DOF2_FIFO_EN_1_SLV_0_FIFO_EN 0x01 |
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#define | C9DOF2_FIFO_EN_2_ACCEL_FIFO_EN 0x10 |
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#define | C9DOF2_FIFO_EN_2_GYRO_Z_FIFO_EN 0x08 |
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#define | C9DOF2_FIFO_EN_2_GYRO_Y_FIFO_EN 0x04 |
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#define | C9DOF2_FIFO_EN_2_GYRO_X_FIFO_EN 0x02 |
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#define | C9DOF2_FIFO_EN_2_TEMP_FIFO_EN 0x01 |
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#define | C9DOF2_FIFO_CFG_CMD 0x01 |
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#define | C9DOF2_GYRO_CFG_1_DLPFCFG_7 0x38 |
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#define | C9DOF2_GYRO_CFG_1_DLPFCFG_6 0x30 |
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#define | C9DOF2_GYRO_CFG_1_DLPFCFG_5 0x28 |
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#define | C9DOF2_GYRO_CFG_1_DLPFCFG_4 0x20 |
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#define | C9DOF2_GYRO_CFG_1_DLPFCFG_3 0x18 |
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#define | C9DOF2_GYRO_CFG_1_DLPFCFG_2 0x10 |
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#define | C9DOF2_GYRO_CFG_1_DLPFCFG_1 0x08 |
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#define | C9DOF2_GYRO_CFG_1_DLPFCFG_0 0x00 |
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#define | C9DOF2_GYRO_CFG_1_FS_SEL_2000 0x06 |
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#define | C9DOF2_GYRO_CFG_1_FS_SEL_1000 0x04 |
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#define | C9DOF2_GYRO_CFG_1_FS_SEL_500 0x02 |
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#define | C9DOF2_GYRO_CFG_1_FS_SEL_250 0x00 |
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#define | C9DOF2_GYRO_CFG_1_FCHOICE_EN 0x01 |
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#define | C9DOF2_GYRO_CFG_1_FCHOICE_BP 0x00 |
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#define | C9DOF2_GYRO_CFG_2_XGYRO_CTEN 0x20 |
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#define | C9DOF2_GYRO_CFG_2_YGYRO_CTEN 0x10 |
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#define | C9DOF2_GYRO_CFG_2_ZGYRO_CTEN 0x08 |
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#define | C9DOF2_GYRO_CFG_2_AVGCFG_7 0x07 |
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#define | C9DOF2_GYRO_CFG_2_AVGCFG_6 0x06 |
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#define | C9DOF2_GYRO_CFG_2_AVGCFG_5 0x05 |
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#define | C9DOF2_GYRO_CFG_2_AVGCFG_4 0x04 |
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#define | C9DOF2_GYRO_CFG_2_AVGCFG_3 0x03 |
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#define | C9DOF2_GYRO_CFG_2_AVGCFG_2 0x02 |
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#define | C9DOF2_GYRO_CFG_2_AVGCFG_1 0x01 |
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#define | C9DOF2_GYRO_CFG_2_AVGCFG_0 0x00 |
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#define | C9DOF2_ODR_ALIGN_CMD_EN 0x01 |
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#define | C9DOF2_ODR_ALIGN_CMD_DIS 0x00 |
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#define | C9DOF2_ACCEL_INTEL_CTL_INTEL_EN 0x02 |
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#define | C9DOF2_ACCEL_INTEL_CTL_INTEL_MODE_INT_CURR 0x01 |
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#define | C9DOF2_ACCEL_INTEL_CTL_INTEL_MODE_INT_INIT 0x00 |
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#define | C9DOF2_ACCEL_CFG_DLPFCFG_7 0x38 |
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#define | C9DOF2_ACCEL_CFG_DLPFCFG_6 0x30 |
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#define | C9DOF2_ACCEL_CFG_DLPFCFG_5 0x28 |
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#define | C9DOF2_ACCEL_CFG_DLPFCFG_4 0x20 |
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#define | C9DOF2_ACCEL_CFG_DLPFCFG_3 0x18 |
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#define | C9DOF2_ACCEL_CFG_DLPFCFG_2 0x10 |
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#define | C9DOF2_ACCEL_CFG_DLPFCFG_1 0x08 |
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#define | C9DOF2_ACCEL_CFG_DLPFCFG_0 0x00 |
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#define | C9DOF2_ACCEL_CFG_FS_SEL_16G 0x06 |
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#define | C9DOF2_ACCEL_CFG_FS_SEL_8G 0x04 |
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#define | C9DOF2_ACCEL_CFG_FS_SEL_4G 0x02 |
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#define | C9DOF2_ACCEL_CFG_FS_SEL_2G 0x00 |
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#define | C9DOF2_ACCEL_CFG_FCHOICE_EN 0x01 |
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#define | C9DOF2_ACCEL_CFG_FCHOICE_BP 0x00 |
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#define | C9DOF2_ACCEL_2_CFG_AX_ST_EN_REG 0x10 |
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#define | C9DOF2_ACCEL_2_CFG_AY_ST_EN_REG 0x08 |
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#define | C9DOF2_ACCEL_2_CFG_AZ_ST_EN_REG 0x04 |
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#define | C9DOF2_ACCEL_2_CFG_DEC3_CFG_32 0x03 |
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#define | C9DOF2_ACCEL_2_CFG_DEC3_CFG_16 0x02 |
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#define | C9DOF2_ACCEL_2_CFG_DEC3_CFG_8 0x01 |
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#define | C9DOF2_ACCEL_2_CFG_DEC3_CFG_4 0x00 |
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#define | C9DOF2_ACCEL_2_CFG_DEC3_CFG_1 0x00 |
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#define | C9DOF2_FSYNC_CFG_DELAY_TIME_EN 0x80 |
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#define | C9DOF2_FSYNC_CFG_WOF_DEGLITCH_EN 0x40 |
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#define | C9DOF2_FSYNC_CFG_WOF_EDGE_INT 0x20 |
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#define | C9DOF2_FSYNC_CFG_EXT_SYNC_SET_ACCEL_ZOUT_L 0x07 |
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#define | C9DOF2_FSYNC_CFG_EXT_SYNC_SET_ACCEL_YOUT_L 0x06 |
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#define | C9DOF2_FSYNC_CFG_EXT_SYNC_SET_ACCEL_XOUT_L 0x05 |
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#define | C9DOF2_FSYNC_CFG_EXT_SYNC_SET_GYRO_ZOUT_L 0x04 |
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#define | C9DOF2_FSYNC_CFG_EXT_SYNC_SET_GYRO_YOUT_L 0x03 |
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#define | C9DOF2_FSYNC_CFG_EXT_SYNC_SET_GYRO_XOUT_L 0x02 |
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#define | C9DOF2_FSYNC_CFG_EXT_SYNC_SET_TEMP_OUT_L 0x01 |
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#define | C9DOF2_FSYNC_CFG_EXT_SYNC_SET_DIS 0x00 |
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#define | C9DOF2_TEMP_CFG_DLPFCFG_7 0x07 |
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#define | C9DOF2_TEMP_CFG_DLPFCFG_6 0x06 |
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#define | C9DOF2_TEMP_CFG_DLPFCFG_5 0x05 |
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#define | C9DOF2_TEMP_CFG_DLPFCFG_4 0x04 |
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#define | C9DOF2_TEMP_CFG_DLPFCFG_3 0x03 |
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#define | C9DOF2_TEMP_CFG_DLPFCFG_2 0x02 |
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#define | C9DOF2_TEMP_CFG_DLPFCFG_1 0x01 |
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#define | C9DOF2_TEMP_CFG_DLPFCFG_0 0x00 |
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#define | C9DOF2_MOD_CTRL_USR_REG_LP_DMP_EN 0x01 |
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#define | C9DOF2_MOD_CTRL_USR_REG_LP_DMP_DIS 0x00 |
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#define | C9DOF2_CNTL2_MODE_SELF_TEST 0x10 |
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#define | C9DOF2_CNTL2_MODE_CONT_MEAS_4 0x08 |
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#define | C9DOF2_CNTL2_MODE_CONT_MEAS_3 0x06 |
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#define | C9DOF2_CNTL2_MODE_CONT_MEAS_2 0x04 |
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#define | C9DOF2_CNTL2_MODE_CONT_MEAS_1 0x02 |
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#define | C9DOF2_CNTL2_MODE_ONE_SHOT 0x01 |
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#define | C9DOF2_CNTL2_MODE_POW_DOWN 0x00 |
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#define | C9DOF2_CNTL3_SOFT_RST 0x01 |
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#define | C9DOF2_WHO_AM_I_ICM20948_VAL 0xEA |
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#define | C9DOF2_GYRO_SENS_FS_SEL_2000 16.4 |
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#define | C9DOF2_GYRO_SENS_FS_SEL_1000 32.8 |
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#define | C9DOF2_GYRO_SENS_FS_SEL_500 65.5 |
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#define | C9DOF2_GYRO_SENS_FS_SEL_250 131.0 |
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#define | C9DOF2_ACCEL_SENS_FS_SEL_16G 2048.0 |
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#define | C9DOF2_ACCEL_SENS_FS_SEL_8G 4096.0 |
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#define | C9DOF2_ACCEL_SENS_FS_SEL_4G 8192.0 |
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#define | C9DOF2_ACCEL_SENS_FS_SEL_2G 16384.0 |
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#define | C9DOF2_POWER_ON 0x01 |
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#define | C9DOF2_POWER_OFF 0x00 |
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#define | C9DOF2_SNC_LOW 0x00 |
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#define | C9DOF2_SNC_HIGH 0x01 |
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#define | C9DOF2_READ_BIT_MASK 0x80 |
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#define | C9DOF2_WRITE_BIT_MASK 0x7F |
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