mikroSDK Reference Manual
MK60D10_features.h
1/*
2** ###################################################################
3** Version: rev. 1.12, 2015-06-08
4** Build: b170228
5**
6** Abstract:
7** Chip specific module features.
8**
9** Copyright 2016 Freescale Semiconductor, Inc.
10** Copyright 2016-2017 NXP
11** Redistribution and use in source and binary forms, with or without modification,
12** are permitted provided that the following conditions are met:
13**
14** o Redistributions of source code must retain the above copyright notice, this list
15** of conditions and the following disclaimer.
16**
17** o Redistributions in binary form must reproduce the above copyright notice, this
18** list of conditions and the following disclaimer in the documentation and/or
19** other materials provided with the distribution.
20**
21** o Neither the name of the copyright holder nor the names of its
22** contributors may be used to endorse or promote products derived from this
23** software without specific prior written permission.
24**
25** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
26** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
29** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
32** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35**
36** http: www.nxp.com
37** mail: support@nxp.com
38**
39** Revisions:
40** - rev. 1.0 (2012-01-03)
41** Initial version
42** - rev. 1.1 (2012-07-09)
43** UART0 - Fixed register definition - CEA709.1-B (LON) registers added.
44** - rev. 1.2 (2012-10-29)
45** Registers updated according to the new reference manual revision - Rev. 2, Jun 2012
46** - rev. 1.3 (2013-06-24)
47** NV_FOPT register - NMI_DIS bit added.
48** SPI - PCSIS bit group in MCR register updated.
49** - rev. 1.4 (2014-01-30)
50** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
51** - rev. 1.5 (2014-07-23)
52** Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
53** Predefined SystemInit() implementation updated:
54** - External clock sources available on TWR board used.
55** - Added 1 ms waiting loop after entering FLL engaged MCG mode.
56** - rev. 1.6 (2014-08-28)
57** Update of startup files - possibility to override DefaultISR added.
58** - rev. 1.7 (2014-10-14)
59** Renamed interrupt vector Watchdog to WDOG_EWM and LPTimer to LPTMR0
60** - rev. 1.8 (2015-01-21)
61** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
62** - rev. 1.9 (2015-05-19)
63** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
64** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
65** Added features for PDB and PORT.
66** - rev. 1.10 (2015-05-25)
67** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
68** - rev. 1.11 (2015-05-27)
69** Several USB features added.
70** - rev. 1.12 (2015-06-08)
71** FTM features BUS_CLOCK and FAST_CLOCK removed.
72**
73** ###################################################################
74*/
75
76#ifndef _MK60D10_FEATURES_H_
77#define _MK60D10_FEATURES_H_
78
79/* SOC module features */
80
81#if defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DN512VLL10) || defined(CPU_MK60DX256VLL10)
82 /* @brief ACMP availability on the SoC. */
83 #define FSL_FEATURE_SOC_ACMP_COUNT (0)
84 /* @brief ADC16 availability on the SoC. */
85 #define FSL_FEATURE_SOC_ADC16_COUNT (2)
86 /* @brief ADC12 availability on the SoC. */
87 #define FSL_FEATURE_SOC_ADC12_COUNT (0)
88 /* @brief AFE availability on the SoC. */
89 #define FSL_FEATURE_SOC_AFE_COUNT (0)
90 /* @brief AIPS availability on the SoC. */
91 #define FSL_FEATURE_SOC_AIPS_COUNT (2)
92 /* @brief AOI availability on the SoC. */
93 #define FSL_FEATURE_SOC_AOI_COUNT (0)
94 /* @brief AXBS availability on the SoC. */
95 #define FSL_FEATURE_SOC_AXBS_COUNT (1)
96 /* @brief ASMC availability on the SoC. */
97 #define FSL_FEATURE_SOC_ASMC_COUNT (0)
98 /* @brief CADC availability on the SoC. */
99 #define FSL_FEATURE_SOC_CADC_COUNT (0)
100 /* @brief FLEXCAN availability on the SoC. */
101 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
102 /* @brief MMCAU availability on the SoC. */
103 #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
104 /* @brief CMP availability on the SoC. */
105 #define FSL_FEATURE_SOC_CMP_COUNT (3)
106 /* @brief CMT availability on the SoC. */
107 #define FSL_FEATURE_SOC_CMT_COUNT (1)
108 /* @brief CNC availability on the SoC. */
109 #define FSL_FEATURE_SOC_CNC_COUNT (0)
110 /* @brief CRC availability on the SoC. */
111 #define FSL_FEATURE_SOC_CRC_COUNT (1)
112 /* @brief DAC availability on the SoC. */
113 #define FSL_FEATURE_SOC_DAC_COUNT (1)
114 /* @brief DAC32 availability on the SoC. */
115 #define FSL_FEATURE_SOC_DAC32_COUNT (0)
116 /* @brief DCDC availability on the SoC. */
117 #define FSL_FEATURE_SOC_DCDC_COUNT (0)
118 /* @brief DDR availability on the SoC. */
119 #define FSL_FEATURE_SOC_DDR_COUNT (0)
120 /* @brief DMA availability on the SoC. */
121 #define FSL_FEATURE_SOC_DMA_COUNT (0)
122 /* @brief EDMA availability on the SoC. */
123 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
124 /* @brief DMAMUX availability on the SoC. */
125 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
126 /* @brief DRY availability on the SoC. */
127 #define FSL_FEATURE_SOC_DRY_COUNT (0)
128 /* @brief DSPI availability on the SoC. */
129 #define FSL_FEATURE_SOC_DSPI_COUNT (3)
130 /* @brief EMVSIM availability on the SoC. */
131 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
132 /* @brief ENC availability on the SoC. */
133 #define FSL_FEATURE_SOC_ENC_COUNT (0)
134 /* @brief ENET availability on the SoC. */
135 #define FSL_FEATURE_SOC_ENET_COUNT (1)
136 /* @brief EWM availability on the SoC. */
137 #define FSL_FEATURE_SOC_EWM_COUNT (1)
138 /* @brief FB availability on the SoC. */
139 #define FSL_FEATURE_SOC_FB_COUNT (1)
140 /* @brief FGPIO availability on the SoC. */
141 #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
142 /* @brief FLEXIO availability on the SoC. */
143 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
144 /* @brief FMC availability on the SoC. */
145 #define FSL_FEATURE_SOC_FMC_COUNT (1)
146 /* @brief FSKDT availability on the SoC. */
147 #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
148 /* @brief FTFA availability on the SoC. */
149 #define FSL_FEATURE_SOC_FTFA_COUNT (0)
150 /* @brief FTFE availability on the SoC. */
151 #define FSL_FEATURE_SOC_FTFE_COUNT (0)
152 /* @brief FTFL availability on the SoC. */
153 #define FSL_FEATURE_SOC_FTFL_COUNT (1)
154 /* @brief FTM availability on the SoC. */
155 #define FSL_FEATURE_SOC_FTM_COUNT (3)
156 /* @brief FTMRA availability on the SoC. */
157 #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
158 /* @brief FTMRE availability on the SoC. */
159 #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
160 /* @brief FTMRH availability on the SoC. */
161 #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
162 /* @brief GPIO availability on the SoC. */
163 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
164 /* @brief HSADC availability on the SoC. */
165 #define FSL_FEATURE_SOC_HSADC_COUNT (0)
166 /* @brief I2C availability on the SoC. */
167 #define FSL_FEATURE_SOC_I2C_COUNT (2)
168 /* @brief I2S availability on the SoC. */
169 #define FSL_FEATURE_SOC_I2S_COUNT (1)
170 /* @brief ICS availability on the SoC. */
171 #define FSL_FEATURE_SOC_ICS_COUNT (0)
172 /* @brief INTMUX availability on the SoC. */
173 #define FSL_FEATURE_SOC_INTMUX_COUNT (0)
174 /* @brief IRQ availability on the SoC. */
175 #define FSL_FEATURE_SOC_IRQ_COUNT (0)
176 /* @brief KBI availability on the SoC. */
177 #define FSL_FEATURE_SOC_KBI_COUNT (0)
178 /* @brief SLCD availability on the SoC. */
179 #define FSL_FEATURE_SOC_SLCD_COUNT (0)
180 /* @brief LCDC availability on the SoC. */
181 #define FSL_FEATURE_SOC_LCDC_COUNT (0)
182 /* @brief LDO availability on the SoC. */
183 #define FSL_FEATURE_SOC_LDO_COUNT (0)
184 /* @brief LLWU availability on the SoC. */
185 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
186 /* @brief LMEM availability on the SoC. */
187 #define FSL_FEATURE_SOC_LMEM_COUNT (0)
188 /* @brief LPI2C availability on the SoC. */
189 #define FSL_FEATURE_SOC_LPI2C_COUNT (0)
190 /* @brief LPIT availability on the SoC. */
191 #define FSL_FEATURE_SOC_LPIT_COUNT (0)
192 /* @brief LPSCI availability on the SoC. */
193 #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
194 /* @brief LPSPI availability on the SoC. */
195 #define FSL_FEATURE_SOC_LPSPI_COUNT (0)
196 /* @brief LPTMR availability on the SoC. */
197 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
198 /* @brief LPTPM availability on the SoC. */
199 #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
200 /* @brief LPUART availability on the SoC. */
201 #define FSL_FEATURE_SOC_LPUART_COUNT (0)
202 /* @brief LTC availability on the SoC. */
203 #define FSL_FEATURE_SOC_LTC_COUNT (0)
204 /* @brief MC availability on the SoC. */
205 #define FSL_FEATURE_SOC_MC_COUNT (0)
206 /* @brief MCG availability on the SoC. */
207 #define FSL_FEATURE_SOC_MCG_COUNT (1)
208 /* @brief MCGLITE availability on the SoC. */
209 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
210 /* @brief MCM availability on the SoC. */
211 #define FSL_FEATURE_SOC_MCM_COUNT (1)
212 /* @brief MMAU availability on the SoC. */
213 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
214 /* @brief MMDVSQ availability on the SoC. */
215 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
216 /* @brief SYSMPU availability on the SoC. */
217 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
218 /* @brief MSCAN availability on the SoC. */
219 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
220 /* @brief MSCM availability on the SoC. */
221 #define FSL_FEATURE_SOC_MSCM_COUNT (0)
222 /* @brief MTB availability on the SoC. */
223 #define FSL_FEATURE_SOC_MTB_COUNT (0)
224 /* @brief MTBDWT availability on the SoC. */
225 #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
226 /* @brief MU availability on the SoC. */
227 #define FSL_FEATURE_SOC_MU_COUNT (0)
228 /* @brief NFC availability on the SoC. */
229 #define FSL_FEATURE_SOC_NFC_COUNT (0)
230 /* @brief OPAMP availability on the SoC. */
231 #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
232 /* @brief OSC availability on the SoC. */
233 #define FSL_FEATURE_SOC_OSC_COUNT (1)
234 /* @brief OSC32 availability on the SoC. */
235 #define FSL_FEATURE_SOC_OSC32_COUNT (0)
236 /* @brief OTFAD availability on the SoC. */
237 #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
238 /* @brief PDB availability on the SoC. */
239 #define FSL_FEATURE_SOC_PDB_COUNT (2)
240 /* @brief PCC availability on the SoC. */
241 #define FSL_FEATURE_SOC_PCC_COUNT (0)
242 /* @brief PGA availability on the SoC. */
243 #define FSL_FEATURE_SOC_PGA_COUNT (0)
244 /* @brief PIT availability on the SoC. */
245 #define FSL_FEATURE_SOC_PIT_COUNT (1)
246 /* @brief PMC availability on the SoC. */
247 #define FSL_FEATURE_SOC_PMC_COUNT (1)
248 /* @brief PORT availability on the SoC. */
249 #define FSL_FEATURE_SOC_PORT_COUNT (5)
250 /* @brief PWM availability on the SoC. */
251 #define FSL_FEATURE_SOC_PWM_COUNT (0)
252 /* @brief PWT availability on the SoC. */
253 #define FSL_FEATURE_SOC_PWT_COUNT (0)
254 /* @brief QuadSPI availability on the SoC. */
255 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
256 /* @brief RCM availability on the SoC. */
257 #define FSL_FEATURE_SOC_RCM_COUNT (1)
258 /* @brief RFSYS availability on the SoC. */
259 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
260 /* @brief RFVBAT availability on the SoC. */
261 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
262 /* @brief RNG availability on the SoC. */
263 #define FSL_FEATURE_SOC_RNG_COUNT (1)
264 /* @brief RNGB availability on the SoC. */
265 #define FSL_FEATURE_SOC_RNGB_COUNT (0)
266 /* @brief ROM availability on the SoC. */
267 #define FSL_FEATURE_SOC_ROM_COUNT (0)
268 /* @brief RSIM availability on the SoC. */
269 #define FSL_FEATURE_SOC_RSIM_COUNT (0)
270 /* @brief RTC availability on the SoC. */
271 #define FSL_FEATURE_SOC_RTC_COUNT (1)
272 /* @brief SCG availability on the SoC. */
273 #define FSL_FEATURE_SOC_SCG_COUNT (0)
274 /* @brief SCI availability on the SoC. */
275 #define FSL_FEATURE_SOC_SCI_COUNT (0)
276 /* @brief SDHC availability on the SoC. */
277 #define FSL_FEATURE_SOC_SDHC_COUNT (1)
278 /* @brief SDRAM availability on the SoC. */
279 #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
280 /* @brief SEMA42 availability on the SoC. */
281 #define FSL_FEATURE_SOC_SEMA42_COUNT (0)
282 /* @brief SIM availability on the SoC. */
283 #define FSL_FEATURE_SOC_SIM_COUNT (1)
284 /* @brief SMC availability on the SoC. */
285 #define FSL_FEATURE_SOC_SMC_COUNT (1)
286 /* @brief SPI availability on the SoC. */
287 #define FSL_FEATURE_SOC_SPI_COUNT (0)
288 /* @brief TMR availability on the SoC. */
289 #define FSL_FEATURE_SOC_TMR_COUNT (0)
290 /* @brief TPM availability on the SoC. */
291 #define FSL_FEATURE_SOC_TPM_COUNT (0)
292 /* @brief TRGMUX availability on the SoC. */
293 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
294 /* @brief TRIAMP availability on the SoC. */
295 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
296 /* @brief TRNG availability on the SoC. */
297 #define FSL_FEATURE_SOC_TRNG_COUNT (0)
298 /* @brief TSI availability on the SoC. */
299 #define FSL_FEATURE_SOC_TSI_COUNT (1)
300 /* @brief TSTMR availability on the SoC. */
301 #define FSL_FEATURE_SOC_TSTMR_COUNT (0)
302 /* @brief UART availability on the SoC. */
303 #define FSL_FEATURE_SOC_UART_COUNT (5)
304 /* @brief USB availability on the SoC. */
305 #define FSL_FEATURE_SOC_USB_COUNT (1)
306 /* @brief USBDCD availability on the SoC. */
307 #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
308 /* @brief USBHS availability on the SoC. */
309 #define FSL_FEATURE_SOC_USBHS_COUNT (0)
310 /* @brief USBHSDCD availability on the SoC. */
311 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
312 /* @brief USBPHY availability on the SoC. */
313 #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
314 /* @brief VREF availability on the SoC. */
315 #define FSL_FEATURE_SOC_VREF_COUNT (1)
316 /* @brief WDOG availability on the SoC. */
317 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
318 /* @brief XBAR availability on the SoC. */
319 #define FSL_FEATURE_SOC_XBAR_COUNT (0)
320 /* @brief XBARA availability on the SoC. */
321 #define FSL_FEATURE_SOC_XBARA_COUNT (0)
322 /* @brief XBARB availability on the SoC. */
323 #define FSL_FEATURE_SOC_XBARB_COUNT (0)
324 /* @brief XCVR availability on the SoC. */
325 #define FSL_FEATURE_SOC_XCVR_COUNT (0)
326 /* @brief XRDC availability on the SoC. */
327 #define FSL_FEATURE_SOC_XRDC_COUNT (0)
328 /* @brief ZLL availability on the SoC. */
329 #define FSL_FEATURE_SOC_ZLL_COUNT (0)
330#elif defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DN512VLQ10) || \
331 defined(CPU_MK60DN512VMC10) || defined(CPU_MK60DN512VMD10) || defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DX256VMC10) || \
332 defined(CPU_MK60DX256VMD10)
333 /* @brief ACMP availability on the SoC. */
334 #define FSL_FEATURE_SOC_ACMP_COUNT (0)
335 /* @brief ADC16 availability on the SoC. */
336 #define FSL_FEATURE_SOC_ADC16_COUNT (2)
337 /* @brief ADC12 availability on the SoC. */
338 #define FSL_FEATURE_SOC_ADC12_COUNT (0)
339 /* @brief AFE availability on the SoC. */
340 #define FSL_FEATURE_SOC_AFE_COUNT (0)
341 /* @brief AIPS availability on the SoC. */
342 #define FSL_FEATURE_SOC_AIPS_COUNT (2)
343 /* @brief AOI availability on the SoC. */
344 #define FSL_FEATURE_SOC_AOI_COUNT (0)
345 /* @brief AXBS availability on the SoC. */
346 #define FSL_FEATURE_SOC_AXBS_COUNT (1)
347 /* @brief ASMC availability on the SoC. */
348 #define FSL_FEATURE_SOC_ASMC_COUNT (0)
349 /* @brief CADC availability on the SoC. */
350 #define FSL_FEATURE_SOC_CADC_COUNT (0)
351 /* @brief FLEXCAN availability on the SoC. */
352 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
353 /* @brief MMCAU availability on the SoC. */
354 #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
355 /* @brief CMP availability on the SoC. */
356 #define FSL_FEATURE_SOC_CMP_COUNT (3)
357 /* @brief CMT availability on the SoC. */
358 #define FSL_FEATURE_SOC_CMT_COUNT (1)
359 /* @brief CNC availability on the SoC. */
360 #define FSL_FEATURE_SOC_CNC_COUNT (0)
361 /* @brief CRC availability on the SoC. */
362 #define FSL_FEATURE_SOC_CRC_COUNT (1)
363 /* @brief DAC availability on the SoC. */
364 #define FSL_FEATURE_SOC_DAC_COUNT (2)
365 /* @brief DAC32 availability on the SoC. */
366 #define FSL_FEATURE_SOC_DAC32_COUNT (0)
367 /* @brief DCDC availability on the SoC. */
368 #define FSL_FEATURE_SOC_DCDC_COUNT (0)
369 /* @brief DDR availability on the SoC. */
370 #define FSL_FEATURE_SOC_DDR_COUNT (0)
371 /* @brief DMA availability on the SoC. */
372 #define FSL_FEATURE_SOC_DMA_COUNT (0)
373 /* @brief EDMA availability on the SoC. */
374 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
375 /* @brief DMAMUX availability on the SoC. */
376 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
377 /* @brief DRY availability on the SoC. */
378 #define FSL_FEATURE_SOC_DRY_COUNT (0)
379 /* @brief DSPI availability on the SoC. */
380 #define FSL_FEATURE_SOC_DSPI_COUNT (3)
381 /* @brief EMVSIM availability on the SoC. */
382 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
383 /* @brief ENC availability on the SoC. */
384 #define FSL_FEATURE_SOC_ENC_COUNT (0)
385 /* @brief ENET availability on the SoC. */
386 #define FSL_FEATURE_SOC_ENET_COUNT (1)
387 /* @brief EWM availability on the SoC. */
388 #define FSL_FEATURE_SOC_EWM_COUNT (1)
389 /* @brief FB availability on the SoC. */
390 #define FSL_FEATURE_SOC_FB_COUNT (1)
391 /* @brief FGPIO availability on the SoC. */
392 #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
393 /* @brief FLEXIO availability on the SoC. */
394 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
395 /* @brief FMC availability on the SoC. */
396 #define FSL_FEATURE_SOC_FMC_COUNT (1)
397 /* @brief FSKDT availability on the SoC. */
398 #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
399 /* @brief FTFA availability on the SoC. */
400 #define FSL_FEATURE_SOC_FTFA_COUNT (0)
401 /* @brief FTFE availability on the SoC. */
402 #define FSL_FEATURE_SOC_FTFE_COUNT (0)
403 /* @brief FTFL availability on the SoC. */
404 #define FSL_FEATURE_SOC_FTFL_COUNT (1)
405 /* @brief FTM availability on the SoC. */
406 #define FSL_FEATURE_SOC_FTM_COUNT (3)
407 /* @brief FTMRA availability on the SoC. */
408 #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
409 /* @brief FTMRE availability on the SoC. */
410 #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
411 /* @brief FTMRH availability on the SoC. */
412 #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
413 /* @brief GPIO availability on the SoC. */
414 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
415 /* @brief HSADC availability on the SoC. */
416 #define FSL_FEATURE_SOC_HSADC_COUNT (0)
417 /* @brief I2C availability on the SoC. */
418 #define FSL_FEATURE_SOC_I2C_COUNT (2)
419 /* @brief I2S availability on the SoC. */
420 #define FSL_FEATURE_SOC_I2S_COUNT (1)
421 /* @brief ICS availability on the SoC. */
422 #define FSL_FEATURE_SOC_ICS_COUNT (0)
423 /* @brief INTMUX availability on the SoC. */
424 #define FSL_FEATURE_SOC_INTMUX_COUNT (0)
425 /* @brief IRQ availability on the SoC. */
426 #define FSL_FEATURE_SOC_IRQ_COUNT (0)
427 /* @brief KBI availability on the SoC. */
428 #define FSL_FEATURE_SOC_KBI_COUNT (0)
429 /* @brief SLCD availability on the SoC. */
430 #define FSL_FEATURE_SOC_SLCD_COUNT (0)
431 /* @brief LCDC availability on the SoC. */
432 #define FSL_FEATURE_SOC_LCDC_COUNT (0)
433 /* @brief LDO availability on the SoC. */
434 #define FSL_FEATURE_SOC_LDO_COUNT (0)
435 /* @brief LLWU availability on the SoC. */
436 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
437 /* @brief LMEM availability on the SoC. */
438 #define FSL_FEATURE_SOC_LMEM_COUNT (0)
439 /* @brief LPI2C availability on the SoC. */
440 #define FSL_FEATURE_SOC_LPI2C_COUNT (0)
441 /* @brief LPIT availability on the SoC. */
442 #define FSL_FEATURE_SOC_LPIT_COUNT (0)
443 /* @brief LPSCI availability on the SoC. */
444 #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
445 /* @brief LPSPI availability on the SoC. */
446 #define FSL_FEATURE_SOC_LPSPI_COUNT (0)
447 /* @brief LPTMR availability on the SoC. */
448 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
449 /* @brief LPTPM availability on the SoC. */
450 #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
451 /* @brief LPUART availability on the SoC. */
452 #define FSL_FEATURE_SOC_LPUART_COUNT (0)
453 /* @brief LTC availability on the SoC. */
454 #define FSL_FEATURE_SOC_LTC_COUNT (0)
455 /* @brief MC availability on the SoC. */
456 #define FSL_FEATURE_SOC_MC_COUNT (0)
457 /* @brief MCG availability on the SoC. */
458 #define FSL_FEATURE_SOC_MCG_COUNT (1)
459 /* @brief MCGLITE availability on the SoC. */
460 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
461 /* @brief MCM availability on the SoC. */
462 #define FSL_FEATURE_SOC_MCM_COUNT (1)
463 /* @brief MMAU availability on the SoC. */
464 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
465 /* @brief MMDVSQ availability on the SoC. */
466 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
467 /* @brief SYSMPU availability on the SoC. */
468 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
469 /* @brief MSCAN availability on the SoC. */
470 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
471 /* @brief MSCM availability on the SoC. */
472 #define FSL_FEATURE_SOC_MSCM_COUNT (0)
473 /* @brief MTB availability on the SoC. */
474 #define FSL_FEATURE_SOC_MTB_COUNT (0)
475 /* @brief MTBDWT availability on the SoC. */
476 #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
477 /* @brief MU availability on the SoC. */
478 #define FSL_FEATURE_SOC_MU_COUNT (0)
479 /* @brief NFC availability on the SoC. */
480 #define FSL_FEATURE_SOC_NFC_COUNT (0)
481 /* @brief OPAMP availability on the SoC. */
482 #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
483 /* @brief OSC availability on the SoC. */
484 #define FSL_FEATURE_SOC_OSC_COUNT (1)
485 /* @brief OSC32 availability on the SoC. */
486 #define FSL_FEATURE_SOC_OSC32_COUNT (0)
487 /* @brief OTFAD availability on the SoC. */
488 #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
489 /* @brief PDB availability on the SoC. */
490 #define FSL_FEATURE_SOC_PDB_COUNT (2)
491 /* @brief PCC availability on the SoC. */
492 #define FSL_FEATURE_SOC_PCC_COUNT (0)
493 /* @brief PGA availability on the SoC. */
494 #define FSL_FEATURE_SOC_PGA_COUNT (0)
495 /* @brief PIT availability on the SoC. */
496 #define FSL_FEATURE_SOC_PIT_COUNT (1)
497 /* @brief PMC availability on the SoC. */
498 #define FSL_FEATURE_SOC_PMC_COUNT (1)
499 /* @brief PORT availability on the SoC. */
500 #define FSL_FEATURE_SOC_PORT_COUNT (5)
501 /* @brief PWM availability on the SoC. */
502 #define FSL_FEATURE_SOC_PWM_COUNT (0)
503 /* @brief PWT availability on the SoC. */
504 #define FSL_FEATURE_SOC_PWT_COUNT (0)
505 /* @brief QuadSPI availability on the SoC. */
506 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
507 /* @brief RCM availability on the SoC. */
508 #define FSL_FEATURE_SOC_RCM_COUNT (1)
509 /* @brief RFSYS availability on the SoC. */
510 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
511 /* @brief RFVBAT availability on the SoC. */
512 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
513 /* @brief RNG availability on the SoC. */
514 #define FSL_FEATURE_SOC_RNG_COUNT (1)
515 /* @brief RNGB availability on the SoC. */
516 #define FSL_FEATURE_SOC_RNGB_COUNT (0)
517 /* @brief ROM availability on the SoC. */
518 #define FSL_FEATURE_SOC_ROM_COUNT (0)
519 /* @brief RSIM availability on the SoC. */
520 #define FSL_FEATURE_SOC_RSIM_COUNT (0)
521 /* @brief RTC availability on the SoC. */
522 #define FSL_FEATURE_SOC_RTC_COUNT (1)
523 /* @brief SCG availability on the SoC. */
524 #define FSL_FEATURE_SOC_SCG_COUNT (0)
525 /* @brief SCI availability on the SoC. */
526 #define FSL_FEATURE_SOC_SCI_COUNT (0)
527 /* @brief SDHC availability on the SoC. */
528 #define FSL_FEATURE_SOC_SDHC_COUNT (1)
529 /* @brief SDRAM availability on the SoC. */
530 #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
531 /* @brief SEMA42 availability on the SoC. */
532 #define FSL_FEATURE_SOC_SEMA42_COUNT (0)
533 /* @brief SIM availability on the SoC. */
534 #define FSL_FEATURE_SOC_SIM_COUNT (1)
535 /* @brief SMC availability on the SoC. */
536 #define FSL_FEATURE_SOC_SMC_COUNT (1)
537 /* @brief SPI availability on the SoC. */
538 #define FSL_FEATURE_SOC_SPI_COUNT (0)
539 /* @brief TMR availability on the SoC. */
540 #define FSL_FEATURE_SOC_TMR_COUNT (0)
541 /* @brief TPM availability on the SoC. */
542 #define FSL_FEATURE_SOC_TPM_COUNT (0)
543 /* @brief TRGMUX availability on the SoC. */
544 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
545 /* @brief TRIAMP availability on the SoC. */
546 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
547 /* @brief TRNG availability on the SoC. */
548 #define FSL_FEATURE_SOC_TRNG_COUNT (0)
549 /* @brief TSI availability on the SoC. */
550 #define FSL_FEATURE_SOC_TSI_COUNT (1)
551 /* @brief TSTMR availability on the SoC. */
552 #define FSL_FEATURE_SOC_TSTMR_COUNT (0)
553 /* @brief UART availability on the SoC. */
554 #define FSL_FEATURE_SOC_UART_COUNT (6)
555 /* @brief USB availability on the SoC. */
556 #define FSL_FEATURE_SOC_USB_COUNT (1)
557 /* @brief USBDCD availability on the SoC. */
558 #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
559 /* @brief USBHS availability on the SoC. */
560 #define FSL_FEATURE_SOC_USBHS_COUNT (0)
561 /* @brief USBHSDCD availability on the SoC. */
562 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
563 /* @brief USBPHY availability on the SoC. */
564 #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
565 /* @brief VREF availability on the SoC. */
566 #define FSL_FEATURE_SOC_VREF_COUNT (1)
567 /* @brief WDOG availability on the SoC. */
568 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
569 /* @brief XBAR availability on the SoC. */
570 #define FSL_FEATURE_SOC_XBAR_COUNT (0)
571 /* @brief XBARA availability on the SoC. */
572 #define FSL_FEATURE_SOC_XBARA_COUNT (0)
573 /* @brief XBARB availability on the SoC. */
574 #define FSL_FEATURE_SOC_XBARB_COUNT (0)
575 /* @brief XCVR availability on the SoC. */
576 #define FSL_FEATURE_SOC_XCVR_COUNT (0)
577 /* @brief XRDC availability on the SoC. */
578 #define FSL_FEATURE_SOC_XRDC_COUNT (0)
579 /* @brief ZLL availability on the SoC. */
580 #define FSL_FEATURE_SOC_ZLL_COUNT (0)
581#endif
582
583/* ADC16 module features */
584
585/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
586#define FSL_FEATURE_ADC16_HAS_PGA (1)
587/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
588#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
589/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
590#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
591/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
592#define FSL_FEATURE_ADC16_HAS_DMA (1)
593/* @brief Has differential mode (bitfield SC1x[DIFF]). */
594#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
595/* @brief Has FIFO (bit SC4[AFDEP]). */
596#define FSL_FEATURE_ADC16_HAS_FIFO (0)
597/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
598#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
599/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
600#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
601/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
602#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
603/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
604#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
605/* @brief Has HW averaging (bit SC3[AVGE]). */
606#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
607/* @brief Has offset correction (register OFS). */
608#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
609/* @brief Maximum ADC resolution. */
610#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
611/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
612#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
613
614/* FLEXCAN module features */
615
616/* @brief Message buffer size */
617#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16)
618/* @brief Has doze mode support (register bit field MCR[DOZE]). */
619#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
620/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
621#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
622/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
623#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
624/* @brief Has extended bit timing register (register CBT). */
625#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
626/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
627#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
628/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
629#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (0)
630/* @brief Has bitfield name BUF31TO0M. */
631#define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0)
632/* @brief Number of interrupt vectors. */
633#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
634/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
635#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (1)
636
637/* CMP module features */
638
639/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
640#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
641/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
642#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
643/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
644#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
645/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
646#define FSL_FEATURE_CMP_HAS_DMA (1)
647/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
648#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
649/* @brief Has DAC Test function in CMP (register DACTEST). */
650#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
651
652/* CRC module features */
653
654/* @brief Has data register with name CRC */
655#define FSL_FEATURE_CRC_HAS_CRC_REG (1)
656
657/* DAC module features */
658
659/* @brief Define the size of hardware buffer */
660#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
661/* @brief Define whether the buffer supports watermark event detection or not. */
662#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
663/* @brief Define whether the buffer supports watermark selection detection or not. */
664#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
665/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
666#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
667/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
668#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
669/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
670#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
671/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
672#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
673/* @brief Define whether FIFO buffer mode is available or not. */
674#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
675/* @brief Define whether swing buffer mode is available or not.. */
676#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
677
678/* EDMA module features */
679
680/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
681#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
682/* @brief Total number of DMA channels on all modules. */
683#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 16)
684/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
685#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
686/* @brief Has DMA_Error interrupt vector. */
687#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
688/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
689#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
690
691/* DMAMUX module features */
692
693/* @brief Number of DMA channels (related to number of register CHCFGn). */
694#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
695/* @brief Total number of DMA channels on all modules. */
696#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16)
697/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
698#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
699
700/* ENET module features */
701
702/* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */
703#define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0)
704/* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */
705#define FSL_FEATURE_ENET_SUPPORT_PTP (1)
706/* @brief Number of associated interrupt vectors. */
707#define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
708/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
709#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (0)
710
711/* EWM module features */
712
713/* @brief Has clock select (register CLKCTRL). */
714#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
715/* @brief Has clock prescaler (register CLKPRESCALER). */
716#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
717
718/* FLEXBUS module features */
719
720/* No feature definitions */
721
722/* FLASH module features */
723
724#if defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DN256VMD10)
725 /* @brief Is of type FTFA. */
726 #define FSL_FEATURE_FLASH_IS_FTFA (0)
727 /* @brief Is of type FTFE. */
728 #define FSL_FEATURE_FLASH_IS_FTFE (0)
729 /* @brief Is of type FTFL. */
730 #define FSL_FEATURE_FLASH_IS_FTFL (1)
731 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
732 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
733 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
734 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
735 /* @brief Has EEPROM region protection (register FEPROT). */
736 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
737 /* @brief Has data flash region protection (register FDPROT). */
738 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
739 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
740 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
741 /* @brief Has flash cache control in FMC module. */
742 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
743 /* @brief Has flash cache control in MCM module. */
744 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
745 /* @brief Has flash cache control in MSCM module. */
746 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
747 /* @brief Has prefetch speculation control in flash, such as kv5x. */
748 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
749 /* @brief P-Flash start address. */
750 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
751 /* @brief P-Flash block count. */
752 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
753 /* @brief P-Flash block size. */
754 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
755 /* @brief P-Flash sector size. */
756 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
757 /* @brief P-Flash write unit size. */
758 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
759 /* @brief P-Flash data path width. */
760 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
761 /* @brief P-Flash block swap feature. */
762 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
763 /* @brief P-Flash protection region count. */
764 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
765 /* @brief Has FlexNVM memory. */
766 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
767 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
768 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
769 /* @brief FlexNVM block count. */
770 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
771 /* @brief FlexNVM block size. */
772 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
773 /* @brief FlexNVM sector size. */
774 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
775 /* @brief FlexNVM write unit size. */
776 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
777 /* @brief FlexNVM data path width. */
778 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
779 /* @brief Has FlexRAM memory. */
780 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
781 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
782 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
783 /* @brief FlexRAM size. */
784 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
785 /* @brief Has 0x00 Read 1s Block command. */
786 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
787 /* @brief Has 0x01 Read 1s Section command. */
788 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
789 /* @brief Has 0x02 Program Check command. */
790 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
791 /* @brief Has 0x03 Read Resource command. */
792 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
793 /* @brief Has 0x06 Program Longword command. */
794 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
795 /* @brief Has 0x07 Program Phrase command. */
796 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
797 /* @brief Has 0x08 Erase Flash Block command. */
798 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
799 /* @brief Has 0x09 Erase Flash Sector command. */
800 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
801 /* @brief Has 0x0B Program Section command. */
802 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
803 /* @brief Has 0x40 Read 1s All Blocks command. */
804 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
805 /* @brief Has 0x41 Read Once command. */
806 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
807 /* @brief Has 0x43 Program Once command. */
808 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
809 /* @brief Has 0x44 Erase All Blocks command. */
810 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
811 /* @brief Has 0x45 Verify Backdoor Access Key command. */
812 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
813 /* @brief Has 0x46 Swap Control command. */
814 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
815 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
816 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
817 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
818 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
819 /* @brief Has 0x4B Erase All Execute-only Segments command. */
820 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
821 /* @brief Has 0x80 Program Partition command. */
822 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
823 /* @brief Has 0x81 Set FlexRAM Function command. */
824 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
825 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
826 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
827 /* @brief P-Flash Erase sector command address alignment. */
828 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
829 /* @brief P-Flash Rrogram/Verify section command address alignment. */
830 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
831 /* @brief P-Flash Read resource command address alignment. */
832 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
833 /* @brief P-Flash Program check command address alignment. */
834 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
835 /* @brief P-Flash Program check command address alignment. */
836 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (8)
837 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
838 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
839 /* @brief FlexNVM Erase sector command address alignment. */
840 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
841 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
842 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
843 /* @brief FlexNVM Read resource command address alignment. */
844 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
845 /* @brief FlexNVM Program check command address alignment. */
846 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
847 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
848 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
849 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
850 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
851 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
852 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
853 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
854 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
855 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
856 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
857 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
858 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
859 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
860 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
861 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
862 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
863 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
864 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
865 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
866 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
867 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
868 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
869 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
870 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
871 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
872 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
873 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
874 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
875 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
876 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
877 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
878 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
879 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
880 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
881 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
882 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
883 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
884 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
885 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
886 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
887 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
888 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
889 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
890 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
891 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
892 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
893 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
894 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
895 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
896 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
897 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
898 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
899 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
900 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
901 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
902 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
903 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
904 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
905 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
906 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
907 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
908 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
909 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
910 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
911#elif defined(CPU_MK60DN512VLL10) || defined(CPU_MK60DN512VLQ10) || defined(CPU_MK60DN512VMC10) || defined(CPU_MK60DN512VMD10)
912 /* @brief Is of type FTFA. */
913 #define FSL_FEATURE_FLASH_IS_FTFA (0)
914 /* @brief Is of type FTFE. */
915 #define FSL_FEATURE_FLASH_IS_FTFE (0)
916 /* @brief Is of type FTFL. */
917 #define FSL_FEATURE_FLASH_IS_FTFL (1)
918 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
919 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
920 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
921 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
922 /* @brief Has EEPROM region protection (register FEPROT). */
923 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
924 /* @brief Has data flash region protection (register FDPROT). */
925 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
926 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
927 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
928 /* @brief Has flash cache control in FMC module. */
929 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
930 /* @brief Has flash cache control in MCM module. */
931 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
932 /* @brief Has flash cache control in MSCM module. */
933 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
934 /* @brief Has prefetch speculation control in flash, such as kv5x. */
935 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
936 /* @brief P-Flash start address. */
937 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
938 /* @brief P-Flash block count. */
939 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
940 /* @brief P-Flash block size. */
941 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144)
942 /* @brief P-Flash sector size. */
943 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
944 /* @brief P-Flash write unit size. */
945 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
946 /* @brief P-Flash data path width. */
947 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
948 /* @brief P-Flash block swap feature. */
949 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
950 /* @brief P-Flash protection region count. */
951 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
952 /* @brief Has FlexNVM memory. */
953 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
954 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
955 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
956 /* @brief FlexNVM block count. */
957 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
958 /* @brief FlexNVM block size. */
959 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
960 /* @brief FlexNVM sector size. */
961 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
962 /* @brief FlexNVM write unit size. */
963 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
964 /* @brief FlexNVM data path width. */
965 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
966 /* @brief Has FlexRAM memory. */
967 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
968 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
969 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
970 /* @brief FlexRAM size. */
971 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
972 /* @brief Has 0x00 Read 1s Block command. */
973 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
974 /* @brief Has 0x01 Read 1s Section command. */
975 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
976 /* @brief Has 0x02 Program Check command. */
977 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
978 /* @brief Has 0x03 Read Resource command. */
979 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
980 /* @brief Has 0x06 Program Longword command. */
981 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
982 /* @brief Has 0x07 Program Phrase command. */
983 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
984 /* @brief Has 0x08 Erase Flash Block command. */
985 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
986 /* @brief Has 0x09 Erase Flash Sector command. */
987 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
988 /* @brief Has 0x0B Program Section command. */
989 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
990 /* @brief Has 0x40 Read 1s All Blocks command. */
991 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
992 /* @brief Has 0x41 Read Once command. */
993 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
994 /* @brief Has 0x43 Program Once command. */
995 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
996 /* @brief Has 0x44 Erase All Blocks command. */
997 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
998 /* @brief Has 0x45 Verify Backdoor Access Key command. */
999 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
1000 /* @brief Has 0x46 Swap Control command. */
1001 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
1002 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
1003 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
1004 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
1005 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
1006 /* @brief Has 0x4B Erase All Execute-only Segments command. */
1007 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
1008 /* @brief Has 0x80 Program Partition command. */
1009 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
1010 /* @brief Has 0x81 Set FlexRAM Function command. */
1011 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
1012 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
1013 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
1014 /* @brief P-Flash Erase sector command address alignment. */
1015 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
1016 /* @brief P-Flash Rrogram/Verify section command address alignment. */
1017 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
1018 /* @brief P-Flash Read resource command address alignment. */
1019 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
1020 /* @brief P-Flash Program check command address alignment. */
1021 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
1022 /* @brief P-Flash Program check command address alignment. */
1023 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (8)
1024 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
1025 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
1026 /* @brief FlexNVM Erase sector command address alignment. */
1027 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
1028 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
1029 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
1030 /* @brief FlexNVM Read resource command address alignment. */
1031 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
1032 /* @brief FlexNVM Program check command address alignment. */
1033 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
1034 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1035 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
1036 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1037 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
1038 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1039 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
1040 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1041 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
1042 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1043 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
1044 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1045 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
1046 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1047 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
1048 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1049 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
1050 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1051 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
1052 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1053 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
1054 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1055 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
1056 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1057 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
1058 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1059 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
1060 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1061 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
1062 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1063 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
1064 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1065 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
1066 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1067 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
1068 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1069 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
1070 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1071 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
1072 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1073 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
1074 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1075 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
1076 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1077 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
1078 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1079 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
1080 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1081 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
1082 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1083 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
1084 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1085 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
1086 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1087 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
1088 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1089 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
1090 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1091 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
1092 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1093 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
1094 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1095 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
1096 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1097 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
1098#elif defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DX256VMC10) || defined(CPU_MK60DX256VMD10)
1099 /* @brief Is of type FTFA. */
1100 #define FSL_FEATURE_FLASH_IS_FTFA (0)
1101 /* @brief Is of type FTFE. */
1102 #define FSL_FEATURE_FLASH_IS_FTFE (0)
1103 /* @brief Is of type FTFL. */
1104 #define FSL_FEATURE_FLASH_IS_FTFL (1)
1105 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
1106 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
1107 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
1108 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
1109 /* @brief Has EEPROM region protection (register FEPROT). */
1110 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
1111 /* @brief Has data flash region protection (register FDPROT). */
1112 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
1113 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
1114 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
1115 /* @brief Has flash cache control in FMC module. */
1116 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
1117 /* @brief Has flash cache control in MCM module. */
1118 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
1119 /* @brief Has flash cache control in MSCM module. */
1120 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
1121 /* @brief Has prefetch speculation control in flash, such as kv5x. */
1122 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
1123 /* @brief P-Flash start address. */
1124 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
1125 /* @brief P-Flash block count. */
1126 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
1127 /* @brief P-Flash block size. */
1128 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144)
1129 /* @brief P-Flash sector size. */
1130 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
1131 /* @brief P-Flash write unit size. */
1132 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
1133 /* @brief P-Flash data path width. */
1134 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
1135 /* @brief P-Flash block swap feature. */
1136 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
1137 /* @brief P-Flash protection region count. */
1138 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
1139 /* @brief Has FlexNVM memory. */
1140 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1)
1141 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
1142 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000)
1143 /* @brief FlexNVM block count. */
1144 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1)
1145 /* @brief FlexNVM block size. */
1146 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (262144)
1147 /* @brief FlexNVM sector size. */
1148 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (2048)
1149 /* @brief FlexNVM write unit size. */
1150 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (4)
1151 /* @brief FlexNVM data path width. */
1152 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (8)
1153 /* @brief Has FlexRAM memory. */
1154 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
1155 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
1156 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
1157 /* @brief FlexRAM size. */
1158 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
1159 /* @brief Has 0x00 Read 1s Block command. */
1160 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
1161 /* @brief Has 0x01 Read 1s Section command. */
1162 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
1163 /* @brief Has 0x02 Program Check command. */
1164 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
1165 /* @brief Has 0x03 Read Resource command. */
1166 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
1167 /* @brief Has 0x06 Program Longword command. */
1168 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
1169 /* @brief Has 0x07 Program Phrase command. */
1170 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
1171 /* @brief Has 0x08 Erase Flash Block command. */
1172 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
1173 /* @brief Has 0x09 Erase Flash Sector command. */
1174 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
1175 /* @brief Has 0x0B Program Section command. */
1176 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
1177 /* @brief Has 0x40 Read 1s All Blocks command. */
1178 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
1179 /* @brief Has 0x41 Read Once command. */
1180 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
1181 /* @brief Has 0x43 Program Once command. */
1182 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
1183 /* @brief Has 0x44 Erase All Blocks command. */
1184 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
1185 /* @brief Has 0x45 Verify Backdoor Access Key command. */
1186 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
1187 /* @brief Has 0x46 Swap Control command. */
1188 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
1189 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
1190 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
1191 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
1192 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
1193 /* @brief Has 0x4B Erase All Execute-only Segments command. */
1194 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
1195 /* @brief Has 0x80 Program Partition command. */
1196 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1)
1197 /* @brief Has 0x81 Set FlexRAM Function command. */
1198 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1)
1199 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
1200 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
1201 /* @brief P-Flash Erase sector command address alignment. */
1202 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
1203 /* @brief P-Flash Rrogram/Verify section command address alignment. */
1204 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
1205 /* @brief P-Flash Read resource command address alignment. */
1206 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
1207 /* @brief P-Flash Program check command address alignment. */
1208 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
1209 /* @brief P-Flash Program check command address alignment. */
1210 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
1211 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
1212 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (4)
1213 /* @brief FlexNVM Erase sector command address alignment. */
1214 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (8)
1215 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
1216 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (8)
1217 /* @brief FlexNVM Read resource command address alignment. */
1218 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
1219 /* @brief FlexNVM Program check command address alignment. */
1220 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4)
1221 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1222 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00040000)
1223 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1224 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
1225 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1226 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
1227 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1228 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00038000)
1229 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1230 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00030000)
1231 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1232 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00020000)
1233 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1234 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0x00000000)
1235 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1236 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
1237 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1238 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000)
1239 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1240 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
1241 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1242 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
1243 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1244 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000)
1245 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1246 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000)
1247 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1248 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000)
1249 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1250 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0x00040000)
1251 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
1252 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00040000)
1253 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1254 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
1255 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1256 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
1257 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1258 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
1259 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1260 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
1261 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1262 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
1263 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1264 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
1265 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1266 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
1267 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1268 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
1269 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1270 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
1271 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1272 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
1273 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1274 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
1275 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1276 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
1277 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1278 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
1279 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1280 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
1281 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1282 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
1283 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
1284 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
1285#endif /* defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DN256VMD10) */
1286
1287/* FTM module features */
1288
1289/* @brief Number of channels. */
1290#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
1291 ((x) == FTM0 ? (8) : \
1292 ((x) == FTM1 ? (2) : \
1293 ((x) == FTM2 ? (2) : (-1))))
1294/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
1295#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
1296/* @brief Has extended deadtime value. */
1297#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0)
1298/* @brief Enable pwm output for the module. */
1299#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
1300/* @brief Has half-cycle reload for the module. */
1301#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0)
1302/* @brief Has reload interrupt. */
1303#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0)
1304/* @brief Has reload initialization trigger. */
1305#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
1306
1307/* GPIO module features */
1308
1309/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
1310#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
1311/* @brief Has port input disable register (PIDR). */
1312#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
1313/* @brief Has dedicated interrupt vector. */
1314#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
1315
1316/* I2C module features */
1317
1318/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
1319#define FSL_FEATURE_I2C_HAS_SMBUS (1)
1320/* @brief Maximum supported baud rate in kilobit per second. */
1321#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
1322/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
1323#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
1324/* @brief Has DMA support (register bit C1[DMAEN]). */
1325#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
1326/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
1327#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (0)
1328/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
1329#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
1330/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
1331#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (0)
1332/* @brief Maximum width of the glitch filter in number of bus clocks. */
1333#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31)
1334/* @brief Has control of the drive capability of the I2C pins. */
1335#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
1336/* @brief Has double buffering support (register S2). */
1337#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
1338/* @brief Has double buffer enable. */
1339#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
1340
1341/* SAI module features */
1342
1343/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
1344#define FSL_FEATURE_SAI_FIFO_COUNT (8)
1345/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
1346#define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
1347/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
1348#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
1349/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
1350#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
1351/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
1352#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
1353/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
1354#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
1355/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
1356#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
1357/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
1358#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
1359/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
1360#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
1361/* @brief Ihe interrupt source number */
1362#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
1363/* @brief Has register of MCR. */
1364#define FSL_FEATURE_SAI_HAS_MCR (1)
1365/* @brief Has register of MDR */
1366#define FSL_FEATURE_SAI_HAS_MDR (1)
1367
1368/* LLWU module features */
1369
1370/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
1371#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
1372/* @brief Has pins 8-15 connected to LLWU device. */
1373#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
1374/* @brief Maximum number of internal modules connected to LLWU device. */
1375#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
1376/* @brief Number of digital filters. */
1377#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
1378/* @brief Has MF register. */
1379#define FSL_FEATURE_LLWU_HAS_MF (0)
1380/* @brief Has PF register. */
1381#define FSL_FEATURE_LLWU_HAS_PF (0)
1382/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
1383#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
1384/* @brief Has no internal module wakeup flag register. */
1385#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
1386/* @brief Has external pin 0 connected to LLWU device. */
1387#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
1388/* @brief Index of port of external pin. */
1389#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
1390/* @brief Number of external pin port on specified port. */
1391#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
1392/* @brief Has external pin 1 connected to LLWU device. */
1393#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
1394/* @brief Index of port of external pin. */
1395#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
1396/* @brief Number of external pin port on specified port. */
1397#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
1398/* @brief Has external pin 2 connected to LLWU device. */
1399#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
1400/* @brief Index of port of external pin. */
1401#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
1402/* @brief Number of external pin port on specified port. */
1403#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
1404/* @brief Has external pin 3 connected to LLWU device. */
1405#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
1406/* @brief Index of port of external pin. */
1407#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
1408/* @brief Number of external pin port on specified port. */
1409#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
1410/* @brief Has external pin 4 connected to LLWU device. */
1411#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
1412/* @brief Index of port of external pin. */
1413#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
1414/* @brief Number of external pin port on specified port. */
1415#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
1416/* @brief Has external pin 5 connected to LLWU device. */
1417#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
1418/* @brief Index of port of external pin. */
1419#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
1420/* @brief Number of external pin port on specified port. */
1421#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
1422/* @brief Has external pin 6 connected to LLWU device. */
1423#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
1424/* @brief Index of port of external pin. */
1425#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
1426/* @brief Number of external pin port on specified port. */
1427#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
1428/* @brief Has external pin 7 connected to LLWU device. */
1429#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
1430/* @brief Index of port of external pin. */
1431#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
1432/* @brief Number of external pin port on specified port. */
1433#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
1434/* @brief Has external pin 8 connected to LLWU device. */
1435#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
1436/* @brief Index of port of external pin. */
1437#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
1438/* @brief Number of external pin port on specified port. */
1439#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
1440/* @brief Has external pin 9 connected to LLWU device. */
1441#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
1442/* @brief Index of port of external pin. */
1443#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
1444/* @brief Number of external pin port on specified port. */
1445#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
1446/* @brief Has external pin 10 connected to LLWU device. */
1447#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
1448/* @brief Index of port of external pin. */
1449#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
1450/* @brief Number of external pin port on specified port. */
1451#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
1452/* @brief Has external pin 11 connected to LLWU device. */
1453#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
1454/* @brief Index of port of external pin. */
1455#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
1456/* @brief Number of external pin port on specified port. */
1457#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
1458/* @brief Has external pin 12 connected to LLWU device. */
1459#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
1460/* @brief Index of port of external pin. */
1461#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
1462/* @brief Number of external pin port on specified port. */
1463#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
1464/* @brief Has external pin 13 connected to LLWU device. */
1465#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
1466/* @brief Index of port of external pin. */
1467#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
1468/* @brief Number of external pin port on specified port. */
1469#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
1470/* @brief Has external pin 14 connected to LLWU device. */
1471#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
1472/* @brief Index of port of external pin. */
1473#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
1474/* @brief Number of external pin port on specified port. */
1475#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
1476/* @brief Has external pin 15 connected to LLWU device. */
1477#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
1478/* @brief Index of port of external pin. */
1479#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
1480/* @brief Number of external pin port on specified port. */
1481#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
1482/* @brief Has external pin 16 connected to LLWU device. */
1483#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
1484/* @brief Index of port of external pin. */
1485#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
1486/* @brief Number of external pin port on specified port. */
1487#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
1488/* @brief Has external pin 17 connected to LLWU device. */
1489#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
1490/* @brief Index of port of external pin. */
1491#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
1492/* @brief Number of external pin port on specified port. */
1493#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
1494/* @brief Has external pin 18 connected to LLWU device. */
1495#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
1496/* @brief Index of port of external pin. */
1497#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
1498/* @brief Number of external pin port on specified port. */
1499#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
1500/* @brief Has external pin 19 connected to LLWU device. */
1501#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
1502/* @brief Index of port of external pin. */
1503#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
1504/* @brief Number of external pin port on specified port. */
1505#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
1506/* @brief Has external pin 20 connected to LLWU device. */
1507#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
1508/* @brief Index of port of external pin. */
1509#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
1510/* @brief Number of external pin port on specified port. */
1511#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
1512/* @brief Has external pin 21 connected to LLWU device. */
1513#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
1514/* @brief Index of port of external pin. */
1515#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
1516/* @brief Number of external pin port on specified port. */
1517#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
1518/* @brief Has external pin 22 connected to LLWU device. */
1519#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
1520/* @brief Index of port of external pin. */
1521#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
1522/* @brief Number of external pin port on specified port. */
1523#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
1524/* @brief Has external pin 23 connected to LLWU device. */
1525#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
1526/* @brief Index of port of external pin. */
1527#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
1528/* @brief Number of external pin port on specified port. */
1529#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
1530/* @brief Has external pin 24 connected to LLWU device. */
1531#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
1532/* @brief Index of port of external pin. */
1533#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
1534/* @brief Number of external pin port on specified port. */
1535#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
1536/* @brief Has external pin 25 connected to LLWU device. */
1537#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
1538/* @brief Index of port of external pin. */
1539#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
1540/* @brief Number of external pin port on specified port. */
1541#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
1542/* @brief Has external pin 26 connected to LLWU device. */
1543#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
1544/* @brief Index of port of external pin. */
1545#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
1546/* @brief Number of external pin port on specified port. */
1547#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
1548/* @brief Has external pin 27 connected to LLWU device. */
1549#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
1550/* @brief Index of port of external pin. */
1551#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
1552/* @brief Number of external pin port on specified port. */
1553#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
1554/* @brief Has external pin 28 connected to LLWU device. */
1555#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
1556/* @brief Index of port of external pin. */
1557#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
1558/* @brief Number of external pin port on specified port. */
1559#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
1560/* @brief Has external pin 29 connected to LLWU device. */
1561#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
1562/* @brief Index of port of external pin. */
1563#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
1564/* @brief Number of external pin port on specified port. */
1565#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
1566/* @brief Has external pin 30 connected to LLWU device. */
1567#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
1568/* @brief Index of port of external pin. */
1569#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
1570/* @brief Number of external pin port on specified port. */
1571#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
1572/* @brief Has external pin 31 connected to LLWU device. */
1573#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
1574/* @brief Index of port of external pin. */
1575#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
1576/* @brief Number of external pin port on specified port. */
1577#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
1578/* @brief Has internal module 0 connected to LLWU device. */
1579#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
1580/* @brief Has internal module 1 connected to LLWU device. */
1581#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
1582/* @brief Has internal module 2 connected to LLWU device. */
1583#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
1584/* @brief Has internal module 3 connected to LLWU device. */
1585#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
1586/* @brief Has internal module 4 connected to LLWU device. */
1587#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
1588/* @brief Has internal module 5 connected to LLWU device. */
1589#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
1590/* @brief Has internal module 6 connected to LLWU device. */
1591#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
1592/* @brief Has internal module 7 connected to LLWU device. */
1593#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
1594/* @brief Has Version ID Register (LLWU_VERID). */
1595#define FSL_FEATURE_LLWU_HAS_VERID (0)
1596/* @brief Has Parameter Register (LLWU_PARAM). */
1597#define FSL_FEATURE_LLWU_HAS_PARAM (0)
1598/* @brief Width of registers of the LLWU. */
1599#define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
1600/* @brief Has DMA Enable register (LLWU_DE). */
1601#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
1602
1603/* LPTMR module features */
1604
1605/* @brief Has shared interrupt handler with another LPTMR module. */
1606#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
1607/* @brief Whether LPTMR counter is 32 bits width. */
1608#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
1609/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
1610#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
1611
1612/* MCG module features */
1613
1614/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
1615#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
1616/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
1617#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
1618/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
1619#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
1620/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
1621#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
1622/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
1623#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
1624/* @brief The PLL clock is divided by 2 before VCO divider. */
1625#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
1626/* @brief FRDIV supports 1280. */
1627#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
1628/* @brief FRDIV supports 1536. */
1629#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
1630/* @brief MCGFFCLK divider. */
1631#define FSL_FEATURE_MCG_FFCLK_DIV (1)
1632/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
1633#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
1634/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
1635#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
1636/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
1637#define FSL_FEATURE_MCG_HAS_PLL1 (0)
1638/* @brief Has 48MHz internal oscillator. */
1639#define FSL_FEATURE_MCG_HAS_IRC_48M (0)
1640/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
1641#define FSL_FEATURE_MCG_HAS_OSC1 (0)
1642/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
1643#define FSL_FEATURE_MCG_HAS_FCFTRIM (0)
1644/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
1645#define FSL_FEATURE_MCG_HAS_LOLRE (1)
1646/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
1647#define FSL_FEATURE_MCG_USE_OSCSEL (1)
1648/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
1649#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
1650/* @brief TBD */
1651#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
1652/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
1653#define FSL_FEATURE_MCG_HAS_PLL (1)
1654/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
1655#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
1656/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
1657#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
1658/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
1659#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1)
1660/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
1661#define FSL_FEATURE_MCG_HAS_FLL (1)
1662/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
1663#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
1664/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
1665#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
1666/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
1667#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
1668/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
1669#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
1670/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
1671#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
1672/* @brief Has external clock monitor (register bit C6[CME]). */
1673#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
1674/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
1675#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
1676/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
1677#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
1678/* @brief Has PEI mode or PBI mode. */
1679#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
1680/* @brief Reset clock mode is BLPI. */
1681#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
1682
1683/* interrupt module features */
1684
1685/* @brief Lowest interrupt request number. */
1686#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
1687/* @brief Highest interrupt request number. */
1688#define FSL_FEATURE_INTERRUPT_IRQ_MAX (94)
1689
1690/* OSC module features */
1691
1692/* @brief Has OSC1 external oscillator. */
1693#define FSL_FEATURE_OSC_HAS_OSC1 (0)
1694/* @brief Has OSC0 external oscillator. */
1695#define FSL_FEATURE_OSC_HAS_OSC0 (0)
1696/* @brief Has OSC external oscillator (without index). */
1697#define FSL_FEATURE_OSC_HAS_OSC (1)
1698/* @brief Number of OSC external oscillators. */
1699#define FSL_FEATURE_OSC_OSC_COUNT (1)
1700/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
1701#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
1702
1703/* PDB module features */
1704
1705/* @brief Define the count of supporting ADC pre-trigger for each channel. */
1706#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
1707/* @brief Has DAC support. */
1708#define FSL_FEATURE_PDB_HAS_DAC (1)
1709/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1710#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
1711
1712/* PIT module features */
1713
1714/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
1715#define FSL_FEATURE_PIT_TIMER_COUNT (4)
1716/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
1717#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
1718/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
1719#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
1720/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1721#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
1722
1723/* PMC module features */
1724
1725/* @brief Has Bandgap Enable In VLPx Operation support. */
1726#define FSL_FEATURE_PMC_HAS_BGEN (1)
1727/* @brief Has Bandgap Buffer Enable. */
1728#define FSL_FEATURE_PMC_HAS_BGBE (1)
1729/* @brief Has Bandgap Buffer Drive Select. */
1730#define FSL_FEATURE_PMC_HAS_BGBDS (0)
1731/* @brief Has Low-Voltage Detect Voltage Select support. */
1732#define FSL_FEATURE_PMC_HAS_LVDV (1)
1733/* @brief Has Low-Voltage Warning Voltage Select support. */
1734#define FSL_FEATURE_PMC_HAS_LVWV (1)
1735/* @brief Has LPO. */
1736#define FSL_FEATURE_PMC_HAS_LPO (0)
1737/* @brief Has VLPx option PMC_REGSC[VLPO]. */
1738#define FSL_FEATURE_PMC_HAS_VLPO (0)
1739/* @brief Has acknowledge isolation support. */
1740#define FSL_FEATURE_PMC_HAS_ACKISO (1)
1741/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
1742#define FSL_FEATURE_PMC_HAS_REGFPM (0)
1743/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
1744#define FSL_FEATURE_PMC_HAS_REGONS (1)
1745/* @brief Has PMC_HVDSC1. */
1746#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
1747/* @brief Has PMC_PARAM. */
1748#define FSL_FEATURE_PMC_HAS_PARAM (0)
1749/* @brief Has PMC_VERID. */
1750#define FSL_FEATURE_PMC_HAS_VERID (0)
1751
1752/* PORT module features */
1753
1754/* @brief Has control lock (register bit PCR[LK]). */
1755#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
1756/* @brief Has open drain control (register bit PCR[ODE]). */
1757#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
1758/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
1759#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
1760/* @brief Has DMA request (register bit field PCR[IRQC] values). */
1761#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
1762/* @brief Has pull resistor selection available. */
1763#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
1764/* @brief Has pull resistor enable (register bit PCR[PE]). */
1765#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
1766/* @brief Has slew rate control (register bit PCR[SRE]). */
1767#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
1768/* @brief Has passive filter (register bit field PCR[PFE]). */
1769#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
1770/* @brief Has drive strength control (register bit PCR[DSE]). */
1771#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
1772/* @brief Has separate drive strength register (HDRVE). */
1773#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
1774/* @brief Has glitch filter (register IOFLT). */
1775#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
1776/* @brief Defines width of PCR[MUX] field. */
1777#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
1778/* @brief Has dedicated interrupt vector. */
1779#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
1780/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
1781#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
1782/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
1783#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
1784/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
1785#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
1786
1787/* RCM module features */
1788
1789/* @brief Has Loss-of-Lock Reset support. */
1790#define FSL_FEATURE_RCM_HAS_LOL (1)
1791/* @brief Has Loss-of-Clock Reset support. */
1792#define FSL_FEATURE_RCM_HAS_LOC (1)
1793/* @brief Has JTAG generated Reset support. */
1794#define FSL_FEATURE_RCM_HAS_JTAG (1)
1795/* @brief Has EzPort generated Reset support. */
1796#define FSL_FEATURE_RCM_HAS_EZPORT (1)
1797/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
1798#define FSL_FEATURE_RCM_HAS_EZPMS (1)
1799/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
1800#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
1801/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
1802#define FSL_FEATURE_RCM_HAS_SSRS (0)
1803/* @brief Has Version ID Register (RCM_VERID). */
1804#define FSL_FEATURE_RCM_HAS_VERID (0)
1805/* @brief Has Parameter Register (RCM_PARAM). */
1806#define FSL_FEATURE_RCM_HAS_PARAM (0)
1807/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
1808#define FSL_FEATURE_RCM_HAS_SRIE (0)
1809/* @brief Width of registers of the RCM. */
1810#define FSL_FEATURE_RCM_REG_WIDTH (8)
1811/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
1812#define FSL_FEATURE_RCM_HAS_CORE1 (0)
1813/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
1814#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
1815/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
1816#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
1817
1818/* RTC module features */
1819
1820/* @brief Has wakeup pin. */
1821#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
1822/* @brief Has wakeup pin selection (bit field CR[WPS]). */
1823#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0)
1824/* @brief Has low power features (registers MER, MCLR and MCHR). */
1825#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
1826/* @brief Has read/write access control (registers WAR and RAR). */
1827#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
1828/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
1829#define FSL_FEATURE_RTC_HAS_SECURITY (0)
1830/* @brief Has RTC_CLKIN available. */
1831#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
1832/* @brief Has prescaler adjust for LPO. */
1833#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
1834/* @brief Has Clock Pin Enable field. */
1835#define FSL_FEATURE_RTC_HAS_CPE (0)
1836/* @brief Has Timer Seconds Interrupt Configuration field. */
1837#define FSL_FEATURE_RTC_HAS_TSIC (0)
1838/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
1839#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
1840
1841/* SDHC module features */
1842
1843/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
1844#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1)
1845/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
1846#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (1)
1847/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
1848#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (1)
1849
1850/* SIM module features */
1851
1852/* @brief Has USB FS divider. */
1853#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1854/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1855#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1)
1856/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1857#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
1858/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1859#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1860/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1861#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1862/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1863#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1864/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1865#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
1866/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1867#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
1868/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1869#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1870/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1871#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
1872/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1873#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
1874/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1875#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1876/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1877#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1878/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1879#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1880/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1881#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
1882/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1883#define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
1884/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1885#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
1886/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1887#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
1888/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1889#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
1890/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1891#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1892/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1893#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1894/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1895#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1896/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1897#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1898/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1899#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1900/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1901#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1902/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1903#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1904/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1905#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
1906/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1907#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
1908/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1909#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
1910/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1911#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
1912/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1913#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
1914/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1915#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
1916/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1917#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
1918/* @brief Has FTM module(s) configuration. */
1919#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
1920/* @brief Number of FTM modules. */
1921#define FSL_FEATURE_SIM_OPT_FTM_COUNT (3)
1922/* @brief Number of FTM triggers with selectable source. */
1923#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
1924/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1925#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
1926/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1927#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
1928/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1929#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
1930/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1931#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
1932/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1933#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1934/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1935#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1936/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1937#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
1938/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1939#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
1940/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1941#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
1942/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1943#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
1944/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1945#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1946/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1947#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1948/* @brief Has TPM module(s) configuration. */
1949#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
1950/* @brief The highest TPM module index. */
1951#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
1952/* @brief Has TPM module with index 0. */
1953#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1954/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1955#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
1956/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1957#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1958/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1959#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
1960/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1961#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
1962/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1963#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
1964/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1965#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1966/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1967#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1968/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1969#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
1970/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1971#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
1972/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1973#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1974/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1975#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1976/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1977#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
1978/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1979#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1980/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1981#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
1982/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1983#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
1984/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1985#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
1986/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1987#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1988/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1989#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1990/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1991#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1992/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1993#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1994/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1995#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1996/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1997#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1998/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1999#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
2000/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
2001#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
2002/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
2003#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
2004/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
2005#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
2006/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
2007#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
2008/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
2009#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1)
2010/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
2011#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
2012/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
2013#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
2014/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
2015#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
2016/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
2017#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
2018/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
2019#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
2020/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
2021#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
2022/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
2023#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
2024/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
2025#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
2026/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
2027#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
2028/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
2029#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
2030/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
2031#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
2032/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
2033#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
2034/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
2035#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
2036/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
2037#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
2038/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
2039#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
2040/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
2041#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
2042/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
2043#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
2044/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
2045#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
2046/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
2047#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
2048/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
2049#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
2050/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
2051#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
2052/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
2053#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
2054/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
2055#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (0)
2056/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
2057#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0)
2058/* @brief Has device die ID (register bit field SDID[DIEID]). */
2059#define FSL_FEATURE_SIM_SDID_HAS_DIEID (0)
2060/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
2061#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
2062/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
2063#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
2064/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
2065#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
2066/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
2067#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
2068/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
2069#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
2070/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
2071#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
2072/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
2073#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
2074/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
2075#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
2076/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
2077#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
2078/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
2079#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
2080/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
2081#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
2082/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
2083#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
2084/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
2085#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1)
2086/* @brief Has miscellanious control register (register MCR). */
2087#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
2088/* @brief Has COP watchdog (registers COPC and SRVCOP). */
2089#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
2090/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
2091#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
2092/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
2093#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (1)
2094
2095/* SMC module features */
2096
2097/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
2098#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
2099/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
2100#define FSL_FEATURE_SMC_HAS_LPOPO (0)
2101/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
2102#define FSL_FEATURE_SMC_HAS_PORPO (0)
2103/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
2104#define FSL_FEATURE_SMC_HAS_LPWUI (1)
2105/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
2106#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
2107/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
2108#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
2109/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
2110#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
2111/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
2112#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
2113/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
2114#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
2115/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
2116#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
2117/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
2118#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
2119/* @brief Has stop submode. */
2120#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
2121/* @brief Has stop submode 0(VLLS0). */
2122#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (0)
2123/* @brief Has stop submode 2(VLLS2). */
2124#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
2125/* @brief Has SMC_PARAM. */
2126#define FSL_FEATURE_SMC_HAS_PARAM (0)
2127/* @brief Has SMC_VERID. */
2128#define FSL_FEATURE_SMC_HAS_VERID (0)
2129/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
2130#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
2131/* @brief Has tamper reset (register bit SRS[TAMPER]). */
2132#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
2133/* @brief Has security violation reset (register bit SRS[SECVIO]). */
2134#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
2135
2136/* DSPI module features */
2137
2138/* @brief Receive/transmit FIFO size in number of items. */
2139#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4)
2140/* @brief Maximum transfer data width in bits. */
2141#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
2142/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
2143#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
2144/* @brief Number of chip select pins. */
2145#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
2146/* @brief Has chip select strobe capability on the PCS5 pin. */
2147#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
2148/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
2149#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
2150/* @brief Has 16-bit data transfer support. */
2151#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
2152/* @brief Has separate DMA RX and TX requests. */
2153#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
2154
2155/* SYSMPU module features */
2156
2157/* @brief Specifies number of descriptors available. */
2158#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12)
2159/* @brief Has process identifier support. */
2160#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (0)
2161/* @brief Total number of MPU slave. */
2162#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5)
2163/* @brief Total number of MPU master. */
2164#define FSL_FEATURE_SYSMPU_MASTER_COUNT (6)
2165
2166/* SysTick module features */
2167
2168/* @brief Systick has external reference clock. */
2169#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
2170/* @brief Systick external reference clock is core clock divided by this value. */
2171#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
2172
2173/* TSI module features */
2174
2175/* @brief TSI module version. */
2176#define FSL_FEATURE_TSI_VERSION (2)
2177/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
2178#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0)
2179/* @brief Number of TSI channels. */
2180#define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
2181
2182/* UART module features */
2183
2184#if defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DN512VLL10) || defined(CPU_MK60DX256VLL10)
2185 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
2186 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
2187 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
2188 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
2189 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
2190 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
2191 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
2192 #define FSL_FEATURE_UART_HAS_FIFO (1)
2193 /* @brief Hardware flow control (RTS, CTS) is supported. */
2194 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
2195 /* @brief Infrared (modulation) is supported. */
2196 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
2197 /* @brief 2 bits long stop bit is available. */
2198 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
2199 /* @brief If 10-bit mode is supported. */
2200 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
2201 /* @brief Baud rate fine adjustment is available. */
2202 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
2203 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
2204 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
2205 /* @brief Baud rate oversampling is available. */
2206 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
2207 /* @brief Baud rate oversampling is available. */
2208 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
2209 /* @brief Peripheral type. */
2210 #define FSL_FEATURE_UART_IS_SCI (0)
2211 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
2212 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
2213 ((x) == UART0 ? (8) : \
2214 ((x) == UART1 ? (8) : \
2215 ((x) == UART2 ? (1) : \
2216 ((x) == UART3 ? (1) : \
2217 ((x) == UART4 ? (1) : (-1))))))
2218 /* @brief Maximal data width without parity bit. */
2219 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
2220 /* @brief Maximal data width with parity bit. */
2221 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
2222 /* @brief Supports two match addresses to filter incoming frames. */
2223 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
2224 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
2225 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
2226 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
2227 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
2228 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
2229 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
2230 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
2231 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
2232 /* @brief Has improved smart card (ISO7816 protocol) support. */
2233 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
2234 /* @brief Has local operation network (CEA709.1-B protocol) support. */
2235 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1)
2236 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
2237 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
2238 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
2239 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
2240 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
2241 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
2242 /* @brief Has separate DMA RX and TX requests. */
2243 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
2244#elif defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DN512VLQ10) || \
2245 defined(CPU_MK60DN512VMC10) || defined(CPU_MK60DN512VMD10) || defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DX256VMC10) || \
2246 defined(CPU_MK60DX256VMD10)
2247 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
2248 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
2249 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
2250 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
2251 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
2252 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
2253 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
2254 #define FSL_FEATURE_UART_HAS_FIFO (1)
2255 /* @brief Hardware flow control (RTS, CTS) is supported. */
2256 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
2257 /* @brief Infrared (modulation) is supported. */
2258 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
2259 /* @brief 2 bits long stop bit is available. */
2260 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
2261 /* @brief If 10-bit mode is supported. */
2262 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
2263 /* @brief Baud rate fine adjustment is available. */
2264 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
2265 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
2266 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
2267 /* @brief Baud rate oversampling is available. */
2268 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
2269 /* @brief Baud rate oversampling is available. */
2270 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
2271 /* @brief Peripheral type. */
2272 #define FSL_FEATURE_UART_IS_SCI (0)
2273 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
2274 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
2275 ((x) == UART0 ? (8) : \
2276 ((x) == UART1 ? (8) : \
2277 ((x) == UART2 ? (1) : \
2278 ((x) == UART3 ? (1) : \
2279 ((x) == UART4 ? (1) : \
2280 ((x) == UART5 ? (1) : (-1)))))))
2281 /* @brief Maximal data width without parity bit. */
2282 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
2283 /* @brief Maximal data width with parity bit. */
2284 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
2285 /* @brief Supports two match addresses to filter incoming frames. */
2286 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
2287 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
2288 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
2289 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
2290 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
2291 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
2292 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
2293 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
2294 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
2295 /* @brief Has improved smart card (ISO7816 protocol) support. */
2296 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
2297 /* @brief Has local operation network (CEA709.1-B protocol) support. */
2298 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1)
2299 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
2300 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
2301 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
2302 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
2303 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
2304 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
2305 /* @brief Has separate DMA RX and TX requests. */
2306 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
2307#endif /* defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DN512VLL10) || defined(CPU_MK60DX256VLL10) */
2308
2309/* USB module features */
2310
2311/* @brief KHCI module instance count */
2312#define FSL_FEATURE_USB_KHCI_COUNT (1)
2313/* @brief HOST mode enabled */
2314#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
2315/* @brief OTG mode enabled */
2316#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
2317/* @brief Size of the USB dedicated RAM */
2318#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
2319/* @brief Has KEEP_ALIVE_CTRL register */
2320#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
2321/* @brief Has the Dynamic SOF threshold compare support */
2322#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
2323/* @brief Has the VBUS detect support */
2324#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
2325/* @brief Has the IRC48M module clock support */
2326#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0)
2327/* @brief Number of endpoints supported */
2328#define FSL_FEATURE_USB_ENDPT_COUNT (16)
2329
2330/* VREF module features */
2331
2332/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
2333#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
2334/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
2335#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
2336/* @brief If high/low buffer mode supported */
2337#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
2338/* @brief Module has also low reference (registers VREFL/VREFH) */
2339#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
2340/* @brief Has VREF_TRM4. */
2341#define FSL_FEATURE_VREF_HAS_TRM4 (0)
2342
2343/* WDOG module features */
2344
2345/* @brief Watchdog is available. */
2346#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
2347/* @brief Has Wait mode support. */
2348#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
2349
2350#endif /* _MK60D10_FEATURES_H_ */
2351