mikroSDK Reference Manual
MKV58F24_features.h
1/*
2** ###################################################################
3** Version: rev. 0.3, 2015-06-08
4** Build: b200409
5**
6** Abstract:
7** Chip specific module features.
8**
9** Copyright 2016 Freescale Semiconductor, Inc.
10** Copyright 2016-2020 NXP
11** All rights reserved.
12**
13** SPDX-License-Identifier: BSD-3-Clause
14**
15** http: www.nxp.com
16** mail: support@nxp.com
17**
18** Revisions:
19** - rev. 0.1 (2015-02-24)
20** Initial version.
21** - rev. 0.2 (2015-05-25)
22** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
23** - rev. 0.3 (2015-06-08)
24** FTM features BUS_CLOCK and FAST_CLOCK removed.
25**
26** ###################################################################
27*/
28
29#ifndef _MKV58F24_FEATURES_H_
30#define _MKV58F24_FEATURES_H_
31
32/* SOC module features */
33
34#if defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F512VLL24)
35 /* @brief ADC16 availability on the SoC. */
36 #define FSL_FEATURE_SOC_ADC16_COUNT (1)
37 /* @brief AIPS availability on the SoC. */
38 #define FSL_FEATURE_SOC_AIPS_COUNT (2)
39 /* @brief AOI availability on the SoC. */
40 #define FSL_FEATURE_SOC_AOI_COUNT (1)
41 /* @brief AXBS availability on the SoC. */
42 #define FSL_FEATURE_SOC_AXBS_COUNT (1)
43 /* @brief FLEXCAN availability on the SoC. */
44 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (3)
45 /* @brief MMCAU availability on the SoC. */
46 #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
47 /* @brief CMP availability on the SoC. */
48 #define FSL_FEATURE_SOC_CMP_COUNT (4)
49 /* @brief CRC availability on the SoC. */
50 #define FSL_FEATURE_SOC_CRC_COUNT (1)
51 /* @brief DAC availability on the SoC. */
52 #define FSL_FEATURE_SOC_DAC_COUNT (1)
53 /* @brief EDMA availability on the SoC. */
54 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
55 /* @brief DMAMUX availability on the SoC. */
56 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
57 /* @brief DSPI availability on the SoC. */
58 #define FSL_FEATURE_SOC_DSPI_COUNT (3)
59 /* @brief ENC availability on the SoC. */
60 #define FSL_FEATURE_SOC_ENC_COUNT (1)
61 /* @brief ENET availability on the SoC. */
62 #define FSL_FEATURE_SOC_ENET_COUNT (1)
63 /* @brief EWM availability on the SoC. */
64 #define FSL_FEATURE_SOC_EWM_COUNT (1)
65 /* @brief FB availability on the SoC. */
66 #define FSL_FEATURE_SOC_FB_COUNT (1)
67 /* @brief FMC availability on the SoC. */
68 #define FSL_FEATURE_SOC_FMC_COUNT (1)
69 /* @brief FTFE availability on the SoC. */
70 #define FSL_FEATURE_SOC_FTFE_COUNT (1)
71 /* @brief FTM availability on the SoC. */
72 #define FSL_FEATURE_SOC_FTM_COUNT (4)
73 /* @brief GPIO availability on the SoC. */
74 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
75 /* @brief HSADC availability on the SoC. */
76 #define FSL_FEATURE_SOC_HSADC_COUNT (2)
77 /* @brief I2C availability on the SoC. */
78 #define FSL_FEATURE_SOC_I2C_COUNT (2)
79 /* @brief LLWU availability on the SoC. */
80 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
81 /* @brief LPTMR availability on the SoC. */
82 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
83 /* @brief MCG availability on the SoC. */
84 #define FSL_FEATURE_SOC_MCG_COUNT (1)
85 /* @brief MCM availability on the SoC. */
86 #define FSL_FEATURE_SOC_MCM_COUNT (1)
87 /* @brief SYSMPU availability on the SoC. */
88 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
89 /* @brief MSCM availability on the SoC. */
90 #define FSL_FEATURE_SOC_MSCM_COUNT (1)
91 /* @brief OSC availability on the SoC. */
92 #define FSL_FEATURE_SOC_OSC_COUNT (1)
93 /* @brief PDB availability on the SoC. */
94 #define FSL_FEATURE_SOC_PDB_COUNT (2)
95 /* @brief PIT availability on the SoC. */
96 #define FSL_FEATURE_SOC_PIT_COUNT (1)
97 /* @brief PMC availability on the SoC. */
98 #define FSL_FEATURE_SOC_PMC_COUNT (1)
99 /* @brief PORT availability on the SoC. */
100 #define FSL_FEATURE_SOC_PORT_COUNT (5)
101 /* @brief PWM availability on the SoC. */
102 #define FSL_FEATURE_SOC_PWM_COUNT (2)
103 /* @brief RCM availability on the SoC. */
104 #define FSL_FEATURE_SOC_RCM_COUNT (1)
105 /* @brief RFSYS availability on the SoC. */
106 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
107 /* @brief RFVBAT availability on the SoC. */
108 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
109 /* @brief SIM availability on the SoC. */
110 #define FSL_FEATURE_SOC_SIM_COUNT (1)
111 /* @brief SMC availability on the SoC. */
112 #define FSL_FEATURE_SOC_SMC_COUNT (1)
113 /* @brief TRNG availability on the SoC. */
114 #define FSL_FEATURE_SOC_TRNG_COUNT (1)
115 /* @brief UART availability on the SoC. */
116 #define FSL_FEATURE_SOC_UART_COUNT (5)
117 /* @brief WDOG availability on the SoC. */
118 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
119 /* @brief XBARA availability on the SoC. */
120 #define FSL_FEATURE_SOC_XBARA_COUNT (1)
121 /* @brief XBARB availability on the SoC. */
122 #define FSL_FEATURE_SOC_XBARB_COUNT (1)
123#elif defined(CPU_MKV58F1M0VLQ24) || defined(CPU_MKV58F1M0VMD24) || defined(CPU_MKV58F512VLQ24) || defined(CPU_MKV58F512VMD24)
124 /* @brief ADC16 availability on the SoC. */
125 #define FSL_FEATURE_SOC_ADC16_COUNT (1)
126 /* @brief AIPS availability on the SoC. */
127 #define FSL_FEATURE_SOC_AIPS_COUNT (2)
128 /* @brief AOI availability on the SoC. */
129 #define FSL_FEATURE_SOC_AOI_COUNT (1)
130 /* @brief AXBS availability on the SoC. */
131 #define FSL_FEATURE_SOC_AXBS_COUNT (1)
132 /* @brief FLEXCAN availability on the SoC. */
133 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (3)
134 /* @brief MMCAU availability on the SoC. */
135 #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
136 /* @brief CMP availability on the SoC. */
137 #define FSL_FEATURE_SOC_CMP_COUNT (4)
138 /* @brief CRC availability on the SoC. */
139 #define FSL_FEATURE_SOC_CRC_COUNT (1)
140 /* @brief DAC availability on the SoC. */
141 #define FSL_FEATURE_SOC_DAC_COUNT (1)
142 /* @brief EDMA availability on the SoC. */
143 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
144 /* @brief DMAMUX availability on the SoC. */
145 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
146 /* @brief DSPI availability on the SoC. */
147 #define FSL_FEATURE_SOC_DSPI_COUNT (3)
148 /* @brief ENC availability on the SoC. */
149 #define FSL_FEATURE_SOC_ENC_COUNT (1)
150 /* @brief ENET availability on the SoC. */
151 #define FSL_FEATURE_SOC_ENET_COUNT (1)
152 /* @brief EWM availability on the SoC. */
153 #define FSL_FEATURE_SOC_EWM_COUNT (1)
154 /* @brief FB availability on the SoC. */
155 #define FSL_FEATURE_SOC_FB_COUNT (1)
156 /* @brief FMC availability on the SoC. */
157 #define FSL_FEATURE_SOC_FMC_COUNT (1)
158 /* @brief FTFE availability on the SoC. */
159 #define FSL_FEATURE_SOC_FTFE_COUNT (1)
160 /* @brief FTM availability on the SoC. */
161 #define FSL_FEATURE_SOC_FTM_COUNT (4)
162 /* @brief GPIO availability on the SoC. */
163 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
164 /* @brief HSADC availability on the SoC. */
165 #define FSL_FEATURE_SOC_HSADC_COUNT (2)
166 /* @brief I2C availability on the SoC. */
167 #define FSL_FEATURE_SOC_I2C_COUNT (2)
168 /* @brief LLWU availability on the SoC. */
169 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
170 /* @brief LPTMR availability on the SoC. */
171 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
172 /* @brief MCG availability on the SoC. */
173 #define FSL_FEATURE_SOC_MCG_COUNT (1)
174 /* @brief MCM availability on the SoC. */
175 #define FSL_FEATURE_SOC_MCM_COUNT (1)
176 /* @brief SYSMPU availability on the SoC. */
177 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
178 /* @brief MSCM availability on the SoC. */
179 #define FSL_FEATURE_SOC_MSCM_COUNT (1)
180 /* @brief OSC availability on the SoC. */
181 #define FSL_FEATURE_SOC_OSC_COUNT (1)
182 /* @brief PDB availability on the SoC. */
183 #define FSL_FEATURE_SOC_PDB_COUNT (2)
184 /* @brief PIT availability on the SoC. */
185 #define FSL_FEATURE_SOC_PIT_COUNT (1)
186 /* @brief PMC availability on the SoC. */
187 #define FSL_FEATURE_SOC_PMC_COUNT (1)
188 /* @brief PORT availability on the SoC. */
189 #define FSL_FEATURE_SOC_PORT_COUNT (5)
190 /* @brief PWM availability on the SoC. */
191 #define FSL_FEATURE_SOC_PWM_COUNT (2)
192 /* @brief RCM availability on the SoC. */
193 #define FSL_FEATURE_SOC_RCM_COUNT (1)
194 /* @brief RFSYS availability on the SoC. */
195 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
196 /* @brief RFVBAT availability on the SoC. */
197 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
198 /* @brief SIM availability on the SoC. */
199 #define FSL_FEATURE_SOC_SIM_COUNT (1)
200 /* @brief SMC availability on the SoC. */
201 #define FSL_FEATURE_SOC_SMC_COUNT (1)
202 /* @brief TRNG availability on the SoC. */
203 #define FSL_FEATURE_SOC_TRNG_COUNT (1)
204 /* @brief UART availability on the SoC. */
205 #define FSL_FEATURE_SOC_UART_COUNT (6)
206 /* @brief WDOG availability on the SoC. */
207 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
208 /* @brief XBARA availability on the SoC. */
209 #define FSL_FEATURE_SOC_XBARA_COUNT (1)
210 /* @brief XBARB availability on the SoC. */
211 #define FSL_FEATURE_SOC_XBARB_COUNT (1)
212#endif
213
214/* ADC16 module features */
215
216/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
217#define FSL_FEATURE_ADC16_HAS_PGA (0)
218/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
219#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
220/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
221#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
222/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
223#define FSL_FEATURE_ADC16_HAS_DMA (1)
224/* @brief Has differential mode (bitfield SC1x[DIFF]). */
225#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
226/* @brief Has FIFO (bit SC4[AFDEP]). */
227#define FSL_FEATURE_ADC16_HAS_FIFO (0)
228/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
229#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
230/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
231#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
232/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
233#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
234/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
235#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
236/* @brief Has HW averaging (bit SC3[AVGE]). */
237#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
238/* @brief Has offset correction (register OFS). */
239#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
240/* @brief Maximum ADC resolution. */
241#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
242/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
243#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
244
245/* AOI module features */
246
247/* @brief Maximum value of AOI0 input mux. */
248#define FSL_FEATURE_AOI_MODULE_INPUTS (4)
249/* @brief Number of AOI0 events (related to number of registers AOI0_BFCRT01n/AOI0_BFCRT23n). */
250#define FSL_FEATURE_AOI_EVENT_COUNT (4)
251
252/* FLEXCAN module features */
253
254/* @brief Message buffer size */
255#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16)
256/* @brief Has doze mode support (register bit field MCR[DOZE]). */
257#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1)
258/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
259#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1)
260/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
261#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
262/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
263#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
264/* @brief Instance has extended bit timing register (register CBT). */
265#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1)
266/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
267#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1)
268/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
269#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1)
270/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
271#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
272/* @brief Has bitfield name BUF31TO0M. */
273#define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (1)
274/* @brief Number of interrupt vectors. */
275#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
276/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
277#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
278
279/* CMP module features */
280
281/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
282#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
283/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
284#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
285/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
286#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
287/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
288#define FSL_FEATURE_CMP_HAS_DMA (1)
289/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
290#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
291/* @brief Has DAC Test function in CMP (register DACTEST). */
292#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
293
294/* CRC module features */
295
296/* @brief Has data register with name CRC */
297#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
298
299/* DAC module features */
300
301/* @brief Define the size of hardware buffer */
302#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
303/* @brief Define whether the buffer supports watermark event detection or not. */
304#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
305/* @brief Define whether the buffer supports watermark selection detection or not. */
306#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
307/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
308#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
309/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
310#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
311/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
312#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
313/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
314#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
315/* @brief Define whether FIFO buffer mode is available or not. */
316#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1)
317/* @brief Define whether swing buffer mode is available or not.. */
318#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
319
320/* EDMA module features */
321
322/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
323#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
324/* @brief Total number of DMA channels on all modules. */
325#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 32)
326/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
327#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2)
328/* @brief Has DMA_Error interrupt vector. */
329#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
330/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
331#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
332/* @brief Channel IRQ entry shared offset. */
333#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16)
334/* @brief If 8 bytes transfer supported. */
335#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0)
336/* @brief If 16 bytes transfer supported. */
337#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
338
339/* DMAMUX module features */
340
341/* @brief Number of DMA channels (related to number of register CHCFGn). */
342#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
343/* @brief Total number of DMA channels on all modules. */
344#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32)
345/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
346#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
347
348/* ENC module features */
349
350/* No feature definitions */
351
352/* ENET module features */
353
354/* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */
355#define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0)
356/* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */
357#define FSL_FEATURE_ENET_SUPPORT_PTP (1)
358/* @brief Number of associated interrupt vectors. */
359#define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
360/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
361#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
362/* @brief Has Extend MDIO Support. */
363#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
364
365/* EWM module features */
366
367/* @brief Has clock select (register CLKCTRL). */
368#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1)
369/* @brief Has clock prescaler (register CLKPRESCALER). */
370#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
371
372/* FLEXBUS module features */
373
374/* No feature definitions */
375
376/* FLASH module features */
377
378#if defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F1M0VLQ24) || defined(CPU_MKV58F1M0VMD24)
379 /* @brief Is of type FTFA. */
380 #define FSL_FEATURE_FLASH_IS_FTFA (0)
381 /* @brief Is of type FTFE. */
382 #define FSL_FEATURE_FLASH_IS_FTFE (1)
383 /* @brief Is of type FTFL. */
384 #define FSL_FEATURE_FLASH_IS_FTFL (0)
385 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
386 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
387 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
388 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
389 /* @brief Has EEPROM region protection (register FEPROT). */
390 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
391 /* @brief Has data flash region protection (register FDPROT). */
392 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
393 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
394 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
395 /* @brief Has flash cache control in FMC module. */
396 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
397 /* @brief Has flash cache control in MCM module. */
398 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
399 /* @brief Has flash cache control in MSCM module. */
400 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
401 /* @brief Has prefetch speculation control in flash, such as kv5x. */
402 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (1)
403 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
404 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
405 /* @brief P-Flash start address. */
406 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x10000000)
407 /* @brief P-Flash block count. */
408 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
409 /* @brief P-Flash block size. */
410 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (1048576)
411 /* @brief P-Flash sector size. */
412 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (8192)
413 /* @brief P-Flash write unit size. */
414 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
415 /* @brief P-Flash data path width. */
416 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (32)
417 /* @brief P-Flash block swap feature. */
418 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
419 /* @brief P-Flash protection region count. */
420 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
421 /* @brief Has FlexNVM memory. */
422 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
423 /* @brief Has FlexNVM alias. */
424 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
425 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
426 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
427 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
428 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
429 /* @brief FlexNVM block count. */
430 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
431 /* @brief FlexNVM block size. */
432 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
433 /* @brief FlexNVM sector size. */
434 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
435 /* @brief FlexNVM write unit size. */
436 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
437 /* @brief FlexNVM data path width. */
438 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
439 /* @brief Has FlexRAM memory. */
440 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
441 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
442 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x18000000)
443 /* @brief FlexRAM size. */
444 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
445 /* @brief Has 0x00 Read 1s Block command. */
446 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
447 /* @brief Has 0x01 Read 1s Section command. */
448 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
449 /* @brief Has 0x02 Program Check command. */
450 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
451 /* @brief Has 0x03 Read Resource command. */
452 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
453 /* @brief Has 0x06 Program Longword command. */
454 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
455 /* @brief Has 0x07 Program Phrase command. */
456 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
457 /* @brief Has 0x08 Erase Flash Block command. */
458 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
459 /* @brief Has 0x09 Erase Flash Sector command. */
460 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
461 /* @brief Has 0x0B Program Section command. */
462 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
463 /* @brief Has 0x40 Read 1s All Blocks command. */
464 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
465 /* @brief Has 0x41 Read Once command. */
466 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
467 /* @brief Has 0x43 Program Once command. */
468 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
469 /* @brief Has 0x44 Erase All Blocks command. */
470 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
471 /* @brief Has 0x45 Verify Backdoor Access Key command. */
472 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
473 /* @brief Has 0x46 Swap Control command. */
474 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
475 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
476 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
477 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
478 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
479 /* @brief Has 0x4B Erase All Execute-only Segments command. */
480 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
481 /* @brief Has 0x80 Program Partition command. */
482 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
483 /* @brief Has 0x81 Set FlexRAM Function command. */
484 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
485 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
486 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (32)
487 /* @brief P-Flash Erase sector command address alignment. */
488 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (32)
489 /* @brief P-Flash Rrogram/Verify section command address alignment. */
490 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (32)
491 /* @brief P-Flash Read resource command address alignment. */
492 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
493 /* @brief P-Flash Program check command address alignment. */
494 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
495 /* @brief P-Flash Program check command address alignment. */
496 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
497 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
498 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
499 /* @brief FlexNVM Erase sector command address alignment. */
500 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
501 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
502 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
503 /* @brief FlexNVM Read resource command address alignment. */
504 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
505 /* @brief FlexNVM Program check command address alignment. */
506 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
507 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
508 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
509 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
510 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
511 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
512 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
513 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
514 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
515 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
516 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
517 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
518 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
519 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
520 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
521 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
522 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
523 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
524 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
525 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
526 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
527 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
528 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
529 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
530 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
531 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
532 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
533 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
534 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
535 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
536 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
537 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
538 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
539 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
540 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
541 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
542 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
543 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
544 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
545 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
546 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
547 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
548 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
549 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
550 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
551 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
552 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
553 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
554 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
555 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
556 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
557 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
558 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
559 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
560 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
561 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
562 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
563 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
564 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
565 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
566 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
567 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
568 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
569 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
570 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
571#elif defined(CPU_MKV58F512VLL24) || defined(CPU_MKV58F512VLQ24) || defined(CPU_MKV58F512VMD24)
572 /* @brief Is of type FTFA. */
573 #define FSL_FEATURE_FLASH_IS_FTFA (0)
574 /* @brief Is of type FTFE. */
575 #define FSL_FEATURE_FLASH_IS_FTFE (1)
576 /* @brief Is of type FTFL. */
577 #define FSL_FEATURE_FLASH_IS_FTFL (0)
578 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
579 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
580 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
581 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
582 /* @brief Has EEPROM region protection (register FEPROT). */
583 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
584 /* @brief Has data flash region protection (register FDPROT). */
585 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
586 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
587 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
588 /* @brief Has flash cache control in FMC module. */
589 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
590 /* @brief Has flash cache control in MCM module. */
591 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
592 /* @brief Has flash cache control in MSCM module. */
593 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
594 /* @brief Has prefetch speculation control in flash, such as kv5x. */
595 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (1)
596 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
597 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
598 /* @brief P-Flash start address. */
599 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x10000000)
600 /* @brief P-Flash block count. */
601 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
602 /* @brief P-Flash block size. */
603 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
604 /* @brief P-Flash sector size. */
605 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (8192)
606 /* @brief P-Flash write unit size. */
607 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
608 /* @brief P-Flash data path width. */
609 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (32)
610 /* @brief P-Flash block swap feature. */
611 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
612 /* @brief P-Flash protection region count. */
613 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
614 /* @brief Has FlexNVM memory. */
615 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
616 /* @brief Has FlexNVM alias. */
617 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
618 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
619 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
620 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
621 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
622 /* @brief FlexNVM block count. */
623 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
624 /* @brief FlexNVM block size. */
625 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
626 /* @brief FlexNVM sector size. */
627 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
628 /* @brief FlexNVM write unit size. */
629 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
630 /* @brief FlexNVM data path width. */
631 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
632 /* @brief Has FlexRAM memory. */
633 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
634 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
635 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x18000000)
636 /* @brief FlexRAM size. */
637 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
638 /* @brief Has 0x00 Read 1s Block command. */
639 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
640 /* @brief Has 0x01 Read 1s Section command. */
641 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
642 /* @brief Has 0x02 Program Check command. */
643 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
644 /* @brief Has 0x03 Read Resource command. */
645 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
646 /* @brief Has 0x06 Program Longword command. */
647 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
648 /* @brief Has 0x07 Program Phrase command. */
649 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
650 /* @brief Has 0x08 Erase Flash Block command. */
651 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
652 /* @brief Has 0x09 Erase Flash Sector command. */
653 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
654 /* @brief Has 0x0B Program Section command. */
655 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
656 /* @brief Has 0x40 Read 1s All Blocks command. */
657 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
658 /* @brief Has 0x41 Read Once command. */
659 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
660 /* @brief Has 0x43 Program Once command. */
661 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
662 /* @brief Has 0x44 Erase All Blocks command. */
663 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
664 /* @brief Has 0x45 Verify Backdoor Access Key command. */
665 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
666 /* @brief Has 0x46 Swap Control command. */
667 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
668 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
669 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
670 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
671 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
672 /* @brief Has 0x4B Erase All Execute-only Segments command. */
673 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
674 /* @brief Has 0x80 Program Partition command. */
675 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
676 /* @brief Has 0x81 Set FlexRAM Function command. */
677 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
678 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
679 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (32)
680 /* @brief P-Flash Erase sector command address alignment. */
681 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (32)
682 /* @brief P-Flash Rrogram/Verify section command address alignment. */
683 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (32)
684 /* @brief P-Flash Read resource command address alignment. */
685 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
686 /* @brief P-Flash Program check command address alignment. */
687 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
688 /* @brief P-Flash Program check command address alignment. */
689 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
690 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
691 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
692 /* @brief FlexNVM Erase sector command address alignment. */
693 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
694 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
695 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
696 /* @brief FlexNVM Read resource command address alignment. */
697 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
698 /* @brief FlexNVM Program check command address alignment. */
699 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
700 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
701 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
702 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
703 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
704 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
705 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
706 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
707 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
708 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
709 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
710 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
711 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
712 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
713 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
714 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
715 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
716 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
717 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
718 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
719 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
720 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
721 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
722 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
723 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
724 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
725 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
726 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
727 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
728 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
729 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
730 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
731 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
732 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
733 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
734 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
735 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
736 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
737 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
738 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
739 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
740 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
741 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
742 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
743 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
744 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
745 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
746 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
747 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
748 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
749 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
750 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
751 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
752 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
753 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
754 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
755 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
756 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
757 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
758 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
759 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
760 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
761 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
762 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
763 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
764#endif /* defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F1M0VLQ24) || defined(CPU_MKV58F1M0VMD24) */
765
766/* FTM module features */
767
768/* @brief Number of channels. */
769#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
770 (((x) == FTM0) ? (8) : \
771 (((x) == FTM1) ? (2) : \
772 (((x) == FTM2) ? (2) : \
773 (((x) == FTM3) ? (8) : (-1)))))
774/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
775#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
776/* @brief Has extended deadtime value. */
777#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0)
778/* @brief Enable pwm output for the module. */
779#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
780/* @brief Has half-cycle reload for the module. */
781#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0)
782/* @brief Has reload interrupt. */
783#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0)
784/* @brief Has reload initialization trigger. */
785#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
786/* @brief Has DMA support, bitfield CnSC[DMA]. */
787#define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1)
788/* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */
789#define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0)
790/* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */
791#define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0)
792/* @brief Has no QDCTRL. */
793#define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0)
794/* @brief If instance has only TPM function. */
795#define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0)
796
797/* GPIO module features */
798
799/* @brief Has GPIO attribute checker register (GACR). */
800#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
801
802/* I2C module features */
803
804/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
805#define FSL_FEATURE_I2C_HAS_SMBUS (1)
806/* @brief Maximum supported baud rate in kilobit per second. */
807#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100)
808/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
809#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
810/* @brief Has DMA support (register bit C1[DMAEN]). */
811#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
812/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
813#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
814/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
815#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
816/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
817#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
818/* @brief Maximum width of the glitch filter in number of bus clocks. */
819#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
820/* @brief Has control of the drive capability of the I2C pins. */
821#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
822/* @brief Has double buffering support (register S2). */
823#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
824/* @brief Has double buffer enable. */
825#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
826
827/* LLWU module features */
828
829#if defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F512VLL24)
830 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
831 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (22)
832 /* @brief Has pins 8-15 connected to LLWU device. */
833 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
834 /* @brief Maximum number of internal modules connected to LLWU device. */
835 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (4)
836 /* @brief Number of digital filters. */
837 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
838 /* @brief Has MF register. */
839 #define FSL_FEATURE_LLWU_HAS_MF (1)
840 /* @brief Has PF register. */
841 #define FSL_FEATURE_LLWU_HAS_PF (1)
842 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
843 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
844 /* @brief Has no internal module wakeup flag register. */
845 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
846 /* @brief Has external pin 0 connected to LLWU device. */
847 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
848 /* @brief Index of port of external pin. */
849 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
850 /* @brief Number of external pin port on specified port. */
851 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
852 /* @brief Has external pin 1 connected to LLWU device. */
853 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
854 /* @brief Index of port of external pin. */
855 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
856 /* @brief Number of external pin port on specified port. */
857 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
858 /* @brief Has external pin 2 connected to LLWU device. */
859 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
860 /* @brief Index of port of external pin. */
861 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
862 /* @brief Number of external pin port on specified port. */
863 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
864 /* @brief Has external pin 3 connected to LLWU device. */
865 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
866 /* @brief Index of port of external pin. */
867 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
868 /* @brief Number of external pin port on specified port. */
869 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
870 /* @brief Has external pin 4 connected to LLWU device. */
871 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
872 /* @brief Index of port of external pin. */
873 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
874 /* @brief Number of external pin port on specified port. */
875 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
876 /* @brief Has external pin 5 connected to LLWU device. */
877 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
878 /* @brief Index of port of external pin. */
879 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
880 /* @brief Number of external pin port on specified port. */
881 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
882 /* @brief Has external pin 6 connected to LLWU device. */
883 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
884 /* @brief Index of port of external pin. */
885 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
886 /* @brief Number of external pin port on specified port. */
887 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
888 /* @brief Has external pin 7 connected to LLWU device. */
889 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
890 /* @brief Index of port of external pin. */
891 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
892 /* @brief Number of external pin port on specified port. */
893 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
894 /* @brief Has external pin 8 connected to LLWU device. */
895 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
896 /* @brief Index of port of external pin. */
897 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
898 /* @brief Number of external pin port on specified port. */
899 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
900 /* @brief Has external pin 9 connected to LLWU device. */
901 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
902 /* @brief Index of port of external pin. */
903 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
904 /* @brief Number of external pin port on specified port. */
905 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
906 /* @brief Has external pin 10 connected to LLWU device. */
907 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
908 /* @brief Index of port of external pin. */
909 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
910 /* @brief Number of external pin port on specified port. */
911 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
912 /* @brief Has external pin 11 connected to LLWU device. */
913 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
914 /* @brief Index of port of external pin. */
915 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
916 /* @brief Number of external pin port on specified port. */
917 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
918 /* @brief Has external pin 12 connected to LLWU device. */
919 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
920 /* @brief Index of port of external pin. */
921 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
922 /* @brief Number of external pin port on specified port. */
923 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
924 /* @brief Has external pin 13 connected to LLWU device. */
925 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
926 /* @brief Index of port of external pin. */
927 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
928 /* @brief Number of external pin port on specified port. */
929 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
930 /* @brief Has external pin 14 connected to LLWU device. */
931 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
932 /* @brief Index of port of external pin. */
933 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
934 /* @brief Number of external pin port on specified port. */
935 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
936 /* @brief Has external pin 15 connected to LLWU device. */
937 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
938 /* @brief Index of port of external pin. */
939 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
940 /* @brief Number of external pin port on specified port. */
941 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
942 /* @brief Has external pin 16 connected to LLWU device. */
943 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
944 /* @brief Index of port of external pin. */
945 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX)
946 /* @brief Number of external pin port on specified port. */
947 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6)
948 /* @brief Has external pin 17 connected to LLWU device. */
949 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
950 /* @brief Index of port of external pin. */
951 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
952 /* @brief Number of external pin port on specified port. */
953 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
954 /* @brief Has external pin 18 connected to LLWU device. */
955 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
956 /* @brief Index of port of external pin. */
957 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
958 /* @brief Number of external pin port on specified port. */
959 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
960 /* @brief Has external pin 19 connected to LLWU device. */
961 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1)
962 /* @brief Index of port of external pin. */
963 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX)
964 /* @brief Number of external pin port on specified port. */
965 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17)
966 /* @brief Has external pin 20 connected to LLWU device. */
967 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1)
968 /* @brief Index of port of external pin. */
969 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX)
970 /* @brief Number of external pin port on specified port. */
971 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18)
972 /* @brief Has external pin 21 connected to LLWU device. */
973 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1)
974 /* @brief Index of port of external pin. */
975 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX)
976 /* @brief Number of external pin port on specified port. */
977 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25)
978 /* @brief Has external pin 22 connected to LLWU device. */
979 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
980 /* @brief Index of port of external pin. */
981 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
982 /* @brief Number of external pin port on specified port. */
983 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
984 /* @brief Has external pin 23 connected to LLWU device. */
985 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
986 /* @brief Index of port of external pin. */
987 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
988 /* @brief Number of external pin port on specified port. */
989 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
990 /* @brief Has external pin 24 connected to LLWU device. */
991 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
992 /* @brief Index of port of external pin. */
993 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
994 /* @brief Number of external pin port on specified port. */
995 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
996 /* @brief Has external pin 25 connected to LLWU device. */
997 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
998 /* @brief Index of port of external pin. */
999 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
1000 /* @brief Number of external pin port on specified port. */
1001 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
1002 /* @brief Has external pin 26 connected to LLWU device. */
1003 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
1004 /* @brief Index of port of external pin. */
1005 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
1006 /* @brief Number of external pin port on specified port. */
1007 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
1008 /* @brief Has external pin 27 connected to LLWU device. */
1009 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
1010 /* @brief Index of port of external pin. */
1011 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
1012 /* @brief Number of external pin port on specified port. */
1013 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
1014 /* @brief Has external pin 28 connected to LLWU device. */
1015 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
1016 /* @brief Index of port of external pin. */
1017 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
1018 /* @brief Number of external pin port on specified port. */
1019 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
1020 /* @brief Has external pin 29 connected to LLWU device. */
1021 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
1022 /* @brief Index of port of external pin. */
1023 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
1024 /* @brief Number of external pin port on specified port. */
1025 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
1026 /* @brief Has external pin 30 connected to LLWU device. */
1027 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
1028 /* @brief Index of port of external pin. */
1029 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
1030 /* @brief Number of external pin port on specified port. */
1031 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
1032 /* @brief Has external pin 31 connected to LLWU device. */
1033 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
1034 /* @brief Index of port of external pin. */
1035 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
1036 /* @brief Number of external pin port on specified port. */
1037 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
1038 /* @brief Has internal module 0 connected to LLWU device. */
1039 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
1040 /* @brief Has internal module 1 connected to LLWU device. */
1041 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
1042 /* @brief Has internal module 2 connected to LLWU device. */
1043 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
1044 /* @brief Has internal module 3 connected to LLWU device. */
1045 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
1046 /* @brief Has internal module 4 connected to LLWU device. */
1047 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
1048 /* @brief Has internal module 5 connected to LLWU device. */
1049 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0)
1050 /* @brief Has internal module 6 connected to LLWU device. */
1051 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
1052 /* @brief Has internal module 7 connected to LLWU device. */
1053 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0)
1054 /* @brief Has Version ID Register (LLWU_VERID). */
1055 #define FSL_FEATURE_LLWU_HAS_VERID (0)
1056 /* @brief Has Parameter Register (LLWU_PARAM). */
1057 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
1058 /* @brief Width of registers of the LLWU. */
1059 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
1060 /* @brief Has DMA Enable register (LLWU_DE). */
1061 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
1062#elif defined(CPU_MKV58F1M0VLQ24) || defined(CPU_MKV58F1M0VMD24) || defined(CPU_MKV58F512VLQ24) || defined(CPU_MKV58F512VMD24)
1063 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
1064 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (26)
1065 /* @brief Has pins 8-15 connected to LLWU device. */
1066 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
1067 /* @brief Maximum number of internal modules connected to LLWU device. */
1068 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (4)
1069 /* @brief Number of digital filters. */
1070 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
1071 /* @brief Has MF register. */
1072 #define FSL_FEATURE_LLWU_HAS_MF (1)
1073 /* @brief Has PF register. */
1074 #define FSL_FEATURE_LLWU_HAS_PF (1)
1075 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
1076 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
1077 /* @brief Has no internal module wakeup flag register. */
1078 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
1079 /* @brief Has external pin 0 connected to LLWU device. */
1080 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
1081 /* @brief Index of port of external pin. */
1082 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
1083 /* @brief Number of external pin port on specified port. */
1084 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
1085 /* @brief Has external pin 1 connected to LLWU device. */
1086 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
1087 /* @brief Index of port of external pin. */
1088 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
1089 /* @brief Number of external pin port on specified port. */
1090 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
1091 /* @brief Has external pin 2 connected to LLWU device. */
1092 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
1093 /* @brief Index of port of external pin. */
1094 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
1095 /* @brief Number of external pin port on specified port. */
1096 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
1097 /* @brief Has external pin 3 connected to LLWU device. */
1098 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
1099 /* @brief Index of port of external pin. */
1100 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
1101 /* @brief Number of external pin port on specified port. */
1102 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
1103 /* @brief Has external pin 4 connected to LLWU device. */
1104 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
1105 /* @brief Index of port of external pin. */
1106 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
1107 /* @brief Number of external pin port on specified port. */
1108 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
1109 /* @brief Has external pin 5 connected to LLWU device. */
1110 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
1111 /* @brief Index of port of external pin. */
1112 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
1113 /* @brief Number of external pin port on specified port. */
1114 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
1115 /* @brief Has external pin 6 connected to LLWU device. */
1116 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
1117 /* @brief Index of port of external pin. */
1118 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
1119 /* @brief Number of external pin port on specified port. */
1120 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
1121 /* @brief Has external pin 7 connected to LLWU device. */
1122 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
1123 /* @brief Index of port of external pin. */
1124 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
1125 /* @brief Number of external pin port on specified port. */
1126 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
1127 /* @brief Has external pin 8 connected to LLWU device. */
1128 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
1129 /* @brief Index of port of external pin. */
1130 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
1131 /* @brief Number of external pin port on specified port. */
1132 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
1133 /* @brief Has external pin 9 connected to LLWU device. */
1134 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
1135 /* @brief Index of port of external pin. */
1136 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
1137 /* @brief Number of external pin port on specified port. */
1138 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
1139 /* @brief Has external pin 10 connected to LLWU device. */
1140 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
1141 /* @brief Index of port of external pin. */
1142 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
1143 /* @brief Number of external pin port on specified port. */
1144 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
1145 /* @brief Has external pin 11 connected to LLWU device. */
1146 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
1147 /* @brief Index of port of external pin. */
1148 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
1149 /* @brief Number of external pin port on specified port. */
1150 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
1151 /* @brief Has external pin 12 connected to LLWU device. */
1152 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
1153 /* @brief Index of port of external pin. */
1154 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
1155 /* @brief Number of external pin port on specified port. */
1156 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
1157 /* @brief Has external pin 13 connected to LLWU device. */
1158 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
1159 /* @brief Index of port of external pin. */
1160 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
1161 /* @brief Number of external pin port on specified port. */
1162 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
1163 /* @brief Has external pin 14 connected to LLWU device. */
1164 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
1165 /* @brief Index of port of external pin. */
1166 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
1167 /* @brief Number of external pin port on specified port. */
1168 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
1169 /* @brief Has external pin 15 connected to LLWU device. */
1170 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
1171 /* @brief Index of port of external pin. */
1172 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
1173 /* @brief Number of external pin port on specified port. */
1174 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
1175 /* @brief Has external pin 16 connected to LLWU device. */
1176 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
1177 /* @brief Index of port of external pin. */
1178 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX)
1179 /* @brief Number of external pin port on specified port. */
1180 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6)
1181 /* @brief Has external pin 17 connected to LLWU device. */
1182 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
1183 /* @brief Index of port of external pin. */
1184 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX)
1185 /* @brief Number of external pin port on specified port. */
1186 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9)
1187 /* @brief Has external pin 18 connected to LLWU device. */
1188 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
1189 /* @brief Index of port of external pin. */
1190 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX)
1191 /* @brief Number of external pin port on specified port. */
1192 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10)
1193 /* @brief Has external pin 19 connected to LLWU device. */
1194 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1)
1195 /* @brief Index of port of external pin. */
1196 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX)
1197 /* @brief Number of external pin port on specified port. */
1198 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17)
1199 /* @brief Has external pin 20 connected to LLWU device. */
1200 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1)
1201 /* @brief Index of port of external pin. */
1202 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX)
1203 /* @brief Number of external pin port on specified port. */
1204 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18)
1205 /* @brief Has external pin 21 connected to LLWU device. */
1206 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1)
1207 /* @brief Index of port of external pin. */
1208 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX)
1209 /* @brief Number of external pin port on specified port. */
1210 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25)
1211 /* @brief Has external pin 22 connected to LLWU device. */
1212 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
1213 /* @brief Index of port of external pin. */
1214 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX)
1215 /* @brief Number of external pin port on specified port. */
1216 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10)
1217 /* @brief Has external pin 23 connected to LLWU device. */
1218 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
1219 /* @brief Index of port of external pin. */
1220 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX)
1221 /* @brief Number of external pin port on specified port. */
1222 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11)
1223 /* @brief Has external pin 24 connected to LLWU device. */
1224 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
1225 /* @brief Index of port of external pin. */
1226 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX)
1227 /* @brief Number of external pin port on specified port. */
1228 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8)
1229 /* @brief Has external pin 25 connected to LLWU device. */
1230 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
1231 /* @brief Index of port of external pin. */
1232 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX)
1233 /* @brief Number of external pin port on specified port. */
1234 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11)
1235 /* @brief Has external pin 26 connected to LLWU device. */
1236 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
1237 /* @brief Index of port of external pin. */
1238 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
1239 /* @brief Number of external pin port on specified port. */
1240 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
1241 /* @brief Has external pin 27 connected to LLWU device. */
1242 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
1243 /* @brief Index of port of external pin. */
1244 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
1245 /* @brief Number of external pin port on specified port. */
1246 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
1247 /* @brief Has external pin 28 connected to LLWU device. */
1248 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
1249 /* @brief Index of port of external pin. */
1250 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
1251 /* @brief Number of external pin port on specified port. */
1252 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
1253 /* @brief Has external pin 29 connected to LLWU device. */
1254 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
1255 /* @brief Index of port of external pin. */
1256 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
1257 /* @brief Number of external pin port on specified port. */
1258 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
1259 /* @brief Has external pin 30 connected to LLWU device. */
1260 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
1261 /* @brief Index of port of external pin. */
1262 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
1263 /* @brief Number of external pin port on specified port. */
1264 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
1265 /* @brief Has external pin 31 connected to LLWU device. */
1266 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
1267 /* @brief Index of port of external pin. */
1268 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
1269 /* @brief Number of external pin port on specified port. */
1270 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
1271 /* @brief Has internal module 0 connected to LLWU device. */
1272 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
1273 /* @brief Has internal module 1 connected to LLWU device. */
1274 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
1275 /* @brief Has internal module 2 connected to LLWU device. */
1276 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
1277 /* @brief Has internal module 3 connected to LLWU device. */
1278 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
1279 /* @brief Has internal module 4 connected to LLWU device. */
1280 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
1281 /* @brief Has internal module 5 connected to LLWU device. */
1282 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0)
1283 /* @brief Has internal module 6 connected to LLWU device. */
1284 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
1285 /* @brief Has internal module 7 connected to LLWU device. */
1286 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0)
1287 /* @brief Has Version ID Register (LLWU_VERID). */
1288 #define FSL_FEATURE_LLWU_HAS_VERID (0)
1289 /* @brief Has Parameter Register (LLWU_PARAM). */
1290 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
1291 /* @brief Width of registers of the LLWU. */
1292 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
1293 /* @brief Has DMA Enable register (LLWU_DE). */
1294 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
1295#endif /* defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F512VLL24) */
1296
1297/* LPTMR module features */
1298
1299/* @brief Has shared interrupt handler with another LPTMR module. */
1300#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
1301/* @brief Whether LPTMR counter is 32 bits width. */
1302#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
1303/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
1304#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
1305
1306/* MCG module features */
1307
1308/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
1309#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
1310/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
1311#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (7)
1312/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
1313#define FSL_FEATURE_MCG_PLL_VDIV_BASE (16)
1314/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
1315#define FSL_FEATURE_MCG_PLL_REF_MIN (8000000)
1316/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
1317#define FSL_FEATURE_MCG_PLL_REF_MAX (16000000)
1318/* @brief The PLL clock is divided by 2 before VCO divider. */
1319#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (1)
1320/* @brief FRDIV supports 1280. */
1321#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
1322/* @brief FRDIV supports 1536. */
1323#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
1324/* @brief MCGFFCLK divider. */
1325#define FSL_FEATURE_MCG_FFCLK_DIV (1)
1326/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
1327#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1)
1328/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
1329#define FSL_FEATURE_MCG_HAS_RTC_32K (0)
1330/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
1331#define FSL_FEATURE_MCG_HAS_PLL1 (0)
1332/* @brief Has 48MHz internal oscillator. */
1333#define FSL_FEATURE_MCG_HAS_IRC_48M (0)
1334/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
1335#define FSL_FEATURE_MCG_HAS_OSC1 (0)
1336/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
1337#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
1338/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
1339#define FSL_FEATURE_MCG_HAS_LOLRE (1)
1340/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
1341#define FSL_FEATURE_MCG_USE_OSCSEL (0)
1342/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
1343#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
1344/* @brief TBD */
1345#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
1346/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
1347#define FSL_FEATURE_MCG_HAS_PLL (1)
1348/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
1349#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
1350/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
1351#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
1352/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
1353#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
1354/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
1355#define FSL_FEATURE_MCG_HAS_FLL (1)
1356/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
1357#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
1358/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
1359#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
1360/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
1361#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
1362/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
1363#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
1364/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
1365#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
1366/* @brief Has external clock monitor (register bit C6[CME]). */
1367#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
1368/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
1369#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
1370/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
1371#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
1372/* @brief Has PEI mode or PBI mode. */
1373#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
1374/* @brief Reset clock mode is BLPI. */
1375#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
1376
1377/* MSCM module features */
1378
1379/* @brief Number of configuration information for processors. */
1380#define FSL_FEATURE_MSCM_HAS_CP_COUNT (2)
1381/* @brief Has data cache. */
1382#define FSL_FEATURE_MSCM_HAS_DATACACHE (0)
1383
1384/* interrupt module features */
1385
1386/* @brief Lowest interrupt request number. */
1387#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
1388/* @brief Highest interrupt request number. */
1389#define FSL_FEATURE_INTERRUPT_IRQ_MAX (120)
1390
1391/* OSC module features */
1392
1393/* @brief Has OSC1 external oscillator. */
1394#define FSL_FEATURE_OSC_HAS_OSC1 (0)
1395/* @brief Has OSC0 external oscillator. */
1396#define FSL_FEATURE_OSC_HAS_OSC0 (0)
1397/* @brief Has OSC external oscillator (without index). */
1398#define FSL_FEATURE_OSC_HAS_OSC (0)
1399/* @brief Number of OSC external oscillators. */
1400#define FSL_FEATURE_OSC_OSC_COUNT (0)
1401/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
1402#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1)
1403
1404/* PDB module features */
1405
1406/* @brief Has DAC support. */
1407#define FSL_FEATURE_PDB_HAS_DAC (1)
1408/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1409#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
1410/* @brief PDB channel number). */
1411#define FSL_FEATURE_PDB_CHANNEL_COUNT (2)
1412/* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */
1413#define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2)
1414/* @brief DAC interval trigger number). */
1415#define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (1)
1416/* @brief Pulse out number). */
1417#define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2)
1418
1419/* PIT module features */
1420
1421/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
1422#define FSL_FEATURE_PIT_TIMER_COUNT (4)
1423/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
1424#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
1425/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
1426#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
1427/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1428#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
1429/* @brief Has timer enable control. */
1430#define FSL_FEATURE_PIT_HAS_MDIS (1)
1431
1432/* PMC module features */
1433
1434/* @brief Has Bandgap Enable In VLPx Operation support. */
1435#define FSL_FEATURE_PMC_HAS_BGEN (1)
1436/* @brief Has Bandgap Buffer Enable. */
1437#define FSL_FEATURE_PMC_HAS_BGBE (1)
1438/* @brief Has Bandgap Buffer Drive Select. */
1439#define FSL_FEATURE_PMC_HAS_BGBDS (0)
1440/* @brief Has Low-Voltage Detect Voltage Select support. */
1441#define FSL_FEATURE_PMC_HAS_LVDV (1)
1442/* @brief Has Low-Voltage Warning Voltage Select support. */
1443#define FSL_FEATURE_PMC_HAS_LVWV (1)
1444/* @brief Has LPO. */
1445#define FSL_FEATURE_PMC_HAS_LPO (0)
1446/* @brief Has VLPx option PMC_REGSC[VLPO]. */
1447#define FSL_FEATURE_PMC_HAS_VLPO (0)
1448/* @brief Has acknowledge isolation support. */
1449#define FSL_FEATURE_PMC_HAS_ACKISO (1)
1450/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
1451#define FSL_FEATURE_PMC_HAS_REGFPM (0)
1452/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
1453#define FSL_FEATURE_PMC_HAS_REGONS (1)
1454/* @brief Has PMC_HVDSC1. */
1455#define FSL_FEATURE_PMC_HAS_HVDSC1 (1)
1456/* @brief Has PMC_PARAM. */
1457#define FSL_FEATURE_PMC_HAS_PARAM (0)
1458/* @brief Has PMC_VERID. */
1459#define FSL_FEATURE_PMC_HAS_VERID (0)
1460
1461/* PORT module features */
1462
1463/* @brief Has control lock (register bit PCR[LK]). */
1464#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
1465/* @brief Has open drain control (register bit PCR[ODE]). */
1466#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
1467/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
1468#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
1469/* @brief Has DMA request (register bit field PCR[IRQC] values). */
1470#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
1471/* @brief Has pull resistor selection available. */
1472#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
1473/* @brief Has pull resistor enable (register bit PCR[PE]). */
1474#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
1475/* @brief Has slew rate control (register bit PCR[SRE]). */
1476#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
1477/* @brief Has passive filter (register bit field PCR[PFE]). */
1478#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
1479/* @brief Has drive strength control (register bit PCR[DSE]). */
1480#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
1481/* @brief Has separate drive strength register (HDRVE). */
1482#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
1483/* @brief Has glitch filter (register IOFLT). */
1484#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
1485/* @brief Defines width of PCR[MUX] field. */
1486#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4)
1487/* @brief Has dedicated interrupt vector. */
1488#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
1489/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
1490#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
1491/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
1492#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
1493/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
1494#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
1495
1496/* PWM module features */
1497
1498/* @brief If EflexPWM has module A channels (outputs). */
1499#define FSL_FEATURE_PWM_HAS_CHANNELA (1)
1500/* @brief If EflexPWM has module B channels (outputs). */
1501#define FSL_FEATURE_PWM_HAS_CHANNELB (1)
1502/* @brief If EflexPWM has module X channels (outputs). */
1503#define FSL_FEATURE_PWM_HAS_CHANNELX (1)
1504/* @brief Number of submodules in each EflexPWM module. */
1505#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
1506
1507/* RCM module features */
1508
1509/* @brief Has Loss-of-Lock Reset support. */
1510#define FSL_FEATURE_RCM_HAS_LOL (1)
1511/* @brief Has Loss-of-Clock Reset support. */
1512#define FSL_FEATURE_RCM_HAS_LOC (1)
1513/* @brief Has JTAG generated Reset support. */
1514#define FSL_FEATURE_RCM_HAS_JTAG (1)
1515/* @brief Has EzPort generated Reset support. */
1516#define FSL_FEATURE_RCM_HAS_EZPORT (0)
1517/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
1518#define FSL_FEATURE_RCM_HAS_EZPMS (0)
1519/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
1520#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
1521/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
1522#define FSL_FEATURE_RCM_HAS_SSRS (1)
1523/* @brief Has Version ID Register (RCM_VERID). */
1524#define FSL_FEATURE_RCM_HAS_VERID (0)
1525/* @brief Has Parameter Register (RCM_PARAM). */
1526#define FSL_FEATURE_RCM_HAS_PARAM (0)
1527/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
1528#define FSL_FEATURE_RCM_HAS_SRIE (0)
1529/* @brief Width of registers of the RCM. */
1530#define FSL_FEATURE_RCM_REG_WIDTH (8)
1531/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
1532#define FSL_FEATURE_RCM_HAS_CORE1 (0)
1533/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
1534#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
1535/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
1536#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
1537
1538/* SIM module features */
1539
1540/* @brief Has USB FS divider. */
1541#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1542/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1543#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1544/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1545#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
1546/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1547#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1548/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1549#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1550/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1551#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1552/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1553#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
1554/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1555#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
1556/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1557#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1558/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1559#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1560/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1561#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
1562/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1563#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1564/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1565#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1566/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1567#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1568/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1569#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
1570/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1571#define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
1572/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1573#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
1574/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1575#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
1576/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1577#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
1578/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1579#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1580/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1581#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1582/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1583#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1584/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1585#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1586/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1587#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1588/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1589#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1590/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1591#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1592/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1593#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
1594/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1595#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
1596/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1597#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
1598/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1599#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
1600/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1601#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
1602/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1603#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
1604/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1605#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
1606/* @brief Has FTM module(s) configuration. */
1607#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
1608/* @brief Number of FTM modules. */
1609#define FSL_FEATURE_SIM_OPT_FTM_COUNT (3)
1610/* @brief Number of FTM triggers with selectable source. */
1611#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (3)
1612/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1613#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
1614/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1615#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
1616/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1617#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
1618/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1619#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
1620/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1621#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1622/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1623#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1624/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1625#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4)
1626/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1627#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
1628/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1629#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
1630/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1631#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
1632/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1633#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
1634/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1635#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
1636/* @brief Has TPM module(s) configuration. */
1637#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
1638/* @brief The highest TPM module index. */
1639#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
1640/* @brief Has TPM module with index 0. */
1641#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1642/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1643#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
1644/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1645#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1646/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1647#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
1648/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1649#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
1650/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1651#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
1652/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1653#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1654/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1655#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1656/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1657#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
1658/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1659#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
1660/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1661#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1662/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1663#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1664/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1665#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1666/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1667#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1668/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1669#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
1670/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1671#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
1672/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1673#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
1674/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1675#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1676/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1677#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1678/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1679#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1680/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1681#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1682/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1683#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1684/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1685#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1686/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1687#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1688/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1689#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
1690/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1691#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
1692/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1693#define FSL_FEATURE_SIM_OPT_ADC_COUNT (0)
1694/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register ADCOPT). */
1695#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (2)
1696/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register ADCOPT). */
1697#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
1698/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register ADCOPT). */
1699#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
1700/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register ADCOPT). */
1701#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
1702/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
1703#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (2)
1704/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
1705#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (2)
1706/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
1707#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
1708/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
1709#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (2)
1710/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
1711#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (2)
1712/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
1713#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
1714/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1715#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
1716/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1717#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
1718/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1719#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1720/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1721#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
1722/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1723#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1724/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1725#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
1726/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1727#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1728/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1729#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1730/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1731#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1732/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1733#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1734/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1735#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1)
1736/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1737#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1738/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1739#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
1740/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1741#define FSL_FEATURE_SIM_SDID_HAS_FAMID (0)
1742/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1743#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1744/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1745#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1746/* @brief Has device die ID (register bit field SDID[DIEID]). */
1747#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1748/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1749#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1750/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1751#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1752/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1753#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1754/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1755#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1756/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1757#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
1758/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1759#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
1760/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1761#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
1762/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1763#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
1764/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1765#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
1766/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1767#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1768/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1769#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1770/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1771#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
1772/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1773#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1774/* @brief Has miscellanious control register (register MCR). */
1775#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1776/* @brief Has COP watchdog (registers COPC and SRVCOP). */
1777#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1778/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1779#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1780/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
1781#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
1782
1783/* SMC module features */
1784
1785/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
1786#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
1787/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
1788#define FSL_FEATURE_SMC_HAS_LPOPO (1)
1789/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
1790#define FSL_FEATURE_SMC_HAS_PORPO (1)
1791/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
1792#define FSL_FEATURE_SMC_HAS_LPWUI (0)
1793/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
1794#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
1795/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
1796#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
1797/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
1798#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1)
1799/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
1800#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1)
1801/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
1802#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
1803/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
1804#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0)
1805/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
1806#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
1807/* @brief Has stop submode. */
1808#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
1809/* @brief Has stop submode 0(VLLS0). */
1810#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
1811/* @brief Has stop submode 1(VLLS1). */
1812#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1)
1813/* @brief Has stop submode 2(VLLS2). */
1814#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
1815/* @brief Has SMC_PARAM. */
1816#define FSL_FEATURE_SMC_HAS_PARAM (0)
1817/* @brief Has SMC_VERID. */
1818#define FSL_FEATURE_SMC_HAS_VERID (0)
1819/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
1820#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
1821/* @brief Has tamper reset (register bit SRS[TAMPER]). */
1822#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
1823/* @brief Has security violation reset (register bit SRS[SECVIO]). */
1824#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
1825/* @brief Width of SMC registers. */
1826#define FSL_FEATURE_SMC_REG_WIDTH (8)
1827
1828/* DSPI module features */
1829
1830/* @brief Receive/transmit FIFO size in number of items. */
1831#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4)
1832/* @brief Maximum transfer data width in bits. */
1833#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
1834/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
1835#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
1836/* @brief Number of chip select pins. */
1837#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
1838/* @brief Number of CTAR registers. */
1839#define FSL_FEATURE_DSPI_CTAR_COUNT (2)
1840/* @brief Has chip select strobe capability on the PCS5 pin. */
1841#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
1842/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
1843#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
1844/* @brief Has 16-bit data transfer support. */
1845#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
1846/* @brief Has separate DMA RX and TX requests. */
1847#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
1848
1849/* SYSMPU module features */
1850
1851/* @brief Specifies number of descriptors available. */
1852#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12)
1853/* @brief Has process identifier support. */
1854#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1)
1855/* @brief Total number of MPU slave. */
1856#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5)
1857/* @brief Total number of MPU master. */
1858#define FSL_FEATURE_SYSMPU_MASTER_COUNT (4)
1859
1860/* SysTick module features */
1861
1862/* @brief Systick has external reference clock. */
1863#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
1864/* @brief Systick external reference clock is core clock divided by this value. */
1865#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
1866
1867/* SCB module features */
1868
1869/* @brief L1 ICACHE line size in byte. */
1870#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
1871/* @brief L1 DCACHE line size in byte. */
1872#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
1873
1874/* UART module features */
1875
1876#if defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F512VLL24)
1877 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
1878 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
1879 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
1880 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
1881 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
1882 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
1883 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1884 #define FSL_FEATURE_UART_HAS_FIFO (1)
1885 /* @brief Hardware flow control (RTS, CTS) is supported. */
1886 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
1887 /* @brief Infrared (modulation) is supported. */
1888 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
1889 /* @brief 2 bits long stop bit is available. */
1890 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
1891 /* @brief If 10-bit mode is supported. */
1892 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
1893 /* @brief Baud rate fine adjustment is available. */
1894 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
1895 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
1896 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
1897 /* @brief Baud rate oversampling is available. */
1898 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
1899 /* @brief Baud rate oversampling is available. */
1900 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
1901 /* @brief Peripheral type. */
1902 #define FSL_FEATURE_UART_IS_SCI (0)
1903 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1904 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
1905 (((x) == UART0) ? (8) : \
1906 (((x) == UART1) ? (8) : \
1907 (((x) == UART2) ? (1) : \
1908 (((x) == UART3) ? (1) : \
1909 (((x) == UART4) ? (1) : (-1))))))
1910 /* @brief Maximal data width without parity bit. */
1911 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
1912 /* @brief Maximal data width with parity bit. */
1913 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
1914 /* @brief Supports two match addresses to filter incoming frames. */
1915 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
1916 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
1917 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
1918 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
1919 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
1920 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
1921 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
1922 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
1923 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
1924 /* @brief Has improved smart card (ISO7816 protocol) support. */
1925 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
1926 /* @brief Has local operation network (CEA709.1-B protocol) support. */
1927 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
1928 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
1929 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
1930 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
1931 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
1932 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
1933 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
1934 /* @brief Has separate DMA RX and TX requests. */
1935 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
1936#elif defined(CPU_MKV58F1M0VLQ24) || defined(CPU_MKV58F1M0VMD24) || defined(CPU_MKV58F512VLQ24) || defined(CPU_MKV58F512VMD24)
1937 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
1938 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
1939 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
1940 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
1941 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
1942 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
1943 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1944 #define FSL_FEATURE_UART_HAS_FIFO (1)
1945 /* @brief Hardware flow control (RTS, CTS) is supported. */
1946 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
1947 /* @brief Infrared (modulation) is supported. */
1948 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
1949 /* @brief 2 bits long stop bit is available. */
1950 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
1951 /* @brief If 10-bit mode is supported. */
1952 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
1953 /* @brief Baud rate fine adjustment is available. */
1954 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
1955 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
1956 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
1957 /* @brief Baud rate oversampling is available. */
1958 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
1959 /* @brief Baud rate oversampling is available. */
1960 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
1961 /* @brief Peripheral type. */
1962 #define FSL_FEATURE_UART_IS_SCI (0)
1963 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1964 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
1965 (((x) == UART0) ? (8) : \
1966 (((x) == UART1) ? (8) : \
1967 (((x) == UART2) ? (1) : \
1968 (((x) == UART3) ? (1) : \
1969 (((x) == UART4) ? (1) : \
1970 (((x) == UART5) ? (1) : (-1)))))))
1971 /* @brief Maximal data width without parity bit. */
1972 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
1973 /* @brief Maximal data width with parity bit. */
1974 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
1975 /* @brief Supports two match addresses to filter incoming frames. */
1976 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
1977 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
1978 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
1979 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
1980 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
1981 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
1982 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
1983 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
1984 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
1985 /* @brief Has improved smart card (ISO7816 protocol) support. */
1986 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
1987 /* @brief Has local operation network (CEA709.1-B protocol) support. */
1988 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
1989 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
1990 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
1991 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
1992 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
1993 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
1994 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
1995 /* @brief Has separate DMA RX and TX requests. */
1996 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
1997#endif /* defined(CPU_MKV58F1M0VLL24) || defined(CPU_MKV58F512VLL24) */
1998
1999/* WDOG module features */
2000
2001/* @brief Watchdog is available. */
2002#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
2003/* @brief Has Wait mode support. */
2004#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
2005
2006/* XBARA module features */
2007
2008/* @brief Has single XBAR module. */
2009#define FSL_FEATURE_XBARA_HAS_SINGLE_MODULE (0)
2010/* @brief Maximum value of XBARA input. */
2011#define FSL_FEATURE_XBARA_MODULE_INPUTS (58)
2012/* @brief Maximum value of XBARA output. */
2013#define FSL_FEATURE_XBARA_MODULE_OUTPUTS (59)
2014/* @brief Half register position. */
2015#define FSL_FEATURE_XBARA_HALF_REGISTER_SHIFT (BP_XBARA_SEL0_SEL1)
2016/* @brief Offset of the control register. */
2017#define FSL_FEATURE_XBARA_CONTROL_REGISTER_OFFSET (HW_XBARA_CTRL0_ADDR(0))
2018/* @brief Number of controled outputs. */
2019#define FSL_FEATURE_XBARA_CONTROL_OUTPUTS_NUMBER (4U)
2020/* @brief Number of interrupt requests. */
2021#define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4)
2022/* @brief Number of controled outputs. */
2023#define FSL_FEATURE_XBARA_OUTPUT_COUNT (4U)
2024/* @brief XBARA has input 0. */
2025#define FSL_FEATURE_XBARA_HAS_INPUT0 (1)
2026/* @brief XBARA has input 1. */
2027#define FSL_FEATURE_XBARA_HAS_INPUT1 (1)
2028/* @brief XBARA has input 2. */
2029#define FSL_FEATURE_XBARA_HAS_INPUT2 (1)
2030/* @brief XBARA has input 3. */
2031#define FSL_FEATURE_XBARA_HAS_INPUT3 (1)
2032/* @brief XBARA has input 4. */
2033#define FSL_FEATURE_XBARA_HAS_INPUT4 (1)
2034/* @brief XBARA has input 5. */
2035#define FSL_FEATURE_XBARA_HAS_INPUT5 (1)
2036/* @brief XBARA has input 6. */
2037#define FSL_FEATURE_XBARA_HAS_INPUT6 (1)
2038/* @brief XBARA has input 7. */
2039#define FSL_FEATURE_XBARA_HAS_INPUT7 (1)
2040/* @brief XBARA has input 8. */
2041#define FSL_FEATURE_XBARA_HAS_INPUT8 (1)
2042/* @brief XBARA has input 9. */
2043#define FSL_FEATURE_XBARA_HAS_INPUT9 (1)
2044/* @brief XBARA has input 10. */
2045#define FSL_FEATURE_XBARA_HAS_INPUT10 (1)
2046/* @brief XBARA has input 11. */
2047#define FSL_FEATURE_XBARA_HAS_INPUT11 (1)
2048/* @brief XBARA has input 12. */
2049#define FSL_FEATURE_XBARA_HAS_INPUT12 (1)
2050/* @brief XBARA has input 13. */
2051#define FSL_FEATURE_XBARA_HAS_INPUT13 (1)
2052/* @brief XBARA has input 14. */
2053#define FSL_FEATURE_XBARA_HAS_INPUT14 (1)
2054/* @brief XBARA has input 15. */
2055#define FSL_FEATURE_XBARA_HAS_INPUT15 (1)
2056/* @brief XBARA has input 16. */
2057#define FSL_FEATURE_XBARA_HAS_INPUT16 (1)
2058/* @brief XBARA has input 17. */
2059#define FSL_FEATURE_XBARA_HAS_INPUT17 (1)
2060/* @brief XBARA has input 18. */
2061#define FSL_FEATURE_XBARA_HAS_INPUT18 (1)
2062/* @brief XBARA has input 19. */
2063#define FSL_FEATURE_XBARA_HAS_INPUT19 (1)
2064/* @brief XBARA has input 20. */
2065#define FSL_FEATURE_XBARA_HAS_INPUT20 (1)
2066/* @brief XBARA has input 21. */
2067#define FSL_FEATURE_XBARA_HAS_INPUT21 (1)
2068/* @brief XBARA has input 22. */
2069#define FSL_FEATURE_XBARA_HAS_INPUT22 (1)
2070/* @brief XBARA has input 23. */
2071#define FSL_FEATURE_XBARA_HAS_INPUT23 (1)
2072/* @brief XBARA has input 24. */
2073#define FSL_FEATURE_XBARA_HAS_INPUT24 (1)
2074/* @brief XBARA has input 25. */
2075#define FSL_FEATURE_XBARA_HAS_INPUT25 (1)
2076/* @brief XBARA has input 26. */
2077#define FSL_FEATURE_XBARA_HAS_INPUT26 (1)
2078/* @brief XBARA has input 27. */
2079#define FSL_FEATURE_XBARA_HAS_INPUT27 (1)
2080/* @brief XBARA has input 28. */
2081#define FSL_FEATURE_XBARA_HAS_INPUT28 (1)
2082/* @brief XBARA has input 29. */
2083#define FSL_FEATURE_XBARA_HAS_INPUT29 (1)
2084/* @brief XBARA has input 30. */
2085#define FSL_FEATURE_XBARA_HAS_INPUT30 (1)
2086/* @brief XBARA has input 31. */
2087#define FSL_FEATURE_XBARA_HAS_INPUT31 (1)
2088/* @brief XBARA has input 32. */
2089#define FSL_FEATURE_XBARA_HAS_INPUT32 (1)
2090/* @brief XBARA has input 33. */
2091#define FSL_FEATURE_XBARA_HAS_INPUT33 (1)
2092/* @brief XBARA has input 34. */
2093#define FSL_FEATURE_XBARA_HAS_INPUT34 (1)
2094/* @brief XBARA has input 35. */
2095#define FSL_FEATURE_XBARA_HAS_INPUT35 (1)
2096/* @brief XBARA has input 36. */
2097#define FSL_FEATURE_XBARA_HAS_INPUT36 (1)
2098/* @brief XBARA has input 37. */
2099#define FSL_FEATURE_XBARA_HAS_INPUT37 (1)
2100/* @brief XBARA has input 38. */
2101#define FSL_FEATURE_XBARA_HAS_INPUT38 (1)
2102/* @brief XBARA has input 39. */
2103#define FSL_FEATURE_XBARA_HAS_INPUT39 (1)
2104/* @brief XBARA has input 40. */
2105#define FSL_FEATURE_XBARA_HAS_INPUT40 (1)
2106/* @brief XBARA has input 41. */
2107#define FSL_FEATURE_XBARA_HAS_INPUT41 (1)
2108/* @brief XBARA has input 42. */
2109#define FSL_FEATURE_XBARA_HAS_INPUT42 (1)
2110/* @brief XBARA has input 43. */
2111#define FSL_FEATURE_XBARA_HAS_INPUT43 (1)
2112/* @brief XBARA has input 44. */
2113#define FSL_FEATURE_XBARA_HAS_INPUT44 (1)
2114/* @brief XBARA has input 45. */
2115#define FSL_FEATURE_XBARA_HAS_INPUT45 (1)
2116/* @brief XBARA has input 46. */
2117#define FSL_FEATURE_XBARA_HAS_INPUT46 (1)
2118/* @brief XBARA has input 47. */
2119#define FSL_FEATURE_XBARA_HAS_INPUT47 (1)
2120/* @brief XBARA has input 48. */
2121#define FSL_FEATURE_XBARA_HAS_INPUT48 (1)
2122/* @brief XBARA has input 49. */
2123#define FSL_FEATURE_XBARA_HAS_INPUT49 (1)
2124/* @brief XBARA has input 50. */
2125#define FSL_FEATURE_XBARA_HAS_INPUT50 (1)
2126/* @brief XBARA has input 51. */
2127#define FSL_FEATURE_XBARA_HAS_INPUT51 (1)
2128/* @brief XBARA has input 52. */
2129#define FSL_FEATURE_XBARA_HAS_INPUT52 (1)
2130/* @brief XBARA has input 53. */
2131#define FSL_FEATURE_XBARA_HAS_INPUT53 (1)
2132/* @brief XBARA has input 54. */
2133#define FSL_FEATURE_XBARA_HAS_INPUT54 (1)
2134/* @brief XBARA has input 55. */
2135#define FSL_FEATURE_XBARA_HAS_INPUT55 (1)
2136/* @brief XBARA has input 56. */
2137#define FSL_FEATURE_XBARA_HAS_INPUT56 (1)
2138/* @brief XBARA has input 57. */
2139#define FSL_FEATURE_XBARA_HAS_INPUT57 (1)
2140/* @brief XBARA has input 58. */
2141#define FSL_FEATURE_XBARA_HAS_INPUT58 (0)
2142/* @brief XBARA has input 59. */
2143#define FSL_FEATURE_XBARA_HAS_INPUT59 (0)
2144/* @brief XBARA has input 60. */
2145#define FSL_FEATURE_XBARA_HAS_INPUT60 (0)
2146/* @brief XBARA has input 61. */
2147#define FSL_FEATURE_XBARA_HAS_INPUT61 (0)
2148/* @brief XBARA has input 62. */
2149#define FSL_FEATURE_XBARA_HAS_INPUT62 (0)
2150/* @brief XBARA has input 63. */
2151#define FSL_FEATURE_XBARA_HAS_INPUT63 (0)
2152/* @brief XBARA has input 64. */
2153#define FSL_FEATURE_XBARA_HAS_INPUT64 (0)
2154/* @brief XBARA has input 65. */
2155#define FSL_FEATURE_XBARA_HAS_INPUT65 (0)
2156/* @brief XBARA has input 66. */
2157#define FSL_FEATURE_XBARA_HAS_INPUT66 (0)
2158/* @brief XBARA has input 67. */
2159#define FSL_FEATURE_XBARA_HAS_INPUT67 (0)
2160/* @brief XBARA has input 68. */
2161#define FSL_FEATURE_XBARA_HAS_INPUT68 (0)
2162/* @brief XBARA has input 69. */
2163#define FSL_FEATURE_XBARA_HAS_INPUT69 (0)
2164/* @brief XBARA has input 70. */
2165#define FSL_FEATURE_XBARA_HAS_INPUT70 (0)
2166/* @brief XBARA has input 71. */
2167#define FSL_FEATURE_XBARA_HAS_INPUT71 (0)
2168/* @brief XBARA has input 72. */
2169#define FSL_FEATURE_XBARA_HAS_INPUT72 (0)
2170/* @brief XBARA has input 73. */
2171#define FSL_FEATURE_XBARA_HAS_INPUT73 (0)
2172/* @brief XBARA has input 74. */
2173#define FSL_FEATURE_XBARA_HAS_INPUT74 (0)
2174/* @brief XBARA has input 75. */
2175#define FSL_FEATURE_XBARA_HAS_INPUT75 (0)
2176/* @brief XBARA has input 76. */
2177#define FSL_FEATURE_XBARA_HAS_INPUT76 (0)
2178/* @brief XBARA has input 77. */
2179#define FSL_FEATURE_XBARA_HAS_INPUT77 (0)
2180/* @brief XBARA has input 78. */
2181#define FSL_FEATURE_XBARA_HAS_INPUT78 (0)
2182/* @brief XBARA has input 79. */
2183#define FSL_FEATURE_XBARA_HAS_INPUT79 (0)
2184/* @brief XBARA has input 80. */
2185#define FSL_FEATURE_XBARA_HAS_INPUT80 (0)
2186/* @brief XBARA has input 81. */
2187#define FSL_FEATURE_XBARA_HAS_INPUT81 (0)
2188/* @brief XBARA has input 82. */
2189#define FSL_FEATURE_XBARA_HAS_INPUT82 (0)
2190/* @brief XBARA has input 83. */
2191#define FSL_FEATURE_XBARA_HAS_INPUT83 (0)
2192/* @brief XBARA has input 84. */
2193#define FSL_FEATURE_XBARA_HAS_INPUT84 (0)
2194/* @brief XBARA has input 85. */
2195#define FSL_FEATURE_XBARA_HAS_INPUT85 (0)
2196/* @brief XBARA has input 86. */
2197#define FSL_FEATURE_XBARA_HAS_INPUT86 (0)
2198/* @brief XBARA has input 87. */
2199#define FSL_FEATURE_XBARA_HAS_INPUT87 (0)
2200/* @brief XBARA has input 88. */
2201#define FSL_FEATURE_XBARA_HAS_INPUT88 (0)
2202/* @brief XBARA has input 89. */
2203#define FSL_FEATURE_XBARA_HAS_INPUT89 (0)
2204/* @brief XBARA has input 90. */
2205#define FSL_FEATURE_XBARA_HAS_INPUT90 (0)
2206/* @brief XBARA has input 91. */
2207#define FSL_FEATURE_XBARA_HAS_INPUT91 (0)
2208/* @brief XBARA has input 92. */
2209#define FSL_FEATURE_XBARA_HAS_INPUT92 (0)
2210/* @brief XBARA has input 93. */
2211#define FSL_FEATURE_XBARA_HAS_INPUT93 (0)
2212/* @brief XBARA has input 94. */
2213#define FSL_FEATURE_XBARA_HAS_INPUT94 (0)
2214/* @brief XBARA has input 95. */
2215#define FSL_FEATURE_XBARA_HAS_INPUT95 (0)
2216/* @brief XBARA has input 96. */
2217#define FSL_FEATURE_XBARA_HAS_INPUT96 (0)
2218/* @brief XBARA has input 97. */
2219#define FSL_FEATURE_XBARA_HAS_INPUT97 (0)
2220/* @brief XBARA has input 98. */
2221#define FSL_FEATURE_XBARA_HAS_INPUT98 (0)
2222/* @brief XBARA has input 99. */
2223#define FSL_FEATURE_XBARA_HAS_INPUT99 (0)
2224/* @brief XBARA has input 100. */
2225#define FSL_FEATURE_XBARA_HAS_INPUT100 (0)
2226/* @brief XBARA has input 101. */
2227#define FSL_FEATURE_XBARA_HAS_INPUT101 (0)
2228/* @brief XBARA has input 102. */
2229#define FSL_FEATURE_XBARA_HAS_INPUT102 (0)
2230/* @brief XBARA has input 103. */
2231#define FSL_FEATURE_XBARA_HAS_INPUT103 (0)
2232/* @brief XBARA has input 104. */
2233#define FSL_FEATURE_XBARA_HAS_INPUT104 (0)
2234/* @brief XBARA has input 105. */
2235#define FSL_FEATURE_XBARA_HAS_INPUT105 (0)
2236/* @brief XBARA has input 106. */
2237#define FSL_FEATURE_XBARA_HAS_INPUT106 (0)
2238/* @brief XBARA has input 107. */
2239#define FSL_FEATURE_XBARA_HAS_INPUT107 (0)
2240/* @brief XBARA has input 108. */
2241#define FSL_FEATURE_XBARA_HAS_INPUT108 (0)
2242/* @brief XBARA has input 109. */
2243#define FSL_FEATURE_XBARA_HAS_INPUT109 (0)
2244/* @brief XBARA has input 110. */
2245#define FSL_FEATURE_XBARA_HAS_INPUT110 (0)
2246/* @brief XBARA has input 111. */
2247#define FSL_FEATURE_XBARA_HAS_INPUT111 (0)
2248/* @brief XBARA has input 112. */
2249#define FSL_FEATURE_XBARA_HAS_INPUT112 (0)
2250/* @brief XBARA has input 113. */
2251#define FSL_FEATURE_XBARA_HAS_INPUT113 (0)
2252/* @brief XBARA has input 114. */
2253#define FSL_FEATURE_XBARA_HAS_INPUT114 (0)
2254/* @brief XBARA has input 115. */
2255#define FSL_FEATURE_XBARA_HAS_INPUT115 (0)
2256/* @brief XBARA has input 116. */
2257#define FSL_FEATURE_XBARA_HAS_INPUT116 (0)
2258/* @brief XBARA has input 117. */
2259#define FSL_FEATURE_XBARA_HAS_INPUT117 (0)
2260/* @brief XBARA has input 118. */
2261#define FSL_FEATURE_XBARA_HAS_INPUT118 (0)
2262/* @brief XBARA has input 119. */
2263#define FSL_FEATURE_XBARA_HAS_INPUT119 (0)
2264/* @brief XBARA has input 120. */
2265#define FSL_FEATURE_XBARA_HAS_INPUT120 (0)
2266/* @brief XBARA has input 121. */
2267#define FSL_FEATURE_XBARA_HAS_INPUT121 (0)
2268/* @brief XBARA has input 122. */
2269#define FSL_FEATURE_XBARA_HAS_INPUT122 (0)
2270/* @brief XBARA has input 123. */
2271#define FSL_FEATURE_XBARA_HAS_INPUT123 (0)
2272/* @brief XBARA has input 124. */
2273#define FSL_FEATURE_XBARA_HAS_INPUT124 (0)
2274/* @brief XBARA has input 125. */
2275#define FSL_FEATURE_XBARA_HAS_INPUT125 (0)
2276/* @brief XBARA has input 126. */
2277#define FSL_FEATURE_XBARA_HAS_INPUT126 (0)
2278/* @brief XBARA has input 127. */
2279#define FSL_FEATURE_XBARA_HAS_INPUT127 (0)
2280/* @brief XBARA has output 0. */
2281#define FSL_FEATURE_XBARA_HAS_OUTPUT0 (1)
2282/* @brief XBARA has output 1. */
2283#define FSL_FEATURE_XBARA_HAS_OUTPUT1 (1)
2284/* @brief XBARA has output 2. */
2285#define FSL_FEATURE_XBARA_HAS_OUTPUT2 (1)
2286/* @brief XBARA has output 3. */
2287#define FSL_FEATURE_XBARA_HAS_OUTPUT3 (1)
2288/* @brief XBARA has output 4. */
2289#define FSL_FEATURE_XBARA_HAS_OUTPUT4 (1)
2290/* @brief XBARA has output 5. */
2291#define FSL_FEATURE_XBARA_HAS_OUTPUT5 (1)
2292/* @brief XBARA has output 6. */
2293#define FSL_FEATURE_XBARA_HAS_OUTPUT6 (1)
2294/* @brief XBARA has output 7. */
2295#define FSL_FEATURE_XBARA_HAS_OUTPUT7 (1)
2296/* @brief XBARA has output 8. */
2297#define FSL_FEATURE_XBARA_HAS_OUTPUT8 (1)
2298/* @brief XBARA has output 9. */
2299#define FSL_FEATURE_XBARA_HAS_OUTPUT9 (1)
2300/* @brief XBARA has output 10. */
2301#define FSL_FEATURE_XBARA_HAS_OUTPUT10 (1)
2302/* @brief XBARA has output 11. */
2303#define FSL_FEATURE_XBARA_HAS_OUTPUT11 (1)
2304/* @brief XBARA has output 12. */
2305#define FSL_FEATURE_XBARA_HAS_OUTPUT12 (1)
2306/* @brief XBARA has output 13. */
2307#define FSL_FEATURE_XBARA_HAS_OUTPUT13 (1)
2308/* @brief XBARA has output 14. */
2309#define FSL_FEATURE_XBARA_HAS_OUTPUT14 (0)
2310/* @brief XBARA has output 15. */
2311#define FSL_FEATURE_XBARA_HAS_OUTPUT15 (1)
2312/* @brief XBARA has output 16. */
2313#define FSL_FEATURE_XBARA_HAS_OUTPUT16 (1)
2314/* @brief XBARA has output 17. */
2315#define FSL_FEATURE_XBARA_HAS_OUTPUT17 (1)
2316/* @brief XBARA has output 18. */
2317#define FSL_FEATURE_XBARA_HAS_OUTPUT18 (1)
2318/* @brief XBARA has output 19. */
2319#define FSL_FEATURE_XBARA_HAS_OUTPUT19 (1)
2320/* @brief XBARA has output 20. */
2321#define FSL_FEATURE_XBARA_HAS_OUTPUT20 (1)
2322/* @brief XBARA has output 21. */
2323#define FSL_FEATURE_XBARA_HAS_OUTPUT21 (1)
2324/* @brief XBARA has output 22. */
2325#define FSL_FEATURE_XBARA_HAS_OUTPUT22 (1)
2326/* @brief XBARA has output 23. */
2327#define FSL_FEATURE_XBARA_HAS_OUTPUT23 (1)
2328/* @brief XBARA has output 24. */
2329#define FSL_FEATURE_XBARA_HAS_OUTPUT24 (1)
2330/* @brief XBARA has output 25. */
2331#define FSL_FEATURE_XBARA_HAS_OUTPUT25 (1)
2332/* @brief XBARA has output 26. */
2333#define FSL_FEATURE_XBARA_HAS_OUTPUT26 (1)
2334/* @brief XBARA has output 27. */
2335#define FSL_FEATURE_XBARA_HAS_OUTPUT27 (1)
2336/* @brief XBARA has output 28. */
2337#define FSL_FEATURE_XBARA_HAS_OUTPUT28 (1)
2338/* @brief XBARA has output 29. */
2339#define FSL_FEATURE_XBARA_HAS_OUTPUT29 (1)
2340/* @brief XBARA has output 30. */
2341#define FSL_FEATURE_XBARA_HAS_OUTPUT30 (1)
2342/* @brief XBARA has output 31. */
2343#define FSL_FEATURE_XBARA_HAS_OUTPUT31 (1)
2344/* @brief XBARA has output 32. */
2345#define FSL_FEATURE_XBARA_HAS_OUTPUT32 (1)
2346/* @brief XBARA has output 33. */
2347#define FSL_FEATURE_XBARA_HAS_OUTPUT33 (1)
2348/* @brief XBARA has output 34. */
2349#define FSL_FEATURE_XBARA_HAS_OUTPUT34 (1)
2350/* @brief XBARA has output 35. */
2351#define FSL_FEATURE_XBARA_HAS_OUTPUT35 (1)
2352/* @brief XBARA has output 36. */
2353#define FSL_FEATURE_XBARA_HAS_OUTPUT36 (1)
2354/* @brief XBARA has output 37. */
2355#define FSL_FEATURE_XBARA_HAS_OUTPUT37 (1)
2356/* @brief XBARA has output 38. */
2357#define FSL_FEATURE_XBARA_HAS_OUTPUT38 (1)
2358/* @brief XBARA has output 39. */
2359#define FSL_FEATURE_XBARA_HAS_OUTPUT39 (1)
2360/* @brief XBARA has output 40. */
2361#define FSL_FEATURE_XBARA_HAS_OUTPUT40 (0)
2362/* @brief XBARA has output 41. */
2363#define FSL_FEATURE_XBARA_HAS_OUTPUT41 (1)
2364/* @brief XBARA has output 42. */
2365#define FSL_FEATURE_XBARA_HAS_OUTPUT42 (1)
2366/* @brief XBARA has output 43. */
2367#define FSL_FEATURE_XBARA_HAS_OUTPUT43 (1)
2368/* @brief XBARA has output 44. */
2369#define FSL_FEATURE_XBARA_HAS_OUTPUT44 (1)
2370/* @brief XBARA has output 45. */
2371#define FSL_FEATURE_XBARA_HAS_OUTPUT45 (1)
2372/* @brief XBARA has output 46. */
2373#define FSL_FEATURE_XBARA_HAS_OUTPUT46 (1)
2374/* @brief XBARA has output 47. */
2375#define FSL_FEATURE_XBARA_HAS_OUTPUT47 (1)
2376/* @brief XBARA has output 48. */
2377#define FSL_FEATURE_XBARA_HAS_OUTPUT48 (1)
2378/* @brief XBARA has output 49. */
2379#define FSL_FEATURE_XBARA_HAS_OUTPUT49 (1)
2380/* @brief XBARA has output 50. */
2381#define FSL_FEATURE_XBARA_HAS_OUTPUT50 (1)
2382/* @brief XBARA has output 51. */
2383#define FSL_FEATURE_XBARA_HAS_OUTPUT51 (1)
2384/* @brief XBARA has output 52. */
2385#define FSL_FEATURE_XBARA_HAS_OUTPUT52 (1)
2386/* @brief XBARA has output 53. */
2387#define FSL_FEATURE_XBARA_HAS_OUTPUT53 (1)
2388/* @brief XBARA has output 54. */
2389#define FSL_FEATURE_XBARA_HAS_OUTPUT54 (1)
2390/* @brief XBARA has output 55. */
2391#define FSL_FEATURE_XBARA_HAS_OUTPUT55 (1)
2392/* @brief XBARA has output 56. */
2393#define FSL_FEATURE_XBARA_HAS_OUTPUT56 (1)
2394/* @brief XBARA has output 57. */
2395#define FSL_FEATURE_XBARA_HAS_OUTPUT57 (1)
2396/* @brief XBARA has output 58. */
2397#define FSL_FEATURE_XBARA_HAS_OUTPUT58 (1)
2398/* @brief XBARA has output 59. */
2399#define FSL_FEATURE_XBARA_HAS_OUTPUT59 (0)
2400/* @brief XBARA has output 60. */
2401#define FSL_FEATURE_XBARA_HAS_OUTPUT60 (0)
2402/* @brief XBARA has output 61. */
2403#define FSL_FEATURE_XBARA_HAS_OUTPUT61 (0)
2404/* @brief XBARA has output 62. */
2405#define FSL_FEATURE_XBARA_HAS_OUTPUT62 (0)
2406/* @brief XBARA has output 63. */
2407#define FSL_FEATURE_XBARA_HAS_OUTPUT63 (0)
2408/* @brief XBARA has output 64. */
2409#define FSL_FEATURE_XBARA_HAS_OUTPUT64 (0)
2410/* @brief XBARA has output 65. */
2411#define FSL_FEATURE_XBARA_HAS_OUTPUT65 (0)
2412/* @brief XBARA has output 66. */
2413#define FSL_FEATURE_XBARA_HAS_OUTPUT66 (0)
2414/* @brief XBARA has output 67. */
2415#define FSL_FEATURE_XBARA_HAS_OUTPUT67 (0)
2416/* @brief XBARA has output 68. */
2417#define FSL_FEATURE_XBARA_HAS_OUTPUT68 (0)
2418/* @brief XBARA has output 69. */
2419#define FSL_FEATURE_XBARA_HAS_OUTPUT69 (0)
2420/* @brief XBARA has output 70. */
2421#define FSL_FEATURE_XBARA_HAS_OUTPUT70 (0)
2422/* @brief XBARA has output 71. */
2423#define FSL_FEATURE_XBARA_HAS_OUTPUT71 (0)
2424/* @brief XBARA has output 72. */
2425#define FSL_FEATURE_XBARA_HAS_OUTPUT72 (0)
2426/* @brief XBARA has output 73. */
2427#define FSL_FEATURE_XBARA_HAS_OUTPUT73 (0)
2428/* @brief XBARA has output 74. */
2429#define FSL_FEATURE_XBARA_HAS_OUTPUT74 (0)
2430/* @brief XBARA has output 75. */
2431#define FSL_FEATURE_XBARA_HAS_OUTPUT75 (0)
2432/* @brief XBARA has output 76. */
2433#define FSL_FEATURE_XBARA_HAS_OUTPUT76 (0)
2434/* @brief XBARA has output 77. */
2435#define FSL_FEATURE_XBARA_HAS_OUTPUT77 (0)
2436/* @brief XBARA has output 78. */
2437#define FSL_FEATURE_XBARA_HAS_OUTPUT78 (0)
2438/* @brief XBARA has output 79. */
2439#define FSL_FEATURE_XBARA_HAS_OUTPUT79 (0)
2440/* @brief XBARA has output 80. */
2441#define FSL_FEATURE_XBARA_HAS_OUTPUT80 (0)
2442/* @brief XBARA has output 81. */
2443#define FSL_FEATURE_XBARA_HAS_OUTPUT81 (0)
2444/* @brief XBARA has output 82. */
2445#define FSL_FEATURE_XBARA_HAS_OUTPUT82 (0)
2446/* @brief XBARA has output 83. */
2447#define FSL_FEATURE_XBARA_HAS_OUTPUT83 (0)
2448/* @brief XBARA has output 84. */
2449#define FSL_FEATURE_XBARA_HAS_OUTPUT84 (0)
2450/* @brief XBARA has output 85. */
2451#define FSL_FEATURE_XBARA_HAS_OUTPUT85 (0)
2452/* @brief XBARA has output 86. */
2453#define FSL_FEATURE_XBARA_HAS_OUTPUT86 (0)
2454/* @brief XBARA has output 87. */
2455#define FSL_FEATURE_XBARA_HAS_OUTPUT87 (0)
2456/* @brief XBARA has output 88. */
2457#define FSL_FEATURE_XBARA_HAS_OUTPUT88 (0)
2458/* @brief XBARA has output 89. */
2459#define FSL_FEATURE_XBARA_HAS_OUTPUT89 (0)
2460/* @brief XBARA has output 90. */
2461#define FSL_FEATURE_XBARA_HAS_OUTPUT90 (0)
2462/* @brief XBARA has output 91. */
2463#define FSL_FEATURE_XBARA_HAS_OUTPUT91 (0)
2464/* @brief XBARA has output 92. */
2465#define FSL_FEATURE_XBARA_HAS_OUTPUT92 (0)
2466/* @brief XBARA has output 93. */
2467#define FSL_FEATURE_XBARA_HAS_OUTPUT93 (0)
2468/* @brief XBARA has output 94. */
2469#define FSL_FEATURE_XBARA_HAS_OUTPUT94 (0)
2470/* @brief XBARA has output 95. */
2471#define FSL_FEATURE_XBARA_HAS_OUTPUT95 (0)
2472/* @brief XBARA has output 96. */
2473#define FSL_FEATURE_XBARA_HAS_OUTPUT96 (0)
2474/* @brief XBARA has output 97. */
2475#define FSL_FEATURE_XBARA_HAS_OUTPUT97 (0)
2476/* @brief XBARA has output 98. */
2477#define FSL_FEATURE_XBARA_HAS_OUTPUT98 (0)
2478/* @brief XBARA has output 99. */
2479#define FSL_FEATURE_XBARA_HAS_OUTPUT99 (0)
2480/* @brief XBARA has output 100. */
2481#define FSL_FEATURE_XBARA_HAS_OUTPUT100 (0)
2482/* @brief XBARA has output 101. */
2483#define FSL_FEATURE_XBARA_HAS_OUTPUT101 (0)
2484/* @brief XBARA has output 102. */
2485#define FSL_FEATURE_XBARA_HAS_OUTPUT102 (0)
2486/* @brief XBARA has output 103. */
2487#define FSL_FEATURE_XBARA_HAS_OUTPUT103 (0)
2488/* @brief XBARA has output 104. */
2489#define FSL_FEATURE_XBARA_HAS_OUTPUT104 (0)
2490/* @brief XBARA has output 105. */
2491#define FSL_FEATURE_XBARA_HAS_OUTPUT105 (0)
2492/* @brief XBARA has output 106. */
2493#define FSL_FEATURE_XBARA_HAS_OUTPUT106 (0)
2494/* @brief XBARA has output 107. */
2495#define FSL_FEATURE_XBARA_HAS_OUTPUT107 (0)
2496/* @brief XBARA has output 108. */
2497#define FSL_FEATURE_XBARA_HAS_OUTPUT108 (0)
2498/* @brief XBARA has output 109. */
2499#define FSL_FEATURE_XBARA_HAS_OUTPUT109 (0)
2500/* @brief XBARA has output 110. */
2501#define FSL_FEATURE_XBARA_HAS_OUTPUT110 (0)
2502/* @brief XBARA has output 111. */
2503#define FSL_FEATURE_XBARA_HAS_OUTPUT111 (0)
2504/* @brief XBARA has output 112. */
2505#define FSL_FEATURE_XBARA_HAS_OUTPUT112 (0)
2506/* @brief XBARA has output 113. */
2507#define FSL_FEATURE_XBARA_HAS_OUTPUT113 (0)
2508/* @brief XBARA has output 114. */
2509#define FSL_FEATURE_XBARA_HAS_OUTPUT114 (0)
2510/* @brief XBARA has output 115. */
2511#define FSL_FEATURE_XBARA_HAS_OUTPUT115 (0)
2512/* @brief XBARA has output 116. */
2513#define FSL_FEATURE_XBARA_HAS_OUTPUT116 (0)
2514/* @brief XBARA has output 117. */
2515#define FSL_FEATURE_XBARA_HAS_OUTPUT117 (0)
2516/* @brief XBARA has output 118. */
2517#define FSL_FEATURE_XBARA_HAS_OUTPUT118 (0)
2518/* @brief XBARA has output 119. */
2519#define FSL_FEATURE_XBARA_HAS_OUTPUT119 (0)
2520/* @brief XBARA has output 120. */
2521#define FSL_FEATURE_XBARA_HAS_OUTPUT120 (0)
2522/* @brief XBARA has output 121. */
2523#define FSL_FEATURE_XBARA_HAS_OUTPUT121 (0)
2524/* @brief XBARA has output 122. */
2525#define FSL_FEATURE_XBARA_HAS_OUTPUT122 (0)
2526/* @brief XBARA has output 123. */
2527#define FSL_FEATURE_XBARA_HAS_OUTPUT123 (0)
2528/* @brief XBARA has output 124. */
2529#define FSL_FEATURE_XBARA_HAS_OUTPUT124 (0)
2530/* @brief XBARA has output 125. */
2531#define FSL_FEATURE_XBARA_HAS_OUTPUT125 (0)
2532/* @brief XBARA has output 126. */
2533#define FSL_FEATURE_XBARA_HAS_OUTPUT126 (0)
2534/* @brief XBARA has output 127. */
2535#define FSL_FEATURE_XBARA_HAS_OUTPUT127 (0)
2536/* @brief XBARA input 0 ID. */
2537#define FSL_FEATURE_XBARA_INPUT0_ID (Vss)
2538/* @brief XBARA input 1 ID. */
2539#define FSL_FEATURE_XBARA_INPUT1_ID (Vdd)
2540/* @brief XBARA input 2 ID. */
2541#define FSL_FEATURE_XBARA_INPUT2_ID (XbarIn2)
2542/* @brief XBARA input 3 ID. */
2543#define FSL_FEATURE_XBARA_INPUT3_ID (XbarIn3)
2544/* @brief XBARA input 4 ID. */
2545#define FSL_FEATURE_XBARA_INPUT4_ID (XbarIn4)
2546/* @brief XBARA input 5 ID. */
2547#define FSL_FEATURE_XBARA_INPUT5_ID (XbarIn5)
2548/* @brief XBARA input 6 ID. */
2549#define FSL_FEATURE_XBARA_INPUT6_ID (XbarIn6)
2550/* @brief XBARA input 7 ID. */
2551#define FSL_FEATURE_XBARA_INPUT7_ID (XbarIn7)
2552/* @brief XBARA input 8 ID. */
2553#define FSL_FEATURE_XBARA_INPUT8_ID (XbarIn8)
2554/* @brief XBARA input 9 ID. */
2555#define FSL_FEATURE_XBARA_INPUT9_ID (XbarIn9)
2556/* @brief XBARA input 10 ID. */
2557#define FSL_FEATURE_XBARA_INPUT10_ID (XbarIn10)
2558/* @brief XBARA input 11 ID. */
2559#define FSL_FEATURE_XBARA_INPUT11_ID (XbarIn11)
2560/* @brief XBARA input 12 ID. */
2561#define FSL_FEATURE_XBARA_INPUT12_ID (Cmp0Output)
2562/* @brief XBARA input 13 ID. */
2563#define FSL_FEATURE_XBARA_INPUT13_ID (Cmp1Output)
2564/* @brief XBARA input 14 ID. */
2565#define FSL_FEATURE_XBARA_INPUT14_ID (Cmp2Output)
2566/* @brief XBARA input 15 ID. */
2567#define FSL_FEATURE_XBARA_INPUT15_ID (Cmp3Output)
2568/* @brief XBARA input 16 ID. */
2569#define FSL_FEATURE_XBARA_INPUT16_ID (Ftm0Match)
2570/* @brief XBARA input 17 ID. */
2571#define FSL_FEATURE_XBARA_INPUT17_ID (Ftm0Extrig)
2572/* @brief XBARA input 18 ID. */
2573#define FSL_FEATURE_XBARA_INPUT18_ID (Ftm3Match)
2574/* @brief XBARA input 19 ID. */
2575#define FSL_FEATURE_XBARA_INPUT19_ID (Ftm3Extrig)
2576/* @brief XBARA input 20 ID. */
2577#define FSL_FEATURE_XBARA_INPUT20_ID (Pwm0Ch0Trg0)
2578/* @brief XBARA input 21 ID. */
2579#define FSL_FEATURE_XBARA_INPUT21_ID (Pwm0Ch0Trg1)
2580/* @brief XBARA input 22 ID. */
2581#define FSL_FEATURE_XBARA_INPUT22_ID (Pwm0Ch1Trg0)
2582/* @brief XBARA input 23 ID. */
2583#define FSL_FEATURE_XBARA_INPUT23_ID (Pwm0Ch1Trg1)
2584/* @brief XBARA input 24 ID. */
2585#define FSL_FEATURE_XBARA_INPUT24_ID (Pwm0Ch2Trg0)
2586/* @brief XBARA input 25 ID. */
2587#define FSL_FEATURE_XBARA_INPUT25_ID (Pwm0Ch2Trg1)
2588/* @brief XBARA input 26 ID. */
2589#define FSL_FEATURE_XBARA_INPUT26_ID (Pwm0Ch3Trg0)
2590/* @brief XBARA input 27 ID. */
2591#define FSL_FEATURE_XBARA_INPUT27_ID (Pwm0Ch3Trg1)
2592/* @brief XBARA input 28 ID. */
2593#define FSL_FEATURE_XBARA_INPUT28_ID (Pdb0Ch1Output)
2594/* @brief XBARA input 29 ID. */
2595#define FSL_FEATURE_XBARA_INPUT29_ID (Pdb0Ch0Output)
2596/* @brief XBARA input 30 ID. */
2597#define FSL_FEATURE_XBARA_INPUT30_ID (Pdb1Ch1Output)
2598/* @brief XBARA input 31 ID. */
2599#define FSL_FEATURE_XBARA_INPUT31_ID (Pdb1Ch0Output)
2600/* @brief XBARA input 32 ID. */
2601#define FSL_FEATURE_XBARA_INPUT32_ID (Hsadc1Cca)
2602/* @brief XBARA input 33 ID. */
2603#define FSL_FEATURE_XBARA_INPUT33_ID (Hsadc0Cca)
2604/* @brief XBARA input 34 ID. */
2605#define FSL_FEATURE_XBARA_INPUT34_ID (Hsadc1Ccb)
2606/* @brief XBARA input 35 ID. */
2607#define FSL_FEATURE_XBARA_INPUT35_ID (Hsadc0Ccb)
2608/* @brief XBARA input 36 ID. */
2609#define FSL_FEATURE_XBARA_INPUT36_ID (Ftm1Match)
2610/* @brief XBARA input 37 ID. */
2611#define FSL_FEATURE_XBARA_INPUT37_ID (Ftm1Extrig)
2612/* @brief XBARA input 38 ID. */
2613#define FSL_FEATURE_XBARA_INPUT38_ID (DmaCh0Done)
2614/* @brief XBARA input 39 ID. */
2615#define FSL_FEATURE_XBARA_INPUT39_ID (DmaCh1Done)
2616/* @brief XBARA input 40 ID. */
2617#define FSL_FEATURE_XBARA_INPUT40_ID (DmaCh6Done)
2618/* @brief XBARA input 41 ID. */
2619#define FSL_FEATURE_XBARA_INPUT41_ID (DmaCh7Done)
2620/* @brief XBARA input 42 ID. */
2621#define FSL_FEATURE_XBARA_INPUT42_ID (PitTrigger0)
2622/* @brief XBARA input 43 ID. */
2623#define FSL_FEATURE_XBARA_INPUT43_ID (PitTrigger1)
2624/* @brief XBARA input 44 ID. */
2625#define FSL_FEATURE_XBARA_INPUT44_ID (Adc0Coco)
2626/* @brief XBARA input 45 ID. */
2627#define FSL_FEATURE_XBARA_INPUT45_ID (Enc0CmpPosMatch)
2628/* @brief XBARA input 46 ID. */
2629#define FSL_FEATURE_XBARA_INPUT46_ID (AndOrInvert0)
2630/* @brief XBARA input 47 ID. */
2631#define FSL_FEATURE_XBARA_INPUT47_ID (AndOrInvert1)
2632/* @brief XBARA input 48 ID. */
2633#define FSL_FEATURE_XBARA_INPUT48_ID (AndOrInvert2)
2634/* @brief XBARA input 49 ID. */
2635#define FSL_FEATURE_XBARA_INPUT49_ID (AndOrInvert3)
2636/* @brief XBARA input 50 ID. */
2637#define FSL_FEATURE_XBARA_INPUT50_ID (PitTrigger2)
2638/* @brief XBARA input 51 ID. */
2639#define FSL_FEATURE_XBARA_INPUT51_ID (PitTrigger3)
2640/* @brief XBARA input 52 ID. */
2641#define FSL_FEATURE_XBARA_INPUT52_ID (Pwm1Ch0Trg0OrTrg1)
2642/* @brief XBARA input 53 ID. */
2643#define FSL_FEATURE_XBARA_INPUT53_ID (Pwm1Ch1Trg0OrTrg1)
2644/* @brief XBARA input 54 ID. */
2645#define FSL_FEATURE_XBARA_INPUT54_ID (Pwm1Ch2Trg0OrTrg1)
2646/* @brief XBARA input 55 ID. */
2647#define FSL_FEATURE_XBARA_INPUT55_ID (Pwm1Ch3Trg0OrTrg1)
2648/* @brief XBARA input 56 ID. */
2649#define FSL_FEATURE_XBARA_INPUT56_ID (Ftm2Match)
2650/* @brief XBARA input 57 ID. */
2651#define FSL_FEATURE_XBARA_INPUT57_ID (Ftm2Extrig)
2652/* @brief XBARA input 58 ID. */
2653#define FSL_FEATURE_XBARA_INPUT58_ID (XBARA_IN_RESERVED58)
2654/* @brief XBARA input 59 ID. */
2655#define FSL_FEATURE_XBARA_INPUT59_ID (XBARA_IN_RESERVED59)
2656/* @brief XBARA input 60 ID. */
2657#define FSL_FEATURE_XBARA_INPUT60_ID (XBARA_IN_RESERVED60)
2658/* @brief XBARA input 61 ID. */
2659#define FSL_FEATURE_XBARA_INPUT61_ID (XBARA_IN_RESERVED61)
2660/* @brief XBARA input 62 ID. */
2661#define FSL_FEATURE_XBARA_INPUT62_ID (XBARA_IN_RESERVED62)
2662/* @brief XBARA input 63 ID. */
2663#define FSL_FEATURE_XBARA_INPUT63_ID (XBARA_IN_RESERVED63)
2664/* @brief XBARA input 64 ID. */
2665#define FSL_FEATURE_XBARA_INPUT64_ID (XBARA_IN_RESERVED64)
2666/* @brief XBARA input 65 ID. */
2667#define FSL_FEATURE_XBARA_INPUT65_ID (XBARA_IN_RESERVED65)
2668/* @brief XBARA input 66 ID. */
2669#define FSL_FEATURE_XBARA_INPUT66_ID (XBARA_IN_RESERVED66)
2670/* @brief XBARA input 67 ID. */
2671#define FSL_FEATURE_XBARA_INPUT67_ID (XBARA_IN_RESERVED67)
2672/* @brief XBARA input 68 ID. */
2673#define FSL_FEATURE_XBARA_INPUT68_ID (XBARA_IN_RESERVED68)
2674/* @brief XBARA input 69 ID. */
2675#define FSL_FEATURE_XBARA_INPUT69_ID (XBARA_IN_RESERVED69)
2676/* @brief XBARA input 70 ID. */
2677#define FSL_FEATURE_XBARA_INPUT70_ID (XBARA_IN_RESERVED70)
2678/* @brief XBARA input 71 ID. */
2679#define FSL_FEATURE_XBARA_INPUT71_ID (XBARA_IN_RESERVED71)
2680/* @brief XBARA input 72 ID. */
2681#define FSL_FEATURE_XBARA_INPUT72_ID (XBARA_IN_RESERVED72)
2682/* @brief XBARA input 73 ID. */
2683#define FSL_FEATURE_XBARA_INPUT73_ID (XBARA_IN_RESERVED73)
2684/* @brief XBARA input 74 ID. */
2685#define FSL_FEATURE_XBARA_INPUT74_ID (XBARA_IN_RESERVED74)
2686/* @brief XBARA input 75 ID. */
2687#define FSL_FEATURE_XBARA_INPUT75_ID (XBARA_IN_RESERVED75)
2688/* @brief XBARA input 76 ID. */
2689#define FSL_FEATURE_XBARA_INPUT76_ID (XBARA_IN_RESERVED76)
2690/* @brief XBARA input 77 ID. */
2691#define FSL_FEATURE_XBARA_INPUT77_ID (XBARA_IN_RESERVED77)
2692/* @brief XBARA input 78 ID. */
2693#define FSL_FEATURE_XBARA_INPUT78_ID (XBARA_IN_RESERVED78)
2694/* @brief XBARA input 79 ID. */
2695#define FSL_FEATURE_XBARA_INPUT79_ID (XBARA_IN_RESERVED79)
2696/* @brief XBARA input 80 ID. */
2697#define FSL_FEATURE_XBARA_INPUT80_ID (XBARA_IN_RESERVED80)
2698/* @brief XBARA input 81 ID. */
2699#define FSL_FEATURE_XBARA_INPUT81_ID (XBARA_IN_RESERVED81)
2700/* @brief XBARA input 82 ID. */
2701#define FSL_FEATURE_XBARA_INPUT82_ID (XBARA_IN_RESERVED82)
2702/* @brief XBARA input 83 ID. */
2703#define FSL_FEATURE_XBARA_INPUT83_ID (XBARA_IN_RESERVED83)
2704/* @brief XBARA input 84 ID. */
2705#define FSL_FEATURE_XBARA_INPUT84_ID (XBARA_IN_RESERVED84)
2706/* @brief XBARA input 85 ID. */
2707#define FSL_FEATURE_XBARA_INPUT85_ID (XBARA_IN_RESERVED85)
2708/* @brief XBARA input 86 ID. */
2709#define FSL_FEATURE_XBARA_INPUT86_ID (XBARA_IN_RESERVED86)
2710/* @brief XBARA input 87 ID. */
2711#define FSL_FEATURE_XBARA_INPUT87_ID (XBARA_IN_RESERVED87)
2712/* @brief XBARA input 88 ID. */
2713#define FSL_FEATURE_XBARA_INPUT88_ID (XBARA_IN_RESERVED88)
2714/* @brief XBARA input 89 ID. */
2715#define FSL_FEATURE_XBARA_INPUT89_ID (XBARA_IN_RESERVED89)
2716/* @brief XBARA input 90 ID. */
2717#define FSL_FEATURE_XBARA_INPUT90_ID (XBARA_IN_RESERVED90)
2718/* @brief XBARA input 91 ID. */
2719#define FSL_FEATURE_XBARA_INPUT91_ID (XBARA_IN_RESERVED91)
2720/* @brief XBARA input 92 ID. */
2721#define FSL_FEATURE_XBARA_INPUT92_ID (XBARA_IN_RESERVED92)
2722/* @brief XBARA input 93 ID. */
2723#define FSL_FEATURE_XBARA_INPUT93_ID (XBARA_IN_RESERVED93)
2724/* @brief XBARA input 94 ID. */
2725#define FSL_FEATURE_XBARA_INPUT94_ID (XBARA_IN_RESERVED94)
2726/* @brief XBARA input 95 ID. */
2727#define FSL_FEATURE_XBARA_INPUT95_ID (XBARA_IN_RESERVED95)
2728/* @brief XBARA input 96 ID. */
2729#define FSL_FEATURE_XBARA_INPUT96_ID (XBARA_IN_RESERVED96)
2730/* @brief XBARA input 97 ID. */
2731#define FSL_FEATURE_XBARA_INPUT97_ID (XBARA_IN_RESERVED97)
2732/* @brief XBARA input 98 ID. */
2733#define FSL_FEATURE_XBARA_INPUT98_ID (XBARA_IN_RESERVED98)
2734/* @brief XBARA input 99 ID. */
2735#define FSL_FEATURE_XBARA_INPUT99_ID (XBARA_IN_RESERVED99)
2736/* @brief XBARA input 100 ID. */
2737#define FSL_FEATURE_XBARA_INPUT100_ID (XBARA_IN_RESERVED100)
2738/* @brief XBARA input 101 ID. */
2739#define FSL_FEATURE_XBARA_INPUT101_ID (XBARA_IN_RESERVED101)
2740/* @brief XBARA input 102 ID. */
2741#define FSL_FEATURE_XBARA_INPUT102_ID (XBARA_IN_RESERVED102)
2742/* @brief XBARA input 103 ID. */
2743#define FSL_FEATURE_XBARA_INPUT103_ID (XBARA_IN_RESERVED103)
2744/* @brief XBARA input 104 ID. */
2745#define FSL_FEATURE_XBARA_INPUT104_ID (XBARA_IN_RESERVED104)
2746/* @brief XBARA input 105 ID. */
2747#define FSL_FEATURE_XBARA_INPUT105_ID (XBARA_IN_RESERVED105)
2748/* @brief XBARA input 106 ID. */
2749#define FSL_FEATURE_XBARA_INPUT106_ID (XBARA_IN_RESERVED106)
2750/* @brief XBARA input 107 ID. */
2751#define FSL_FEATURE_XBARA_INPUT107_ID (XBARA_IN_RESERVED107)
2752/* @brief XBARA input 108 ID. */
2753#define FSL_FEATURE_XBARA_INPUT108_ID (XBARA_IN_RESERVED108)
2754/* @brief XBARA input 109 ID. */
2755#define FSL_FEATURE_XBARA_INPUT109_ID (XBARA_IN_RESERVED109)
2756/* @brief XBARA input 110 ID. */
2757#define FSL_FEATURE_XBARA_INPUT110_ID (XBARA_IN_RESERVED110)
2758/* @brief XBARA input 111 ID. */
2759#define FSL_FEATURE_XBARA_INPUT111_ID (XBARA_IN_RESERVED111)
2760/* @brief XBARA input 112 ID. */
2761#define FSL_FEATURE_XBARA_INPUT112_ID (XBARA_IN_RESERVED112)
2762/* @brief XBARA input 113 ID. */
2763#define FSL_FEATURE_XBARA_INPUT113_ID (XBARA_IN_RESERVED113)
2764/* @brief XBARA input 114 ID. */
2765#define FSL_FEATURE_XBARA_INPUT114_ID (XBARA_IN_RESERVED114)
2766/* @brief XBARA input 115 ID. */
2767#define FSL_FEATURE_XBARA_INPUT115_ID (XBARA_IN_RESERVED115)
2768/* @brief XBARA input 116 ID. */
2769#define FSL_FEATURE_XBARA_INPUT116_ID (XBARA_IN_RESERVED116)
2770/* @brief XBARA input 117 ID. */
2771#define FSL_FEATURE_XBARA_INPUT117_ID (XBARA_IN_RESERVED117)
2772/* @brief XBARA input 118 ID. */
2773#define FSL_FEATURE_XBARA_INPUT118_ID (XBARA_IN_RESERVED118)
2774/* @brief XBARA input 119 ID. */
2775#define FSL_FEATURE_XBARA_INPUT119_ID (XBARA_IN_RESERVED119)
2776/* @brief XBARA input 120 ID. */
2777#define FSL_FEATURE_XBARA_INPUT120_ID (XBARA_IN_RESERVED120)
2778/* @brief XBARA input 121 ID. */
2779#define FSL_FEATURE_XBARA_INPUT121_ID (XBARA_IN_RESERVED121)
2780/* @brief XBARA input 122 ID. */
2781#define FSL_FEATURE_XBARA_INPUT122_ID (XBARA_IN_RESERVED122)
2782/* @brief XBARA input 123 ID. */
2783#define FSL_FEATURE_XBARA_INPUT123_ID (XBARA_IN_RESERVED123)
2784/* @brief XBARA input 124 ID. */
2785#define FSL_FEATURE_XBARA_INPUT124_ID (XBARA_IN_RESERVED124)
2786/* @brief XBARA input 125 ID. */
2787#define FSL_FEATURE_XBARA_INPUT125_ID (XBARA_IN_RESERVED125)
2788/* @brief XBARA input 126 ID. */
2789#define FSL_FEATURE_XBARA_INPUT126_ID (XBARA_IN_RESERVED126)
2790/* @brief XBARA input 127 ID. */
2791#define FSL_FEATURE_XBARA_INPUT127_ID (XBARA_IN_RESERVED127)
2792/* @brief XBARA output 0 ID. */
2793#define FSL_FEATURE_XBARA_OUTPUT0_ID (Dmamux18)
2794/* @brief XBARA output 1 ID. */
2795#define FSL_FEATURE_XBARA_OUTPUT1_ID (Dmamux19)
2796/* @brief XBARA output 2 ID. */
2797#define FSL_FEATURE_XBARA_OUTPUT2_ID (Dmamux20)
2798/* @brief XBARA output 3 ID. */
2799#define FSL_FEATURE_XBARA_OUTPUT3_ID (Dmamux21)
2800/* @brief XBARA output 4 ID. */
2801#define FSL_FEATURE_XBARA_OUTPUT4_ID (XbOut4)
2802/* @brief XBARA output 5 ID. */
2803#define FSL_FEATURE_XBARA_OUTPUT5_ID (XbOut5)
2804/* @brief XBARA output 6 ID. */
2805#define FSL_FEATURE_XBARA_OUTPUT6_ID (XbOut6)
2806/* @brief XBARA output 7 ID. */
2807#define FSL_FEATURE_XBARA_OUTPUT7_ID (XbOut7)
2808/* @brief XBARA output 8 ID. */
2809#define FSL_FEATURE_XBARA_OUTPUT8_ID (XbOut8)
2810/* @brief XBARA output 9 ID. */
2811#define FSL_FEATURE_XBARA_OUTPUT9_ID (XbOut9)
2812/* @brief XBARA output 10 ID. */
2813#define FSL_FEATURE_XBARA_OUTPUT10_ID (XbOut10)
2814/* @brief XBARA output 11 ID. */
2815#define FSL_FEATURE_XBARA_OUTPUT11_ID (XbOut11)
2816/* @brief XBARA output 12 ID. */
2817#define FSL_FEATURE_XBARA_OUTPUT12_ID (Hsadc0ATrig)
2818/* @brief XBARA output 13 ID. */
2819#define FSL_FEATURE_XBARA_OUTPUT13_ID (Hsadc0BTrig)
2820/* @brief XBARA output 14 ID. */
2821#define FSL_FEATURE_XBARA_OUTPUT14_ID (XBARA_OUT_RESERVED14)
2822/* @brief XBARA output 15 ID. */
2823#define FSL_FEATURE_XBARA_OUTPUT15_ID (Dac12bSync)
2824/* @brief XBARA output 16 ID. */
2825#define FSL_FEATURE_XBARA_OUTPUT16_ID (Cmp0)
2826/* @brief XBARA output 17 ID. */
2827#define FSL_FEATURE_XBARA_OUTPUT17_ID (Cmp1)
2828/* @brief XBARA output 18 ID. */
2829#define FSL_FEATURE_XBARA_OUTPUT18_ID (Cmp2)
2830/* @brief XBARA output 19 ID. */
2831#define FSL_FEATURE_XBARA_OUTPUT19_ID (Cmp3)
2832/* @brief XBARA output 20 ID. */
2833#define FSL_FEATURE_XBARA_OUTPUT20_ID (PwmCh0ExtA)
2834/* @brief XBARA output 21 ID. */
2835#define FSL_FEATURE_XBARA_OUTPUT21_ID (PwmCh1ExtA)
2836/* @brief XBARA output 22 ID. */
2837#define FSL_FEATURE_XBARA_OUTPUT22_ID (PwmCh2ExtA)
2838/* @brief XBARA output 23 ID. */
2839#define FSL_FEATURE_XBARA_OUTPUT23_ID (PwmCh3ExtA)
2840/* @brief XBARA output 24 ID. */
2841#define FSL_FEATURE_XBARA_OUTPUT24_ID (Pwm0Ch0ExtSync)
2842/* @brief XBARA output 25 ID. */
2843#define FSL_FEATURE_XBARA_OUTPUT25_ID (Pwm0Ch1ExtSync)
2844/* @brief XBARA output 26 ID. */
2845#define FSL_FEATURE_XBARA_OUTPUT26_ID (Pwm0Ch2ExtSync)
2846/* @brief XBARA output 27 ID. */
2847#define FSL_FEATURE_XBARA_OUTPUT27_ID (Pwm0Ch3ExtSync)
2848/* @brief XBARA output 28 ID. */
2849#define FSL_FEATURE_XBARA_OUTPUT28_ID (PwmExtClk)
2850/* @brief XBARA output 29 ID. */
2851#define FSL_FEATURE_XBARA_OUTPUT29_ID (Pwm0Fault0)
2852/* @brief XBARA output 30 ID. */
2853#define FSL_FEATURE_XBARA_OUTPUT30_ID (Pwm0Fault1)
2854/* @brief XBARA output 31 ID. */
2855#define FSL_FEATURE_XBARA_OUTPUT31_ID (Pwm0Fault2)
2856/* @brief XBARA output 32 ID. */
2857#define FSL_FEATURE_XBARA_OUTPUT32_ID (Pwm0Fault3)
2858/* @brief XBARA output 33 ID. */
2859#define FSL_FEATURE_XBARA_OUTPUT33_ID (Pwm0Force)
2860/* @brief XBARA output 34 ID. */
2861#define FSL_FEATURE_XBARA_OUTPUT34_ID (Ftm0Trig2)
2862/* @brief XBARA output 35 ID. */
2863#define FSL_FEATURE_XBARA_OUTPUT35_ID (Ftm1Trig2)
2864/* @brief XBARA output 36 ID. */
2865#define FSL_FEATURE_XBARA_OUTPUT36_ID (Ftm2Trig2)
2866/* @brief XBARA output 37 ID. */
2867#define FSL_FEATURE_XBARA_OUTPUT37_ID (Ftm3Trig2)
2868/* @brief XBARA output 38 ID. */
2869#define FSL_FEATURE_XBARA_OUTPUT38_ID (Pdb0InCh12)
2870/* @brief XBARA output 39 ID. */
2871#define FSL_FEATURE_XBARA_OUTPUT39_ID (Adc0Hdwt)
2872/* @brief XBARA output 40 ID. */
2873#define FSL_FEATURE_XBARA_OUTPUT40_ID (XBARA_OUT_RESERVED40)
2874/* @brief XBARA output 41 ID. */
2875#define FSL_FEATURE_XBARA_OUTPUT41_ID (Pdb1InCh12)
2876/* @brief XBARA output 42 ID. */
2877#define FSL_FEATURE_XBARA_OUTPUT42_ID (Hsadc1ATrig)
2878/* @brief XBARA output 43 ID. */
2879#define FSL_FEATURE_XBARA_OUTPUT43_ID (Hsadc1BTrig)
2880/* @brief XBARA output 44 ID. */
2881#define FSL_FEATURE_XBARA_OUTPUT44_ID (EncPhA)
2882/* @brief XBARA output 45 ID. */
2883#define FSL_FEATURE_XBARA_OUTPUT45_ID (EncPhB)
2884/* @brief XBARA output 46 ID. */
2885#define FSL_FEATURE_XBARA_OUTPUT46_ID (EncIndex)
2886/* @brief XBARA output 47 ID. */
2887#define FSL_FEATURE_XBARA_OUTPUT47_ID (EncHome)
2888/* @brief XBARA output 48 ID. */
2889#define FSL_FEATURE_XBARA_OUTPUT48_ID (EncCapTrigger)
2890/* @brief XBARA output 49 ID. */
2891#define FSL_FEATURE_XBARA_OUTPUT49_ID (Ftm0Fault3)
2892/* @brief XBARA output 50 ID. */
2893#define FSL_FEATURE_XBARA_OUTPUT50_ID (Ftm1Fault1)
2894/* @brief XBARA output 51 ID. */
2895#define FSL_FEATURE_XBARA_OUTPUT51_ID (Ftm2Fault1)
2896/* @brief XBARA output 52 ID. */
2897#define FSL_FEATURE_XBARA_OUTPUT52_ID (Ftm3Fault3)
2898/* @brief XBARA output 53 ID. */
2899#define FSL_FEATURE_XBARA_OUTPUT53_ID (Pwm1Ch0ExtSync)
2900/* @brief XBARA output 54 ID. */
2901#define FSL_FEATURE_XBARA_OUTPUT54_ID (Pwm1Ch1ExtSync)
2902/* @brief XBARA output 55 ID. */
2903#define FSL_FEATURE_XBARA_OUTPUT55_ID (Pwm1Ch2ExtSync)
2904/* @brief XBARA output 56 ID. */
2905#define FSL_FEATURE_XBARA_OUTPUT56_ID (Pwm1Ch3ExtSync)
2906/* @brief XBARA output 57 ID. */
2907#define FSL_FEATURE_XBARA_OUTPUT57_ID (Pwm1Force)
2908/* @brief XBARA output 58 ID. */
2909#define FSL_FEATURE_XBARA_OUTPUT58_ID (EwmIn)
2910/* @brief XBARA output 59 ID. */
2911#define FSL_FEATURE_XBARA_OUTPUT59_ID (XBARA_OUT_RESERVED59)
2912/* @brief XBARA output 60 ID. */
2913#define FSL_FEATURE_XBARA_OUTPUT60_ID (XBARA_OUT_RESERVED60)
2914/* @brief XBARA output 61 ID. */
2915#define FSL_FEATURE_XBARA_OUTPUT61_ID (XBARA_OUT_RESERVED61)
2916/* @brief XBARA output 62 ID. */
2917#define FSL_FEATURE_XBARA_OUTPUT62_ID (XBARA_OUT_RESERVED62)
2918/* @brief XBARA output 63 ID. */
2919#define FSL_FEATURE_XBARA_OUTPUT63_ID (XBARA_OUT_RESERVED63)
2920/* @brief XBARA output 64 ID. */
2921#define FSL_FEATURE_XBARA_OUTPUT64_ID (XBARA_OUT_RESERVED64)
2922/* @brief XBARA output 65 ID. */
2923#define FSL_FEATURE_XBARA_OUTPUT65_ID (XBARA_OUT_RESERVED65)
2924/* @brief XBARA output 66 ID. */
2925#define FSL_FEATURE_XBARA_OUTPUT66_ID (XBARA_OUT_RESERVED66)
2926/* @brief XBARA output 67 ID. */
2927#define FSL_FEATURE_XBARA_OUTPUT67_ID (XBARA_OUT_RESERVED67)
2928/* @brief XBARA output 68 ID. */
2929#define FSL_FEATURE_XBARA_OUTPUT68_ID (XBARA_OUT_RESERVED68)
2930/* @brief XBARA output 69 ID. */
2931#define FSL_FEATURE_XBARA_OUTPUT69_ID (XBARA_OUT_RESERVED69)
2932/* @brief XBARA output 70 ID. */
2933#define FSL_FEATURE_XBARA_OUTPUT70_ID (XBARA_OUT_RESERVED70)
2934/* @brief XBARA output 71 ID. */
2935#define FSL_FEATURE_XBARA_OUTPUT71_ID (XBARA_OUT_RESERVED71)
2936/* @brief XBARA output 72 ID. */
2937#define FSL_FEATURE_XBARA_OUTPUT72_ID (XBARA_OUT_RESERVED72)
2938/* @brief XBARA output 73 ID. */
2939#define FSL_FEATURE_XBARA_OUTPUT73_ID (XBARA_OUT_RESERVED73)
2940/* @brief XBARA output 74 ID. */
2941#define FSL_FEATURE_XBARA_OUTPUT74_ID (XBARA_OUT_RESERVED74)
2942/* @brief XBARA output 75 ID. */
2943#define FSL_FEATURE_XBARA_OUTPUT75_ID (XBARA_OUT_RESERVED75)
2944/* @brief XBARA output 76 ID. */
2945#define FSL_FEATURE_XBARA_OUTPUT76_ID (XBARA_OUT_RESERVED76)
2946/* @brief XBARA output 77 ID. */
2947#define FSL_FEATURE_XBARA_OUTPUT77_ID (XBARA_OUT_RESERVED77)
2948/* @brief XBARA output 78 ID. */
2949#define FSL_FEATURE_XBARA_OUTPUT78_ID (XBARA_OUT_RESERVED78)
2950/* @brief XBARA output 79 ID. */
2951#define FSL_FEATURE_XBARA_OUTPUT79_ID (XBARA_OUT_RESERVED79)
2952/* @brief XBARA output 80 ID. */
2953#define FSL_FEATURE_XBARA_OUTPUT80_ID (XBARA_OUT_RESERVED80)
2954/* @brief XBARA output 81 ID. */
2955#define FSL_FEATURE_XBARA_OUTPUT81_ID (XBARA_OUT_RESERVED81)
2956/* @brief XBARA output 82 ID. */
2957#define FSL_FEATURE_XBARA_OUTPUT82_ID (XBARA_OUT_RESERVED82)
2958/* @brief XBARA output 83 ID. */
2959#define FSL_FEATURE_XBARA_OUTPUT83_ID (XBARA_OUT_RESERVED83)
2960/* @brief XBARA output 84 ID. */
2961#define FSL_FEATURE_XBARA_OUTPUT84_ID (XBARA_OUT_RESERVED84)
2962/* @brief XBARA output 85 ID. */
2963#define FSL_FEATURE_XBARA_OUTPUT85_ID (XBARA_OUT_RESERVED85)
2964/* @brief XBARA output 86 ID. */
2965#define FSL_FEATURE_XBARA_OUTPUT86_ID (XBARA_OUT_RESERVED86)
2966/* @brief XBARA output 87 ID. */
2967#define FSL_FEATURE_XBARA_OUTPUT87_ID (XBARA_OUT_RESERVED87)
2968/* @brief XBARA output 88 ID. */
2969#define FSL_FEATURE_XBARA_OUTPUT88_ID (XBARA_OUT_RESERVED88)
2970/* @brief XBARA output 89 ID. */
2971#define FSL_FEATURE_XBARA_OUTPUT89_ID (XBARA_OUT_RESERVED89)
2972/* @brief XBARA output 90 ID. */
2973#define FSL_FEATURE_XBARA_OUTPUT90_ID (XBARA_OUT_RESERVED90)
2974/* @brief XBARA output 91 ID. */
2975#define FSL_FEATURE_XBARA_OUTPUT91_ID (XBARA_OUT_RESERVED91)
2976/* @brief XBARA output 92 ID. */
2977#define FSL_FEATURE_XBARA_OUTPUT92_ID (XBARA_OUT_RESERVED92)
2978/* @brief XBARA output 93 ID. */
2979#define FSL_FEATURE_XBARA_OUTPUT93_ID (XBARA_OUT_RESERVED93)
2980/* @brief XBARA output 94 ID. */
2981#define FSL_FEATURE_XBARA_OUTPUT94_ID (XBARA_OUT_RESERVED94)
2982/* @brief XBARA output 95 ID. */
2983#define FSL_FEATURE_XBARA_OUTPUT95_ID (XBARA_OUT_RESERVED95)
2984/* @brief XBARA output 96 ID. */
2985#define FSL_FEATURE_XBARA_OUTPUT96_ID (XBARA_OUT_RESERVED96)
2986/* @brief XBARA output 97 ID. */
2987#define FSL_FEATURE_XBARA_OUTPUT97_ID (XBARA_OUT_RESERVED97)
2988/* @brief XBARA output 98 ID. */
2989#define FSL_FEATURE_XBARA_OUTPUT98_ID (XBARA_OUT_RESERVED98)
2990/* @brief XBARA output 99 ID. */
2991#define FSL_FEATURE_XBARA_OUTPUT99_ID (XBARA_OUT_RESERVED99)
2992/* @brief XBARA output 100 ID. */
2993#define FSL_FEATURE_XBARA_OUTPUT100_ID (XBARA_OUT_RESERVED100)
2994/* @brief XBARA output 101 ID. */
2995#define FSL_FEATURE_XBARA_OUTPUT101_ID (XBARA_OUT_RESERVED101)
2996/* @brief XBARA output 102 ID. */
2997#define FSL_FEATURE_XBARA_OUTPUT102_ID (XBARA_OUT_RESERVED102)
2998/* @brief XBARA output 103 ID. */
2999#define FSL_FEATURE_XBARA_OUTPUT103_ID (XBARA_OUT_RESERVED103)
3000/* @brief XBARA output 104 ID. */
3001#define FSL_FEATURE_XBARA_OUTPUT104_ID (XBARA_OUT_RESERVED104)
3002/* @brief XBARA output 105 ID. */
3003#define FSL_FEATURE_XBARA_OUTPUT105_ID (XBARA_OUT_RESERVED105)
3004/* @brief XBARA output 106 ID. */
3005#define FSL_FEATURE_XBARA_OUTPUT106_ID (XBARA_OUT_RESERVED106)
3006/* @brief XBARA output 107 ID. */
3007#define FSL_FEATURE_XBARA_OUTPUT107_ID (XBARA_OUT_RESERVED107)
3008/* @brief XBARA output 108 ID. */
3009#define FSL_FEATURE_XBARA_OUTPUT108_ID (XBARA_OUT_RESERVED108)
3010/* @brief XBARA output 109 ID. */
3011#define FSL_FEATURE_XBARA_OUTPUT109_ID (XBARA_OUT_RESERVED109)
3012/* @brief XBARA output 110 ID. */
3013#define FSL_FEATURE_XBARA_OUTPUT110_ID (XBARA_OUT_RESERVED110)
3014/* @brief XBARA output 111 ID. */
3015#define FSL_FEATURE_XBARA_OUTPUT111_ID (XBARA_OUT_RESERVED111)
3016/* @brief XBARA output 112 ID. */
3017#define FSL_FEATURE_XBARA_OUTPUT112_ID (XBARA_OUT_RESERVED112)
3018/* @brief XBARA output 113 ID. */
3019#define FSL_FEATURE_XBARA_OUTPUT113_ID (XBARA_OUT_RESERVED113)
3020/* @brief XBARA output 114 ID. */
3021#define FSL_FEATURE_XBARA_OUTPUT114_ID (XBARA_OUT_RESERVED114)
3022/* @brief XBARA output 115 ID. */
3023#define FSL_FEATURE_XBARA_OUTPUT115_ID (XBARA_OUT_RESERVED115)
3024/* @brief XBARA output 116 ID. */
3025#define FSL_FEATURE_XBARA_OUTPUT116_ID (XBARA_OUT_RESERVED116)
3026/* @brief XBARA output 117 ID. */
3027#define FSL_FEATURE_XBARA_OUTPUT117_ID (XBARA_OUT_RESERVED117)
3028/* @brief XBARA output 118 ID. */
3029#define FSL_FEATURE_XBARA_OUTPUT118_ID (XBARA_OUT_RESERVED118)
3030/* @brief XBARA output 119 ID. */
3031#define FSL_FEATURE_XBARA_OUTPUT119_ID (XBARA_OUT_RESERVED119)
3032/* @brief XBARA output 120 ID. */
3033#define FSL_FEATURE_XBARA_OUTPUT120_ID (XBARA_OUT_RESERVED120)
3034/* @brief XBARA output 121 ID. */
3035#define FSL_FEATURE_XBARA_OUTPUT121_ID (XBARA_OUT_RESERVED121)
3036/* @brief XBARA output 122 ID. */
3037#define FSL_FEATURE_XBARA_OUTPUT122_ID (XBARA_OUT_RESERVED122)
3038/* @brief XBARA output 123 ID. */
3039#define FSL_FEATURE_XBARA_OUTPUT123_ID (XBARA_OUT_RESERVED123)
3040/* @brief XBARA output 124 ID. */
3041#define FSL_FEATURE_XBARA_OUTPUT124_ID (XBARA_OUT_RESERVED124)
3042/* @brief XBARA output 125 ID. */
3043#define FSL_FEATURE_XBARA_OUTPUT125_ID (XBARA_OUT_RESERVED125)
3044/* @brief XBARA output 126 ID. */
3045#define FSL_FEATURE_XBARA_OUTPUT126_ID (XBARA_OUT_RESERVED126)
3046/* @brief XBARA output 127 ID. */
3047#define FSL_FEATURE_XBARA_OUTPUT127_ID (XBARA_OUT_RESERVED127)
3048
3049/* XBARB module features */
3050
3051/* @brief Has single XBAR module. */
3052#define FSL_FEATURE_XBARB_HAS_SINGLE_MODULE (0)
3053/* @brief Maximum value of XBARB input. */
3054#define FSL_FEATURE_XBARB_MODULE_INPUTS (39)
3055/* @brief Maximum value of XBARB output. */
3056#define FSL_FEATURE_XBARB_MODULE_OUTPUTS (16)
3057/* @brief Half register position. */
3058#define FSL_FEATURE_XBARB_HALF_REGISTER_SHIFT (BP_XBARB_SEL0_SEL1)
3059/* @brief Number of interrupt requests. */
3060#define FSL_FEATURE_XBARB_INTERRUPT_COUNT (0)
3061/* @brief XBARB has input 0. */
3062#define FSL_FEATURE_XBARB_HAS_INPUT0 (1)
3063/* @brief XBARB has input 1. */
3064#define FSL_FEATURE_XBARB_HAS_INPUT1 (1)
3065/* @brief XBARB has input 2. */
3066#define FSL_FEATURE_XBARB_HAS_INPUT2 (1)
3067/* @brief XBARB has input 3. */
3068#define FSL_FEATURE_XBARB_HAS_INPUT3 (1)
3069/* @brief XBARB has input 4. */
3070#define FSL_FEATURE_XBARB_HAS_INPUT4 (1)
3071/* @brief XBARB has input 5. */
3072#define FSL_FEATURE_XBARB_HAS_INPUT5 (1)
3073/* @brief XBARB has input 6. */
3074#define FSL_FEATURE_XBARB_HAS_INPUT6 (1)
3075/* @brief XBARB has input 7. */
3076#define FSL_FEATURE_XBARB_HAS_INPUT7 (1)
3077/* @brief XBARB has input 8. */
3078#define FSL_FEATURE_XBARB_HAS_INPUT8 (1)
3079/* @brief XBARB has input 9. */
3080#define FSL_FEATURE_XBARB_HAS_INPUT9 (1)
3081/* @brief XBARB has input 10. */
3082#define FSL_FEATURE_XBARB_HAS_INPUT10 (1)
3083/* @brief XBARB has input 11. */
3084#define FSL_FEATURE_XBARB_HAS_INPUT11 (1)
3085/* @brief XBARB has input 12. */
3086#define FSL_FEATURE_XBARB_HAS_INPUT12 (1)
3087/* @brief XBARB has input 13. */
3088#define FSL_FEATURE_XBARB_HAS_INPUT13 (1)
3089/* @brief XBARB has input 14. */
3090#define FSL_FEATURE_XBARB_HAS_INPUT14 (1)
3091/* @brief XBARB has input 15. */
3092#define FSL_FEATURE_XBARB_HAS_INPUT15 (1)
3093/* @brief XBARB has input 16. */
3094#define FSL_FEATURE_XBARB_HAS_INPUT16 (1)
3095/* @brief XBARB has input 17. */
3096#define FSL_FEATURE_XBARB_HAS_INPUT17 (1)
3097/* @brief XBARB has input 18. */
3098#define FSL_FEATURE_XBARB_HAS_INPUT18 (1)
3099/* @brief XBARB has input 19. */
3100#define FSL_FEATURE_XBARB_HAS_INPUT19 (1)
3101/* @brief XBARB has input 20. */
3102#define FSL_FEATURE_XBARB_HAS_INPUT20 (1)
3103/* @brief XBARB has input 21. */
3104#define FSL_FEATURE_XBARB_HAS_INPUT21 (1)
3105/* @brief XBARB has input 22. */
3106#define FSL_FEATURE_XBARB_HAS_INPUT22 (1)
3107/* @brief XBARB has input 23. */
3108#define FSL_FEATURE_XBARB_HAS_INPUT23 (1)
3109/* @brief XBARB has input 24. */
3110#define FSL_FEATURE_XBARB_HAS_INPUT24 (1)
3111/* @brief XBARB has input 25. */
3112#define FSL_FEATURE_XBARB_HAS_INPUT25 (1)
3113/* @brief XBARB has input 26. */
3114#define FSL_FEATURE_XBARB_HAS_INPUT26 (1)
3115/* @brief XBARB has input 27. */
3116#define FSL_FEATURE_XBARB_HAS_INPUT27 (1)
3117/* @brief XBARB has input 28. */
3118#define FSL_FEATURE_XBARB_HAS_INPUT28 (1)
3119/* @brief XBARB has input 29. */
3120#define FSL_FEATURE_XBARB_HAS_INPUT29 (1)
3121/* @brief XBARB has input 30. */
3122#define FSL_FEATURE_XBARB_HAS_INPUT30 (1)
3123/* @brief XBARB has input 31. */
3124#define FSL_FEATURE_XBARB_HAS_INPUT31 (1)
3125/* @brief XBARB has input 32. */
3126#define FSL_FEATURE_XBARB_HAS_INPUT32 (1)
3127/* @brief XBARB has input 33. */
3128#define FSL_FEATURE_XBARB_HAS_INPUT33 (1)
3129/* @brief XBARB has input 34. */
3130#define FSL_FEATURE_XBARB_HAS_INPUT34 (1)
3131/* @brief XBARB has input 35. */
3132#define FSL_FEATURE_XBARB_HAS_INPUT35 (1)
3133/* @brief XBARB has input 36. */
3134#define FSL_FEATURE_XBARB_HAS_INPUT36 (1)
3135/* @brief XBARB has input 37. */
3136#define FSL_FEATURE_XBARB_HAS_INPUT37 (1)
3137/* @brief XBARB has input 38. */
3138#define FSL_FEATURE_XBARB_HAS_INPUT38 (1)
3139/* @brief XBARB has input 39. */
3140#define FSL_FEATURE_XBARB_HAS_INPUT39 (0)
3141/* @brief XBARB has input 40. */
3142#define FSL_FEATURE_XBARB_HAS_INPUT40 (0)
3143/* @brief XBARB has input 41. */
3144#define FSL_FEATURE_XBARB_HAS_INPUT41 (0)
3145/* @brief XBARB has input 42. */
3146#define FSL_FEATURE_XBARB_HAS_INPUT42 (0)
3147/* @brief XBARB has input 43. */
3148#define FSL_FEATURE_XBARB_HAS_INPUT43 (0)
3149/* @brief XBARB has input 44. */
3150#define FSL_FEATURE_XBARB_HAS_INPUT44 (0)
3151/* @brief XBARB has input 45. */
3152#define FSL_FEATURE_XBARB_HAS_INPUT45 (0)
3153/* @brief XBARB has input 46. */
3154#define FSL_FEATURE_XBARB_HAS_INPUT46 (0)
3155/* @brief XBARB has input 47. */
3156#define FSL_FEATURE_XBARB_HAS_INPUT47 (0)
3157/* @brief XBARB has input 48. */
3158#define FSL_FEATURE_XBARB_HAS_INPUT48 (0)
3159/* @brief XBARB has input 49. */
3160#define FSL_FEATURE_XBARB_HAS_INPUT49 (0)
3161/* @brief XBARB has input 50. */
3162#define FSL_FEATURE_XBARB_HAS_INPUT50 (0)
3163/* @brief XBARB has input 51. */
3164#define FSL_FEATURE_XBARB_HAS_INPUT51 (0)
3165/* @brief XBARB has input 52. */
3166#define FSL_FEATURE_XBARB_HAS_INPUT52 (0)
3167/* @brief XBARB has input 53. */
3168#define FSL_FEATURE_XBARB_HAS_INPUT53 (0)
3169/* @brief XBARB has input 54. */
3170#define FSL_FEATURE_XBARB_HAS_INPUT54 (0)
3171/* @brief XBARB has input 55. */
3172#define FSL_FEATURE_XBARB_HAS_INPUT55 (0)
3173/* @brief XBARB has input 56. */
3174#define FSL_FEATURE_XBARB_HAS_INPUT56 (0)
3175/* @brief XBARB has input 57. */
3176#define FSL_FEATURE_XBARB_HAS_INPUT57 (0)
3177/* @brief XBARB has input 58. */
3178#define FSL_FEATURE_XBARB_HAS_INPUT58 (0)
3179/* @brief XBARB has input 59. */
3180#define FSL_FEATURE_XBARB_HAS_INPUT59 (0)
3181/* @brief XBARB has input 60. */
3182#define FSL_FEATURE_XBARB_HAS_INPUT60 (0)
3183/* @brief XBARB has input 61. */
3184#define FSL_FEATURE_XBARB_HAS_INPUT61 (0)
3185/* @brief XBARB has input 62. */
3186#define FSL_FEATURE_XBARB_HAS_INPUT62 (0)
3187/* @brief XBARB has input 63. */
3188#define FSL_FEATURE_XBARB_HAS_INPUT63 (0)
3189/* @brief XBARB has input 64. */
3190#define FSL_FEATURE_XBARB_HAS_INPUT64 (0)
3191/* @brief XBARB has input 65. */
3192#define FSL_FEATURE_XBARB_HAS_INPUT65 (0)
3193/* @brief XBARB has input 66. */
3194#define FSL_FEATURE_XBARB_HAS_INPUT66 (0)
3195/* @brief XBARB has input 67. */
3196#define FSL_FEATURE_XBARB_HAS_INPUT67 (0)
3197/* @brief XBARB has input 68. */
3198#define FSL_FEATURE_XBARB_HAS_INPUT68 (0)
3199/* @brief XBARB has input 69. */
3200#define FSL_FEATURE_XBARB_HAS_INPUT69 (0)
3201/* @brief XBARB has input 70. */
3202#define FSL_FEATURE_XBARB_HAS_INPUT70 (0)
3203/* @brief XBARB has input 71. */
3204#define FSL_FEATURE_XBARB_HAS_INPUT71 (0)
3205/* @brief XBARB has input 72. */
3206#define FSL_FEATURE_XBARB_HAS_INPUT72 (0)
3207/* @brief XBARB has input 73. */
3208#define FSL_FEATURE_XBARB_HAS_INPUT73 (0)
3209/* @brief XBARB has input 74. */
3210#define FSL_FEATURE_XBARB_HAS_INPUT74 (0)
3211/* @brief XBARB has input 75. */
3212#define FSL_FEATURE_XBARB_HAS_INPUT75 (0)
3213/* @brief XBARB has input 76. */
3214#define FSL_FEATURE_XBARB_HAS_INPUT76 (0)
3215/* @brief XBARB has input 77. */
3216#define FSL_FEATURE_XBARB_HAS_INPUT77 (0)
3217/* @brief XBARB has input 78. */
3218#define FSL_FEATURE_XBARB_HAS_INPUT78 (0)
3219/* @brief XBARB has input 79. */
3220#define FSL_FEATURE_XBARB_HAS_INPUT79 (0)
3221/* @brief XBARB has input 80. */
3222#define FSL_FEATURE_XBARB_HAS_INPUT80 (0)
3223/* @brief XBARB has input 81. */
3224#define FSL_FEATURE_XBARB_HAS_INPUT81 (0)
3225/* @brief XBARB has input 82. */
3226#define FSL_FEATURE_XBARB_HAS_INPUT82 (0)
3227/* @brief XBARB has input 83. */
3228#define FSL_FEATURE_XBARB_HAS_INPUT83 (0)
3229/* @brief XBARB has input 84. */
3230#define FSL_FEATURE_XBARB_HAS_INPUT84 (0)
3231/* @brief XBARB has input 85. */
3232#define FSL_FEATURE_XBARB_HAS_INPUT85 (0)
3233/* @brief XBARB has input 86. */
3234#define FSL_FEATURE_XBARB_HAS_INPUT86 (0)
3235/* @brief XBARB has input 87. */
3236#define FSL_FEATURE_XBARB_HAS_INPUT87 (0)
3237/* @brief XBARB has input 88. */
3238#define FSL_FEATURE_XBARB_HAS_INPUT88 (0)
3239/* @brief XBARB has input 89. */
3240#define FSL_FEATURE_XBARB_HAS_INPUT89 (0)
3241/* @brief XBARB has input 90. */
3242#define FSL_FEATURE_XBARB_HAS_INPUT90 (0)
3243/* @brief XBARB has input 91. */
3244#define FSL_FEATURE_XBARB_HAS_INPUT91 (0)
3245/* @brief XBARB has input 92. */
3246#define FSL_FEATURE_XBARB_HAS_INPUT92 (0)
3247/* @brief XBARB has input 93. */
3248#define FSL_FEATURE_XBARB_HAS_INPUT93 (0)
3249/* @brief XBARB has input 94. */
3250#define FSL_FEATURE_XBARB_HAS_INPUT94 (0)
3251/* @brief XBARB has input 95. */
3252#define FSL_FEATURE_XBARB_HAS_INPUT95 (0)
3253/* @brief XBARB has input 96. */
3254#define FSL_FEATURE_XBARB_HAS_INPUT96 (0)
3255/* @brief XBARB has input 97. */
3256#define FSL_FEATURE_XBARB_HAS_INPUT97 (0)
3257/* @brief XBARB has input 98. */
3258#define FSL_FEATURE_XBARB_HAS_INPUT98 (0)
3259/* @brief XBARB has input 99. */
3260#define FSL_FEATURE_XBARB_HAS_INPUT99 (0)
3261/* @brief XBARB has input 100. */
3262#define FSL_FEATURE_XBARB_HAS_INPUT100 (0)
3263/* @brief XBARB has input 101. */
3264#define FSL_FEATURE_XBARB_HAS_INPUT101 (0)
3265/* @brief XBARB has input 102. */
3266#define FSL_FEATURE_XBARB_HAS_INPUT102 (0)
3267/* @brief XBARB has input 103. */
3268#define FSL_FEATURE_XBARB_HAS_INPUT103 (0)
3269/* @brief XBARB has input 104. */
3270#define FSL_FEATURE_XBARB_HAS_INPUT104 (0)
3271/* @brief XBARB has input 105. */
3272#define FSL_FEATURE_XBARB_HAS_INPUT105 (0)
3273/* @brief XBARB has input 106. */
3274#define FSL_FEATURE_XBARB_HAS_INPUT106 (0)
3275/* @brief XBARB has input 107. */
3276#define FSL_FEATURE_XBARB_HAS_INPUT107 (0)
3277/* @brief XBARB has input 108. */
3278#define FSL_FEATURE_XBARB_HAS_INPUT108 (0)
3279/* @brief XBARB has input 109. */
3280#define FSL_FEATURE_XBARB_HAS_INPUT109 (0)
3281/* @brief XBARB has input 110. */
3282#define FSL_FEATURE_XBARB_HAS_INPUT110 (0)
3283/* @brief XBARB has input 111. */
3284#define FSL_FEATURE_XBARB_HAS_INPUT111 (0)
3285/* @brief XBARB has input 112. */
3286#define FSL_FEATURE_XBARB_HAS_INPUT112 (0)
3287/* @brief XBARB has input 113. */
3288#define FSL_FEATURE_XBARB_HAS_INPUT113 (0)
3289/* @brief XBARB has input 114. */
3290#define FSL_FEATURE_XBARB_HAS_INPUT114 (0)
3291/* @brief XBARB has input 115. */
3292#define FSL_FEATURE_XBARB_HAS_INPUT115 (0)
3293/* @brief XBARB has input 116. */
3294#define FSL_FEATURE_XBARB_HAS_INPUT116 (0)
3295/* @brief XBARB has input 117. */
3296#define FSL_FEATURE_XBARB_HAS_INPUT117 (0)
3297/* @brief XBARB has input 118. */
3298#define FSL_FEATURE_XBARB_HAS_INPUT118 (0)
3299/* @brief XBARB has input 119. */
3300#define FSL_FEATURE_XBARB_HAS_INPUT119 (0)
3301/* @brief XBARB has input 120. */
3302#define FSL_FEATURE_XBARB_HAS_INPUT120 (0)
3303/* @brief XBARB has input 121. */
3304#define FSL_FEATURE_XBARB_HAS_INPUT121 (0)
3305/* @brief XBARB has input 122. */
3306#define FSL_FEATURE_XBARB_HAS_INPUT122 (0)
3307/* @brief XBARB has input 123. */
3308#define FSL_FEATURE_XBARB_HAS_INPUT123 (0)
3309/* @brief XBARB has input 124. */
3310#define FSL_FEATURE_XBARB_HAS_INPUT124 (0)
3311/* @brief XBARB has input 125. */
3312#define FSL_FEATURE_XBARB_HAS_INPUT125 (0)
3313/* @brief XBARB has input 126. */
3314#define FSL_FEATURE_XBARB_HAS_INPUT126 (0)
3315/* @brief XBARB has input 127. */
3316#define FSL_FEATURE_XBARB_HAS_INPUT127 (0)
3317/* @brief XBARB has output 0. */
3318#define FSL_FEATURE_XBARB_HAS_OUTPUT0 (1)
3319/* @brief XBARB has output 1. */
3320#define FSL_FEATURE_XBARB_HAS_OUTPUT1 (1)
3321/* @brief XBARB has output 2. */
3322#define FSL_FEATURE_XBARB_HAS_OUTPUT2 (1)
3323/* @brief XBARB has output 3. */
3324#define FSL_FEATURE_XBARB_HAS_OUTPUT3 (1)
3325/* @brief XBARB has output 4. */
3326#define FSL_FEATURE_XBARB_HAS_OUTPUT4 (1)
3327/* @brief XBARB has output 5. */
3328#define FSL_FEATURE_XBARB_HAS_OUTPUT5 (1)
3329/* @brief XBARB has output 6. */
3330#define FSL_FEATURE_XBARB_HAS_OUTPUT6 (1)
3331/* @brief XBARB has output 7. */
3332#define FSL_FEATURE_XBARB_HAS_OUTPUT7 (1)
3333/* @brief XBARB has output 8. */
3334#define FSL_FEATURE_XBARB_HAS_OUTPUT8 (1)
3335/* @brief XBARB has output 9. */
3336#define FSL_FEATURE_XBARB_HAS_OUTPUT9 (1)
3337/* @brief XBARB has output 10. */
3338#define FSL_FEATURE_XBARB_HAS_OUTPUT10 (1)
3339/* @brief XBARB has output 11. */
3340#define FSL_FEATURE_XBARB_HAS_OUTPUT11 (1)
3341/* @brief XBARB has output 12. */
3342#define FSL_FEATURE_XBARB_HAS_OUTPUT12 (1)
3343/* @brief XBARB has output 13. */
3344#define FSL_FEATURE_XBARB_HAS_OUTPUT13 (1)
3345/* @brief XBARB has output 14. */
3346#define FSL_FEATURE_XBARB_HAS_OUTPUT14 (1)
3347/* @brief XBARB has output 15. */
3348#define FSL_FEATURE_XBARB_HAS_OUTPUT15 (1)
3349/* @brief XBARB has output 16. */
3350#define FSL_FEATURE_XBARB_HAS_OUTPUT16 (0)
3351/* @brief XBARB has output 17. */
3352#define FSL_FEATURE_XBARB_HAS_OUTPUT17 (0)
3353/* @brief XBARB has output 18. */
3354#define FSL_FEATURE_XBARB_HAS_OUTPUT18 (0)
3355/* @brief XBARB has output 19. */
3356#define FSL_FEATURE_XBARB_HAS_OUTPUT19 (0)
3357/* @brief XBARB has output 20. */
3358#define FSL_FEATURE_XBARB_HAS_OUTPUT20 (0)
3359/* @brief XBARB has output 21. */
3360#define FSL_FEATURE_XBARB_HAS_OUTPUT21 (0)
3361/* @brief XBARB has output 22. */
3362#define FSL_FEATURE_XBARB_HAS_OUTPUT22 (0)
3363/* @brief XBARB has output 23. */
3364#define FSL_FEATURE_XBARB_HAS_OUTPUT23 (0)
3365/* @brief XBARB has output 24. */
3366#define FSL_FEATURE_XBARB_HAS_OUTPUT24 (0)
3367/* @brief XBARB has output 25. */
3368#define FSL_FEATURE_XBARB_HAS_OUTPUT25 (0)
3369/* @brief XBARB has output 26. */
3370#define FSL_FEATURE_XBARB_HAS_OUTPUT26 (0)
3371/* @brief XBARB has output 27. */
3372#define FSL_FEATURE_XBARB_HAS_OUTPUT27 (0)
3373/* @brief XBARB has output 28. */
3374#define FSL_FEATURE_XBARB_HAS_OUTPUT28 (0)
3375/* @brief XBARB has output 29. */
3376#define FSL_FEATURE_XBARB_HAS_OUTPUT29 (0)
3377/* @brief XBARB has output 30. */
3378#define FSL_FEATURE_XBARB_HAS_OUTPUT30 (0)
3379/* @brief XBARB has output 31. */
3380#define FSL_FEATURE_XBARB_HAS_OUTPUT31 (0)
3381/* @brief XBARB has output 32. */
3382#define FSL_FEATURE_XBARB_HAS_OUTPUT32 (0)
3383/* @brief XBARB has output 33. */
3384#define FSL_FEATURE_XBARB_HAS_OUTPUT33 (0)
3385/* @brief XBARB has output 34. */
3386#define FSL_FEATURE_XBARB_HAS_OUTPUT34 (0)
3387/* @brief XBARB has output 35. */
3388#define FSL_FEATURE_XBARB_HAS_OUTPUT35 (0)
3389/* @brief XBARB has output 36. */
3390#define FSL_FEATURE_XBARB_HAS_OUTPUT36 (0)
3391/* @brief XBARB has output 37. */
3392#define FSL_FEATURE_XBARB_HAS_OUTPUT37 (0)
3393/* @brief XBARB has output 38. */
3394#define FSL_FEATURE_XBARB_HAS_OUTPUT38 (0)
3395/* @brief XBARB has output 39. */
3396#define FSL_FEATURE_XBARB_HAS_OUTPUT39 (0)
3397/* @brief XBARB has output 40. */
3398#define FSL_FEATURE_XBARB_HAS_OUTPUT40 (0)
3399/* @brief XBARB has output 41. */
3400#define FSL_FEATURE_XBARB_HAS_OUTPUT41 (0)
3401/* @brief XBARB has output 42. */
3402#define FSL_FEATURE_XBARB_HAS_OUTPUT42 (0)
3403/* @brief XBARB has output 43. */
3404#define FSL_FEATURE_XBARB_HAS_OUTPUT43 (0)
3405/* @brief XBARB has output 44. */
3406#define FSL_FEATURE_XBARB_HAS_OUTPUT44 (0)
3407/* @brief XBARB has output 45. */
3408#define FSL_FEATURE_XBARB_HAS_OUTPUT45 (0)
3409/* @brief XBARB has output 46. */
3410#define FSL_FEATURE_XBARB_HAS_OUTPUT46 (0)
3411/* @brief XBARB has output 47. */
3412#define FSL_FEATURE_XBARB_HAS_OUTPUT47 (0)
3413/* @brief XBARB has output 48. */
3414#define FSL_FEATURE_XBARB_HAS_OUTPUT48 (0)
3415/* @brief XBARB has output 49. */
3416#define FSL_FEATURE_XBARB_HAS_OUTPUT49 (0)
3417/* @brief XBARB has output 50. */
3418#define FSL_FEATURE_XBARB_HAS_OUTPUT50 (0)
3419/* @brief XBARB has output 51. */
3420#define FSL_FEATURE_XBARB_HAS_OUTPUT51 (0)
3421/* @brief XBARB has output 52. */
3422#define FSL_FEATURE_XBARB_HAS_OUTPUT52 (0)
3423/* @brief XBARB has output 53. */
3424#define FSL_FEATURE_XBARB_HAS_OUTPUT53 (0)
3425/* @brief XBARB has output 54. */
3426#define FSL_FEATURE_XBARB_HAS_OUTPUT54 (0)
3427/* @brief XBARB has output 55. */
3428#define FSL_FEATURE_XBARB_HAS_OUTPUT55 (0)
3429/* @brief XBARB has output 56. */
3430#define FSL_FEATURE_XBARB_HAS_OUTPUT56 (0)
3431/* @brief XBARB has output 57. */
3432#define FSL_FEATURE_XBARB_HAS_OUTPUT57 (0)
3433/* @brief XBARB has output 58. */
3434#define FSL_FEATURE_XBARB_HAS_OUTPUT58 (0)
3435/* @brief XBARB has output 59. */
3436#define FSL_FEATURE_XBARB_HAS_OUTPUT59 (0)
3437/* @brief XBARB has output 60. */
3438#define FSL_FEATURE_XBARB_HAS_OUTPUT60 (0)
3439/* @brief XBARB has output 61. */
3440#define FSL_FEATURE_XBARB_HAS_OUTPUT61 (0)
3441/* @brief XBARB has output 62. */
3442#define FSL_FEATURE_XBARB_HAS_OUTPUT62 (0)
3443/* @brief XBARB has output 63. */
3444#define FSL_FEATURE_XBARB_HAS_OUTPUT63 (0)
3445/* @brief XBARB has output 64. */
3446#define FSL_FEATURE_XBARB_HAS_OUTPUT64 (0)
3447/* @brief XBARB has output 65. */
3448#define FSL_FEATURE_XBARB_HAS_OUTPUT65 (0)
3449/* @brief XBARB has output 66. */
3450#define FSL_FEATURE_XBARB_HAS_OUTPUT66 (0)
3451/* @brief XBARB has output 67. */
3452#define FSL_FEATURE_XBARB_HAS_OUTPUT67 (0)
3453/* @brief XBARB has output 68. */
3454#define FSL_FEATURE_XBARB_HAS_OUTPUT68 (0)
3455/* @brief XBARB has output 69. */
3456#define FSL_FEATURE_XBARB_HAS_OUTPUT69 (0)
3457/* @brief XBARB has output 70. */
3458#define FSL_FEATURE_XBARB_HAS_OUTPUT70 (0)
3459/* @brief XBARB has output 71. */
3460#define FSL_FEATURE_XBARB_HAS_OUTPUT71 (0)
3461/* @brief XBARB has output 72. */
3462#define FSL_FEATURE_XBARB_HAS_OUTPUT72 (0)
3463/* @brief XBARB has output 73. */
3464#define FSL_FEATURE_XBARB_HAS_OUTPUT73 (0)
3465/* @brief XBARB has output 74. */
3466#define FSL_FEATURE_XBARB_HAS_OUTPUT74 (0)
3467/* @brief XBARB has output 75. */
3468#define FSL_FEATURE_XBARB_HAS_OUTPUT75 (0)
3469/* @brief XBARB has output 76. */
3470#define FSL_FEATURE_XBARB_HAS_OUTPUT76 (0)
3471/* @brief XBARB has output 77. */
3472#define FSL_FEATURE_XBARB_HAS_OUTPUT77 (0)
3473/* @brief XBARB has output 78. */
3474#define FSL_FEATURE_XBARB_HAS_OUTPUT78 (0)
3475/* @brief XBARB has output 79. */
3476#define FSL_FEATURE_XBARB_HAS_OUTPUT79 (0)
3477/* @brief XBARB has output 80. */
3478#define FSL_FEATURE_XBARB_HAS_OUTPUT80 (0)
3479/* @brief XBARB has output 81. */
3480#define FSL_FEATURE_XBARB_HAS_OUTPUT81 (0)
3481/* @brief XBARB has output 82. */
3482#define FSL_FEATURE_XBARB_HAS_OUTPUT82 (0)
3483/* @brief XBARB has output 83. */
3484#define FSL_FEATURE_XBARB_HAS_OUTPUT83 (0)
3485/* @brief XBARB has output 84. */
3486#define FSL_FEATURE_XBARB_HAS_OUTPUT84 (0)
3487/* @brief XBARB has output 85. */
3488#define FSL_FEATURE_XBARB_HAS_OUTPUT85 (0)
3489/* @brief XBARB has output 86. */
3490#define FSL_FEATURE_XBARB_HAS_OUTPUT86 (0)
3491/* @brief XBARB has output 87. */
3492#define FSL_FEATURE_XBARB_HAS_OUTPUT87 (0)
3493/* @brief XBARB has output 88. */
3494#define FSL_FEATURE_XBARB_HAS_OUTPUT88 (0)
3495/* @brief XBARB has output 89. */
3496#define FSL_FEATURE_XBARB_HAS_OUTPUT89 (0)
3497/* @brief XBARB has output 90. */
3498#define FSL_FEATURE_XBARB_HAS_OUTPUT90 (0)
3499/* @brief XBARB has output 91. */
3500#define FSL_FEATURE_XBARB_HAS_OUTPUT91 (0)
3501/* @brief XBARB has output 92. */
3502#define FSL_FEATURE_XBARB_HAS_OUTPUT92 (0)
3503/* @brief XBARB has output 93. */
3504#define FSL_FEATURE_XBARB_HAS_OUTPUT93 (0)
3505/* @brief XBARB has output 94. */
3506#define FSL_FEATURE_XBARB_HAS_OUTPUT94 (0)
3507/* @brief XBARB has output 95. */
3508#define FSL_FEATURE_XBARB_HAS_OUTPUT95 (0)
3509/* @brief XBARB has output 96. */
3510#define FSL_FEATURE_XBARB_HAS_OUTPUT96 (0)
3511/* @brief XBARB has output 97. */
3512#define FSL_FEATURE_XBARB_HAS_OUTPUT97 (0)
3513/* @brief XBARB has output 98. */
3514#define FSL_FEATURE_XBARB_HAS_OUTPUT98 (0)
3515/* @brief XBARB has output 99. */
3516#define FSL_FEATURE_XBARB_HAS_OUTPUT99 (0)
3517/* @brief XBARB has output 100. */
3518#define FSL_FEATURE_XBARB_HAS_OUTPUT100 (0)
3519/* @brief XBARB has output 101. */
3520#define FSL_FEATURE_XBARB_HAS_OUTPUT101 (0)
3521/* @brief XBARB has output 102. */
3522#define FSL_FEATURE_XBARB_HAS_OUTPUT102 (0)
3523/* @brief XBARB has output 103. */
3524#define FSL_FEATURE_XBARB_HAS_OUTPUT103 (0)
3525/* @brief XBARB has output 104. */
3526#define FSL_FEATURE_XBARB_HAS_OUTPUT104 (0)
3527/* @brief XBARB has output 105. */
3528#define FSL_FEATURE_XBARB_HAS_OUTPUT105 (0)
3529/* @brief XBARB has output 106. */
3530#define FSL_FEATURE_XBARB_HAS_OUTPUT106 (0)
3531/* @brief XBARB has output 107. */
3532#define FSL_FEATURE_XBARB_HAS_OUTPUT107 (0)
3533/* @brief XBARB has output 108. */
3534#define FSL_FEATURE_XBARB_HAS_OUTPUT108 (0)
3535/* @brief XBARB has output 109. */
3536#define FSL_FEATURE_XBARB_HAS_OUTPUT109 (0)
3537/* @brief XBARB has output 110. */
3538#define FSL_FEATURE_XBARB_HAS_OUTPUT110 (0)
3539/* @brief XBARB has output 111. */
3540#define FSL_FEATURE_XBARB_HAS_OUTPUT111 (0)
3541/* @brief XBARB has output 112. */
3542#define FSL_FEATURE_XBARB_HAS_OUTPUT112 (0)
3543/* @brief XBARB has output 113. */
3544#define FSL_FEATURE_XBARB_HAS_OUTPUT113 (0)
3545/* @brief XBARB has output 114. */
3546#define FSL_FEATURE_XBARB_HAS_OUTPUT114 (0)
3547/* @brief XBARB has output 115. */
3548#define FSL_FEATURE_XBARB_HAS_OUTPUT115 (0)
3549/* @brief XBARB has output 116. */
3550#define FSL_FEATURE_XBARB_HAS_OUTPUT116 (0)
3551/* @brief XBARB has output 117. */
3552#define FSL_FEATURE_XBARB_HAS_OUTPUT117 (0)
3553/* @brief XBARB has output 118. */
3554#define FSL_FEATURE_XBARB_HAS_OUTPUT118 (0)
3555/* @brief XBARB has output 119. */
3556#define FSL_FEATURE_XBARB_HAS_OUTPUT119 (0)
3557/* @brief XBARB has output 120. */
3558#define FSL_FEATURE_XBARB_HAS_OUTPUT120 (0)
3559/* @brief XBARB has output 121. */
3560#define FSL_FEATURE_XBARB_HAS_OUTPUT121 (0)
3561/* @brief XBARB has output 122. */
3562#define FSL_FEATURE_XBARB_HAS_OUTPUT122 (0)
3563/* @brief XBARB has output 123. */
3564#define FSL_FEATURE_XBARB_HAS_OUTPUT123 (0)
3565/* @brief XBARB has output 124. */
3566#define FSL_FEATURE_XBARB_HAS_OUTPUT124 (0)
3567/* @brief XBARB has output 125. */
3568#define FSL_FEATURE_XBARB_HAS_OUTPUT125 (0)
3569/* @brief XBARB has output 126. */
3570#define FSL_FEATURE_XBARB_HAS_OUTPUT126 (0)
3571/* @brief XBARB has output 127. */
3572#define FSL_FEATURE_XBARB_HAS_OUTPUT127 (0)
3573/* @brief XBARB input 0 ID. */
3574#define FSL_FEATURE_XBARB_INPUT0_ID (Cmp0Output)
3575/* @brief XBARB input 1 ID. */
3576#define FSL_FEATURE_XBARB_INPUT1_ID (Cmp1Output)
3577/* @brief XBARB input 2 ID. */
3578#define FSL_FEATURE_XBARB_INPUT2_ID (Cmp2Output)
3579/* @brief XBARB input 3 ID. */
3580#define FSL_FEATURE_XBARB_INPUT3_ID (Cmp3Output)
3581/* @brief XBARB input 4 ID. */
3582#define FSL_FEATURE_XBARB_INPUT4_ID (Ftm0Match)
3583/* @brief XBARB input 5 ID. */
3584#define FSL_FEATURE_XBARB_INPUT5_ID (Ftm0Extrig)
3585/* @brief XBARB input 6 ID. */
3586#define FSL_FEATURE_XBARB_INPUT6_ID (Ftm3Match)
3587/* @brief XBARB input 7 ID. */
3588#define FSL_FEATURE_XBARB_INPUT7_ID (Ftm3Extrig)
3589/* @brief XBARB input 8 ID. */
3590#define FSL_FEATURE_XBARB_INPUT8_ID (Pwm0Ch0Trg0)
3591/* @brief XBARB input 9 ID. */
3592#define FSL_FEATURE_XBARB_INPUT9_ID (Pwm0Ch1Trg0)
3593/* @brief XBARB input 10 ID. */
3594#define FSL_FEATURE_XBARB_INPUT10_ID (Pwm0Ch2Trg0)
3595/* @brief XBARB input 11 ID. */
3596#define FSL_FEATURE_XBARB_INPUT11_ID (Pwm0Ch3Trg0)
3597/* @brief XBARB input 12 ID. */
3598#define FSL_FEATURE_XBARB_INPUT12_ID (Pdb0Ch0Output)
3599/* @brief XBARB input 13 ID. */
3600#define FSL_FEATURE_XBARB_INPUT13_ID (Hsadc0Cca)
3601/* @brief XBARB input 14 ID. */
3602#define FSL_FEATURE_XBARB_INPUT14_ID (XbarIn2)
3603/* @brief XBARB input 15 ID. */
3604#define FSL_FEATURE_XBARB_INPUT15_ID (XbarIn3)
3605/* @brief XBARB input 16 ID. */
3606#define FSL_FEATURE_XBARB_INPUT16_ID (Ftm1Match)
3607/* @brief XBARB input 17 ID. */
3608#define FSL_FEATURE_XBARB_INPUT17_ID (Ftm1Extrig)
3609/* @brief XBARB input 18 ID. */
3610#define FSL_FEATURE_XBARB_INPUT18_ID (DmaCh0Done)
3611/* @brief XBARB input 19 ID. */
3612#define FSL_FEATURE_XBARB_INPUT19_ID (DmaCh1Done)
3613/* @brief XBARB input 20 ID. */
3614#define FSL_FEATURE_XBARB_INPUT20_ID (XbarIn10)
3615/* @brief XBARB input 21 ID. */
3616#define FSL_FEATURE_XBARB_INPUT21_ID (XbarIn11)
3617/* @brief XBARB input 22 ID. */
3618#define FSL_FEATURE_XBARB_INPUT22_ID (DmaCh6Done)
3619/* @brief XBARB input 23 ID. */
3620#define FSL_FEATURE_XBARB_INPUT23_ID (DmaCh7Done)
3621/* @brief XBARB input 24 ID. */
3622#define FSL_FEATURE_XBARB_INPUT24_ID (PitTrigger0)
3623/* @brief XBARB input 25 ID. */
3624#define FSL_FEATURE_XBARB_INPUT25_ID (PitTrigger1)
3625/* @brief XBARB input 26 ID. */
3626#define FSL_FEATURE_XBARB_INPUT26_ID (Pdb1Ch0Output)
3627/* @brief XBARB input 27 ID. */
3628#define FSL_FEATURE_XBARB_INPUT27_ID (Hsadc0Ccb)
3629/* @brief XBARB input 28 ID. */
3630#define FSL_FEATURE_XBARB_INPUT28_ID (Pwm1Ch0Trg0OrTrg1)
3631/* @brief XBARB input 29 ID. */
3632#define FSL_FEATURE_XBARB_INPUT29_ID (Pwm1Ch1Trg0OrTrg1)
3633/* @brief XBARB input 30 ID. */
3634#define FSL_FEATURE_XBARB_INPUT30_ID (Pwm1Ch2Trg0OrTrg1)
3635/* @brief XBARB input 31 ID. */
3636#define FSL_FEATURE_XBARB_INPUT31_ID (Pwm1Ch3Trg0OrTrg1)
3637/* @brief XBARB input 32 ID. */
3638#define FSL_FEATURE_XBARB_INPUT32_ID (Ftm2Match)
3639/* @brief XBARB input 33 ID. */
3640#define FSL_FEATURE_XBARB_INPUT33_ID (Ftm2Extrig)
3641/* @brief XBARB input 34 ID. */
3642#define FSL_FEATURE_XBARB_INPUT34_ID (Pdb0Ch1Output)
3643/* @brief XBARB input 35 ID. */
3644#define FSL_FEATURE_XBARB_INPUT35_ID (Pdb1Ch1Output)
3645/* @brief XBARB input 36 ID. */
3646#define FSL_FEATURE_XBARB_INPUT36_ID (Hsadc1Cca)
3647/* @brief XBARB input 37 ID. */
3648#define FSL_FEATURE_XBARB_INPUT37_ID (Hsadc1Ccb)
3649/* @brief XBARB input 38 ID. */
3650#define FSL_FEATURE_XBARB_INPUT38_ID (Adc0Coco)
3651/* @brief XBARB input 39 ID. */
3652#define FSL_FEATURE_XBARB_INPUT39_ID (XBARB_IN_RESERVED39)
3653/* @brief XBARB input 40 ID. */
3654#define FSL_FEATURE_XBARB_INPUT40_ID (XBARB_IN_RESERVED40)
3655/* @brief XBARB input 41 ID. */
3656#define FSL_FEATURE_XBARB_INPUT41_ID (XBARB_IN_RESERVED41)
3657/* @brief XBARB input 42 ID. */
3658#define FSL_FEATURE_XBARB_INPUT42_ID (XBARB_IN_RESERVED42)
3659/* @brief XBARB input 43 ID. */
3660#define FSL_FEATURE_XBARB_INPUT43_ID (XBARB_IN_RESERVED43)
3661/* @brief XBARB input 44 ID. */
3662#define FSL_FEATURE_XBARB_INPUT44_ID (XBARB_IN_RESERVED44)
3663/* @brief XBARB input 45 ID. */
3664#define FSL_FEATURE_XBARB_INPUT45_ID (XBARB_IN_RESERVED45)
3665/* @brief XBARB input 46 ID. */
3666#define FSL_FEATURE_XBARB_INPUT46_ID (XBARB_IN_RESERVED46)
3667/* @brief XBARB input 47 ID. */
3668#define FSL_FEATURE_XBARB_INPUT47_ID (XBARB_IN_RESERVED47)
3669/* @brief XBARB input 48 ID. */
3670#define FSL_FEATURE_XBARB_INPUT48_ID (XBARB_IN_RESERVED48)
3671/* @brief XBARB input 49 ID. */
3672#define FSL_FEATURE_XBARB_INPUT49_ID (XBARB_IN_RESERVED49)
3673/* @brief XBARB input 50 ID. */
3674#define FSL_FEATURE_XBARB_INPUT50_ID (XBARB_IN_RESERVED50)
3675/* @brief XBARB input 51 ID. */
3676#define FSL_FEATURE_XBARB_INPUT51_ID (XBARB_IN_RESERVED51)
3677/* @brief XBARB input 52 ID. */
3678#define FSL_FEATURE_XBARB_INPUT52_ID (XBARB_IN_RESERVED52)
3679/* @brief XBARB input 53 ID. */
3680#define FSL_FEATURE_XBARB_INPUT53_ID (XBARB_IN_RESERVED53)
3681/* @brief XBARB input 54 ID. */
3682#define FSL_FEATURE_XBARB_INPUT54_ID (XBARB_IN_RESERVED54)
3683/* @brief XBARB input 55 ID. */
3684#define FSL_FEATURE_XBARB_INPUT55_ID (XBARB_IN_RESERVED55)
3685/* @brief XBARB input 56 ID. */
3686#define FSL_FEATURE_XBARB_INPUT56_ID (XBARB_IN_RESERVED56)
3687/* @brief XBARB input 57 ID. */
3688#define FSL_FEATURE_XBARB_INPUT57_ID (XBARB_IN_RESERVED57)
3689/* @brief XBARB input 58 ID. */
3690#define FSL_FEATURE_XBARB_INPUT58_ID (XBARB_IN_RESERVED58)
3691/* @brief XBARB input 59 ID. */
3692#define FSL_FEATURE_XBARB_INPUT59_ID (XBARB_IN_RESERVED59)
3693/* @brief XBARB input 60 ID. */
3694#define FSL_FEATURE_XBARB_INPUT60_ID (XBARB_IN_RESERVED60)
3695/* @brief XBARB input 61 ID. */
3696#define FSL_FEATURE_XBARB_INPUT61_ID (XBARB_IN_RESERVED61)
3697/* @brief XBARB input 62 ID. */
3698#define FSL_FEATURE_XBARB_INPUT62_ID (XBARB_IN_RESERVED62)
3699/* @brief XBARB input 63 ID. */
3700#define FSL_FEATURE_XBARB_INPUT63_ID (XBARB_IN_RESERVED63)
3701/* @brief XBARB input 64 ID. */
3702#define FSL_FEATURE_XBARB_INPUT64_ID (XBARB_IN_RESERVED64)
3703/* @brief XBARB input 65 ID. */
3704#define FSL_FEATURE_XBARB_INPUT65_ID (XBARB_IN_RESERVED65)
3705/* @brief XBARB input 66 ID. */
3706#define FSL_FEATURE_XBARB_INPUT66_ID (XBARB_IN_RESERVED66)
3707/* @brief XBARB input 67 ID. */
3708#define FSL_FEATURE_XBARB_INPUT67_ID (XBARB_IN_RESERVED67)
3709/* @brief XBARB input 68 ID. */
3710#define FSL_FEATURE_XBARB_INPUT68_ID (XBARB_IN_RESERVED68)
3711/* @brief XBARB input 69 ID. */
3712#define FSL_FEATURE_XBARB_INPUT69_ID (XBARB_IN_RESERVED69)
3713/* @brief XBARB input 70 ID. */
3714#define FSL_FEATURE_XBARB_INPUT70_ID (XBARB_IN_RESERVED70)
3715/* @brief XBARB input 71 ID. */
3716#define FSL_FEATURE_XBARB_INPUT71_ID (XBARB_IN_RESERVED71)
3717/* @brief XBARB input 72 ID. */
3718#define FSL_FEATURE_XBARB_INPUT72_ID (XBARB_IN_RESERVED72)
3719/* @brief XBARB input 73 ID. */
3720#define FSL_FEATURE_XBARB_INPUT73_ID (XBARB_IN_RESERVED73)
3721/* @brief XBARB input 74 ID. */
3722#define FSL_FEATURE_XBARB_INPUT74_ID (XBARB_IN_RESERVED74)
3723/* @brief XBARB input 75 ID. */
3724#define FSL_FEATURE_XBARB_INPUT75_ID (XBARB_IN_RESERVED75)
3725/* @brief XBARB input 76 ID. */
3726#define FSL_FEATURE_XBARB_INPUT76_ID (XBARB_IN_RESERVED76)
3727/* @brief XBARB input 77 ID. */
3728#define FSL_FEATURE_XBARB_INPUT77_ID (XBARB_IN_RESERVED77)
3729/* @brief XBARB input 78 ID. */
3730#define FSL_FEATURE_XBARB_INPUT78_ID (XBARB_IN_RESERVED78)
3731/* @brief XBARB input 79 ID. */
3732#define FSL_FEATURE_XBARB_INPUT79_ID (XBARB_IN_RESERVED79)
3733/* @brief XBARB input 80 ID. */
3734#define FSL_FEATURE_XBARB_INPUT80_ID (XBARB_IN_RESERVED80)
3735/* @brief XBARB input 81 ID. */
3736#define FSL_FEATURE_XBARB_INPUT81_ID (XBARB_IN_RESERVED81)
3737/* @brief XBARB input 82 ID. */
3738#define FSL_FEATURE_XBARB_INPUT82_ID (XBARB_IN_RESERVED82)
3739/* @brief XBARB input 83 ID. */
3740#define FSL_FEATURE_XBARB_INPUT83_ID (XBARB_IN_RESERVED83)
3741/* @brief XBARB input 84 ID. */
3742#define FSL_FEATURE_XBARB_INPUT84_ID (XBARB_IN_RESERVED84)
3743/* @brief XBARB input 85 ID. */
3744#define FSL_FEATURE_XBARB_INPUT85_ID (XBARB_IN_RESERVED85)
3745/* @brief XBARB input 86 ID. */
3746#define FSL_FEATURE_XBARB_INPUT86_ID (XBARB_IN_RESERVED86)
3747/* @brief XBARB input 87 ID. */
3748#define FSL_FEATURE_XBARB_INPUT87_ID (XBARB_IN_RESERVED87)
3749/* @brief XBARB input 88 ID. */
3750#define FSL_FEATURE_XBARB_INPUT88_ID (XBARB_IN_RESERVED88)
3751/* @brief XBARB input 89 ID. */
3752#define FSL_FEATURE_XBARB_INPUT89_ID (XBARB_IN_RESERVED89)
3753/* @brief XBARB input 90 ID. */
3754#define FSL_FEATURE_XBARB_INPUT90_ID (XBARB_IN_RESERVED90)
3755/* @brief XBARB input 91 ID. */
3756#define FSL_FEATURE_XBARB_INPUT91_ID (XBARB_IN_RESERVED91)
3757/* @brief XBARB input 92 ID. */
3758#define FSL_FEATURE_XBARB_INPUT92_ID (XBARB_IN_RESERVED92)
3759/* @brief XBARB input 93 ID. */
3760#define FSL_FEATURE_XBARB_INPUT93_ID (XBARB_IN_RESERVED93)
3761/* @brief XBARB input 94 ID. */
3762#define FSL_FEATURE_XBARB_INPUT94_ID (XBARB_IN_RESERVED94)
3763/* @brief XBARB input 95 ID. */
3764#define FSL_FEATURE_XBARB_INPUT95_ID (XBARB_IN_RESERVED95)
3765/* @brief XBARB input 96 ID. */
3766#define FSL_FEATURE_XBARB_INPUT96_ID (XBARB_IN_RESERVED96)
3767/* @brief XBARB input 97 ID. */
3768#define FSL_FEATURE_XBARB_INPUT97_ID (XBARB_IN_RESERVED97)
3769/* @brief XBARB input 98 ID. */
3770#define FSL_FEATURE_XBARB_INPUT98_ID (XBARB_IN_RESERVED98)
3771/* @brief XBARB input 99 ID. */
3772#define FSL_FEATURE_XBARB_INPUT99_ID (XBARB_IN_RESERVED99)
3773/* @brief XBARB input 100 ID. */
3774#define FSL_FEATURE_XBARB_INPUT100_ID (XBARB_IN_RESERVED100)
3775/* @brief XBARB input 101 ID. */
3776#define FSL_FEATURE_XBARB_INPUT101_ID (XBARB_IN_RESERVED101)
3777/* @brief XBARB input 102 ID. */
3778#define FSL_FEATURE_XBARB_INPUT102_ID (XBARB_IN_RESERVED102)
3779/* @brief XBARB input 103 ID. */
3780#define FSL_FEATURE_XBARB_INPUT103_ID (XBARB_IN_RESERVED103)
3781/* @brief XBARB input 104 ID. */
3782#define FSL_FEATURE_XBARB_INPUT104_ID (XBARB_IN_RESERVED104)
3783/* @brief XBARB input 105 ID. */
3784#define FSL_FEATURE_XBARB_INPUT105_ID (XBARB_IN_RESERVED105)
3785/* @brief XBARB input 106 ID. */
3786#define FSL_FEATURE_XBARB_INPUT106_ID (XBARB_IN_RESERVED106)
3787/* @brief XBARB input 107 ID. */
3788#define FSL_FEATURE_XBARB_INPUT107_ID (XBARB_IN_RESERVED107)
3789/* @brief XBARB input 108 ID. */
3790#define FSL_FEATURE_XBARB_INPUT108_ID (XBARB_IN_RESERVED108)
3791/* @brief XBARB input 109 ID. */
3792#define FSL_FEATURE_XBARB_INPUT109_ID (XBARB_IN_RESERVED109)
3793/* @brief XBARB input 110 ID. */
3794#define FSL_FEATURE_XBARB_INPUT110_ID (XBARB_IN_RESERVED110)
3795/* @brief XBARB input 111 ID. */
3796#define FSL_FEATURE_XBARB_INPUT111_ID (XBARB_IN_RESERVED111)
3797/* @brief XBARB input 112 ID. */
3798#define FSL_FEATURE_XBARB_INPUT112_ID (XBARB_IN_RESERVED112)
3799/* @brief XBARB input 113 ID. */
3800#define FSL_FEATURE_XBARB_INPUT113_ID (XBARB_IN_RESERVED113)
3801/* @brief XBARB input 114 ID. */
3802#define FSL_FEATURE_XBARB_INPUT114_ID (XBARB_IN_RESERVED114)
3803/* @brief XBARB input 115 ID. */
3804#define FSL_FEATURE_XBARB_INPUT115_ID (XBARB_IN_RESERVED115)
3805/* @brief XBARB input 116 ID. */
3806#define FSL_FEATURE_XBARB_INPUT116_ID (XBARB_IN_RESERVED116)
3807/* @brief XBARB input 117 ID. */
3808#define FSL_FEATURE_XBARB_INPUT117_ID (XBARB_IN_RESERVED117)
3809/* @brief XBARB input 118 ID. */
3810#define FSL_FEATURE_XBARB_INPUT118_ID (XBARB_IN_RESERVED118)
3811/* @brief XBARB input 119 ID. */
3812#define FSL_FEATURE_XBARB_INPUT119_ID (XBARB_IN_RESERVED119)
3813/* @brief XBARB input 120 ID. */
3814#define FSL_FEATURE_XBARB_INPUT120_ID (XBARB_IN_RESERVED120)
3815/* @brief XBARB input 121 ID. */
3816#define FSL_FEATURE_XBARB_INPUT121_ID (XBARB_IN_RESERVED121)
3817/* @brief XBARB input 122 ID. */
3818#define FSL_FEATURE_XBARB_INPUT122_ID (XBARB_IN_RESERVED122)
3819/* @brief XBARB input 123 ID. */
3820#define FSL_FEATURE_XBARB_INPUT123_ID (XBARB_IN_RESERVED123)
3821/* @brief XBARB input 124 ID. */
3822#define FSL_FEATURE_XBARB_INPUT124_ID (XBARB_IN_RESERVED124)
3823/* @brief XBARB input 125 ID. */
3824#define FSL_FEATURE_XBARB_INPUT125_ID (XBARB_IN_RESERVED125)
3825/* @brief XBARB input 126 ID. */
3826#define FSL_FEATURE_XBARB_INPUT126_ID (XBARB_IN_RESERVED126)
3827/* @brief XBARB input 127 ID. */
3828#define FSL_FEATURE_XBARB_INPUT127_ID (XBARB_IN_RESERVED127)
3829/* @brief XBARB output 0 ID. */
3830#define FSL_FEATURE_XBARB_OUTPUT0_ID (AoiIn0)
3831/* @brief XBARB output 1 ID. */
3832#define FSL_FEATURE_XBARB_OUTPUT1_ID (AoiIn1)
3833/* @brief XBARB output 2 ID. */
3834#define FSL_FEATURE_XBARB_OUTPUT2_ID (AoiIn2)
3835/* @brief XBARB output 3 ID. */
3836#define FSL_FEATURE_XBARB_OUTPUT3_ID (AoiIn3)
3837/* @brief XBARB output 4 ID. */
3838#define FSL_FEATURE_XBARB_OUTPUT4_ID (AoiIn4)
3839/* @brief XBARB output 5 ID. */
3840#define FSL_FEATURE_XBARB_OUTPUT5_ID (AoiIn5)
3841/* @brief XBARB output 6 ID. */
3842#define FSL_FEATURE_XBARB_OUTPUT6_ID (AoiIn6)
3843/* @brief XBARB output 7 ID. */
3844#define FSL_FEATURE_XBARB_OUTPUT7_ID (AoiIn7)
3845/* @brief XBARB output 8 ID. */
3846#define FSL_FEATURE_XBARB_OUTPUT8_ID (AoiIn8)
3847/* @brief XBARB output 9 ID. */
3848#define FSL_FEATURE_XBARB_OUTPUT9_ID (AoiIn9)
3849/* @brief XBARB output 10 ID. */
3850#define FSL_FEATURE_XBARB_OUTPUT10_ID (AoiIn10)
3851/* @brief XBARB output 11 ID. */
3852#define FSL_FEATURE_XBARB_OUTPUT11_ID (AoiIn11)
3853/* @brief XBARB output 12 ID. */
3854#define FSL_FEATURE_XBARB_OUTPUT12_ID (AoiIn12)
3855/* @brief XBARB output 13 ID. */
3856#define FSL_FEATURE_XBARB_OUTPUT13_ID (AoiIn13)
3857/* @brief XBARB output 14 ID. */
3858#define FSL_FEATURE_XBARB_OUTPUT14_ID (AoiIn14)
3859/* @brief XBARB output 15 ID. */
3860#define FSL_FEATURE_XBARB_OUTPUT15_ID (AoiIn15)
3861/* @brief XBARB output 16 ID. */
3862#define FSL_FEATURE_XBARB_OUTPUT16_ID (XBARB_OUT_RESERVED16)
3863/* @brief XBARB output 17 ID. */
3864#define FSL_FEATURE_XBARB_OUTPUT17_ID (XBARB_OUT_RESERVED17)
3865/* @brief XBARB output 18 ID. */
3866#define FSL_FEATURE_XBARB_OUTPUT18_ID (XBARB_OUT_RESERVED18)
3867/* @brief XBARB output 19 ID. */
3868#define FSL_FEATURE_XBARB_OUTPUT19_ID (XBARB_OUT_RESERVED19)
3869/* @brief XBARB output 20 ID. */
3870#define FSL_FEATURE_XBARB_OUTPUT20_ID (XBARB_OUT_RESERVED20)
3871/* @brief XBARB output 21 ID. */
3872#define FSL_FEATURE_XBARB_OUTPUT21_ID (XBARB_OUT_RESERVED21)
3873/* @brief XBARB output 22 ID. */
3874#define FSL_FEATURE_XBARB_OUTPUT22_ID (XBARB_OUT_RESERVED22)
3875/* @brief XBARB output 23 ID. */
3876#define FSL_FEATURE_XBARB_OUTPUT23_ID (XBARB_OUT_RESERVED23)
3877/* @brief XBARB output 24 ID. */
3878#define FSL_FEATURE_XBARB_OUTPUT24_ID (XBARB_OUT_RESERVED24)
3879/* @brief XBARB output 25 ID. */
3880#define FSL_FEATURE_XBARB_OUTPUT25_ID (XBARB_OUT_RESERVED25)
3881/* @brief XBARB output 26 ID. */
3882#define FSL_FEATURE_XBARB_OUTPUT26_ID (XBARB_OUT_RESERVED26)
3883/* @brief XBARB output 27 ID. */
3884#define FSL_FEATURE_XBARB_OUTPUT27_ID (XBARB_OUT_RESERVED27)
3885/* @brief XBARB output 28 ID. */
3886#define FSL_FEATURE_XBARB_OUTPUT28_ID (XBARB_OUT_RESERVED28)
3887/* @brief XBARB output 29 ID. */
3888#define FSL_FEATURE_XBARB_OUTPUT29_ID (XBARB_OUT_RESERVED29)
3889/* @brief XBARB output 30 ID. */
3890#define FSL_FEATURE_XBARB_OUTPUT30_ID (XBARB_OUT_RESERVED30)
3891/* @brief XBARB output 31 ID. */
3892#define FSL_FEATURE_XBARB_OUTPUT31_ID (XBARB_OUT_RESERVED31)
3893/* @brief XBARB output 32 ID. */
3894#define FSL_FEATURE_XBARB_OUTPUT32_ID (XBARB_OUT_RESERVED32)
3895/* @brief XBARB output 33 ID. */
3896#define FSL_FEATURE_XBARB_OUTPUT33_ID (XBARB_OUT_RESERVED33)
3897/* @brief XBARB output 34 ID. */
3898#define FSL_FEATURE_XBARB_OUTPUT34_ID (XBARB_OUT_RESERVED34)
3899/* @brief XBARB output 35 ID. */
3900#define FSL_FEATURE_XBARB_OUTPUT35_ID (XBARB_OUT_RESERVED35)
3901/* @brief XBARB output 36 ID. */
3902#define FSL_FEATURE_XBARB_OUTPUT36_ID (XBARB_OUT_RESERVED36)
3903/* @brief XBARB output 37 ID. */
3904#define FSL_FEATURE_XBARB_OUTPUT37_ID (XBARB_OUT_RESERVED37)
3905/* @brief XBARB output 38 ID. */
3906#define FSL_FEATURE_XBARB_OUTPUT38_ID (XBARB_OUT_RESERVED38)
3907/* @brief XBARB output 39 ID. */
3908#define FSL_FEATURE_XBARB_OUTPUT39_ID (XBARB_OUT_RESERVED39)
3909/* @brief XBARB output 40 ID. */
3910#define FSL_FEATURE_XBARB_OUTPUT40_ID (XBARB_OUT_RESERVED40)
3911/* @brief XBARB output 41 ID. */
3912#define FSL_FEATURE_XBARB_OUTPUT41_ID (XBARB_OUT_RESERVED41)
3913/* @brief XBARB output 42 ID. */
3914#define FSL_FEATURE_XBARB_OUTPUT42_ID (XBARB_OUT_RESERVED42)
3915/* @brief XBARB output 43 ID. */
3916#define FSL_FEATURE_XBARB_OUTPUT43_ID (XBARB_OUT_RESERVED43)
3917/* @brief XBARB output 44 ID. */
3918#define FSL_FEATURE_XBARB_OUTPUT44_ID (XBARB_OUT_RESERVED44)
3919/* @brief XBARB output 45 ID. */
3920#define FSL_FEATURE_XBARB_OUTPUT45_ID (XBARB_OUT_RESERVED45)
3921/* @brief XBARB output 46 ID. */
3922#define FSL_FEATURE_XBARB_OUTPUT46_ID (XBARB_OUT_RESERVED46)
3923/* @brief XBARB output 47 ID. */
3924#define FSL_FEATURE_XBARB_OUTPUT47_ID (XBARB_OUT_RESERVED47)
3925/* @brief XBARB output 48 ID. */
3926#define FSL_FEATURE_XBARB_OUTPUT48_ID (XBARB_OUT_RESERVED48)
3927/* @brief XBARB output 49 ID. */
3928#define FSL_FEATURE_XBARB_OUTPUT49_ID (XBARB_OUT_RESERVED49)
3929/* @brief XBARB output 50 ID. */
3930#define FSL_FEATURE_XBARB_OUTPUT50_ID (XBARB_OUT_RESERVED50)
3931/* @brief XBARB output 51 ID. */
3932#define FSL_FEATURE_XBARB_OUTPUT51_ID (XBARB_OUT_RESERVED51)
3933/* @brief XBARB output 52 ID. */
3934#define FSL_FEATURE_XBARB_OUTPUT52_ID (XBARB_OUT_RESERVED52)
3935/* @brief XBARB output 53 ID. */
3936#define FSL_FEATURE_XBARB_OUTPUT53_ID (XBARB_OUT_RESERVED53)
3937/* @brief XBARB output 54 ID. */
3938#define FSL_FEATURE_XBARB_OUTPUT54_ID (XBARB_OUT_RESERVED54)
3939/* @brief XBARB output 55 ID. */
3940#define FSL_FEATURE_XBARB_OUTPUT55_ID (XBARB_OUT_RESERVED55)
3941/* @brief XBARB output 56 ID. */
3942#define FSL_FEATURE_XBARB_OUTPUT56_ID (XBARB_OUT_RESERVED56)
3943/* @brief XBARB output 57 ID. */
3944#define FSL_FEATURE_XBARB_OUTPUT57_ID (XBARB_OUT_RESERVED57)
3945/* @brief XBARB output 58 ID. */
3946#define FSL_FEATURE_XBARB_OUTPUT58_ID (XBARB_OUT_RESERVED58)
3947/* @brief XBARB output 59 ID. */
3948#define FSL_FEATURE_XBARB_OUTPUT59_ID (XBARB_OUT_RESERVED59)
3949/* @brief XBARB output 60 ID. */
3950#define FSL_FEATURE_XBARB_OUTPUT60_ID (XBARB_OUT_RESERVED60)
3951/* @brief XBARB output 61 ID. */
3952#define FSL_FEATURE_XBARB_OUTPUT61_ID (XBARB_OUT_RESERVED61)
3953/* @brief XBARB output 62 ID. */
3954#define FSL_FEATURE_XBARB_OUTPUT62_ID (XBARB_OUT_RESERVED62)
3955/* @brief XBARB output 63 ID. */
3956#define FSL_FEATURE_XBARB_OUTPUT63_ID (XBARB_OUT_RESERVED63)
3957/* @brief XBARB output 64 ID. */
3958#define FSL_FEATURE_XBARB_OUTPUT64_ID (XBARB_OUT_RESERVED64)
3959/* @brief XBARB output 65 ID. */
3960#define FSL_FEATURE_XBARB_OUTPUT65_ID (XBARB_OUT_RESERVED65)
3961/* @brief XBARB output 66 ID. */
3962#define FSL_FEATURE_XBARB_OUTPUT66_ID (XBARB_OUT_RESERVED66)
3963/* @brief XBARB output 67 ID. */
3964#define FSL_FEATURE_XBARB_OUTPUT67_ID (XBARB_OUT_RESERVED67)
3965/* @brief XBARB output 68 ID. */
3966#define FSL_FEATURE_XBARB_OUTPUT68_ID (XBARB_OUT_RESERVED68)
3967/* @brief XBARB output 69 ID. */
3968#define FSL_FEATURE_XBARB_OUTPUT69_ID (XBARB_OUT_RESERVED69)
3969/* @brief XBARB output 70 ID. */
3970#define FSL_FEATURE_XBARB_OUTPUT70_ID (XBARB_OUT_RESERVED70)
3971/* @brief XBARB output 71 ID. */
3972#define FSL_FEATURE_XBARB_OUTPUT71_ID (XBARB_OUT_RESERVED71)
3973/* @brief XBARB output 72 ID. */
3974#define FSL_FEATURE_XBARB_OUTPUT72_ID (XBARB_OUT_RESERVED72)
3975/* @brief XBARB output 73 ID. */
3976#define FSL_FEATURE_XBARB_OUTPUT73_ID (XBARB_OUT_RESERVED73)
3977/* @brief XBARB output 74 ID. */
3978#define FSL_FEATURE_XBARB_OUTPUT74_ID (XBARB_OUT_RESERVED74)
3979/* @brief XBARB output 75 ID. */
3980#define FSL_FEATURE_XBARB_OUTPUT75_ID (XBARB_OUT_RESERVED75)
3981/* @brief XBARB output 76 ID. */
3982#define FSL_FEATURE_XBARB_OUTPUT76_ID (XBARB_OUT_RESERVED76)
3983/* @brief XBARB output 77 ID. */
3984#define FSL_FEATURE_XBARB_OUTPUT77_ID (XBARB_OUT_RESERVED77)
3985/* @brief XBARB output 78 ID. */
3986#define FSL_FEATURE_XBARB_OUTPUT78_ID (XBARB_OUT_RESERVED78)
3987/* @brief XBARB output 79 ID. */
3988#define FSL_FEATURE_XBARB_OUTPUT79_ID (XBARB_OUT_RESERVED79)
3989/* @brief XBARB output 80 ID. */
3990#define FSL_FEATURE_XBARB_OUTPUT80_ID (XBARB_OUT_RESERVED80)
3991/* @brief XBARB output 81 ID. */
3992#define FSL_FEATURE_XBARB_OUTPUT81_ID (XBARB_OUT_RESERVED81)
3993/* @brief XBARB output 82 ID. */
3994#define FSL_FEATURE_XBARB_OUTPUT82_ID (XBARB_OUT_RESERVED82)
3995/* @brief XBARB output 83 ID. */
3996#define FSL_FEATURE_XBARB_OUTPUT83_ID (XBARB_OUT_RESERVED83)
3997/* @brief XBARB output 84 ID. */
3998#define FSL_FEATURE_XBARB_OUTPUT84_ID (XBARB_OUT_RESERVED84)
3999/* @brief XBARB output 85 ID. */
4000#define FSL_FEATURE_XBARB_OUTPUT85_ID (XBARB_OUT_RESERVED85)
4001/* @brief XBARB output 86 ID. */
4002#define FSL_FEATURE_XBARB_OUTPUT86_ID (XBARB_OUT_RESERVED86)
4003/* @brief XBARB output 87 ID. */
4004#define FSL_FEATURE_XBARB_OUTPUT87_ID (XBARB_OUT_RESERVED87)
4005/* @brief XBARB output 88 ID. */
4006#define FSL_FEATURE_XBARB_OUTPUT88_ID (XBARB_OUT_RESERVED88)
4007/* @brief XBARB output 89 ID. */
4008#define FSL_FEATURE_XBARB_OUTPUT89_ID (XBARB_OUT_RESERVED89)
4009/* @brief XBARB output 90 ID. */
4010#define FSL_FEATURE_XBARB_OUTPUT90_ID (XBARB_OUT_RESERVED90)
4011/* @brief XBARB output 91 ID. */
4012#define FSL_FEATURE_XBARB_OUTPUT91_ID (XBARB_OUT_RESERVED91)
4013/* @brief XBARB output 92 ID. */
4014#define FSL_FEATURE_XBARB_OUTPUT92_ID (XBARB_OUT_RESERVED92)
4015/* @brief XBARB output 93 ID. */
4016#define FSL_FEATURE_XBARB_OUTPUT93_ID (XBARB_OUT_RESERVED93)
4017/* @brief XBARB output 94 ID. */
4018#define FSL_FEATURE_XBARB_OUTPUT94_ID (XBARB_OUT_RESERVED94)
4019/* @brief XBARB output 95 ID. */
4020#define FSL_FEATURE_XBARB_OUTPUT95_ID (XBARB_OUT_RESERVED95)
4021/* @brief XBARB output 96 ID. */
4022#define FSL_FEATURE_XBARB_OUTPUT96_ID (XBARB_OUT_RESERVED96)
4023/* @brief XBARB output 97 ID. */
4024#define FSL_FEATURE_XBARB_OUTPUT97_ID (XBARB_OUT_RESERVED97)
4025/* @brief XBARB output 98 ID. */
4026#define FSL_FEATURE_XBARB_OUTPUT98_ID (XBARB_OUT_RESERVED98)
4027/* @brief XBARB output 99 ID. */
4028#define FSL_FEATURE_XBARB_OUTPUT99_ID (XBARB_OUT_RESERVED99)
4029/* @brief XBARB output 100 ID. */
4030#define FSL_FEATURE_XBARB_OUTPUT100_ID (XBARB_OUT_RESERVED100)
4031/* @brief XBARB output 101 ID. */
4032#define FSL_FEATURE_XBARB_OUTPUT101_ID (XBARB_OUT_RESERVED101)
4033/* @brief XBARB output 102 ID. */
4034#define FSL_FEATURE_XBARB_OUTPUT102_ID (XBARB_OUT_RESERVED102)
4035/* @brief XBARB output 103 ID. */
4036#define FSL_FEATURE_XBARB_OUTPUT103_ID (XBARB_OUT_RESERVED103)
4037/* @brief XBARB output 104 ID. */
4038#define FSL_FEATURE_XBARB_OUTPUT104_ID (XBARB_OUT_RESERVED104)
4039/* @brief XBARB output 105 ID. */
4040#define FSL_FEATURE_XBARB_OUTPUT105_ID (XBARB_OUT_RESERVED105)
4041/* @brief XBARB output 106 ID. */
4042#define FSL_FEATURE_XBARB_OUTPUT106_ID (XBARB_OUT_RESERVED106)
4043/* @brief XBARB output 107 ID. */
4044#define FSL_FEATURE_XBARB_OUTPUT107_ID (XBARB_OUT_RESERVED107)
4045/* @brief XBARB output 108 ID. */
4046#define FSL_FEATURE_XBARB_OUTPUT108_ID (XBARB_OUT_RESERVED108)
4047/* @brief XBARB output 109 ID. */
4048#define FSL_FEATURE_XBARB_OUTPUT109_ID (XBARB_OUT_RESERVED109)
4049/* @brief XBARB output 110 ID. */
4050#define FSL_FEATURE_XBARB_OUTPUT110_ID (XBARB_OUT_RESERVED110)
4051/* @brief XBARB output 111 ID. */
4052#define FSL_FEATURE_XBARB_OUTPUT111_ID (XBARB_OUT_RESERVED111)
4053/* @brief XBARB output 112 ID. */
4054#define FSL_FEATURE_XBARB_OUTPUT112_ID (XBARB_OUT_RESERVED112)
4055/* @brief XBARB output 113 ID. */
4056#define FSL_FEATURE_XBARB_OUTPUT113_ID (XBARB_OUT_RESERVED113)
4057/* @brief XBARB output 114 ID. */
4058#define FSL_FEATURE_XBARB_OUTPUT114_ID (XBARB_OUT_RESERVED114)
4059/* @brief XBARB output 115 ID. */
4060#define FSL_FEATURE_XBARB_OUTPUT115_ID (XBARB_OUT_RESERVED115)
4061/* @brief XBARB output 116 ID. */
4062#define FSL_FEATURE_XBARB_OUTPUT116_ID (XBARB_OUT_RESERVED116)
4063/* @brief XBARB output 117 ID. */
4064#define FSL_FEATURE_XBARB_OUTPUT117_ID (XBARB_OUT_RESERVED117)
4065/* @brief XBARB output 118 ID. */
4066#define FSL_FEATURE_XBARB_OUTPUT118_ID (XBARB_OUT_RESERVED118)
4067/* @brief XBARB output 119 ID. */
4068#define FSL_FEATURE_XBARB_OUTPUT119_ID (XBARB_OUT_RESERVED119)
4069/* @brief XBARB output 120 ID. */
4070#define FSL_FEATURE_XBARB_OUTPUT120_ID (XBARB_OUT_RESERVED120)
4071/* @brief XBARB output 121 ID. */
4072#define FSL_FEATURE_XBARB_OUTPUT121_ID (XBARB_OUT_RESERVED121)
4073/* @brief XBARB output 122 ID. */
4074#define FSL_FEATURE_XBARB_OUTPUT122_ID (XBARB_OUT_RESERVED122)
4075/* @brief XBARB output 123 ID. */
4076#define FSL_FEATURE_XBARB_OUTPUT123_ID (XBARB_OUT_RESERVED123)
4077/* @brief XBARB output 124 ID. */
4078#define FSL_FEATURE_XBARB_OUTPUT124_ID (XBARB_OUT_RESERVED124)
4079/* @brief XBARB output 125 ID. */
4080#define FSL_FEATURE_XBARB_OUTPUT125_ID (XBARB_OUT_RESERVED125)
4081/* @brief XBARB output 126 ID. */
4082#define FSL_FEATURE_XBARB_OUTPUT126_ID (XBARB_OUT_RESERVED126)
4083/* @brief XBARB output 127 ID. */
4084#define FSL_FEATURE_XBARB_OUTPUT127_ID (XBARB_OUT_RESERVED127)
4085
4086#endif /* _MKV58F24_FEATURES_H_ */
4087