usb_hw.h

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/****************************************************************************
**
** Copyright (C) 2024 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
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** This file is part of the mikroSDK package
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** Alternatively, this file may be used for
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** General Public License version 3 as published by the Free Software
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#ifndef _USB_HW_H_
#define _USB_HW_H_
 
#ifdef __cplusplus
extern "C"{
#endif
 
#include "mcu.h"
#include "interrupts.h"
// Note: Added for MikroE implementation.
// MikroE interrupt source uses NVIC -> (IRQx + 16).
#define NVIC_EnableIRQ(_x)  interrupt_enable(_x + 16)
#define NVIC_DisableIRQ(_x) interrupt_disable(_x + 16)
 
// Clock value in Hz provided externally.
extern volatile uint32_t SystemCoreClock;
 
static inline void usb_hw_init(void) {
    // System Clock Configuration Clock enable.
    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
    RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
    // Enable access to the backup domain.
    PWR->CR1 |= PWR_CR1_DBP;
    // Modify LSE drive capability. (lower driving capability)
    RCC->BDCR &= ~RCC_BDCR_LSEDRV_Msk;
    // Enable clock for PORT_A.
    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
    GPIOA->PUPDR = 0x64000000UL;
    GPIOA->OSPEEDR = 0xFC00000UL;
    GPIOA->OTYPER = 0UL;
    GPIOA->AFR[1] = 0xAA000UL;
    GPIOA->MODER = 0xAAB3FFFFUL;
    // Enable VDDUSB.
    if (!(RCC->APB1ENR1 & RCC_APB1ENR1_PWREN)) {
        RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
        PWR->CR2 |= PWR_CR2_USV;
        RCC->APB1ENR1 &= ~RCC_APB1ENR1_PWREN;
    } else {
        PWR->CR2 |= PWR_CR2_USV;
    }
    #ifdef RCC_CRRCR_HSI48ON
    // Turn HSI48 on. Only for  L496/L4A6 devices.
    RCC->CRRCR |= RCC_CRRCR_HSI48ON;
    // Wait for HSI48 to stabilize.
    while(!(RCC->CRRCR & RCC_CRRCR_HSI48RDY));
    // Select HSI48 as USB clock source.
    RCC->CCIPR &= ~RCC_CCIPR_CLK48SEL;
    #endif
    // USB_OTG_FS Clock enable.
    RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
}
 
 // usb
 // middleware
 
#ifdef __cplusplus
}
#endif
 
#endif // _USB_HW_H_
// ------------------------------------------------------------------------- END