mikroSDK Reference Manual
stm32f4xx_hal_cortex.h
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1
18/* Define to prevent recursive inclusion -------------------------------------*/
19#ifndef __STM32F4xx_HAL_CORTEX_H
20#define __STM32F4xx_HAL_CORTEX_H
21
22#ifdef __cplusplus
23 extern "C" {
24#endif
25
26/* Includes ------------------------------------------------------------------*/
27#include "stm32f4xx_hal_def.h"
28
36/* Exported types ------------------------------------------------------------*/
41#if (__MPU_PRESENT == 1U)
46typedef struct
47{
48 uint8_t Enable;
50 uint8_t Number;
52 uint32_t BaseAddress;
53 uint8_t Size;
55 uint8_t SubRegionDisable;
57 uint8_t TypeExtField;
59 uint8_t AccessPermission;
61 uint8_t DisableExec;
63 uint8_t IsShareable;
65 uint8_t IsCacheable;
67 uint8_t IsBufferable;
69}MPU_Region_InitTypeDef;
73#endif /* __MPU_PRESENT */
74
79/* Exported constants --------------------------------------------------------*/
80
88#define NVIC_PRIORITYGROUP_0 0x00000007U
90#define NVIC_PRIORITYGROUP_1 0x00000006U
92#define NVIC_PRIORITYGROUP_2 0x00000005U
94#define NVIC_PRIORITYGROUP_3 0x00000004U
96#define NVIC_PRIORITYGROUP_4 0x00000003U
105#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
106#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
107
112#if (__MPU_PRESENT == 1)
116#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
117#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
118#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
119#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
120
128#define MPU_REGION_ENABLE ((uint8_t)0x01)
129#define MPU_REGION_DISABLE ((uint8_t)0x00)
137#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
138#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
146#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
147#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
155#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
156#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
164#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
165#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
173#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
174#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
175#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
183#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
184#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
185#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
186#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
187#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
188#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
189#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
190#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
191#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
192#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
193#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
194#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
195#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
196#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
197#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
198#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
199#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
200#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
201#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
202#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
203#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
204#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
205#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
206#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
207#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
208#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
209#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
210#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
218#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
219#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
220#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
221#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
222#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
223#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
231#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
232#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
233#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
234#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
235#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
236#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
237#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
238#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
242#endif /* __MPU_PRESENT */
243
249/* Exported Macros -----------------------------------------------------------*/
250
251/* Exported functions --------------------------------------------------------*/
259/* Initialization and de-initialization functions *****************************/
260void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
261void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
262void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
263void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
264void HAL_NVIC_SystemReset(void);
265uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
273/* Peripheral Control functions ***********************************************/
274uint32_t HAL_NVIC_GetPriorityGrouping(void);
275void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
276uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
277void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
278void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
279uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
280void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
281void HAL_SYSTICK_IRQHandler(void);
282void HAL_SYSTICK_Callback(void);
283
284#if (__MPU_PRESENT == 1U)
285void HAL_MPU_Enable(uint32_t MPU_Control);
286void HAL_MPU_Disable(void);
287void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
288#endif /* __MPU_PRESENT */
297/* Private types -------------------------------------------------------------*/
298/* Private variables ---------------------------------------------------------*/
299/* Private constants ---------------------------------------------------------*/
300/* Private macros ------------------------------------------------------------*/
304#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
305 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
306 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
307 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
308 ((GROUP) == NVIC_PRIORITYGROUP_4))
309
310#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
311
312#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
313
314#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
315
316#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
317 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
318
319#if (__MPU_PRESENT == 1U)
320#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
321 ((STATE) == MPU_REGION_DISABLE))
322
323#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
324 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
325
326#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
327 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
328
329#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
330 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
331
332#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
333 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
334
335#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
336 ((TYPE) == MPU_TEX_LEVEL1) || \
337 ((TYPE) == MPU_TEX_LEVEL2))
338
339#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
340 ((TYPE) == MPU_REGION_PRIV_RW) || \
341 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
342 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
343 ((TYPE) == MPU_REGION_PRIV_RO) || \
344 ((TYPE) == MPU_REGION_PRIV_RO_URO))
345
346#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
347 ((NUMBER) == MPU_REGION_NUMBER1) || \
348 ((NUMBER) == MPU_REGION_NUMBER2) || \
349 ((NUMBER) == MPU_REGION_NUMBER3) || \
350 ((NUMBER) == MPU_REGION_NUMBER4) || \
351 ((NUMBER) == MPU_REGION_NUMBER5) || \
352 ((NUMBER) == MPU_REGION_NUMBER6) || \
353 ((NUMBER) == MPU_REGION_NUMBER7))
354
355#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
356 ((SIZE) == MPU_REGION_SIZE_64B) || \
357 ((SIZE) == MPU_REGION_SIZE_128B) || \
358 ((SIZE) == MPU_REGION_SIZE_256B) || \
359 ((SIZE) == MPU_REGION_SIZE_512B) || \
360 ((SIZE) == MPU_REGION_SIZE_1KB) || \
361 ((SIZE) == MPU_REGION_SIZE_2KB) || \
362 ((SIZE) == MPU_REGION_SIZE_4KB) || \
363 ((SIZE) == MPU_REGION_SIZE_8KB) || \
364 ((SIZE) == MPU_REGION_SIZE_16KB) || \
365 ((SIZE) == MPU_REGION_SIZE_32KB) || \
366 ((SIZE) == MPU_REGION_SIZE_64KB) || \
367 ((SIZE) == MPU_REGION_SIZE_128KB) || \
368 ((SIZE) == MPU_REGION_SIZE_256KB) || \
369 ((SIZE) == MPU_REGION_SIZE_512KB) || \
370 ((SIZE) == MPU_REGION_SIZE_1MB) || \
371 ((SIZE) == MPU_REGION_SIZE_2MB) || \
372 ((SIZE) == MPU_REGION_SIZE_4MB) || \
373 ((SIZE) == MPU_REGION_SIZE_8MB) || \
374 ((SIZE) == MPU_REGION_SIZE_16MB) || \
375 ((SIZE) == MPU_REGION_SIZE_32MB) || \
376 ((SIZE) == MPU_REGION_SIZE_64MB) || \
377 ((SIZE) == MPU_REGION_SIZE_128MB) || \
378 ((SIZE) == MPU_REGION_SIZE_256MB) || \
379 ((SIZE) == MPU_REGION_SIZE_512MB) || \
380 ((SIZE) == MPU_REGION_SIZE_1GB) || \
381 ((SIZE) == MPU_REGION_SIZE_2GB) || \
382 ((SIZE) == MPU_REGION_SIZE_4GB))
383
384#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
385#endif /* __MPU_PRESENT */
386
391/* Private functions ---------------------------------------------------------*/
392
401#ifdef __cplusplus
402}
403#endif
404
405#endif /* __STM32F4xx_HAL_CORTEX_H */
406
407
IRQn
IRQn
Definition MK60D10.h:157
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f107xc.h:70
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.