core__cm7_8h_source.html

/**************************************************************************/

/*

 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.

 *

 * SPDX-License-Identifier: Apache-2.0

 *

 * Licensed under the Apache License, Version 2.0 (the License); you may

 * not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 * www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an AS IS BASIS, WITHOUT

 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 */


#if   defined ( __ICCARM__ )

  #pragma system_include         /* treat file as system include file for MISRA check */

#elif defined (__clang__)

  #pragma clang system_header   /* treat file as system include file */

#endif


#ifndef __CORE_CM7_H_GENERIC

#define __CORE_CM7_H_GENERIC


#include <stdint.h>


#ifdef __cplusplus

 extern "C" {

#endif


/*******************************************************************************

 *                 CMSIS definitions

 ******************************************************************************/

#include "cmsis_version.h"


/* CMSIS CM7 definitions */

#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)

#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)


#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \

                                    __CM7_CMSIS_VERSION_SUB           )

#define __CORTEX_M                (7U)

#if defined ( __CC_ARM )

  #if defined __TARGET_FPU_VFP

    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)

      #define __FPU_USED       1U

    #else

      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

      #define __FPU_USED       0U

    #endif

  #else

    #define __FPU_USED         0U

  #endif


#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

  #if defined __ARM_FP

    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)

      #define __FPU_USED       1U

    #else

      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

      #define __FPU_USED       0U

    #endif

  #else

    #define __FPU_USED         0U

  #endif


#elif defined ( __GNUC__ )

  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)

      #define __FPU_USED       1U

    #else

      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

      #define __FPU_USED       0U

    #endif

  #else

    #define __FPU_USED         0U

  #endif


#elif defined ( __ICCARM__ )

  #if defined __ARMVFP__

    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)

      #define __FPU_USED       1U

    #else

      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

      #define __FPU_USED       0U

    #endif

  #else

    #define __FPU_USED         0U

  #endif


#elif defined ( __TI_ARM__ )

  #if defined __TI_VFP_SUPPORT__

    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)

      #define __FPU_USED       1U

    #else

      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

      #define __FPU_USED       0U

    #endif

  #else

    #define __FPU_USED         0U

  #endif


#elif defined ( __TASKING__ )

  #if defined __FPU_VFP__

    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)

      #define __FPU_USED       1U

    #else

      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

      #define __FPU_USED       0U

    #endif

  #else

    #define __FPU_USED         0U

  #endif


#elif defined ( __CSMC__ )

  #if ( __CSMC__ & 0x400U)

    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)

      #define __FPU_USED       1U

    #else

      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

      #define __FPU_USED       0U

    #endif

  #else

    #define __FPU_USED         0U

  #endif


#endif


#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */


#ifdef __cplusplus

}

#endif


#endif /* __CORE_CM7_H_GENERIC */


#ifndef __CMSIS_GENERIC


#ifndef __CORE_CM7_H_DEPENDANT

#define __CORE_CM7_H_DEPENDANT


#ifdef __cplusplus

 extern "C" {

#endif


/* check device defines and use defaults */

#if defined __CHECK_DEVICE_DEFINES

  #ifndef __CM7_REV

    #define __CM7_REV               0x0000U

    #warning "__CM7_REV not defined in device header file; using default!"

  #endif


  #ifndef __FPU_PRESENT

    #define __FPU_PRESENT             0U

    #warning "__FPU_PRESENT not defined in device header file; using default!"

  #endif


  #ifndef __MPU_PRESENT

    #define __MPU_PRESENT             0U

    #warning "__MPU_PRESENT not defined in device header file; using default!"

  #endif


  #ifndef __ICACHE_PRESENT

    #define __ICACHE_PRESENT          0U

    #warning "__ICACHE_PRESENT not defined in device header file; using default!"

  #endif


  #ifndef __DCACHE_PRESENT

    #define __DCACHE_PRESENT          0U

    #warning "__DCACHE_PRESENT not defined in device header file; using default!"

  #endif


  #ifndef __DTCM_PRESENT

    #define __DTCM_PRESENT            0U

    #warning "__DTCM_PRESENT        not defined in device header file; using default!"

  #endif


  #ifndef __NVIC_PRIO_BITS

    #define __NVIC_PRIO_BITS          3U

    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

  #endif


  #ifndef __Vendor_SysTickConfig

    #define __Vendor_SysTickConfig    0U

    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

  #endif

#endif


/* IO definitions (access restrictions to peripheral registers) */

#ifdef __cplusplus

  #define   __I     volatile

#else

  #define   __I     volatile const

#endif

#define     __O     volatile

#define     __IO    volatile

/* following defines should be used for structure members */

#define     __IM     volatile const

#define     __OM     volatile

#define     __IOM    volatile

/*******************************************************************************

 *                 Register Abstraction

  Core Register contain:

  - Core Register

  - Core NVIC Register

  - Core SCB Register

  - Core SysTick Register

  - Core Debug Register

  - Core MPU Register

  - Core FPU Register

 ******************************************************************************/

typedef union

{

  struct

  {

    uint32_t _reserved0:16;

    uint32_t GE:4;

    uint32_t _reserved1:7;

    uint32_t Q:1;

    uint32_t V:1;

    uint32_t C:1;

    uint32_t Z:1;

    uint32_t N:1;

  } b;

  uint32_t w;

} APSR_Type;


/* APSR Register Definitions */

#define APSR_N_Pos                         31U

#define APSR_N_Msk                         (1UL << APSR_N_Pos)

#define APSR_Z_Pos                         30U

#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)

#define APSR_C_Pos                         29U

#define APSR_C_Msk                         (1UL << APSR_C_Pos)

#define APSR_V_Pos                         28U

#define APSR_V_Msk                         (1UL << APSR_V_Pos)

#define APSR_Q_Pos                         27U

#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)

#define APSR_GE_Pos                        16U

#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)

typedef union

{

  struct

  {

    uint32_t ISR:9;

    uint32_t _reserved0:23;

  } b;

  uint32_t w;

} IPSR_Type;


/* IPSR Register Definitions */

#define IPSR_ISR_Pos                        0U

#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)

typedef union

{

  struct

  {

    uint32_t ISR:9;

    uint32_t _reserved0:1;

    uint32_t ICI_IT_1:6;

    uint32_t GE:4;

    uint32_t _reserved1:4;

    uint32_t T:1;

    uint32_t ICI_IT_2:2;

    uint32_t Q:1;

    uint32_t V:1;

    uint32_t C:1;

    uint32_t Z:1;

    uint32_t N:1;

  } b;

  uint32_t w;

} xPSR_Type;


/* xPSR Register Definitions */

#define xPSR_N_Pos                         31U

#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)

#define xPSR_Z_Pos                         30U

#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)

#define xPSR_C_Pos                         29U

#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)

#define xPSR_V_Pos                         28U

#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)

#define xPSR_Q_Pos                         27U

#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)

#define xPSR_ICI_IT_2_Pos                  25U

#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)

#define xPSR_T_Pos                         24U

#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)

#define xPSR_GE_Pos                        16U

#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)

#define xPSR_ICI_IT_1_Pos                  10U

#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)

#define xPSR_ISR_Pos                        0U

#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)

typedef union

{

  struct

  {

    uint32_t nPRIV:1;

    uint32_t SPSEL:1;

    uint32_t FPCA:1;

    uint32_t _reserved0:29;

  } b;

  uint32_t w;

} CONTROL_Type;


/* CONTROL Register Definitions */

#define CONTROL_FPCA_Pos                    2U

#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)

#define CONTROL_SPSEL_Pos                   1U

#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)

#define CONTROL_nPRIV_Pos                   0U

#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)

typedef struct

{

  __IOM uint32_t ISER[8U];

        uint32_t RESERVED0[24U];

  __IOM uint32_t ICER[8U];

        uint32_t RESERVED1[24U];

  __IOM uint32_t ISPR[8U];

        uint32_t RESERVED2[24U];

  __IOM uint32_t ICPR[8U];

        uint32_t RESERVED3[24U];

  __IOM uint32_t IABR[8U];

        uint32_t RESERVED4[56U];

  __IOM uint8_t  IP[240U];

        uint32_t RESERVED5[644U];

  __OM  uint32_t STIR;

}  NVIC_Type;


/* Software Triggered Interrupt Register Definitions */

#define NVIC_STIR_INTID_Pos                 0U

#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

typedef struct

{

  __IM  uint32_t CPUID;

  __IOM uint32_t ICSR;

  __IOM uint32_t VTOR;

  __IOM uint32_t AIRCR;

  __IOM uint32_t SCR;

  __IOM uint32_t CCR;

  __IOM uint8_t  SHPR[12U];

  __IOM uint32_t SHCSR;

  __IOM uint32_t CFSR;

  __IOM uint32_t HFSR;

  __IOM uint32_t DFSR;

  __IOM uint32_t MMFAR;

  __IOM uint32_t BFAR;

  __IOM uint32_t AFSR;

  __IM  uint32_t ID_PFR[2U];

  __IM  uint32_t ID_DFR;

  __IM  uint32_t ID_AFR;

  __IM  uint32_t ID_MFR[4U];

  __IM  uint32_t ID_ISAR[5U];

        uint32_t RESERVED0[1U];

  __IM  uint32_t CLIDR;

  __IM  uint32_t CTR;

  __IM  uint32_t CCSIDR;

  __IOM uint32_t CSSELR;

  __IOM uint32_t CPACR;

        uint32_t RESERVED3[93U];

  __OM  uint32_t STIR;

        uint32_t RESERVED4[15U];

  __IM  uint32_t MVFR0;

  __IM  uint32_t MVFR1;

  __IM  uint32_t MVFR2;

        uint32_t RESERVED5[1U];

  __OM  uint32_t ICIALLU;

        uint32_t RESERVED6[1U];

  __OM  uint32_t ICIMVAU;

  __OM  uint32_t DCIMVAC;

  __OM  uint32_t DCISW;

  __OM  uint32_t DCCMVAU;

  __OM  uint32_t DCCMVAC;

  __OM  uint32_t DCCSW;

  __OM  uint32_t DCCIMVAC;

  __OM  uint32_t DCCISW;

        uint32_t RESERVED7[6U];

  __IOM uint32_t ITCMCR;

  __IOM uint32_t DTCMCR;

  __IOM uint32_t AHBPCR;

  __IOM uint32_t CACR;

  __IOM uint32_t AHBSCR;

        uint32_t RESERVED8[1U];

  __IOM uint32_t ABFSR;

} SCB_Type;


/* SCB CPUID Register Definitions */

#define SCB_CPUID_IMPLEMENTER_Pos          24U

#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define SCB_CPUID_VARIANT_Pos              20U

#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)

#define SCB_CPUID_ARCHITECTURE_Pos         16U

#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define SCB_CPUID_PARTNO_Pos                4U

#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define SCB_CPUID_REVISION_Pos              0U

#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

/* SCB Interrupt Control State Register Definitions */

#define SCB_ICSR_NMIPENDSET_Pos            31U

#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define SCB_ICSR_PENDSVSET_Pos             28U

#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)

#define SCB_ICSR_PENDSVCLR_Pos             27U

#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define SCB_ICSR_PENDSTSET_Pos             26U

#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)

#define SCB_ICSR_PENDSTCLR_Pos             25U

#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define SCB_ICSR_ISRPREEMPT_Pos            23U

#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define SCB_ICSR_ISRPENDING_Pos            22U

#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)

#define SCB_ICSR_VECTPENDING_Pos           12U

#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define SCB_ICSR_RETTOBASE_Pos             11U

#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)

#define SCB_ICSR_VECTACTIVE_Pos             0U

#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

/* SCB Vector Table Offset Register Definitions */

#define SCB_VTOR_TBLOFF_Pos                 7U

#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

/* SCB Application Interrupt and Reset Control Register Definitions */

#define SCB_AIRCR_VECTKEY_Pos              16U

#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define SCB_AIRCR_VECTKEYSTAT_Pos          16U

#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define SCB_AIRCR_ENDIANESS_Pos            15U

#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define SCB_AIRCR_PRIGROUP_Pos              8U

#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define SCB_AIRCR_SYSRESETREQ_Pos           2U

#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U

#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define SCB_AIRCR_VECTRESET_Pos             0U

#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

/* SCB System Control Register Definitions */

#define SCB_SCR_SEVONPEND_Pos               4U

#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)

#define SCB_SCR_SLEEPDEEP_Pos               2U

#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define SCB_SCR_SLEEPONEXIT_Pos             1U

#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)

/* SCB Configuration Control Register Definitions */

#define SCB_CCR_BP_Pos                      18U

#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)

#define SCB_CCR_IC_Pos                      17U

#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)

#define SCB_CCR_DC_Pos                      16U

#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)

#define SCB_CCR_STKALIGN_Pos                9U

#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)

#define SCB_CCR_BFHFNMIGN_Pos               8U

#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define SCB_CCR_DIV_0_TRP_Pos               4U

#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define SCB_CCR_UNALIGN_TRP_Pos             3U

#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define SCB_CCR_USERSETMPEND_Pos            1U

#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)

#define SCB_CCR_NONBASETHRDENA_Pos          0U

#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

/* SCB System Handler Control and State Register Definitions */

#define SCB_SHCSR_USGFAULTENA_Pos          18U

#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define SCB_SHCSR_BUSFAULTENA_Pos          17U

#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define SCB_SHCSR_MEMFAULTENA_Pos          16U

#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define SCB_SHCSR_SVCALLPENDED_Pos         15U

#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U

#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U

#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define SCB_SHCSR_USGFAULTPENDED_Pos       12U

#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define SCB_SHCSR_SYSTICKACT_Pos           11U

#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define SCB_SHCSR_PENDSVACT_Pos            10U

#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define SCB_SHCSR_MONITORACT_Pos            8U

#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)

#define SCB_SHCSR_SVCALLACT_Pos             7U

#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define SCB_SHCSR_USGFAULTACT_Pos           3U

#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define SCB_SHCSR_BUSFAULTACT_Pos           1U

#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define SCB_SHCSR_MEMFAULTACT_Pos           0U

#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

/* SCB Configurable Fault Status Register Definitions */

#define SCB_CFSR_USGFAULTSR_Pos            16U

#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define SCB_CFSR_BUSFAULTSR_Pos             8U

#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define SCB_CFSR_MEMFAULTSR_Pos             0U

#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */

#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)

#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)

#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)

#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)

#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

/* BusFault Status Register (part of SCB Configurable Fault Status Register) */

#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)

#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)

#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)

#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)

#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)

#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)

/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */

#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)

#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)

#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)

#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)

#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)

/* SCB Hard Fault Status Register Definitions */

#define SCB_HFSR_DEBUGEVT_Pos              31U

#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define SCB_HFSR_FORCED_Pos                30U

#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)

#define SCB_HFSR_VECTTBL_Pos                1U

#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)

/* SCB Debug Fault Status Register Definitions */

#define SCB_DFSR_EXTERNAL_Pos               4U

#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)

#define SCB_DFSR_VCATCH_Pos                 3U

#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)

#define SCB_DFSR_DWTTRAP_Pos                2U

#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)

#define SCB_DFSR_BKPT_Pos                   1U

#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)

#define SCB_DFSR_HALTED_Pos                 0U

#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)

/* SCB Cache Level ID Register Definitions */

#define SCB_CLIDR_LOUU_Pos                 27U

#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)

#define SCB_CLIDR_LOC_Pos                  24U

#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)

/* SCB Cache Type Register Definitions */

#define SCB_CTR_FORMAT_Pos                 29U

#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)

#define SCB_CTR_CWG_Pos                    24U

#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)

#define SCB_CTR_ERG_Pos                    20U

#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)

#define SCB_CTR_DMINLINE_Pos               16U

#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)

#define SCB_CTR_IMINLINE_Pos                0U

#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

/* SCB Cache Size ID Register Definitions */

#define SCB_CCSIDR_WT_Pos                  31U

#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)

#define SCB_CCSIDR_WB_Pos                  30U

#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)

#define SCB_CCSIDR_RA_Pos                  29U

#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)

#define SCB_CCSIDR_WA_Pos                  28U

#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)

#define SCB_CCSIDR_NUMSETS_Pos             13U

#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U

#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define SCB_CCSIDR_LINESIZE_Pos             0U

#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

/* SCB Cache Size Selection Register Definitions */

#define SCB_CSSELR_LEVEL_Pos                1U

#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)

#define SCB_CSSELR_IND_Pos                  0U

#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)

/* SCB Software Triggered Interrupt Register Definitions */

#define SCB_STIR_INTID_Pos                  0U

#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

/* SCB D-Cache Invalidate by Set-way Register Definitions */

#define SCB_DCISW_WAY_Pos                  30U

#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)

#define SCB_DCISW_SET_Pos                   5U

#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)

/* SCB D-Cache Clean by Set-way Register Definitions */

#define SCB_DCCSW_WAY_Pos                  30U

#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)

#define SCB_DCCSW_SET_Pos                   5U

#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)

/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */

#define SCB_DCCISW_WAY_Pos                 30U

#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)

#define SCB_DCCISW_SET_Pos                  5U

#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)

/* Instruction Tightly-Coupled Memory Control Register Definitions */

#define SCB_ITCMCR_SZ_Pos                   3U

#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)

#define SCB_ITCMCR_RETEN_Pos                2U

#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)

#define SCB_ITCMCR_RMW_Pos                  1U

#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)

#define SCB_ITCMCR_EN_Pos                   0U

#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)

/* Data Tightly-Coupled Memory Control Register Definitions */

#define SCB_DTCMCR_SZ_Pos                   3U

#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)

#define SCB_DTCMCR_RETEN_Pos                2U

#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)

#define SCB_DTCMCR_RMW_Pos                  1U

#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)

#define SCB_DTCMCR_EN_Pos                   0U

#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)

/* AHBP Control Register Definitions */

#define SCB_AHBPCR_SZ_Pos                   1U

#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)

#define SCB_AHBPCR_EN_Pos                   0U

#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)

/* L1 Cache Control Register Definitions */

#define SCB_CACR_FORCEWT_Pos                2U

#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)

#define SCB_CACR_ECCEN_Pos                  1U

#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)

#define SCB_CACR_SIWT_Pos                   0U

#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)

/* AHBS Control Register Definitions */

#define SCB_AHBSCR_INITCOUNT_Pos           11U

#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

#define SCB_AHBSCR_TPRI_Pos                 2U

#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

#define SCB_AHBSCR_CTL_Pos                  0U

#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

/* Auxiliary Bus Fault Status Register Definitions */

#define SCB_ABFSR_AXIMTYPE_Pos              8U

#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)

#define SCB_ABFSR_EPPB_Pos                  4U

#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)

#define SCB_ABFSR_AXIM_Pos                  3U

#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)

#define SCB_ABFSR_AHBP_Pos                  2U

#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)

#define SCB_ABFSR_DTCM_Pos                  1U

#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)

#define SCB_ABFSR_ITCM_Pos                  0U

#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

typedef struct

{

        uint32_t RESERVED0[1U];

  __IM  uint32_t ICTR;

  __IOM uint32_t ACTLR;

} SCnSCB_Type;


/* Interrupt Controller Type Register Definitions */

#define SCnSCB_ICTR_INTLINESNUM_Pos         0U

#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

/* Auxiliary Control Register Definitions */

#define SCnSCB_ACTLR_DISDYNADD_Pos         26U

#define SCnSCB_ACTLR_DISDYNADD_Msk         (1UL << SCnSCB_ACTLR_DISDYNADD_Pos)

#define SCnSCB_ACTLR_DISISSCH1_Pos         21U

#define SCnSCB_ACTLR_DISISSCH1_Msk         (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos)

#define SCnSCB_ACTLR_DISDI_Pos             16U

#define SCnSCB_ACTLR_DISDI_Msk             (0x1FUL << SCnSCB_ACTLR_DISDI_Pos)

#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos     15U

#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk     (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos)

#define SCnSCB_ACTLR_DISBTACALLOC_Pos      14U

#define SCnSCB_ACTLR_DISBTACALLOC_Msk      (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos)

#define SCnSCB_ACTLR_DISBTACREAD_Pos       13U

#define SCnSCB_ACTLR_DISBTACREAD_Msk       (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos)

#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U

#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)

#define SCnSCB_ACTLR_DISRAMODE_Pos         11U

#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)

#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U

#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)

#define SCnSCB_ACTLR_DISFOLD_Pos            2U

#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U

#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)

typedef struct

{

  __IOM uint32_t CTRL;

  __IOM uint32_t LOAD;

  __IOM uint32_t VAL;

  __IM  uint32_t CALIB;

} SysTick_Type;


/* SysTick Control / Status Register Definitions */

#define SysTick_CTRL_COUNTFLAG_Pos         16U

#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define SysTick_CTRL_CLKSOURCE_Pos          2U

#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define SysTick_CTRL_TICKINT_Pos            1U

#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)

#define SysTick_CTRL_ENABLE_Pos             0U

#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)

/* SysTick Reload Register Definitions */

#define SysTick_LOAD_RELOAD_Pos             0U

#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)

/* SysTick Current Register Definitions */

#define SysTick_VAL_CURRENT_Pos             0U

#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)

/* SysTick Calibration Register Definitions */

#define SysTick_CALIB_NOREF_Pos            31U

#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)

#define SysTick_CALIB_SKEW_Pos             30U

#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)

#define SysTick_CALIB_TENMS_Pos             0U

#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

typedef struct

{

  __OM  union

  {

    __OM  uint8_t    u8;

    __OM  uint16_t   u16;

    __OM  uint32_t   u32;

  }  PORT [32U];

        uint32_t RESERVED0[864U];

  __IOM uint32_t TER;

        uint32_t RESERVED1[15U];

  __IOM uint32_t TPR;

        uint32_t RESERVED2[15U];

  __IOM uint32_t TCR;

        uint32_t RESERVED3[32U];

        uint32_t RESERVED4[43U];

  __OM  uint32_t LAR;

  __IM  uint32_t LSR;

        uint32_t RESERVED5[6U];

  __IM  uint32_t PID4;

  __IM  uint32_t PID5;

  __IM  uint32_t PID6;

  __IM  uint32_t PID7;

  __IM  uint32_t PID0;

  __IM  uint32_t PID1;

  __IM  uint32_t PID2;

  __IM  uint32_t PID3;

  __IM  uint32_t CID0;

  __IM  uint32_t CID1;

  __IM  uint32_t CID2;

  __IM  uint32_t CID3;

} ITM_Type;


/* ITM Trace Privilege Register Definitions */

#define ITM_TPR_PRIVMASK_Pos                0U

#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

/* ITM Trace Control Register Definitions */

#define ITM_TCR_BUSY_Pos                   23U

#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)

#define ITM_TCR_TraceBusID_Pos             16U

#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define ITM_TCR_GTSFREQ_Pos                10U

#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)

#define ITM_TCR_TSPrescale_Pos              8U

#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)

#define ITM_TCR_SWOENA_Pos                  4U

#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)

#define ITM_TCR_DWTENA_Pos                  3U

#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)

#define ITM_TCR_SYNCENA_Pos                 2U

#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)

#define ITM_TCR_TSENA_Pos                   1U

#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)

#define ITM_TCR_ITMENA_Pos                  0U

#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)

/* ITM Lock Status Register Definitions */

#define ITM_LSR_ByteAcc_Pos                 2U

#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)

#define ITM_LSR_Access_Pos                  1U

#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)

#define ITM_LSR_Present_Pos                 0U

#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)                /* end of group CMSIS_ITM */


typedef struct

{

  __IOM uint32_t CTRL;

  __IOM uint32_t CYCCNT;

  __IOM uint32_t CPICNT;

  __IOM uint32_t EXCCNT;

  __IOM uint32_t SLEEPCNT;

  __IOM uint32_t LSUCNT;

  __IOM uint32_t FOLDCNT;

  __IM  uint32_t PCSR;

  __IOM uint32_t COMP0;

  __IOM uint32_t MASK0;

  __IOM uint32_t FUNCTION0;

        uint32_t RESERVED0[1U];

  __IOM uint32_t COMP1;

  __IOM uint32_t MASK1;

  __IOM uint32_t FUNCTION1;

        uint32_t RESERVED1[1U];

  __IOM uint32_t COMP2;

  __IOM uint32_t MASK2;

  __IOM uint32_t FUNCTION2;

        uint32_t RESERVED2[1U];

  __IOM uint32_t COMP3;

  __IOM uint32_t MASK3;

  __IOM uint32_t FUNCTION3;

        uint32_t RESERVED3[981U];

  __OM  uint32_t LAR;

  __IM  uint32_t LSR;

} DWT_Type;


/* DWT Control Register Definitions */

#define DWT_CTRL_NUMCOMP_Pos               28U

#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define DWT_CTRL_NOTRCPKT_Pos              27U

#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define DWT_CTRL_NOEXTTRIG_Pos             26U

#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define DWT_CTRL_NOCYCCNT_Pos              25U

#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define DWT_CTRL_NOPRFCNT_Pos              24U

#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define DWT_CTRL_CYCEVTENA_Pos             22U

#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

#define DWT_CTRL_FOLDEVTENA_Pos            21U

#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

#define DWT_CTRL_LSUEVTENA_Pos             20U

#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

#define DWT_CTRL_SLEEPEVTENA_Pos           19U

#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

#define DWT_CTRL_EXCEVTENA_Pos             18U

#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

#define DWT_CTRL_CPIEVTENA_Pos             17U

#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

#define DWT_CTRL_EXCTRCENA_Pos             16U

#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

#define DWT_CTRL_PCSAMPLENA_Pos            12U

#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

#define DWT_CTRL_SYNCTAP_Pos               10U

#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)

#define DWT_CTRL_CYCTAP_Pos                 9U

#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)

#define DWT_CTRL_POSTINIT_Pos               5U

#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)

#define DWT_CTRL_POSTPRESET_Pos             1U

#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)

#define DWT_CTRL_CYCCNTENA_Pos              0U

#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

/* DWT CPI Count Register Definitions */

#define DWT_CPICNT_CPICNT_Pos               0U

#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

/* DWT Exception Overhead Count Register Definitions */

#define DWT_EXCCNT_EXCCNT_Pos               0U

#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

/* DWT Sleep Count Register Definitions */

#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U

#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

/* DWT LSU Count Register Definitions */

#define DWT_LSUCNT_LSUCNT_Pos               0U

#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

/* DWT Folded-instruction Count Register Definitions */

#define DWT_FOLDCNT_FOLDCNT_Pos             0U

#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

/* DWT Comparator Mask Register Definitions */

#define DWT_MASK_MASK_Pos                   0U

#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)

/* DWT Comparator Function Register Definitions */

#define DWT_FUNCTION_MATCHED_Pos           24U

#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define DWT_FUNCTION_DATAVADDR1_Pos        16U

#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

#define DWT_FUNCTION_DATAVADDR0_Pos        12U

#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

#define DWT_FUNCTION_DATAVSIZE_Pos         10U

#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define DWT_FUNCTION_LNK1ENA_Pos            9U

#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

#define DWT_FUNCTION_DATAVMATCH_Pos         8U

#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

#define DWT_FUNCTION_CYCMATCH_Pos           7U

#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

#define DWT_FUNCTION_EMITRANGE_Pos          5U

#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

#define DWT_FUNCTION_FUNCTION_Pos           0U

#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)     /* end of group CMSIS_DWT */


typedef struct

{

  __IM  uint32_t SSPSR;

  __IOM uint32_t CSPSR;

        uint32_t RESERVED0[2U];

  __IOM uint32_t ACPR;

        uint32_t RESERVED1[55U];

  __IOM uint32_t SPPR;

        uint32_t RESERVED2[131U];

  __IM  uint32_t FFSR;

  __IOM uint32_t FFCR;

  __IM  uint32_t FSCR;

        uint32_t RESERVED3[759U];

  __IM  uint32_t TRIGGER;

  __IM  uint32_t FIFO0;

  __IM  uint32_t ITATBCTR2;

        uint32_t RESERVED4[1U];

  __IM  uint32_t ITATBCTR0;

  __IM  uint32_t FIFO1;

  __IOM uint32_t ITCTRL;

        uint32_t RESERVED5[39U];

  __IOM uint32_t CLAIMSET;

  __IOM uint32_t CLAIMCLR;

        uint32_t RESERVED7[8U];

  __IM  uint32_t DEVID;

  __IM  uint32_t DEVTYPE;

} TPI_Type;


/* TPI Asynchronous Clock Prescaler Register Definitions */

#define TPI_ACPR_PRESCALER_Pos              0U

#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

/* TPI Selected Pin Protocol Register Definitions */

#define TPI_SPPR_TXMODE_Pos                 0U

#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

/* TPI Formatter and Flush Status Register Definitions */

#define TPI_FFSR_FtNonStop_Pos              3U

#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define TPI_FFSR_TCPresent_Pos              2U

#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)

#define TPI_FFSR_FtStopped_Pos              1U

#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)

#define TPI_FFSR_FlInProg_Pos               0U

#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

/* TPI Formatter and Flush Control Register Definitions */

#define TPI_FFCR_TrigIn_Pos                 8U

#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)

#define TPI_FFCR_EnFCont_Pos                1U

#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)

/* TPI TRIGGER Register Definitions */

#define TPI_TRIGGER_TRIGGER_Pos             0U

#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

/* TPI Integration ETM Data Register Definitions (FIFO0) */

#define TPI_FIFO0_ITM_ATVALID_Pos          29U

#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define TPI_FIFO0_ITM_bytecount_Pos        27U

#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define TPI_FIFO0_ETM_ATVALID_Pos          26U

#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define TPI_FIFO0_ETM_bytecount_Pos        24U

#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define TPI_FIFO0_ETM2_Pos                 16U

#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define TPI_FIFO0_ETM1_Pos                  8U

#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define TPI_FIFO0_ETM0_Pos                  0U

#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)

/* TPI ITATBCTR2 Register Definitions */

#define TPI_ITATBCTR2_ATREADY2_Pos          0U

#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)

#define TPI_ITATBCTR2_ATREADY1_Pos          0U

#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)

/* TPI Integration ITM Data Register Definitions (FIFO1) */

#define TPI_FIFO1_ITM_ATVALID_Pos          29U

#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define TPI_FIFO1_ITM_bytecount_Pos        27U

#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define TPI_FIFO1_ETM_ATVALID_Pos          26U

#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define TPI_FIFO1_ETM_bytecount_Pos        24U

#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define TPI_FIFO1_ITM2_Pos                 16U

#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define TPI_FIFO1_ITM1_Pos                  8U

#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define TPI_FIFO1_ITM0_Pos                  0U

#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)

/* TPI ITATBCTR0 Register Definitions */

#define TPI_ITATBCTR0_ATREADY2_Pos          0U

#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)

#define TPI_ITATBCTR0_ATREADY1_Pos          0U

#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)

/* TPI Integration Mode Control Register Definitions */

#define TPI_ITCTRL_Mode_Pos                 0U

#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

/* TPI DEVID Register Definitions */

#define TPI_DEVID_NRZVALID_Pos             11U

#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define TPI_DEVID_MANCVALID_Pos            10U

#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define TPI_DEVID_PTINVALID_Pos             9U

#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define TPI_DEVID_MinBufSz_Pos              6U

#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define TPI_DEVID_AsynClkIn_Pos             5U

#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define TPI_DEVID_NrTraceInput_Pos          0U

#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

/* TPI DEVTYPE Register Definitions */

#define TPI_DEVTYPE_SubType_Pos             4U

#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

#define TPI_DEVTYPE_MajorType_Pos           0U

#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)         /* end of group CMSIS_TPI */


#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)

typedef struct

{

  __IM  uint32_t TYPE;

  __IOM uint32_t CTRL;

  __IOM uint32_t RNR;

  __IOM uint32_t RBAR;

  __IOM uint32_t RASR;

  __IOM uint32_t RBAR_A1;

  __IOM uint32_t RASR_A1;

  __IOM uint32_t RBAR_A2;

  __IOM uint32_t RASR_A2;

  __IOM uint32_t RBAR_A3;

  __IOM uint32_t RASR_A3;

} MPU_Type;


#define MPU_TYPE_RALIASES                  4U


/* MPU Type Register Definitions */

#define MPU_TYPE_IREGION_Pos               16U

#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)

#define MPU_TYPE_DREGION_Pos                8U

#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)

#define MPU_TYPE_SEPARATE_Pos               0U

#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)

/* MPU Control Register Definitions */

#define MPU_CTRL_PRIVDEFENA_Pos             2U

#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)

#define MPU_CTRL_HFNMIENA_Pos               1U

#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)

#define MPU_CTRL_ENABLE_Pos                 0U

#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

/* MPU Region Number Register Definitions */

#define MPU_RNR_REGION_Pos                  0U

#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)

/* MPU Region Base Address Register Definitions */

#define MPU_RBAR_ADDR_Pos                   5U

#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

#define MPU_RBAR_VALID_Pos                  4U

#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)

#define MPU_RBAR_REGION_Pos                 0U

#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

/* MPU Region Attribute and Size Register Definitions */

#define MPU_RASR_ATTRS_Pos                 16U

#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)

#define MPU_RASR_XN_Pos                    28U

#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)

#define MPU_RASR_AP_Pos                    24U

#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)

#define MPU_RASR_TEX_Pos                   19U

#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)

#define MPU_RASR_S_Pos                     18U

#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)

#define MPU_RASR_C_Pos                     17U

#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)

#define MPU_RASR_B_Pos                     16U

#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)

#define MPU_RASR_SRD_Pos                    8U

#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)

#define MPU_RASR_SIZE_Pos                   1U

#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)

#define MPU_RASR_ENABLE_Pos                 0U

#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)

#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */


typedef struct

{

        uint32_t RESERVED0[1U];

  __IOM uint32_t FPCCR;

  __IOM uint32_t FPCAR;

  __IOM uint32_t FPDSCR;

  __IM  uint32_t MVFR0;

  __IM  uint32_t MVFR1;

  __IM  uint32_t MVFR2;

} FPU_Type;


/* Floating-Point Context Control Register Definitions */

#define FPU_FPCCR_ASPEN_Pos                31U

#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)

#define FPU_FPCCR_LSPEN_Pos                30U

#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)

#define FPU_FPCCR_MONRDY_Pos                8U

#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)

#define FPU_FPCCR_BFRDY_Pos                 6U

#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)

#define FPU_FPCCR_MMRDY_Pos                 5U

#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)

#define FPU_FPCCR_HFRDY_Pos                 4U

#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)

#define FPU_FPCCR_THREAD_Pos                3U

#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)

#define FPU_FPCCR_USER_Pos                  1U

#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)

#define FPU_FPCCR_LSPACT_Pos                0U

#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

/* Floating-Point Context Address Register Definitions */

#define FPU_FPCAR_ADDRESS_Pos               3U

#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

/* Floating-Point Default Status Control Register Definitions */

#define FPU_FPDSCR_AHP_Pos                 26U

#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)

#define FPU_FPDSCR_DN_Pos                  25U

#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)

#define FPU_FPDSCR_FZ_Pos                  24U

#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)

#define FPU_FPDSCR_RMode_Pos               22U

#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)

/* Media and FP Feature Register 0 Definitions */

#define FPU_MVFR0_FP_rounding_modes_Pos    28U

#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define FPU_MVFR0_Short_vectors_Pos        24U

#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define FPU_MVFR0_Square_root_Pos          20U

#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)

#define FPU_MVFR0_Divide_Pos               16U

#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)

#define FPU_MVFR0_FP_excep_trapping_Pos    12U

#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define FPU_MVFR0_Double_precision_Pos      8U

#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define FPU_MVFR0_Single_precision_Pos      4U

#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define FPU_MVFR0_A_SIMD_registers_Pos      0U

#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

/* Media and FP Feature Register 1 Definitions */

#define FPU_MVFR1_FP_fused_MAC_Pos         28U

#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define FPU_MVFR1_FP_HPFP_Pos              24U

#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define FPU_MVFR1_D_NaN_mode_Pos            4U

#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define FPU_MVFR1_FtZ_mode_Pos              0U

#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

/* Media and FP Feature Register 2 Definitions */


#define FPU_MVFR2_VFP_Misc_Pos              4U

#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

typedef struct

{

  __IOM uint32_t DHCSR;

  __OM  uint32_t DCRSR;

  __IOM uint32_t DCRDR;

  __IOM uint32_t DEMCR;

} CoreDebug_Type;


/* Debug Halting Control and Status Register Definitions */

#define CoreDebug_DHCSR_DBGKEY_Pos         16U

#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U

#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U

#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define CoreDebug_DHCSR_S_SLEEP_Pos        18U

#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define CoreDebug_DHCSR_S_HALT_Pos         17U

#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define CoreDebug_DHCSR_S_REGRDY_Pos       16U

#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U

#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define CoreDebug_DHCSR_C_STEP_Pos          2U

#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define CoreDebug_DHCSR_C_HALT_Pos          1U

#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U

#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

/* Debug Core Register Selector Register Definitions */

#define CoreDebug_DCRSR_REGWnR_Pos         16U

#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define CoreDebug_DCRSR_REGSEL_Pos          0U

#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

/* Debug Exception and Monitor Control Register Definitions */

#define CoreDebug_DEMCR_TRCENA_Pos         24U

#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define CoreDebug_DEMCR_MON_REQ_Pos        19U

#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define CoreDebug_DEMCR_MON_STEP_Pos       18U

#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define CoreDebug_DEMCR_MON_PEND_Pos       17U

#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define CoreDebug_DEMCR_MON_EN_Pos         16U

#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U

#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define CoreDebug_DEMCR_VC_INTERR_Pos       9U

#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U

#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define CoreDebug_DEMCR_VC_STATERR_Pos      7U

#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U

#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U

#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define CoreDebug_DEMCR_VC_MMERR_Pos        4U

#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U

#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)


#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)


/* Memory mapping of Core Hardware */

#define SCS_BASE            (0xE000E000UL)

#define ITM_BASE            (0xE0000000UL)

#define DWT_BASE            (0xE0001000UL)

#define TPI_BASE            (0xE0040000UL)

#define CoreDebug_BASE      (0xE000EDF0UL)

#define SysTick_BASE        (SCS_BASE +  0x0010UL)

#define NVIC_BASE           (SCS_BASE +  0x0100UL)

#define SCB_BASE            (SCS_BASE +  0x0D00UL)

#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )

#define SCB                 ((SCB_Type       *)     SCB_BASE      )

#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )

#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )

#define ITM                 ((ITM_Type       *)     ITM_BASE      )

#define DWT                 ((DWT_Type       *)     DWT_BASE      )

#define TPI                 ((TPI_Type       *)     TPI_BASE      )

#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)

#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)

  #define MPU_BASE          (SCS_BASE +  0x0D90UL)

  #define MPU               ((MPU_Type       *)     MPU_BASE      )

#endif


#define FPU_BASE            (SCS_BASE +  0x0F30UL)

#define FPU                 ((FPU_Type       *)     FPU_BASE      )

/*******************************************************************************

 *                Hardware Abstraction Layer

  Core Function Interface contains:

  - Core NVIC Functions

  - Core SysTick Functions

  - Core Debug Functions

  - Core Register Access Functions

 ******************************************************************************/

/* ##########################   NVIC functions  #################################### */

#ifdef CMSIS_NVIC_VIRTUAL

  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE

    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"

  #endif

  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE

#else

  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping

  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping

  #define NVIC_EnableIRQ              __NVIC_EnableIRQ

  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ

  #define NVIC_DisableIRQ             __NVIC_DisableIRQ

  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ

  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ

  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ

  #define NVIC_GetActive              __NVIC_GetActive

  #define NVIC_SetPriority            __NVIC_SetPriority

  #define NVIC_GetPriority            __NVIC_GetPriority

  #define NVIC_SystemReset            __NVIC_SystemReset

#endif /* CMSIS_NVIC_VIRTUAL */


#ifdef CMSIS_VECTAB_VIRTUAL

  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE

    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"

  #endif

  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE

#else

  #define NVIC_SetVector              __NVIC_SetVector

  #define NVIC_GetVector              __NVIC_GetVector

#endif  /* (CMSIS_VECTAB_VIRTUAL) */


#define NVIC_USER_IRQ_OFFSET          16


/* The following EXC_RETURN values are saved the LR on exception entry */

#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */

#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */

#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */

#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */

#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */

#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */


__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

{

  uint32_t reg_value;

  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */


  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */

  reg_value  =  (reg_value                                   |

                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */

  SCB->AIRCR =  reg_value;

}


__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)

{

  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));

}


__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)

{

  if ((int32_t)(IRQn) >= 0)

  {

    __COMPILER_BARRIER();

    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));

    __COMPILER_BARRIER();

  }

}


__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)

{

  if ((int32_t)(IRQn) >= 0)

  {

    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

  }

  else

  {

    return(0U);

  }

}


__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)

{

  if ((int32_t)(IRQn) >= 0)

  {

    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));

    __DSB();

    __ISB();

  }

}


__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)

{

  if ((int32_t)(IRQn) >= 0)

  {

    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

  }

  else

  {

    return(0U);

  }

}


__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)

{

  if ((int32_t)(IRQn) >= 0)

  {

    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));

  }

}


__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)

{

  if ((int32_t)(IRQn) >= 0)

  {

    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));

  }

}


__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)

{

  if ((int32_t)(IRQn) >= 0)

  {

    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

  }

  else

  {

    return(0U);

  }

}


__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

{

  if ((int32_t)(IRQn) >= 0)

  {

    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

  }

  else

  {

    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

  }

}


__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)

{


  if ((int32_t)(IRQn) >= 0)

  {

    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));

  }

  else

  {

    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));

  }

}


__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

{

  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

  uint32_t PreemptPriorityBits;

  uint32_t SubPriorityBits;


  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));


  return (

           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |

           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))

         );

}


__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)

{

  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

  uint32_t PreemptPriorityBits;

  uint32_t SubPriorityBits;


  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));


  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);

  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);

}


__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)

{

  uint32_t vectors = (uint32_t )SCB->VTOR;

  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;

  __DSB();

}


__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)

{

  uint32_t vectors = (uint32_t )SCB->VTOR;

  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));

}


__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)

{

  __DSB();                                                          /* Ensure all outstanding memory accesses included

                                                                       buffered write are completed before reset */

  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |

                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */

  __DSB();                                                          /* Ensure completion of memory access */


  for(;;)                                                           /* wait until reset */

  {

    __NOP();

  }

}


/* ##########################  MPU functions  #################################### */


#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)


#include "mpu_armv7.h"


#endif


/* ##########################  FPU functions  #################################### */

__STATIC_INLINE uint32_t SCB_GetFPUType(void)

{

  uint32_t mvfr0;


  mvfr0 = SCB->MVFR0;

  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)

  {

    return 2U;           /* Double + Single precision FPU */

  }

  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)

  {

    return 1U;           /* Single precision FPU */

  }

  else

  {

    return 0U;           /* No FPU */

  }

}


/* ##########################  Cache functions  #################################### */

/* Cache Size ID Register Macros */

#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )


#define __SCB_DCACHE_LINE_SIZE  32U

#define __SCB_ICACHE_LINE_SIZE  32U


__STATIC_FORCEINLINE void SCB_EnableICache (void)

{

  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)

    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */


    __DSB();

    __ISB();

    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */

    __DSB();

    __ISB();

    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */

    __DSB();

    __ISB();

  #endif

}


__STATIC_FORCEINLINE void SCB_DisableICache (void)

{

  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)

    __DSB();

    __ISB();

    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */

    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */

    __DSB();

    __ISB();

  #endif

}


__STATIC_FORCEINLINE void SCB_InvalidateICache (void)

{

  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)

    __DSB();

    __ISB();

    SCB->ICIALLU = 0UL;

    __DSB();

    __ISB();

  #endif

}


__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)

{

  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)

    if ( isize > 0 ) {

       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));

      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;


      __DSB();


      do {

        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */

        op_addr += __SCB_ICACHE_LINE_SIZE;

        op_size -= __SCB_ICACHE_LINE_SIZE;

      } while ( op_size > 0 );


      __DSB();

      __ISB();

    }

  #endif

}


__STATIC_FORCEINLINE void SCB_EnableDCache (void)

{

  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)

    uint32_t ccsidr;

    uint32_t sets;

    uint32_t ways;


    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */


    SCB->CSSELR = 0U;                       /* select Level 1 data cache */

    __DSB();


    ccsidr = SCB->CCSIDR;


                                            /* invalidate D-Cache */

    sets = (uint32_t)(CCSIDR_SETS(ccsidr));

    do {

      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));

      do {

        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |

                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );

        #if defined ( __CC_ARM )

          __schedule_barrier();

        #endif

      } while (ways-- != 0U);

    } while(sets-- != 0U);

    __DSB();


    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */


    __DSB();

    __ISB();

  #endif

}


__STATIC_FORCEINLINE void SCB_DisableDCache (void)

{

  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)

    uint32_t ccsidr;

    uint32_t sets;

    uint32_t ways;


    SCB->CSSELR = 0U;                       /* select Level 1 data cache */

    __DSB();


    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */

    __DSB();


    ccsidr = SCB->CCSIDR;


                                            /* clean & invalidate D-Cache */

    sets = (uint32_t)(CCSIDR_SETS(ccsidr));

    do {

      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));

      do {

        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |

                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );

        #if defined ( __CC_ARM )

          __schedule_barrier();

        #endif

      } while (ways-- != 0U);

    } while(sets-- != 0U);


    __DSB();

    __ISB();

  #endif

}


__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)

{

  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)

    uint32_t ccsidr;

    uint32_t sets;

    uint32_t ways;


    SCB->CSSELR = 0U;                       /* select Level 1 data cache */

    __DSB();


    ccsidr = SCB->CCSIDR;


                                            /* invalidate D-Cache */

    sets = (uint32_t)(CCSIDR_SETS(ccsidr));

    do {

      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));

      do {

        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |

                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );

        #if defined ( __CC_ARM )

          __schedule_barrier();

        #endif

      } while (ways-- != 0U);

    } while(sets-- != 0U);


    __DSB();

    __ISB();

  #endif

}


__STATIC_FORCEINLINE void SCB_CleanDCache (void)

{

  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)

    uint32_t ccsidr;

    uint32_t sets;

    uint32_t ways;


    SCB->CSSELR = 0U;                       /* select Level 1 data cache */

    __DSB();


    ccsidr = SCB->CCSIDR;


                                            /* clean D-Cache */

    sets = (uint32_t)(CCSIDR_SETS(ccsidr));

    do {

      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));

      do {

        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |

                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );

        #if defined ( __CC_ARM )

          __schedule_barrier();

        #endif

      } while (ways-- != 0U);

    } while(sets-- != 0U);


    __DSB();

    __ISB();

  #endif

}


__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)

{

  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)

    uint32_t ccsidr;

    uint32_t sets;

    uint32_t ways;


    SCB->CSSELR = 0U;                       /* select Level 1 data cache */

    __DSB();


    ccsidr = SCB->CCSIDR;


                                            /* clean & invalidate D-Cache */

    sets = (uint32_t)(CCSIDR_SETS(ccsidr));

    do {

      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));

      do {

        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |

                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );

        #if defined ( __CC_ARM )

          __schedule_barrier();

        #endif

      } while (ways-- != 0U);

    } while(sets-- != 0U);


    __DSB();

    __ISB();

  #endif

}


__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)

{

  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)

    if ( dsize > 0 ) {

       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));

      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;


      __DSB();


      do {

        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */

        op_addr += __SCB_DCACHE_LINE_SIZE;

        op_size -= __SCB_DCACHE_LINE_SIZE;

      } while ( op_size > 0 );


      __DSB();

      __ISB();

    }

  #endif

}


__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)

{

  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)

    if ( dsize > 0 ) {

       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));

      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;


      __DSB();


      do {

        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */

        op_addr += __SCB_DCACHE_LINE_SIZE;

        op_size -= __SCB_DCACHE_LINE_SIZE;

      } while ( op_size > 0 );


      __DSB();

      __ISB();

    }

  #endif

}


__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)

{

  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)

    if ( dsize > 0 ) {

       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));

      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;


      __DSB();


      do {

        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */

        op_addr +=          __SCB_DCACHE_LINE_SIZE;

        op_size -=          __SCB_DCACHE_LINE_SIZE;

      } while ( op_size > 0 );


      __DSB();

      __ISB();

    }

  #endif

}


/* ##################################    SysTick function  ############################################ */

#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)


__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

{

  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)

  {

    return (1UL);                                                   /* Reload value impossible */

  }


  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

                   SysTick_CTRL_TICKINT_Msk   |

                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

  return (0UL);                                                     /* Function successful */

}


#endif


/* ##################################### Debug In/Output function ########################################### */

extern volatile int32_t ITM_RxBuffer;

#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U)

__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

{

  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */

      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */

  {

    while (ITM->PORT[0U].u32 == 0UL)

    {

      __NOP();

    }

    ITM->PORT[0U].u8 = (uint8_t)ch;

  }

  return (ch);

}


__STATIC_INLINE int32_t ITM_ReceiveChar (void)

{

  int32_t ch = -1;                           /* no character available */


  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)

  {

    ch = ITM_RxBuffer;

    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

  }


  return (ch);

}


__STATIC_INLINE int32_t ITM_CheckChar (void)

{


  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)

  {

    return (0);                              /* no character available */

  }

  else

  {

    return (1);                              /*    character available */

  }

}


#ifdef __cplusplus

}

#endif


#endif /* __CORE_CM7_H_DEPENDANT */


#endif /* __CMSIS_GENERIC */


SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition core_cm7.h:998

SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition core_cm7.h:1002

FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition core_cm7.h:1600

SCB_DCCISW_SET_Pos
#define SCB_DCCISW_SET_Pos
Definition core_cm7.h:833

SCB_CCR_DC_Msk
#define SCB_CCR_DC_Msk
Definition core_cm7.h:600

SCB_DCCSW_SET_Msk
#define SCB_DCCSW_SET_Msk
Definition core_cm7.h:827

SCB_DCCSW_WAY_Pos
#define SCB_DCCSW_WAY_Pos
Definition core_cm7.h:823

ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition core_cm7.h:1094

SCB_DCCSW_WAY_Msk
#define SCB_DCCSW_WAY_Msk
Definition core_cm7.h:824

SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition core_cm7.h:571

SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition core_cm7.h:562

FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition core_cm7.h:1603

SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition core_cm7.h:995

SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition core_cm7.h:992

SCB_DCISW_WAY_Pos
#define SCB_DCISW_WAY_Pos
Definition core_cm7.h:816

SCB_DCCISW_WAY_Pos
#define SCB_DCCISW_WAY_Pos
Definition core_cm7.h:830

SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition core_cm7.h:561

SCB
#define SCB
Definition core_cm7.h:1778

SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition core_cm7.h:574

SCB_DCISW_SET_Msk
#define SCB_DCISW_SET_Msk
Definition core_cm7.h:820

ITM
#define ITM
Definition core_cm7.h:1781

SCB_DCISW_WAY_Msk
#define SCB_DCISW_WAY_Msk
Definition core_cm7.h:817

NVIC
#define NVIC
Definition core_cm7.h:1780

SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition core_cm7.h:570

SysTick
#define SysTick
Definition core_cm7.h:1779

SCB_DCCSW_SET_Pos
#define SCB_DCCSW_SET_Pos
Definition core_cm7.h:826

SCB_DCISW_SET_Pos
#define SCB_DCISW_SET_Pos
Definition core_cm7.h:819

SCB_DCCISW_SET_Msk
#define SCB_DCCISW_SET_Msk
Definition core_cm7.h:834

SCB_DCCISW_WAY_Msk
#define SCB_DCCISW_WAY_Msk
Definition core_cm7.h:831

SCB_CCR_IC_Msk
#define SCB_CCR_IC_Msk
Definition core_cm7.h:597

SCB_EnableDCache
__STATIC_FORCEINLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition core_cm7.h:2325

SCB_DisableICache
__STATIC_FORCEINLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition core_cm7.h:2262

SCB_CleanInvalidateDCache
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition core_cm7.h:2473

SCB_InvalidateICache
__STATIC_FORCEINLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
Definition core_cm7.h:2279

SCB_CleanInvalidateDCache_by_Addr
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean and Invalidate by address.
Definition core_cm7.h:2572

__SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE
Definition core_cm7.h:2234

SCB_EnableICache
__STATIC_FORCEINLINE void SCB_EnableICache(void)
Enable I-Cache.
Definition core_cm7.h:2241

SCB_InvalidateDCache_by_Addr
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr(void *addr, int32_t dsize)
D-Cache Invalidate by address.
Definition core_cm7.h:2512

SCB_InvalidateDCache
__STATIC_FORCEINLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
Definition core_cm7.h:2403

SCB_CleanDCache_by_Addr
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean by address.
Definition core_cm7.h:2542

__SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE
Definition core_cm7.h:2235

SCB_CleanDCache
__STATIC_FORCEINLINE void SCB_CleanDCache(void)
Clean D-Cache.
Definition core_cm7.h:2438

SCB_InvalidateICache_by_Addr
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr(void *addr, int32_t isize)
I-Cache Invalidate by address.
Definition core_cm7.h:2299

SCB_DisableDCache
__STATIC_FORCEINLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition core_cm7.h:2365

__NOP
#define __NOP()
No Operation.
Definition cmsis_gcc.h:903

__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition cmsis_gcc.h:944

__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition cmsis_gcc.h:933

__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition core_cm3.h:1757

__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition core_cm3.h:1730

NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition core_cm3.h:1707

__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition core_cm3.h:1746

__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition core_cm3.h:1633

__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition core_cm3.h:1594

__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition core_cm3.h:1560

SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition core_cm3.h:1799

__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition core_cm3.h:1503

__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition core_cm3.h:1491

__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition core_cm3.h:1611

__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition core_cm3.h:1579

__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition core_cm3.h:1522

NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition core_cm3.h:1680

__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition core_cm3.h:1541

__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition core_cm3.h:1655

__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition core_cm3.h:1472

xPSR_Type::@36::ICI_IT_2
uint32_t ICI_IT_2
Definition core_cm7.h:341

SCB_Type::DCCMVAC
__OM uint32_t DCCMVAC
Definition core_cm7.h:495

SCB_Type::AHBPCR
__IOM uint32_t AHBPCR
Definition core_cm7.h:502

ITM_RxBuffer
volatile int32_t ITM_RxBuffer

xPSR_Type::@36::N
uint32_t N
Definition core_cm7.h:346

SCB_Type::DCISW
__OM uint32_t DCISW
Definition core_cm7.h:493

APSR_Type::@34::Z
uint32_t Z
Definition core_cm7.h:284

SCB_Type::MVFR2
__IM uint32_t MVFR2
Definition core_cm7.h:487

SCB_Type::DTCMCR
__IOM uint32_t DTCMCR
Definition core_cm7.h:501

xPSR_Type::@36::_reserved0
uint32_t _reserved0
Definition core_cm7.h:336

xPSR_Type::@36::_reserved1
uint32_t _reserved1
Definition core_cm7.h:339

APSR_Type::@34::_reserved1
uint32_t _reserved1
Definition core_cm7.h:280

SCB_Type::ABFSR
__IOM uint32_t ABFSR
Definition core_cm7.h:506

xPSR_Type::@36::C
uint32_t C
Definition core_cm7.h:344

DWT_Type::LSR
__IM uint32_t LSR
Definition core_cm7.h:1146

APSR_Type::@34::GE
uint32_t GE
Definition core_cm7.h:279

DWT_Type::LAR
__OM uint32_t LAR
Definition core_cm7.h:1145

SCB_Type::DCIMVAC
__OM uint32_t DCIMVAC
Definition core_cm7.h:492

SCB_Type::DCCIMVAC
__OM uint32_t DCCIMVAC
Definition core_cm7.h:497

SCB_Type::CACR
__IOM uint32_t CACR
Definition core_cm7.h:503

SCB_Type::ICIALLU
__OM uint32_t ICIALLU
Definition core_cm7.h:489

xPSR_Type::@36::ISR
uint32_t ISR
Definition core_cm7.h:335

xPSR_Type::@36::Q
uint32_t Q
Definition core_cm7.h:342

SCB_Type::ICIMVAU
__OM uint32_t ICIMVAU
Definition core_cm7.h:491

APSR_Type::@34::C
uint32_t C
Definition core_cm7.h:283

xPSR_Type::@36::T
uint32_t T
Definition core_cm7.h:340

APSR_Type::@34::V
uint32_t V
Definition core_cm7.h:282

SCB_Type::MVFR1
__IM uint32_t MVFR1
Definition core_cm7.h:486

SCB_Type::MVFR0
__IM uint32_t MVFR0
Definition core_cm7.h:485

xPSR_Type::@36::Z
uint32_t Z
Definition core_cm7.h:345

APSR_Type::@34::_reserved0
uint32_t _reserved0
Definition core_cm7.h:278

SCB_Type::AHBSCR
__IOM uint32_t AHBSCR
Definition core_cm7.h:504

ITM_Type::@38::u32
__OM uint32_t u32
Definition core_cm7.h:1037

APSR_Type::@34::Q
uint32_t Q
Definition core_cm7.h:281

xPSR_Type::@36::V
uint32_t V
Definition core_cm7.h:343

xPSR_Type::@36::ICI_IT_1
uint32_t ICI_IT_1
Definition core_cm7.h:337

SCB_Type::ID_AFR
__IM uint32_t ID_AFR
Definition core_cm7.h:473

xPSR_Type::@36::GE
uint32_t GE
Definition core_cm7.h:338

ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition core_cm7.h:2649

CONTROL_Type::@37::SPSEL
uint32_t SPSEL
Definition core_cm7.h:391

SCB_Type::DCCMVAU
__OM uint32_t DCCMVAU
Definition core_cm7.h:494

SCB_Type::DCCSW
__OM uint32_t DCCSW
Definition core_cm7.h:496

CONTROL_Type::@37::nPRIV
uint32_t nPRIV
Definition core_cm7.h:390

ITM_Type::@38::u8
__OM uint8_t u8
Definition core_cm7.h:1035

SCB_Type::ITCMCR
__IOM uint32_t ITCMCR
Definition core_cm7.h:500

CONTROL_Type::@37::_reserved0
uint32_t _reserved0
Definition core_cm7.h:393

CONTROL_Type::@37::FPCA
uint32_t FPCA
Definition core_cm7.h:392

ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition core_cm3.h:1893

ITM_SendChar
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition core_cm3.h:1872

SCB_Type::CSSELR
__IOM uint32_t CSSELR
Definition core_cm7.h:480

SCB_Type::STIR
__OM uint32_t STIR
Definition core_cm7.h:483

SCB_Type::CLIDR
__IM uint32_t CLIDR
Definition core_cm7.h:477

SCB_Type::ID_DFR
__IM uint32_t ID_DFR
Definition core_cm7.h:472

IPSR_Type::@35::ISR
uint32_t ISR
Definition core_cm7.h:317

ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition core_cm3.h:1913

IPSR_Type::@35::_reserved0
uint32_t _reserved0
Definition core_cm7.h:318

SCB_Type::CTR
__IM uint32_t CTR
Definition core_cm7.h:478

SCB_Type::DCCISW
__OM uint32_t DCCISW
Definition core_cm7.h:498

APSR_Type::@34::N
uint32_t N
Definition core_cm7.h:285

ITM_Type::@38::u16
__OM uint16_t u16
Definition core_cm7.h:1036

SCB_Type::CCSIDR
__IM uint32_t CCSIDR
Definition core_cm7.h:479

__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition MK60D10.h:294

IRQn
IRQn
Definition MK60D10.h:157

SysTick_IRQn
@ SysTick_IRQn
Definition MK60D10.h:170

IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f107xc.h:70

CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition core_cm3.h:1247

DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition core_cm3.h:842

FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition core_cm4.h:1305

ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition core_cm3.h:754

MPU_Type
Definition MK60N512MD100.h:5546

NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition core_cm3.h:341

SCB_Type
Structure type to access the System Control Block (SCB).
Definition core_cm3.h:375

SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition core_cm3.h:656

SysTick_Type
Structure type to access the System Timer (SysTick).
Definition core_cm3.h:702

TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition core_cm3.h:989

APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition core_cm3.h:207

CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition core_cm3.h:310

IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition core_cm3.h:241

xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition core_cm3.h:259