mikroSDK Reference Manual
dcd_stm32_fsdev_pvt_st.h
1
29// This file contains source copied from ST's HAL, and thus should have their copyright statement.
30
31// PMA_LENGTH is PMA buffer size in bytes.
32// On 512-byte devices, access with a stride of two words (use every other 16-bit address)
33// On 1024-byte devices, access with a stride of one word (use every 16-bit address)
34
35#ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
36#define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
37
38// Note: Added for MikroE implementation.
39#ifdef __PROJECT_MIKROSDK_MIKROE__
40#include "mcu.h"
41#include "interrupts.h"
42#endif
43
44#if CFG_TUSB_MCU == OPT_MCU_STM32F0
45 // Note: Changed for MikroE implementation.
46 #ifndef __PROJECT_MIKROSDK_MIKROE__
47 #include "stm32f0xx.h"
48 #endif
49 #define PMA_LENGTH (1024u)
50 // F0x2 models are crystal-less
51 // All have internal D+ pull-up
52 // 070RB: 2 x 16 bits/word memory LPM Support, BCD Support
53 // PMA dedicated to USB (no sharing with CAN)
54
55#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
56 // Note: Changed for MikroE implementation.
57 #ifndef __PROJECT_MIKROSDK_MIKROE__
58 #include "stm32f1xx.h"
59 #endif
60 #define PMA_LENGTH (512u)
61 // NO internal Pull-ups
62 // *B, and *C: 2 x 16 bits/word
63
64 // F1 names this differently from the rest
65 #define USB_CNTR_LPMODE USB_CNTR_LP_MODE
66
67 // Note: Changed for MikroE implementation.
68 // Note: Added STM32F373xB for MikroE implementation.
69#elif defined(STM32F302xB) || defined(STM32F302xC) || \
70 defined(STM32F303xB) || defined(STM32F303xC) || \
71 defined(STM32F373xB) || defined(STM32F373xC)
72 #ifndef __PROJECT_MIKROSDK_MIKROE__
73 #include "stm32f3xx.h"
74 #endif
75 #define PMA_LENGTH (512u)
76 // NO internal Pull-ups
77 // *B, and *C: 1 x 16 bits/word
78 // PMA dedicated to USB (no sharing with CAN)
79
80 // Note: Changed for MikroE implementation.
81 // Note: Added STM32F373x8 for MikroE implementation.
82#elif defined(STM32F302x6) || defined(STM32F302x8) || \
83 defined(STM32F302xD) || defined(STM32F302xE) || \
84 defined(STM32F303xD) || defined(STM32F303xE) || \
85 defined(STM32F373x8)
86 #ifndef __PROJECT_MIKROSDK_MIKROE__
87 #include "stm32f3xx.h"
88 #endif
89 #define PMA_LENGTH (1024u)
90 // NO internal Pull-ups
91 // *6, *8, *D, and *E: 2 x 16 bits/word LPM Support
92 // When CAN clock is enabled, USB can use first 768 bytes ONLY.
93
94#elif CFG_TUSB_MCU == OPT_MCU_STM32L0
95 // Note: Changed for MikroE implementation.
96 #ifndef __PROJECT_MIKROSDK_MIKROE__
97 #include "stm32l0xx.h"
98 #endif
99 #define PMA_LENGTH (1024u)
100
101#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
102 // Note: Changed for MikroE implementation.
103 #ifndef __PROJECT_MIKROSDK_MIKROE__
104 #include "stm32l1xx.h"
105 #endif
106 #define PMA_LENGTH (512u)
107
108#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
109 #include "stm32g4xx.h"
110 #define PMA_LENGTH (1024u)
111
112#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
113 // Note: Changed for MikroE implementation.
114 #ifndef __PROJECT_MIKROSDK_MIKROE__
115 #include "stm32g0xx.h"
116 #endif
117 #define PMA_32BIT_ACCESS
118 #define PMA_LENGTH (2048u)
119 #undef USB_PMAADDR
120 #define USB_PMAADDR USB_DRD_PMAADDR
121 #define USB_TypeDef USB_DRD_TypeDef
122 #define EP0R CHEP0R
123 #define USB_EP_CTR_RX USB_EP_VTRX
124 #define USB_EP_CTR_TX USB_EP_VTTX
125 #define USB_EP_T_FIELD USB_CHEP_UTYPE
126 #define USB_EPREG_MASK USB_CHEP_REG_MASK
127 #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
128 #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
129 #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
130 #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
131 #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
132 #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
133 #define USB_EPRX_STAT USB_CH_RX_VALID
134 #define USB_EPKIND_MASK USB_EP_KIND_MASK
135 #define USB USB_DRD_FS
136 #define USB_CNTR_FRES USB_CNTR_USBRST
137 #define USB_CNTR_RESUME USB_CNTR_L2RES
138 #define USB_ISTR_EP_ID USB_ISTR_IDN
139 #define USB_EPADDR_FIELD USB_CHEP_ADDR
140 #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
141 #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
142
143#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
144 #include "stm32wbxx.h"
145 #define PMA_LENGTH (1024u)
146 /* ST provided header has incorrect value */
147 #undef USB_PMAADDR
148 #define USB_PMAADDR USB1_PMAADDR
149
150#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
151 // Note: Changed for MikroE implementation.
152 #ifndef __PROJECT_MIKROSDK_MIKROE__
153 #include "stm32l4xx.h"
154 #endif
155 #define PMA_LENGTH (1024u)
156
157#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
158 #include "stm32l5xx.h"
159 #define PMA_LENGTH (1024u)
160
161 #ifndef USB_PMAADDR
162 #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS))
163 #endif
164
165#else
166 #error You are using an untested or unimplemented STM32 variant. Please update the driver.
167 // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
168#endif
169
170// For purposes of accessing the packet
171#if ((PMA_LENGTH) == 512u)
172 #define PMA_STRIDE (2u)
173#elif ((PMA_LENGTH) == 1024u)
174 #define PMA_STRIDE (1u)
175#endif
176
177// For type-safety create a new macro for the volatile address of PMAADDR
178// The compiler should warn us if we cast it to a non-volatile type?
179#ifdef PMA_32BIT_ACCESS
180static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR;
181#else
182// Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
183static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
184
185TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
186{
187 size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
188 total_word_offset *= PMA_STRIDE;
189 return &(pma[total_word_offset]);
190}
191
192TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
193{
194 return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u);
195}
196
197TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
198{
199 return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u);
200}
201#endif
202
203/* Aligned buffer size according to hardware */
204TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size)
205{
206 /* The STM32 full speed USB peripheral supports only a limited set of
207 * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */
208 uint16_t blocksize = (size > 62) ? 32 : 2;
209
210 // Round up while dividing requested size by blocksize
211 uint16_t numblocks = (size + blocksize - 1) / blocksize ;
212
213 return numblocks * blocksize;
214}
215
216/* SetENDPOINT */
217TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue)
218{
219#ifdef PMA_32BIT_ACCESS
220 (void) USBx;
221 __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4);
222 *reg = wRegValue;
223#else
224 __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
225 *reg = (uint16_t)wRegValue;
226#endif
227}
228
229/* GetENDPOINT */
230TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) {
231#ifdef PMA_32BIT_ACCESS
232 (void) USBx;
233 __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4);
234#else
235 __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
236#endif
237 return *reg;
238}
239
240TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType)
241{
242 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
243 regVal &= (uint32_t)USB_EP_T_MASK;
244 regVal |= wType;
245 regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high
246 pcd_set_endpoint(USBx, bEpIdx, regVal);
247}
248
249TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx)
250{
251 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
252 regVal &= USB_EP_T_FIELD;
253 return regVal;
254}
261TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx)
262{
263 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
264 regVal &= USB_EPREG_MASK;
265 regVal &= ~USB_EP_CTR_RX;
266 regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0)
267 pcd_set_endpoint(USBx, bEpIdx, regVal);
268}
269
270TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx)
271{
272 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
273 regVal &= USB_EPREG_MASK;
274 regVal &= ~USB_EP_CTR_TX;
275 regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0)
276 pcd_set_endpoint(USBx, bEpIdx,regVal);
277}
284TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
285{
286#ifdef PMA_32BIT_ACCESS
287 (void) USBx;
288 return (pma32[2*bEpIdx] & 0x03FF0000) >> 16;
289#else
290 __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
291 return *regPtr & 0x3ffU;
292#endif
293}
294
295TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
296{
297#ifdef PMA_32BIT_ACCESS
298 (void) USBx;
299 return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16;
300#else
301 __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
302 return *regPtr & 0x3ffU;
303#endif
304}
305
313TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t bAddr)
314{
315 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
316 regVal &= USB_EPREG_MASK;
317 regVal |= bAddr;
318 regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
319 pcd_set_endpoint(USBx, bEpIdx,regVal);
320}
321
322TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx)
323{
324#ifdef PMA_32BIT_ACCESS
325 (void) USBx;
326 return pma32[2*bEpIdx] & 0x0000FFFFu ;
327#else
328 return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u);
329#endif
330}
331
332TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx)
333{
334#ifdef PMA_32BIT_ACCESS
335 (void) USBx;
336 return pma32[2*bEpIdx + 1] & 0x0000FFFFu;
337#else
338 return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u);
339#endif
340}
341
342TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr)
343{
344#ifdef PMA_32BIT_ACCESS
345 (void) USBx;
346 pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
347#else
348 *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u) = addr;
349#endif
350}
351
352TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr)
353{
354#ifdef PMA_32BIT_ACCESS
355 (void) USBx;
356 pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
357#else
358 *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u) = addr;
359#endif
360}
361
362TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
363{
364#ifdef PMA_32BIT_ACCESS
365 (void) USBx;
366 pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
367#else
368 __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
369 *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
370#endif
371}
372
373TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
374{
375#ifdef PMA_32BIT_ACCESS
376 (void) USBx;
377 pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
378#else
379 __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
380 *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
381#endif
382}
383
384TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t blocksize, uint32_t numblocks)
385{
386 /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
387#ifdef PMA_32BIT_ACCESS
388 (void) USBx;
389 pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26);
390#else
391 __IO uint16_t *pdwReg = pcd_btable_word_ptr(USBx, rxtx_idx*2u + 1u);
392 *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10);
393#endif
394}
395
396TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount)
397{
398 wCount = pcd_aligned_buffer_size(wCount);
399
400 /* We assume that the buffer size is already aligned to hardware requirements. */
401 uint16_t blocksize = (wCount > 62) ? 1 : 0;
402 uint16_t numblocks = wCount / (blocksize ? 32 : 2);
403
404 /* There should be no remainder in the above calculation */
405 TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, );
406
407 /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
408 pcd_set_ep_blsize_num_blocks(USBx, rxtx_idx, blocksize, numblocks);
409}
410
411TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
412{
413 pcd_set_ep_bufsize(USBx, 2*bEpIdx, wCount);
414}
415
416TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
417{
418 pcd_set_ep_bufsize(USBx, 2*bEpIdx + 1, wCount);
419}
420
428TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState)
429{
430 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
431 regVal &= USB_EPTX_DTOGMASK;
432
433 /* toggle first bit ? */
434 if((USB_EPTX_DTOG1 & (wState))!= 0U)
435 {
436 regVal ^= USB_EPTX_DTOG1;
437 }
438 /* toggle second bit ? */
439 if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U)
440 {
441 regVal ^= USB_EPTX_DTOG2;
442 }
443
444 regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
445 pcd_set_endpoint(USBx, bEpIdx, regVal);
446} /* pcd_set_ep_tx_status */
447
456TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState)
457{
458 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
459 regVal &= USB_EPRX_DTOGMASK;
460
461 /* toggle first bit ? */
462 if((USB_EPRX_DTOG1 & wState)!= 0U)
463 {
464 regVal ^= USB_EPRX_DTOG1;
465 }
466 /* toggle second bit ? */
467 if((USB_EPRX_DTOG2 & wState)!= 0U)
468 {
469 regVal ^= USB_EPRX_DTOG2;
470 }
471
472 regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
473 pcd_set_endpoint(USBx, bEpIdx, regVal);
474} /* pcd_set_ep_rx_status */
475
476TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx)
477{
478 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
479 return (regVal & USB_EPRX_STAT) >> (12u);
480} /* pcd_get_ep_rx_status */
481
482
489TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx)
490{
491 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
492 regVal &= USB_EPREG_MASK;
493 regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX;
494 pcd_set_endpoint(USBx, bEpIdx, regVal);
495}
496
497TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx)
498{
499 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
500 regVal &= USB_EPREG_MASK;
501 regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX;
502 pcd_set_endpoint(USBx, bEpIdx, regVal);
503}
504
512TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx)
513{
514 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
515 if((regVal & USB_EP_DTOG_RX) != 0)
516 {
517 pcd_rx_dtog(USBx,bEpIdx);
518 }
519}
520
521TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx)
522{
523 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
524 if((regVal & USB_EP_DTOG_TX) != 0)
525 {
526 pcd_tx_dtog(USBx,bEpIdx);
527 }
528}
529
537TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx)
538{
539 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
540 regVal |= USB_EP_KIND;
541 regVal &= USB_EPREG_MASK;
542 regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
543 pcd_set_endpoint(USBx, bEpIdx, regVal);
544}
545TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx)
546{
547 uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
548 regVal &= USB_EPKIND_MASK;
549 regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
550 pcd_set_endpoint(USBx, bEpIdx, regVal);
551}
552
553// This checks if the device has "LPM"
554#if defined(USB_ISTR_L1REQ)
555#define USB_ISTR_L1REQ_FORCED (USB_ISTR_L1REQ)
556#else
557#define USB_ISTR_L1REQ_FORCED ((uint16_t)0x0000U)
558#endif
559
560#define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \
561 USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED )
562
563// Number of endpoints in hardware
564// TODO should use TUP_DCD_ENDPOINT_MAX
565#define STFSDEV_EP_COUNT (8u)
566
567#endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */
__O
#define __O
Definition core_cm3.h:169
__IO
#define __IO
Definition core_cm3.h:170
__I
#define __I
Definition core_cm3.h:167
stm32f1xx.h
CMSIS STM32F1xx Device Peripheral Access Layer Header File.