mikroSDK Reference Manual
dwc2_type.h
1
17#ifndef _TUSB_DWC2_TYPES_H_
18#define _TUSB_DWC2_TYPES_H_
19
20#include "stdint.h"
21
22#ifdef __cplusplus
23 extern "C" {
24#endif
25
26// Controller
27typedef struct
28{
29 uintptr_t reg_base;
30 uint32_t irqnum;
31 uint8_t ep_count;
32 uint32_t ep_fifo_size;
33}dwc2_controller_t;
34
35/* DWC OTG HW Release versions */
36#define DWC2_CORE_REV_2_71a 0x4f54271a
37#define DWC2_CORE_REV_2_72a 0x4f54272a
38#define DWC2_CORE_REV_2_80a 0x4f54280a
39#define DWC2_CORE_REV_2_90a 0x4f54290a
40#define DWC2_CORE_REV_2_91a 0x4f54291a
41#define DWC2_CORE_REV_2_92a 0x4f54292a
42#define DWC2_CORE_REV_2_94a 0x4f54294a
43#define DWC2_CORE_REV_3_00a 0x4f54300a
44#define DWC2_CORE_REV_3_10a 0x4f54310a
45#define DWC2_CORE_REV_4_00a 0x4f54400a
46#define DWC2_CORE_REV_4_20a 0x4f54420a
47#define DWC2_FS_IOT_REV_1_00a 0x5531100a
48#define DWC2_HS_IOT_REV_1_00a 0x5532100a
49#define DWC2_CORE_REV_MASK 0x0000ffff
50
51/* DWC OTG HW Core ID */
52#define DWC2_OTG_ID 0x4f540000
53#define DWC2_FS_IOT_ID 0x55310000
54#define DWC2_HS_IOT_ID 0x55320000
55
56#ifdef __cplusplus
57 extern "C" {
58#endif
59
60#if 0
61// HS PHY
62typedef struct
63{
64 volatile uint32_t HS_PHYC_PLL; // This register is used to control the PLL of the HS PHY. 000h */
65 volatile uint32_t Reserved04; // Reserved 004h */
66 volatile uint32_t Reserved08; // Reserved 008h */
67 volatile uint32_t HS_PHYC_TUNE; // This register is used to control the tuning interface of the High Speed PHY. 00Ch */
68 volatile uint32_t Reserved10; // Reserved 010h */
69 volatile uint32_t Reserved14; // Reserved 014h */
70 volatile uint32_t HS_PHYC_LDO; // This register is used to control the regulator (LDO). 018h */
71} HS_PHYC_GlobalTypeDef;
72#endif
73
74enum {
75 HS_PHY_TYPE_NONE = 0 , // not supported
76 HS_PHY_TYPE_UTMI , // internal PHY (mostly)
77 HS_PHY_TYPE_ULPI , // external PHY
78 HS_PHY_TYPE_UTMI_ULPI ,
79};
80
81enum {
82 FS_PHY_TYPE_NONE = 0, // not supported
83 FS_PHY_TYPE_DEDICATED,
84 FS_PHY_TYPE_UTMI,
85 FS_PHY_TYPE_ULPI,
86};
87
88typedef struct TU_ATTR_PACKED
89{
90 uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP
91 uint32_t arch : 2; // 0: slave-only | 1: External DMA | 2: Internal DMA | 3: others
92 uint32_t point2point : 1; // 0: support hub and split | 1: no hub, no split
93 uint32_t hs_phy_type : 2; // 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
94 uint32_t fs_phy_type : 2; // 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
95 uint32_t num_dev_ep : 4; // Number of device endpoints (not including EP0)
96 uint32_t num_host_ch : 4; // Number of host channel
97 uint32_t period_channel_support : 1; // Support Periodic OUT Host Channel
98 uint32_t enable_dynamic_fifo : 1; // Dynamic FIFO Sizing Enabled
99 uint32_t mul_cpu_int : 1; // Multi-Processor Interrupt Enabled
100 uint32_t reserved21 : 1;
101 uint32_t nperiod_tx_q_depth : 2; // Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
102 uint32_t host_period_tx_q_depth : 2; // Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
103 uint32_t dev_token_q_depth : 5; // Device IN token sequence learning queue depth: 0-30
104 uint32_t otg_enable_ic_usb : 1; // IC_USB mode specified for mode of operation
105} dwc2_ghwcfg2_t;
106
107TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size");
108
109typedef struct TU_ATTR_PACKED
110{
111 uint32_t xfer_size_width : 4; // Transfer size counter in bits = 11 + n (max 19 bits)
112 uint32_t packet_size_width : 3; // Packet size counter in bits = 4 + n (max 10 bits)
113 uint32_t otg_enable : 1; // 1 is OTG capable
114 uint32_t i2c_enable : 1; // I2C interface is available
115 uint32_t vendor_ctrl_itf : 1; // Vendor control interface is available
116 uint32_t optional_feature_removed : 1; // remove User ID, GPIO, SOF toggle & counter
117 uint32_t synch_reset : 1; // 0: async reset | 1: synch reset
118 uint32_t otg_adp_support : 1; // ADP logic is present along with HSOTG controller
119 uint32_t otg_enable_hsic : 1; // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
120 uint32_t battery_charger_support : 1; // support battery charger
121 uint32_t lpm_mode : 1; // LPC mode
122 uint32_t total_fifo_size : 16; // DFIFO depth value in terms of 32-bit words
123}dwc2_ghwcfg3_t;
124
125TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size");
126
127typedef struct TU_ATTR_PACKED
128{
129 uint32_t num_dev_period_in_ep : 4; // Number of Device Periodic IN Endpoints
130 uint32_t power_optimized : 1; // Partial Power Down Enabled
131 uint32_t ahb_freq_min : 1; // 1: minimum of AHB frequency is less than 60 MHz
132 uint32_t hibernation : 1; // Hibernation feature is enabled
133 uint32_t reserved7 : 3;
134 uint32_t service_interval_mode : 1; // Service Interval supported
135 uint32_t ipg_isoc_en : 1; // IPG ISOC supported
136 uint32_t acg_enable : 1; // ACG enabled
137 uint32_t reserved13 : 1;
138 uint32_t utmi_phy_data_width : 2; // 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
139 uint32_t dev_ctrl_ep_num : 4; // Number of Device control endpoints in addition to EP0
140 uint32_t iddg_filter_enabled : 1;
141 uint32_t vbus_valid_filter_enabled : 1;
142 uint32_t a_valid_filter_enabled : 1;
143 uint32_t b_valid_filter_enabled : 1;
144 uint32_t dedicated_fifos : 1; // Dedicated tx fifo for device IN Endpoint is enabled
145 uint32_t num_dev_in_eps : 4; // Number of Device IN Endpoints including EP0
146 uint32_t dma_desc_enable : 1; // scatter/gather DMA configuration
147 uint32_t dma_dynamic : 1; // Dynamic scatter/gather DMA
148}dwc2_ghwcfg4_t;
149
150TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size");
151
152// Host Channel
153typedef struct
154{
155 volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics
156 volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control
157 volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt
158 volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask
159 volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size
160 volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address
161 uint32_t reserved518; // 518 + 20*ch
162 volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address
163} dwc2_channel_t;
164
165// Endpoint IN
166typedef struct
167{
168 volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control
169 uint32_t reserved04; // 904
170 volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt
171 uint32_t reserved0c; // 90C
172 volatile uint32_t dieptsiz; // 910 + 20*ep Device IN Endpoint Transfer Size
173 volatile uint32_t diepdma; // 914 + 20*ep Device IN Endpoint DMA Address
174 volatile uint32_t dtxfsts; // 918 + 20*ep Device IN Endpoint Tx FIFO Status
175 uint32_t reserved1c; // 91C
176} dwc2_epin_t;
177
178// Endpoint OUT
179typedef struct
180{
181 volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control
182 uint32_t reserved04; // B04
183 volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt
184 uint32_t reserved0c; // B0C
185 volatile uint32_t doeptsiz; // B10 + 20*ep Device OUT Endpoint Transfer Size
186 volatile uint32_t doepdma; // B14 + 20*ep Device OUT Endpoint DMA Address
187 uint32_t reserved18[2]; // B18..B1C
188} dwc2_epout_t;
189
190typedef struct
191{
192 //------------- Core Global -------------//
193 volatile uint32_t gotgctl; // 000 OTG Control and Status
194 volatile uint32_t gotgint; // 004 OTG Interrupt
195 volatile uint32_t gahbcfg; // 008 AHB Configuration
196 volatile uint32_t gusbcfg; // 00c USB Configuration
197 volatile uint32_t grstctl; // 010 Reset
198 volatile uint32_t gintsts; // 014 Interrupt
199 volatile uint32_t gintmsk; // 018 Interrupt Mask
200 volatile uint32_t grxstsr; // 01c Receive Status Debug Read
201 volatile uint32_t grxstsp; // 020 Receive Status Read/Pop
202 volatile uint32_t grxfsiz; // 024 Receive FIFO Size
203union {
204 volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size
205 volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size
206};
207 volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status
208 volatile uint32_t gi2cctl; // 030 I2C Address
209 volatile uint32_t gpvndctl; // 034 PHY Vendor Control
210union {
211 volatile uint32_t ggpio; // 038 General Purpose IO
212 volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration
213};
214 volatile uint32_t guid; // 03C User (Application programmable) ID
215 volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version
216 volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
217union {
218 volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2
219 dwc2_ghwcfg2_t ghwcfg2_bm;
220};
221union {
222 volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3
223 dwc2_ghwcfg3_t ghwcfg3_bm;
224};
225union {
226 volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4
227 dwc2_ghwcfg4_t ghwcfg4_bm;
228};
229 volatile uint32_t glpmcfg; // 054 Core LPM Configuration
230 volatile uint32_t gpwrdn; // 058 Power Down
231 volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration
232 volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status
233 uint32_t reserved64[39]; // 064..0FF
234 volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size
235 volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size
236 uint32_t reserved140[176]; // 140..3FF
237
238 //------------- Host -------------//
239 volatile uint32_t hcfg; // 400 Host Configuration
240 volatile uint32_t hfir; // 404 Host Frame Interval
241 volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining
242 uint32_t reserved40c; // 40C
243 volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status
244 volatile uint32_t haint; // 414 Host All Channels Interrupt
245 volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask
246 volatile uint32_t hflbaddr; // 41C Host Frame List Base Address
247 uint32_t reserved420[8]; // 420..43F
248 volatile uint32_t hprt; // 440 Host Port Control and Status
249 uint32_t reserved444[47]; // 444..4FF
250
251 //------------- Host Channel -------------//
252 dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15
253 uint32_t reserved700[64]; // 700..7FF
254
255 //------------- Device -------------//
256 volatile uint32_t dcfg; // 800 Device Configuration
257 volatile uint32_t dctl; // 804 Device Control
258 volatile uint32_t dsts; // 808 Device Status (RO)
259 uint32_t reserved80c; // 80C
260 volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask
261 volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask
262 volatile uint32_t daint; // 818 Device All Endpoints Interrupt
263 volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask
264 volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1
265 volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2
266 volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time
267 volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time
268 volatile uint32_t dthrctl; // 830 Device threshold Control
269 volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask
270 volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt
271 volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk
272 volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask
273 volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask
274 uint32_t reserved8c0[16]; // 8C0..8FF
275
276 //------------- Device Endpoint -------------//
277 dwc2_epin_t epin[16]; // 900..AFF IN Endpoints
278 dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints
279 uint32_t reservedd00[64]; // D00..DFF
280
281 //------------- Power Clock -------------//
282 volatile uint32_t pcgctl; // E00 Power and Clock Gating Control
283 volatile uint32_t pcgctl1; // E04
284 uint32_t reservede08[126]; // E08..FFF
285
286 //------------- FIFOs -------------//
287 // Word-accessed only using first pointer since it auto shift
288 volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO
289} dwc2_regs_t;
290
291TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size");
292TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size");
293TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x0800, "incorrect size");
294TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin ) == 0x0900, "incorrect size");
295TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0x0B00, "incorrect size");
296TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctl ) == 0x0E00, "incorrect size");
297TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
298
299//--------------------------------------------------------------------+
300// Register Bit Definitions
301//--------------------------------------------------------------------+
302
303/******************** Bit definition for GOTGCTL register ********************/
304#define GOTGCTL_SRQSCS_Pos (0U)
305#define GOTGCTL_SRQSCS_Msk (0x1UL << GOTGCTL_SRQSCS_Pos) // 0x00000001 */
306#define GOTGCTL_SRQSCS GOTGCTL_SRQSCS_Msk // Session request success */
307#define GOTGCTL_SRQ_Pos (1U)
308#define GOTGCTL_SRQ_Msk (0x1UL << GOTGCTL_SRQ_Pos) // 0x00000002 */
309#define GOTGCTL_SRQ GOTGCTL_SRQ_Msk // Session request */
310#define GOTGCTL_VBVALOEN_Pos (2U)
311#define GOTGCTL_VBVALOEN_Msk (0x1UL << GOTGCTL_VBVALOEN_Pos) // 0x00000004 */
312#define GOTGCTL_VBVALOEN GOTGCTL_VBVALOEN_Msk // VBUS valid override enable */
313#define GOTGCTL_VBVALOVAL_Pos (3U)
314#define GOTGCTL_VBVALOVAL_Msk (0x1UL << GOTGCTL_VBVALOVAL_Pos) // 0x00000008 */
315#define GOTGCTL_VBVALOVAL GOTGCTL_VBVALOVAL_Msk // VBUS valid override value */
316#define GOTGCTL_AVALOEN_Pos (4U)
317#define GOTGCTL_AVALOEN_Msk (0x1UL << GOTGCTL_AVALOEN_Pos) // 0x00000010 */
318#define GOTGCTL_AVALOEN GOTGCTL_AVALOEN_Msk // A-peripheral session valid override enable */
319#define GOTGCTL_AVALOVAL_Pos (5U)
320#define GOTGCTL_AVALOVAL_Msk (0x1UL << GOTGCTL_AVALOVAL_Pos) // 0x00000020 */
321#define GOTGCTL_AVALOVAL GOTGCTL_AVALOVAL_Msk // A-peripheral session valid override value */
322#define GOTGCTL_BVALOEN_Pos (6U)
323#define GOTGCTL_BVALOEN_Msk (0x1UL << GOTGCTL_BVALOEN_Pos) // 0x00000040 */
324#define GOTGCTL_BVALOEN GOTGCTL_BVALOEN_Msk // B-peripheral session valid override enable */
325#define GOTGCTL_BVALOVAL_Pos (7U)
326#define GOTGCTL_BVALOVAL_Msk (0x1UL << GOTGCTL_BVALOVAL_Pos) // 0x00000080 */
327#define GOTGCTL_BVALOVAL GOTGCTL_BVALOVAL_Msk // B-peripheral session valid override value */
328#define GOTGCTL_HNGSCS_Pos (8U)
329#define GOTGCTL_HNGSCS_Msk (0x1UL << GOTGCTL_HNGSCS_Pos) // 0x00000100 */
330#define GOTGCTL_HNGSCS GOTGCTL_HNGSCS_Msk // Host set HNP enable */
331#define GOTGCTL_HNPRQ_Pos (9U)
332#define GOTGCTL_HNPRQ_Msk (0x1UL << GOTGCTL_HNPRQ_Pos) // 0x00000200 */
333#define GOTGCTL_HNPRQ GOTGCTL_HNPRQ_Msk // HNP request */
334#define GOTGCTL_HSHNPEN_Pos (10U)
335#define GOTGCTL_HSHNPEN_Msk (0x1UL << GOTGCTL_HSHNPEN_Pos) // 0x00000400 */
336#define GOTGCTL_HSHNPEN GOTGCTL_HSHNPEN_Msk // Host set HNP enable */
337#define GOTGCTL_DHNPEN_Pos (11U)
338#define GOTGCTL_DHNPEN_Msk (0x1UL << GOTGCTL_DHNPEN_Pos) // 0x00000800 */
339#define GOTGCTL_DHNPEN GOTGCTL_DHNPEN_Msk // Device HNP enabled */
340#define GOTGCTL_EHEN_Pos (12U)
341#define GOTGCTL_EHEN_Msk (0x1UL << GOTGCTL_EHEN_Pos) // 0x00001000 */
342#define GOTGCTL_EHEN GOTGCTL_EHEN_Msk // Embedded host enable */
343#define GOTGCTL_CIDSTS_Pos (16U)
344#define GOTGCTL_CIDSTS_Msk (0x1UL << GOTGCTL_CIDSTS_Pos) // 0x00010000 */
345#define GOTGCTL_CIDSTS GOTGCTL_CIDSTS_Msk // Connector ID status */
346#define GOTGCTL_DBCT_Pos (17U)
347#define GOTGCTL_DBCT_Msk (0x1UL << GOTGCTL_DBCT_Pos) // 0x00020000 */
348#define GOTGCTL_DBCT GOTGCTL_DBCT_Msk // Long/short debounce time */
349#define GOTGCTL_ASVLD_Pos (18U)
350#define GOTGCTL_ASVLD_Msk (0x1UL << GOTGCTL_ASVLD_Pos) // 0x00040000 */
351#define GOTGCTL_ASVLD GOTGCTL_ASVLD_Msk // A-session valid */
352#define GOTGCTL_BSESVLD_Pos (19U)
353#define GOTGCTL_BSESVLD_Msk (0x1UL << GOTGCTL_BSESVLD_Pos) // 0x00080000 */
354#define GOTGCTL_BSESVLD GOTGCTL_BSESVLD_Msk // B-session valid */
355#define GOTGCTL_OTGVER_Pos (20U)
356#define GOTGCTL_OTGVER_Msk (0x1UL << GOTGCTL_OTGVER_Pos) // 0x00100000 */
357#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk // OTG version */
358
359/******************** Bit definition for HCFG register ********************/
360#define HCFG_FSLSPCS_Pos (0U)
361#define HCFG_FSLSPCS_Msk (0x3UL << HCFG_FSLSPCS_Pos) // 0x00000003 */
362#define HCFG_FSLSPCS HCFG_FSLSPCS_Msk // FS/LS PHY clock select */
363#define HCFG_FSLSPCS_0 (0x1UL << HCFG_FSLSPCS_Pos) // 0x00000001 */
364#define HCFG_FSLSPCS_1 (0x2UL << HCFG_FSLSPCS_Pos) // 0x00000002 */
365#define HCFG_FSLSS_Pos (2U)
366#define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) // 0x00000004 */
367#define HCFG_FSLSS HCFG_FSLSS_Msk // FS- and LS-only support */
368
369/******************** Bit definition for PCGCR register ********************/
370#define PCGCR_STPPCLK_Pos (0U)
371#define PCGCR_STPPCLK_Msk (0x1UL << PCGCR_STPPCLK_Pos) // 0x00000001 */
372#define PCGCR_STPPCLK PCGCR_STPPCLK_Msk // Stop PHY clock */
373#define PCGCR_GATEHCLK_Pos (1U)
374#define PCGCR_GATEHCLK_Msk (0x1UL << PCGCR_GATEHCLK_Pos) // 0x00000002 */
375#define PCGCR_GATEHCLK PCGCR_GATEHCLK_Msk // Gate HCLK */
376#define PCGCR_PHYSUSP_Pos (4U)
377#define PCGCR_PHYSUSP_Msk (0x1UL << PCGCR_PHYSUSP_Pos) // 0x00000010 */
378#define PCGCR_PHYSUSP PCGCR_PHYSUSP_Msk // PHY suspended */
379
380/******************** Bit definition for GOTGINT register ********************/
381#define GOTGINT_SEDET_Pos (2U)
382#define GOTGINT_SEDET_Msk (0x1UL << GOTGINT_SEDET_Pos) // 0x00000004 */
383#define GOTGINT_SEDET GOTGINT_SEDET_Msk // Session end detected */
384#define GOTGINT_SRSSCHG_Pos (8U)
385#define GOTGINT_SRSSCHG_Msk (0x1UL << GOTGINT_SRSSCHG_Pos) // 0x00000100 */
386#define GOTGINT_SRSSCHG GOTGINT_SRSSCHG_Msk // Session request success status change */
387#define GOTGINT_HNSSCHG_Pos (9U)
388#define GOTGINT_HNSSCHG_Msk (0x1UL << GOTGINT_HNSSCHG_Pos) // 0x00000200 */
389#define GOTGINT_HNSSCHG GOTGINT_HNSSCHG_Msk // Host negotiation success status change */
390#define GOTGINT_HNGDET_Pos (17U)
391#define GOTGINT_HNGDET_Msk (0x1UL << GOTGINT_HNGDET_Pos) // 0x00020000 */
392#define GOTGINT_HNGDET GOTGINT_HNGDET_Msk // Host negotiation detected */
393#define GOTGINT_ADTOCHG_Pos (18U)
394#define GOTGINT_ADTOCHG_Msk (0x1UL << GOTGINT_ADTOCHG_Pos) // 0x00040000 */
395#define GOTGINT_ADTOCHG GOTGINT_ADTOCHG_Msk // A-device timeout change */
396#define GOTGINT_DBCDNE_Pos (19U)
397#define GOTGINT_DBCDNE_Msk (0x1UL << GOTGINT_DBCDNE_Pos) // 0x00080000 */
398#define GOTGINT_DBCDNE GOTGINT_DBCDNE_Msk // Debounce done */
399#define GOTGINT_IDCHNG_Pos (20U)
400#define GOTGINT_IDCHNG_Msk (0x1UL << GOTGINT_IDCHNG_Pos) // 0x00100000 */
401#define GOTGINT_IDCHNG GOTGINT_IDCHNG_Msk // Change in ID pin input value */
402
403/******************** Bit definition for DCFG register ********************/
404#define DCFG_DSPD_Pos (0U)
405#define DCFG_DSPD_Msk (0x3UL << DCFG_DSPD_Pos) // 0x00000003
406#define DCFG_DSPD_HS 0 // Highspeed
407#define DCFG_DSPD_FS_HSPHY 1 // Fullspeed on HS PHY
408#define DCFG_DSPD_LS 2 // Lowspeed
409#define DCFG_DSPD_FS 3 // Fullspeed on FS PHY
410
411#define DCFG_NZLSOHSK_Pos (2U)
412#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) // 0x00000004 */
413#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk // Nonzero-length status OUT handshake */
414
415#define DCFG_DAD_Pos (4U)
416#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) // 0x000007F0 */
417#define DCFG_DAD DCFG_DAD_Msk // Device address */
418#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) // 0x00000010 */
419#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) // 0x00000020 */
420#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) // 0x00000040 */
421#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) // 0x00000080 */
422#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) // 0x00000100 */
423#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) // 0x00000200 */
424#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) // 0x00000400 */
425
426#define DCFG_PFIVL_Pos (11U)
427#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) // 0x00001800 */
428#define DCFG_PFIVL DCFG_PFIVL_Msk // Periodic (micro)frame interval */
429#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800 */
430#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000 */
431
432#define DCFG_XCVRDLY_Pos (14U)
433#define DCFG_XCVRDLY_Msk (0x1UL << DCFG_XCVRDLY_Pos)
434#define DCFG_XCVRDLY DCFG_XCVRDLY_Msk // Enables delay between xcvr_sel and txvalid during device chirp
435
436#define DCFG_PERSCHIVL_Pos (24U)
437#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000 */
438#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval */
439#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) // 0x01000000 */
440#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) // 0x02000000 */
441
442/******************** Bit definition for DCTL register ********************/
443#define DCTL_RWUSIG_Pos (0U)
444#define DCTL_RWUSIG_Msk (0x1UL << DCTL_RWUSIG_Pos) // 0x00000001 */
445#define DCTL_RWUSIG DCTL_RWUSIG_Msk // Remote wakeup signaling */
446#define DCTL_SDIS_Pos (1U)
447#define DCTL_SDIS_Msk (0x1UL << DCTL_SDIS_Pos) // 0x00000002 */
448#define DCTL_SDIS DCTL_SDIS_Msk // Soft disconnect */
449#define DCTL_GINSTS_Pos (2U)
450#define DCTL_GINSTS_Msk (0x1UL << DCTL_GINSTS_Pos) // 0x00000004 */
451#define DCTL_GINSTS DCTL_GINSTS_Msk // Global IN NAK status */
452#define DCTL_GONSTS_Pos (3U)
453#define DCTL_GONSTS_Msk (0x1UL << DCTL_GONSTS_Pos) // 0x00000008 */
454#define DCTL_GONSTS DCTL_GONSTS_Msk // Global OUT NAK status */
455
456#define DCTL_TCTL_Pos (4U)
457#define DCTL_TCTL_Msk (0x7UL << DCTL_TCTL_Pos) // 0x00000070 */
458#define DCTL_TCTL DCTL_TCTL_Msk // Test control */
459#define DCTL_TCTL_0 (0x1UL << DCTL_TCTL_Pos) // 0x00000010 */
460#define DCTL_TCTL_1 (0x2UL << DCTL_TCTL_Pos) // 0x00000020 */
461#define DCTL_TCTL_2 (0x4UL << DCTL_TCTL_Pos) // 0x00000040 */
462#define DCTL_SGINAK_Pos (7U)
463#define DCTL_SGINAK_Msk (0x1UL << DCTL_SGINAK_Pos) // 0x00000080 */
464#define DCTL_SGINAK DCTL_SGINAK_Msk // Set global IN NAK */
465#define DCTL_CGINAK_Pos (8U)
466#define DCTL_CGINAK_Msk (0x1UL << DCTL_CGINAK_Pos) // 0x00000100 */
467#define DCTL_CGINAK DCTL_CGINAK_Msk // Clear global IN NAK */
468#define DCTL_SGONAK_Pos (9U)
469#define DCTL_SGONAK_Msk (0x1UL << DCTL_SGONAK_Pos) // 0x00000200 */
470#define DCTL_SGONAK DCTL_SGONAK_Msk // Set global OUT NAK */
471#define DCTL_CGONAK_Pos (10U)
472#define DCTL_CGONAK_Msk (0x1UL << DCTL_CGONAK_Pos) // 0x00000400 */
473#define DCTL_CGONAK DCTL_CGONAK_Msk // Clear global OUT NAK */
474#define DCTL_POPRGDNE_Pos (11U)
475#define DCTL_POPRGDNE_Msk (0x1UL << DCTL_POPRGDNE_Pos) // 0x00000800 */
476#define DCTL_POPRGDNE DCTL_POPRGDNE_Msk // Power-on programming done */
477
478/******************** Bit definition for HFIR register ********************/
479#define HFIR_FRIVL_Pos (0U)
480#define HFIR_FRIVL_Msk (0xFFFFUL << HFIR_FRIVL_Pos) // 0x0000FFFF */
481#define HFIR_FRIVL HFIR_FRIVL_Msk // Frame interval */
482
483/******************** Bit definition for HFNUM register ********************/
484#define HFNUM_FRNUM_Pos (0U)
485#define HFNUM_FRNUM_Msk (0xFFFFUL << HFNUM_FRNUM_Pos) // 0x0000FFFF */
486#define HFNUM_FRNUM HFNUM_FRNUM_Msk // Frame number */
487#define HFNUM_FTREM_Pos (16U)
488#define HFNUM_FTREM_Msk (0xFFFFUL << HFNUM_FTREM_Pos) // 0xFFFF0000 */
489#define HFNUM_FTREM HFNUM_FTREM_Msk // Frame time remaining */
490
491/******************** Bit definition for DSTS register ********************/
492#define DSTS_SUSPSTS_Pos (0U)
493#define DSTS_SUSPSTS_Msk (0x1UL << DSTS_SUSPSTS_Pos) // 0x00000001 */
494#define DSTS_SUSPSTS DSTS_SUSPSTS_Msk // Suspend status */
495#define DSTS_ENUMSPD_Pos (1U)
496#define DSTS_ENUMSPD_Msk (0x3UL << DSTS_ENUMSPD_Pos) // 0x00000006 */
497#define DSTS_ENUMSPD DSTS_ENUMSPD_Msk // Enumerated speed */
498#define DSTS_ENUMSPD_HS 0 // Highspeed
499#define DSTS_ENUMSPD_FS_HSPHY 1 // Fullspeed on HS PHY
500#define DSTS_ENUMSPD_LS 2 // Lowspeed
501#define DSTS_ENUMSPD_FS 3 // Fullspeed on FS PHY
502
503
504#define DSTS_EERR_Pos (3U)
505#define DSTS_EERR_Msk (0x1UL << DSTS_EERR_Pos) // 0x00000008 */
506#define DSTS_EERR DSTS_EERR_Msk // Erratic error */
507#define DSTS_FNSOF_Pos (8U)
508#define DSTS_FNSOF_Msk (0x3FFFUL << DSTS_FNSOF_Pos) // 0x003FFF00 */
509#define DSTS_FNSOF DSTS_FNSOF_Msk // Frame number of the received SOF */
510
511/******************** Bit definition for GAHBCFG register ********************/
512#define GAHBCFG_GINT_Pos (0U)
513#define GAHBCFG_GINT_Msk (0x1UL << GAHBCFG_GINT_Pos) // 0x00000001 */
514#define GAHBCFG_GINT GAHBCFG_GINT_Msk // Global interrupt mask */
515#define GAHBCFG_HBSTLEN_Pos (1U)
516#define GAHBCFG_HBSTLEN_Msk (0xFUL << GAHBCFG_HBSTLEN_Pos) // 0x0000001E */
517#define GAHBCFG_HBSTLEN GAHBCFG_HBSTLEN_Msk // Burst length/type */
518#define GAHBCFG_HBSTLEN_0 (0x0UL << GAHBCFG_HBSTLEN_Pos) // Single */
519#define GAHBCFG_HBSTLEN_1 (0x1UL << GAHBCFG_HBSTLEN_Pos) // INCR */
520#define GAHBCFG_HBSTLEN_2 (0x3UL << GAHBCFG_HBSTLEN_Pos) // INCR4 */
521#define GAHBCFG_HBSTLEN_3 (0x5UL << GAHBCFG_HBSTLEN_Pos) // INCR8 */
522#define GAHBCFG_HBSTLEN_4 (0x7UL << GAHBCFG_HBSTLEN_Pos) // INCR16 */
523#define GAHBCFG_DMAEN_Pos (5U)
524#define GAHBCFG_DMAEN_Msk (0x1UL << GAHBCFG_DMAEN_Pos) // 0x00000020 */
525#define GAHBCFG_DMAEN GAHBCFG_DMAEN_Msk // DMA enable */
526#define GAHBCFG_TXFELVL_Pos (7U)
527#define GAHBCFG_TXFELVL_Msk (0x1UL << GAHBCFG_TXFELVL_Pos) // 0x00000080 */
528#define GAHBCFG_TXFELVL GAHBCFG_TXFELVL_Msk // TxFIFO empty level */
529#define GAHBCFG_PTXFELVL_Pos (8U)
530#define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) // 0x00000100 */
531#define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk // Periodic TxFIFO empty level */
532
533#define GSNPSID_ID_MASK TU_GENMASK(31, 16)
534
535/******************** Bit definition for GUSBCFG register ********************/
536#define GUSBCFG_TOCAL_Pos (0U)
537#define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) // 0x00000007 */
538#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // FS timeout calibration */
539#define GUSBCFG_PHYIF16_Pos (3U)
540#define GUSBCFG_PHYIF16_Msk (0x1UL << GUSBCFG_PHYIF16_Pos) // 0x00000008 */
541#define GUSBCFG_PHYIF16 GUSBCFG_PHYIF16_Msk // PHY Interface (PHYIf) */
542#define GUSBCFG_ULPI_UTMI_SEL_Pos (4U)
543#define GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) // 0x00000010 */
544#define GUSBCFG_ULPI_UTMI_SEL GUSBCFG_ULPI_UTMI_SEL_Msk // ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
545#define GUSBCFG_PHYSEL_Pos (6U)
546#define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) // 0x00000040 */
547#define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
548#define GUSBCFG_DDRSEL TU_BIT(7) // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
549#define GUSBCFG_SRPCAP_Pos (8U)
550#define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) // 0x00000100 */
551#define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk // SRP-capable */
552#define GUSBCFG_HNPCAP_Pos (9U)
553#define GUSBCFG_HNPCAP_Msk (0x1UL << GUSBCFG_HNPCAP_Pos) // 0x00000200 */
554#define GUSBCFG_HNPCAP GUSBCFG_HNPCAP_Msk // HNP-capable */
555#define GUSBCFG_TRDT_Pos (10U)
556#define GUSBCFG_TRDT_Msk (0xFUL << GUSBCFG_TRDT_Pos) // 0x00003C00 */
557#define GUSBCFG_TRDT GUSBCFG_TRDT_Msk // USB turnaround time */
558#define GUSBCFG_PHYLPCS_Pos (15U)
559#define GUSBCFG_PHYLPCS_Msk (0x1UL << GUSBCFG_PHYLPCS_Pos) // 0x00008000 */
560#define GUSBCFG_PHYLPCS GUSBCFG_PHYLPCS_Msk // PHY Low-power clock select */
561#define GUSBCFG_ULPIFSLS_Pos (17U)
562#define GUSBCFG_ULPIFSLS_Msk (0x1UL << GUSBCFG_ULPIFSLS_Pos) // 0x00020000 */
563#define GUSBCFG_ULPIFSLS GUSBCFG_ULPIFSLS_Msk // ULPI FS/LS select */
564#define GUSBCFG_ULPIAR_Pos (18U)
565#define GUSBCFG_ULPIAR_Msk (0x1UL << GUSBCFG_ULPIAR_Pos) // 0x00040000 */
566#define GUSBCFG_ULPIAR GUSBCFG_ULPIAR_Msk // ULPI Auto-resume */
567#define GUSBCFG_ULPICSM_Pos (19U)
568#define GUSBCFG_ULPICSM_Msk (0x1UL << GUSBCFG_ULPICSM_Pos) // 0x00080000 */
569#define GUSBCFG_ULPICSM GUSBCFG_ULPICSM_Msk // ULPI Clock SuspendM */
570#define GUSBCFG_ULPIEVBUSD_Pos (20U)
571#define GUSBCFG_ULPIEVBUSD_Msk (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) // 0x00100000 */
572#define GUSBCFG_ULPIEVBUSD GUSBCFG_ULPIEVBUSD_Msk // ULPI External VBUS Drive */
573#define GUSBCFG_ULPIEVBUSI_Pos (21U)
574#define GUSBCFG_ULPIEVBUSI_Msk (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) // 0x00200000 */
575#define GUSBCFG_ULPIEVBUSI GUSBCFG_ULPIEVBUSI_Msk // ULPI external VBUS indicator */
576#define GUSBCFG_TSDPS_Pos (22U)
577#define GUSBCFG_TSDPS_Msk (0x1UL << GUSBCFG_TSDPS_Pos) // 0x00400000 */
578#define GUSBCFG_TSDPS GUSBCFG_TSDPS_Msk // TermSel DLine pulsing selection */
579#define GUSBCFG_PCCI_Pos (23U)
580#define GUSBCFG_PCCI_Msk (0x1UL << GUSBCFG_PCCI_Pos) // 0x00800000 */
581#define GUSBCFG_PCCI GUSBCFG_PCCI_Msk // Indicator complement */
582#define GUSBCFG_PTCI_Pos (24U)
583#define GUSBCFG_PTCI_Msk (0x1UL << GUSBCFG_PTCI_Pos) // 0x01000000 */
584#define GUSBCFG_PTCI GUSBCFG_PTCI_Msk // Indicator pass through */
585#define GUSBCFG_ULPIIPD_Pos (25U)
586#define GUSBCFG_ULPIIPD_Msk (0x1UL << GUSBCFG_ULPIIPD_Pos) // 0x02000000 */
587#define GUSBCFG_ULPIIPD GUSBCFG_ULPIIPD_Msk // ULPI interface protect disable */
588#define GUSBCFG_FHMOD_Pos (29U)
589#define GUSBCFG_FHMOD_Msk (0x1UL << GUSBCFG_FHMOD_Pos) // 0x20000000 */
590#define GUSBCFG_FHMOD GUSBCFG_FHMOD_Msk // Forced host mode */
591#define GUSBCFG_FDMOD_Pos (30U)
592#define GUSBCFG_FDMOD_Msk (0x1UL << GUSBCFG_FDMOD_Pos) // 0x40000000 */
593#define GUSBCFG_FDMOD GUSBCFG_FDMOD_Msk // Forced peripheral mode */
594#define GUSBCFG_CTXPKT_Pos (31U)
595#define GUSBCFG_CTXPKT_Msk (0x1UL << GUSBCFG_CTXPKT_Pos) // 0x80000000 */
596#define GUSBCFG_CTXPKT GUSBCFG_CTXPKT_Msk // Corrupt Tx packet */
597
598/******************** Bit definition for GRSTCTL register ********************/
599#define GRSTCTL_CSRST_Pos (0U)
600#define GRSTCTL_CSRST_Msk (0x1UL << GRSTCTL_CSRST_Pos) // 0x00000001 */
601#define GRSTCTL_CSRST GRSTCTL_CSRST_Msk // Core soft reset */
602#define GRSTCTL_HSRST_Pos (1U)
603#define GRSTCTL_HSRST_Msk (0x1UL << GRSTCTL_HSRST_Pos) // 0x00000002 */
604#define GRSTCTL_HSRST GRSTCTL_HSRST_Msk // HCLK soft reset */
605#define GRSTCTL_FCRST_Pos (2U)
606#define GRSTCTL_FCRST_Msk (0x1UL << GRSTCTL_FCRST_Pos) // 0x00000004 */
607#define GRSTCTL_FCRST GRSTCTL_FCRST_Msk // Host frame counter reset */
608#define GRSTCTL_RXFFLSH_Pos (4U)
609#define GRSTCTL_RXFFLSH_Msk (0x1UL << GRSTCTL_RXFFLSH_Pos) // 0x00000010 */
610#define GRSTCTL_RXFFLSH GRSTCTL_RXFFLSH_Msk // RxFIFO flush */
611#define GRSTCTL_TXFFLSH_Pos (5U)
612#define GRSTCTL_TXFFLSH_Msk (0x1UL << GRSTCTL_TXFFLSH_Pos) // 0x00000020 */
613#define GRSTCTL_TXFFLSH GRSTCTL_TXFFLSH_Msk // TxFIFO flush */
614#define GRSTCTL_TXFNUM_Pos (6U)
615#define GRSTCTL_TXFNUM_Msk (0x1FUL << GRSTCTL_TXFNUM_Pos) // 0x000007C0 */
616#define GRSTCTL_TXFNUM GRSTCTL_TXFNUM_Msk // TxFIFO number */
617#define GRSTCTL_TXFNUM_0 (0x01UL << GRSTCTL_TXFNUM_Pos) // 0x00000040 */
618#define GRSTCTL_TXFNUM_1 (0x02UL << GRSTCTL_TXFNUM_Pos) // 0x00000080 */
619#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) // 0x00000100 */
620#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) // 0x00000200 */
621#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) // 0x00000400 */
622#define GRSTCTL_CSFTRST_DONE_Pos (29)
623#define GRSTCTL_CSFTRST_DONE (1u << GRSTCTL_CSFTRST_DONE_Pos) // Reset Done, only available from v4.20a
624#define GRSTCTL_DMAREQ_Pos (30U)
625#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) // 0x40000000 */
626#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk // DMA request signal */
627#define GRSTCTL_AHBIDL_Pos (31U)
628#define GRSTCTL_AHBIDL_Msk (0x1UL << GRSTCTL_AHBIDL_Pos) // 0x80000000 */
629#define GRSTCTL_AHBIDL GRSTCTL_AHBIDL_Msk // AHB master idle */
630
631/******************** Bit definition for DIEPMSK register ********************/
632#define DIEPMSK_XFRCM_Pos (0U)
633#define DIEPMSK_XFRCM_Msk (0x1UL << DIEPMSK_XFRCM_Pos) // 0x00000001 */
634#define DIEPMSK_XFRCM DIEPMSK_XFRCM_Msk // Transfer completed interrupt mask */
635#define DIEPMSK_EPDM_Pos (1U)
636#define DIEPMSK_EPDM_Msk (0x1UL << DIEPMSK_EPDM_Pos) // 0x00000002 */
637#define DIEPMSK_EPDM DIEPMSK_EPDM_Msk // Endpoint disabled interrupt mask */
638#define DIEPMSK_TOM_Pos (3U)
639#define DIEPMSK_TOM_Msk (0x1UL << DIEPMSK_TOM_Pos) // 0x00000008 */
640#define DIEPMSK_TOM DIEPMSK_TOM_Msk // Timeout condition mask (nonisochronous endpoints) */
641#define DIEPMSK_ITTXFEMSK_Pos (4U)
642#define DIEPMSK_ITTXFEMSK_Msk (0x1UL << DIEPMSK_ITTXFEMSK_Pos) // 0x00000010 */
643#define DIEPMSK_ITTXFEMSK DIEPMSK_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask */
644#define DIEPMSK_INEPNMM_Pos (5U)
645#define DIEPMSK_INEPNMM_Msk (0x1UL << DIEPMSK_INEPNMM_Pos) // 0x00000020 */
646#define DIEPMSK_INEPNMM DIEPMSK_INEPNMM_Msk // IN token received with EP mismatch mask */
647#define DIEPMSK_INEPNEM_Pos (6U)
648#define DIEPMSK_INEPNEM_Msk (0x1UL << DIEPMSK_INEPNEM_Pos) // 0x00000040 */
649#define DIEPMSK_INEPNEM DIEPMSK_INEPNEM_Msk // IN endpoint NAK effective mask */
650#define DIEPMSK_TXFURM_Pos (8U)
651#define DIEPMSK_TXFURM_Msk (0x1UL << DIEPMSK_TXFURM_Pos) // 0x00000100 */
652#define DIEPMSK_TXFURM DIEPMSK_TXFURM_Msk // FIFO underrun mask */
653#define DIEPMSK_BIM_Pos (9U)
654#define DIEPMSK_BIM_Msk (0x1UL << DIEPMSK_BIM_Pos) // 0x00000200 */
655#define DIEPMSK_BIM DIEPMSK_BIM_Msk // BNA interrupt mask */
656
657/******************** Bit definition for HPTXSTS register ********************/
658#define HPTXSTS_PTXFSAVL_Pos (0U)
659#define HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) // 0x0000FFFF */
660#define HPTXSTS_PTXFSAVL HPTXSTS_PTXFSAVL_Msk // Periodic transmit data FIFO space available */
661#define HPTXSTS_PTXQSAV_Pos (16U)
662#define HPTXSTS_PTXQSAV_Msk (0xFFUL << HPTXSTS_PTXQSAV_Pos) // 0x00FF0000 */
663#define HPTXSTS_PTXQSAV HPTXSTS_PTXQSAV_Msk // Periodic transmit request queue space available */
664#define HPTXSTS_PTXQSAV_0 (0x01UL << HPTXSTS_PTXQSAV_Pos) // 0x00010000 */
665#define HPTXSTS_PTXQSAV_1 (0x02UL << HPTXSTS_PTXQSAV_Pos) // 0x00020000 */
666#define HPTXSTS_PTXQSAV_2 (0x04UL << HPTXSTS_PTXQSAV_Pos) // 0x00040000 */
667#define HPTXSTS_PTXQSAV_3 (0x08UL << HPTXSTS_PTXQSAV_Pos) // 0x00080000 */
668#define HPTXSTS_PTXQSAV_4 (0x10UL << HPTXSTS_PTXQSAV_Pos) // 0x00100000 */
669#define HPTXSTS_PTXQSAV_5 (0x20UL << HPTXSTS_PTXQSAV_Pos) // 0x00200000 */
670#define HPTXSTS_PTXQSAV_6 (0x40UL << HPTXSTS_PTXQSAV_Pos) // 0x00400000 */
671#define HPTXSTS_PTXQSAV_7 (0x80UL << HPTXSTS_PTXQSAV_Pos) // 0x00800000 */
672
673#define HPTXSTS_PTXQTOP_Pos (24U)
674#define HPTXSTS_PTXQTOP_Msk (0xFFUL << HPTXSTS_PTXQTOP_Pos) // 0xFF000000 */
675#define HPTXSTS_PTXQTOP HPTXSTS_PTXQTOP_Msk // Top of the periodic transmit request queue */
676#define HPTXSTS_PTXQTOP_0 (0x01UL << HPTXSTS_PTXQTOP_Pos) // 0x01000000 */
677#define HPTXSTS_PTXQTOP_1 (0x02UL << HPTXSTS_PTXQTOP_Pos) // 0x02000000 */
678#define HPTXSTS_PTXQTOP_2 (0x04UL << HPTXSTS_PTXQTOP_Pos) // 0x04000000 */
679#define HPTXSTS_PTXQTOP_3 (0x08UL << HPTXSTS_PTXQTOP_Pos) // 0x08000000 */
680#define HPTXSTS_PTXQTOP_4 (0x10UL << HPTXSTS_PTXQTOP_Pos) // 0x10000000 */
681#define HPTXSTS_PTXQTOP_5 (0x20UL << HPTXSTS_PTXQTOP_Pos) // 0x20000000 */
682#define HPTXSTS_PTXQTOP_6 (0x40UL << HPTXSTS_PTXQTOP_Pos) // 0x40000000 */
683#define HPTXSTS_PTXQTOP_7 (0x80UL << HPTXSTS_PTXQTOP_Pos) // 0x80000000 */
684
685/******************** Bit definition for HAINT register ********************/
686#define HAINT_HAINT_Pos (0U)
687#define HAINT_HAINT_Msk (0xFFFFUL << HAINT_HAINT_Pos) // 0x0000FFFF */
688#define HAINT_HAINT HAINT_HAINT_Msk // Channel interrupts */
689
690/******************** Bit definition for DOEPMSK register ********************/
691#define DOEPMSK_XFRCM_Pos (0U)
692#define DOEPMSK_XFRCM_Msk (0x1UL << DOEPMSK_XFRCM_Pos) // 0x00000001 */
693#define DOEPMSK_XFRCM DOEPMSK_XFRCM_Msk // Transfer completed interrupt mask */
694#define DOEPMSK_EPDM_Pos (1U)
695#define DOEPMSK_EPDM_Msk (0x1UL << DOEPMSK_EPDM_Pos) // 0x00000002 */
696#define DOEPMSK_EPDM DOEPMSK_EPDM_Msk // Endpoint disabled interrupt mask */
697#define DOEPMSK_AHBERRM_Pos (2U)
698#define DOEPMSK_AHBERRM_Msk (0x1UL << DOEPMSK_AHBERRM_Pos) // 0x00000004 */
699#define DOEPMSK_AHBERRM DOEPMSK_AHBERRM_Msk // OUT transaction AHB Error interrupt mask */
700#define DOEPMSK_STUPM_Pos (3U)
701#define DOEPMSK_STUPM_Msk (0x1UL << DOEPMSK_STUPM_Pos) // 0x00000008 */
702#define DOEPMSK_STUPM DOEPMSK_STUPM_Msk // SETUP phase done mask */
703#define DOEPMSK_OTEPDM_Pos (4U)
704#define DOEPMSK_OTEPDM_Msk (0x1UL << DOEPMSK_OTEPDM_Pos) // 0x00000010 */
705#define DOEPMSK_OTEPDM DOEPMSK_OTEPDM_Msk // OUT token received when endpoint disabled mask */
706#define DOEPMSK_OTEPSPRM_Pos (5U)
707#define DOEPMSK_OTEPSPRM_Msk (0x1UL << DOEPMSK_OTEPSPRM_Pos) // 0x00000020 */
708#define DOEPMSK_OTEPSPRM DOEPMSK_OTEPSPRM_Msk // Status Phase Received mask */
709#define DOEPMSK_B2BSTUP_Pos (6U)
710#define DOEPMSK_B2BSTUP_Msk (0x1UL << DOEPMSK_B2BSTUP_Pos) // 0x00000040 */
711#define DOEPMSK_B2BSTUP DOEPMSK_B2BSTUP_Msk // Back-to-back SETUP packets received mask */
712#define DOEPMSK_OPEM_Pos (8U)
713#define DOEPMSK_OPEM_Msk (0x1UL << DOEPMSK_OPEM_Pos) // 0x00000100 */
714#define DOEPMSK_OPEM DOEPMSK_OPEM_Msk // OUT packet error mask */
715#define DOEPMSK_BOIM_Pos (9U)
716#define DOEPMSK_BOIM_Msk (0x1UL << DOEPMSK_BOIM_Pos) // 0x00000200 */
717#define DOEPMSK_BOIM DOEPMSK_BOIM_Msk // BNA interrupt mask */
718#define DOEPMSK_BERRM_Pos (12U)
719#define DOEPMSK_BERRM_Msk (0x1UL << DOEPMSK_BERRM_Pos) // 0x00001000 */
720#define DOEPMSK_BERRM DOEPMSK_BERRM_Msk // Babble error interrupt mask */
721#define DOEPMSK_NAKM_Pos (13U)
722#define DOEPMSK_NAKM_Msk (0x1UL << DOEPMSK_NAKM_Pos) // 0x00002000 */
723#define DOEPMSK_NAKM DOEPMSK_NAKM_Msk // OUT Packet NAK interrupt mask */
724#define DOEPMSK_NYETM_Pos (14U)
725#define DOEPMSK_NYETM_Msk (0x1UL << DOEPMSK_NYETM_Pos) // 0x00004000 */
726#define DOEPMSK_NYETM DOEPMSK_NYETM_Msk // NYET interrupt mask */
727
728/******************** Bit definition for GINTSTS register ********************/
729#define GINTSTS_CMOD_Pos (0U)
730#define GINTSTS_CMOD_Msk (0x1UL << GINTSTS_CMOD_Pos) // 0x00000001 */
731#define GINTSTS_CMOD GINTSTS_CMOD_Msk // Current mode of operation */
732#define GINTSTS_MMIS_Pos (1U)
733#define GINTSTS_MMIS_Msk (0x1UL << GINTSTS_MMIS_Pos) // 0x00000002 */
734#define GINTSTS_MMIS GINTSTS_MMIS_Msk // Mode mismatch interrupt */
735#define GINTSTS_OTGINT_Pos (2U)
736#define GINTSTS_OTGINT_Msk (0x1UL << GINTSTS_OTGINT_Pos) // 0x00000004 */
737#define GINTSTS_OTGINT GINTSTS_OTGINT_Msk // OTG interrupt */
738#define GINTSTS_SOF_Pos (3U)
739#define GINTSTS_SOF_Msk (0x1UL << GINTSTS_SOF_Pos) // 0x00000008 */
740#define GINTSTS_SOF GINTSTS_SOF_Msk // Start of frame */
741#define GINTSTS_RXFLVL_Pos (4U)
742#define GINTSTS_RXFLVL_Msk (0x1UL << GINTSTS_RXFLVL_Pos) // 0x00000010 */
743#define GINTSTS_RXFLVL GINTSTS_RXFLVL_Msk // RxFIFO nonempty */
744#define GINTSTS_NPTXFE_Pos (5U)
745#define GINTSTS_NPTXFE_Msk (0x1UL << GINTSTS_NPTXFE_Pos) // 0x00000020 */
746#define GINTSTS_NPTXFE GINTSTS_NPTXFE_Msk // Nonperiodic TxFIFO empty */
747#define GINTSTS_GINAKEFF_Pos (6U)
748#define GINTSTS_GINAKEFF_Msk (0x1UL << GINTSTS_GINAKEFF_Pos) // 0x00000040 */
749#define GINTSTS_GINAKEFF GINTSTS_GINAKEFF_Msk // Global IN nonperiodic NAK effective */
750#define GINTSTS_BOUTNAKEFF_Pos (7U)
751#define GINTSTS_BOUTNAKEFF_Msk (0x1UL << GINTSTS_BOUTNAKEFF_Pos) // 0x00000080 */
752#define GINTSTS_BOUTNAKEFF GINTSTS_BOUTNAKEFF_Msk // Global OUT NAK effective */
753#define GINTSTS_ESUSP_Pos (10U)
754#define GINTSTS_ESUSP_Msk (0x1UL << GINTSTS_ESUSP_Pos) // 0x00000400 */
755#define GINTSTS_ESUSP GINTSTS_ESUSP_Msk // Early suspend */
756#define GINTSTS_USBSUSP_Pos (11U)
757#define GINTSTS_USBSUSP_Msk (0x1UL << GINTSTS_USBSUSP_Pos) // 0x00000800 */
758#define GINTSTS_USBSUSP GINTSTS_USBSUSP_Msk // USB suspend */
759#define GINTSTS_USBRST_Pos (12U)
760#define GINTSTS_USBRST_Msk (0x1UL << GINTSTS_USBRST_Pos) // 0x00001000 */
761#define GINTSTS_USBRST GINTSTS_USBRST_Msk // USB reset */
762#define GINTSTS_ENUMDNE_Pos (13U)
763#define GINTSTS_ENUMDNE_Msk (0x1UL << GINTSTS_ENUMDNE_Pos) // 0x00002000 */
764#define GINTSTS_ENUMDNE GINTSTS_ENUMDNE_Msk // Enumeration done */
765#define GINTSTS_ISOODRP_Pos (14U)
766#define GINTSTS_ISOODRP_Msk (0x1UL << GINTSTS_ISOODRP_Pos) // 0x00004000 */
767#define GINTSTS_ISOODRP GINTSTS_ISOODRP_Msk // Isochronous OUT packet dropped interrupt */
768#define GINTSTS_EOPF_Pos (15U)
769#define GINTSTS_EOPF_Msk (0x1UL << GINTSTS_EOPF_Pos) // 0x00008000 */
770#define GINTSTS_EOPF GINTSTS_EOPF_Msk // End of periodic frame interrupt */
771#define GINTSTS_IEPINT_Pos (18U)
772#define GINTSTS_IEPINT_Msk (0x1UL << GINTSTS_IEPINT_Pos) // 0x00040000 */
773#define GINTSTS_IEPINT GINTSTS_IEPINT_Msk // IN endpoint interrupt */
774#define GINTSTS_OEPINT_Pos (19U)
775#define GINTSTS_OEPINT_Msk (0x1UL << GINTSTS_OEPINT_Pos) // 0x00080000 */
776#define GINTSTS_OEPINT GINTSTS_OEPINT_Msk // OUT endpoint interrupt */
777#define GINTSTS_IISOIXFR_Pos (20U)
778#define GINTSTS_IISOIXFR_Msk (0x1UL << GINTSTS_IISOIXFR_Pos) // 0x00100000 */
779#define GINTSTS_IISOIXFR GINTSTS_IISOIXFR_Msk // Incomplete isochronous IN transfer */
780#define GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
781#define GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) // 0x00200000 */
782#define GINTSTS_PXFR_INCOMPISOOUT GINTSTS_PXFR_INCOMPISOOUT_Msk // Incomplete periodic transfer */
783#define GINTSTS_DATAFSUSP_Pos (22U)
784#define GINTSTS_DATAFSUSP_Msk (0x1UL << GINTSTS_DATAFSUSP_Pos) // 0x00400000 */
785#define GINTSTS_DATAFSUSP GINTSTS_DATAFSUSP_Msk // Data fetch suspended */
786#define GINTSTS_RSTDET_Pos (23U)
787#define GINTSTS_RSTDET_Msk (0x1UL << GINTSTS_RSTDET_Pos) // 0x00800000 */
788#define GINTSTS_RSTDET GINTSTS_RSTDET_Msk // Reset detected interrupt */
789#define GINTSTS_HPRTINT_Pos (24U)
790#define GINTSTS_HPRTINT_Msk (0x1UL << GINTSTS_HPRTINT_Pos) // 0x01000000 */
791#define GINTSTS_HPRTINT GINTSTS_HPRTINT_Msk // Host port interrupt */
792#define GINTSTS_HCINT_Pos (25U)
793#define GINTSTS_HCINT_Msk (0x1UL << GINTSTS_HCINT_Pos) // 0x02000000 */
794#define GINTSTS_HCINT GINTSTS_HCINT_Msk // Host channels interrupt */
795#define GINTSTS_PTXFE_Pos (26U)
796#define GINTSTS_PTXFE_Msk (0x1UL << GINTSTS_PTXFE_Pos) // 0x04000000 */
797#define GINTSTS_PTXFE GINTSTS_PTXFE_Msk // Periodic TxFIFO empty */
798#define GINTSTS_LPMINT_Pos (27U)
799#define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) // 0x08000000 */
800#define GINTSTS_LPMINT GINTSTS_LPMINT_Msk // LPM interrupt */
801#define GINTSTS_CIDSCHG_Pos (28U)
802#define GINTSTS_CIDSCHG_Msk (0x1UL << GINTSTS_CIDSCHG_Pos) // 0x10000000 */
803#define GINTSTS_CIDSCHG GINTSTS_CIDSCHG_Msk // Connector ID status change */
804#define GINTSTS_DISCINT_Pos (29U)
805#define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) // 0x20000000 */
806#define GINTSTS_DISCINT GINTSTS_DISCINT_Msk // Disconnect detected interrupt */
807#define GINTSTS_SRQINT_Pos (30U)
808#define GINTSTS_SRQINT_Msk (0x1UL << GINTSTS_SRQINT_Pos) // 0x40000000 */
809#define GINTSTS_SRQINT GINTSTS_SRQINT_Msk // Session request/new session detected interrupt */
810#define GINTSTS_WKUINT_Pos (31U)
811#define GINTSTS_WKUINT_Msk (0x1UL << GINTSTS_WKUINT_Pos) // 0x80000000 */
812#define GINTSTS_WKUINT GINTSTS_WKUINT_Msk // Resume/remote wakeup detected interrupt */
813
814/******************** Bit definition for GINTMSK register ********************/
815#define GINTMSK_MMISM_Pos (1U)
816#define GINTMSK_MMISM_Msk (0x1UL << GINTMSK_MMISM_Pos) // 0x00000002 */
817#define GINTMSK_MMISM GINTMSK_MMISM_Msk // Mode mismatch interrupt mask */
818#define GINTMSK_OTGINT_Pos (2U)
819#define GINTMSK_OTGINT_Msk (0x1UL << GINTMSK_OTGINT_Pos) // 0x00000004 */
820#define GINTMSK_OTGINT GINTMSK_OTGINT_Msk // OTG interrupt mask */
821#define GINTMSK_SOFM_Pos (3U)
822#define GINTMSK_SOFM_Msk (0x1UL << GINTMSK_SOFM_Pos) // 0x00000008 */
823#define GINTMSK_SOFM GINTMSK_SOFM_Msk // Start of frame mask */
824#define GINTMSK_RXFLVLM_Pos (4U)
825#define GINTMSK_RXFLVLM_Msk (0x1UL << GINTMSK_RXFLVLM_Pos) // 0x00000010 */
826#define GINTMSK_RXFLVLM GINTMSK_RXFLVLM_Msk // Receive FIFO nonempty mask */
827#define GINTMSK_NPTXFEM_Pos (5U)
828#define GINTMSK_NPTXFEM_Msk (0x1UL << GINTMSK_NPTXFEM_Pos) // 0x00000020 */
829#define GINTMSK_NPTXFEM GINTMSK_NPTXFEM_Msk // Nonperiodic TxFIFO empty mask */
830#define GINTMSK_GINAKEFFM_Pos (6U)
831#define GINTMSK_GINAKEFFM_Msk (0x1UL << GINTMSK_GINAKEFFM_Pos) // 0x00000040 */
832#define GINTMSK_GINAKEFFM GINTMSK_GINAKEFFM_Msk // Global nonperiodic IN NAK effective mask */
833#define GINTMSK_GONAKEFFM_Pos (7U)
834#define GINTMSK_GONAKEFFM_Msk (0x1UL << GINTMSK_GONAKEFFM_Pos) // 0x00000080 */
835#define GINTMSK_GONAKEFFM GINTMSK_GONAKEFFM_Msk // Global OUT NAK effective mask */
836#define GINTMSK_ESUSPM_Pos (10U)
837#define GINTMSK_ESUSPM_Msk (0x1UL << GINTMSK_ESUSPM_Pos) // 0x00000400 */
838#define GINTMSK_ESUSPM GINTMSK_ESUSPM_Msk // Early suspend mask */
839#define GINTMSK_USBSUSPM_Pos (11U)
840#define GINTMSK_USBSUSPM_Msk (0x1UL << GINTMSK_USBSUSPM_Pos) // 0x00000800 */
841#define GINTMSK_USBSUSPM GINTMSK_USBSUSPM_Msk // USB suspend mask */
842#define GINTMSK_USBRST_Pos (12U)
843#define GINTMSK_USBRST_Msk (0x1UL << GINTMSK_USBRST_Pos) // 0x00001000 */
844#define GINTMSK_USBRST GINTMSK_USBRST_Msk // USB reset mask */
845#define GINTMSK_ENUMDNEM_Pos (13U)
846#define GINTMSK_ENUMDNEM_Msk (0x1UL << GINTMSK_ENUMDNEM_Pos) // 0x00002000 */
847#define GINTMSK_ENUMDNEM GINTMSK_ENUMDNEM_Msk // Enumeration done mask */
848#define GINTMSK_ISOODRPM_Pos (14U)
849#define GINTMSK_ISOODRPM_Msk (0x1UL << GINTMSK_ISOODRPM_Pos) // 0x00004000 */
850#define GINTMSK_ISOODRPM GINTMSK_ISOODRPM_Msk // Isochronous OUT packet dropped interrupt mask */
851#define GINTMSK_EOPFM_Pos (15U)
852#define GINTMSK_EOPFM_Msk (0x1UL << GINTMSK_EOPFM_Pos) // 0x00008000 */
853#define GINTMSK_EOPFM GINTMSK_EOPFM_Msk // End of periodic frame interrupt mask */
854#define GINTMSK_EPMISM_Pos (17U)
855#define GINTMSK_EPMISM_Msk (0x1UL << GINTMSK_EPMISM_Pos) // 0x00020000 */
856#define GINTMSK_EPMISM GINTMSK_EPMISM_Msk // Endpoint mismatch interrupt mask */
857#define GINTMSK_IEPINT_Pos (18U)
858#define GINTMSK_IEPINT_Msk (0x1UL << GINTMSK_IEPINT_Pos) // 0x00040000 */
859#define GINTMSK_IEPINT GINTMSK_IEPINT_Msk // IN endpoints interrupt mask */
860#define GINTMSK_OEPINT_Pos (19U)
861#define GINTMSK_OEPINT_Msk (0x1UL << GINTMSK_OEPINT_Pos) // 0x00080000 */
862#define GINTMSK_OEPINT GINTMSK_OEPINT_Msk // OUT endpoints interrupt mask */
863#define GINTMSK_IISOIXFRM_Pos (20U)
864#define GINTMSK_IISOIXFRM_Msk (0x1UL << GINTMSK_IISOIXFRM_Pos) // 0x00100000 */
865#define GINTMSK_IISOIXFRM GINTMSK_IISOIXFRM_Msk // Incomplete isochronous IN transfer mask */
866#define GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
867#define GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) // 0x00200000 */
868#define GINTMSK_PXFRM_IISOOXFRM GINTMSK_PXFRM_IISOOXFRM_Msk // Incomplete periodic transfer mask */
869#define GINTMSK_FSUSPM_Pos (22U)
870#define GINTMSK_FSUSPM_Msk (0x1UL << GINTMSK_FSUSPM_Pos) // 0x00400000 */
871#define GINTMSK_FSUSPM GINTMSK_FSUSPM_Msk // Data fetch suspended mask */
872#define GINTMSK_RSTDEM_Pos (23U)
873#define GINTMSK_RSTDEM_Msk (0x1UL << GINTMSK_RSTDEM_Pos) // 0x00800000 */
874#define GINTMSK_RSTDEM GINTMSK_RSTDEM_Msk // Reset detected interrupt mask */
875#define GINTMSK_PRTIM_Pos (24U)
876#define GINTMSK_PRTIM_Msk (0x1UL << GINTMSK_PRTIM_Pos) // 0x01000000 */
877#define GINTMSK_PRTIM GINTMSK_PRTIM_Msk // Host port interrupt mask */
878#define GINTMSK_HCIM_Pos (25U)
879#define GINTMSK_HCIM_Msk (0x1UL << GINTMSK_HCIM_Pos) // 0x02000000 */
880#define GINTMSK_HCIM GINTMSK_HCIM_Msk // Host channels interrupt mask */
881#define GINTMSK_PTXFEM_Pos (26U)
882#define GINTMSK_PTXFEM_Msk (0x1UL << GINTMSK_PTXFEM_Pos) // 0x04000000 */
883#define GINTMSK_PTXFEM GINTMSK_PTXFEM_Msk // Periodic TxFIFO empty mask */
884#define GINTMSK_LPMINTM_Pos (27U)
885#define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) // 0x08000000 */
886#define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk // LPM interrupt Mask */
887#define GINTMSK_CIDSCHGM_Pos (28U)
888#define GINTMSK_CIDSCHGM_Msk (0x1UL << GINTMSK_CIDSCHGM_Pos) // 0x10000000 */
889#define GINTMSK_CIDSCHGM GINTMSK_CIDSCHGM_Msk // Connector ID status change mask */
890#define GINTMSK_DISCINT_Pos (29U)
891#define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) // 0x20000000 */
892#define GINTMSK_DISCINT GINTMSK_DISCINT_Msk // Disconnect detected interrupt mask */
893#define GINTMSK_SRQIM_Pos (30U)
894#define GINTMSK_SRQIM_Msk (0x1UL << GINTMSK_SRQIM_Pos) // 0x40000000 */
895#define GINTMSK_SRQIM GINTMSK_SRQIM_Msk // Session request/new session detected interrupt mask */
896#define GINTMSK_WUIM_Pos (31U)
897#define GINTMSK_WUIM_Msk (0x1UL << GINTMSK_WUIM_Pos) // 0x80000000 */
898#define GINTMSK_WUIM GINTMSK_WUIM_Msk // Resume/remote wakeup detected interrupt mask */
899
900/******************** Bit definition for DAINT register ********************/
901#define DAINT_IEPINT_Pos (0U)
902#define DAINT_IEPINT_Msk (0xFFFFUL << DAINT_IEPINT_Pos) // 0x0000FFFF */
903#define DAINT_IEPINT DAINT_IEPINT_Msk // IN endpoint interrupt bits */
904#define DAINT_OEPINT_Pos (16U)
905#define DAINT_OEPINT_Msk (0xFFFFUL << DAINT_OEPINT_Pos) // 0xFFFF0000 */
906#define DAINT_OEPINT DAINT_OEPINT_Msk // OUT endpoint interrupt bits */
907
908/******************** Bit definition for HAINTMSK register ********************/
909#define HAINTMSK_HAINTM_Pos (0U)
910#define HAINTMSK_HAINTM_Msk (0xFFFFUL << HAINTMSK_HAINTM_Pos) // 0x0000FFFF */
911#define HAINTMSK_HAINTM HAINTMSK_HAINTM_Msk // Channel interrupt mask */
912
913/******************** Bit definition for GRXSTSP register ********************/
914#define GRXSTSP_EPNUM_Pos (0U)
915#define GRXSTSP_EPNUM_Msk (0xFUL << GRXSTSP_EPNUM_Pos) // 0x0000000F */
916#define GRXSTSP_EPNUM GRXSTSP_EPNUM_Msk // IN EP interrupt mask bits */
917#define GRXSTSP_BCNT_Pos (4U)
918#define GRXSTSP_BCNT_Msk (0x7FFUL << GRXSTSP_BCNT_Pos) // 0x00007FF0 */
919#define GRXSTSP_BCNT GRXSTSP_BCNT_Msk // OUT EP interrupt mask bits */
920#define GRXSTSP_DPID_Pos (15U)
921#define GRXSTSP_DPID_Msk (0x3UL << GRXSTSP_DPID_Pos) // 0x00018000 */
922#define GRXSTSP_DPID GRXSTSP_DPID_Msk // OUT EP interrupt mask bits */
923#define GRXSTSP_PKTSTS_Pos (17U)
924#define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) // 0x001E0000 */
925#define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk // OUT EP interrupt mask bits */
926
927#define GRXSTS_PKTSTS_GLOBALOUTNAK 1
928#define GRXSTS_PKTSTS_OUTRX 2
929#define GRXSTS_PKTSTS_HCHIN 2
930#define GRXSTS_PKTSTS_OUTDONE 3
931#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
932#define GRXSTS_PKTSTS_SETUPDONE 4
933#define GRXSTS_PKTSTS_DATATOGGLEERR 5
934#define GRXSTS_PKTSTS_SETUPRX 6
935#define GRXSTS_PKTSTS_HCHHALTED 7
936
937
938/******************** Bit definition for DAINTMSK register ********************/
939#define DAINTMSK_IEPM_Pos (0U)
940#define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) // 0x0000FFFF */
941#define DAINTMSK_IEPM DAINTMSK_IEPM_Msk // IN EP interrupt mask bits */
942#define DAINTMSK_OEPM_Pos (16U)
943#define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) // 0xFFFF0000 */
944#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk // OUT EP interrupt mask bits */
945
946#if 0
947/******************** Bit definition for OTG register ********************/
948#define CHNUM_Pos (0U)
949#define CHNUM_Msk (0xFUL << CHNUM_Pos) // 0x0000000F */
950#define CHNUM CHNUM_Msk // Channel number */
951#define CHNUM_0 (0x1UL << CHNUM_Pos) // 0x00000001 */
952#define CHNUM_1 (0x2UL << CHNUM_Pos) // 0x00000002 */
953#define CHNUM_2 (0x4UL << CHNUM_Pos) // 0x00000004 */
954#define CHNUM_3 (0x8UL << CHNUM_Pos) // 0x00000008 */
955#define BCNT_Pos (4U)
956#define BCNT_Msk (0x7FFUL << BCNT_Pos) // 0x00007FF0 */
957#define BCNT BCNT_Msk // Byte count */
958
959#define DPID_Pos (15U)
960#define DPID_Msk (0x3UL << DPID_Pos) // 0x00018000 */
961#define DPID DPID_Msk // Data PID */
962#define DPID_0 (0x1UL << DPID_Pos) // 0x00008000 */
963#define DPID_1 (0x2UL << DPID_Pos) // 0x00010000 */
964
965#define PKTSTS_Pos (17U)
966#define PKTSTS_Msk (0xFUL << PKTSTS_Pos) // 0x001E0000 */
967#define PKTSTS PKTSTS_Msk // Packet status */
968#define PKTSTS_0 (0x1UL << PKTSTS_Pos) // 0x00020000 */
969#define PKTSTS_1 (0x2UL << PKTSTS_Pos) // 0x00040000 */
970#define PKTSTS_2 (0x4UL << PKTSTS_Pos) // 0x00080000 */
971#define PKTSTS_3 (0x8UL << PKTSTS_Pos) // 0x00100000 */
972
973#define EPNUM_Pos (0U)
974#define EPNUM_Msk (0xFUL << EPNUM_Pos) // 0x0000000F */
975#define EPNUM EPNUM_Msk // Endpoint number */
976#define EPNUM_0 (0x1UL << EPNUM_Pos) // 0x00000001 */
977#define EPNUM_1 (0x2UL << EPNUM_Pos) // 0x00000002 */
978#define EPNUM_2 (0x4UL << EPNUM_Pos) // 0x00000004 */
979#define EPNUM_3 (0x8UL << EPNUM_Pos) // 0x00000008 */
980
981#define FRMNUM_Pos (21U)
982#define FRMNUM_Msk (0xFUL << FRMNUM_Pos) // 0x01E00000 */
983#define FRMNUM FRMNUM_Msk // Frame number */
984#define FRMNUM_0 (0x1UL << FRMNUM_Pos) // 0x00200000 */
985#define FRMNUM_1 (0x2UL << FRMNUM_Pos) // 0x00400000 */
986#define FRMNUM_2 (0x4UL << FRMNUM_Pos) // 0x00800000 */
987#define FRMNUM_3 (0x8UL << FRMNUM_Pos) // 0x01000000 */
988#endif
989
990/******************** Bit definition for GRXFSIZ register ********************/
991#define GRXFSIZ_RXFD_Pos (0U)
992#define GRXFSIZ_RXFD_Msk (0xFFFFUL << GRXFSIZ_RXFD_Pos) // 0x0000FFFF */
993#define GRXFSIZ_RXFD GRXFSIZ_RXFD_Msk // RxFIFO depth */
994
995/******************** Bit definition for DVBUSDIS register ********************/
996#define DVBUSDIS_VBUSDT_Pos (0U)
997#define DVBUSDIS_VBUSDT_Msk (0xFFFFUL << DVBUSDIS_VBUSDT_Pos) // 0x0000FFFF */
998#define DVBUSDIS_VBUSDT DVBUSDIS_VBUSDT_Msk // Device VBUS discharge time */
999
1000/******************** Bit definition for OTG register ********************/
1001#define GNPTXFSIZ_NPTXFSA_Pos (0U)
1002#define GNPTXFSIZ_NPTXFSA_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFSA_Pos) // 0x0000FFFF */
1003#define GNPTXFSIZ_NPTXFSA GNPTXFSIZ_NPTXFSA_Msk // Nonperiodic transmit RAM start address */
1004#define GNPTXFSIZ_NPTXFD_Pos (16U)
1005#define GNPTXFSIZ_NPTXFD_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFD_Pos) // 0xFFFF0000 */
1006#define GNPTXFSIZ_NPTXFD GNPTXFSIZ_NPTXFD_Msk // Nonperiodic TxFIFO depth */
1007#define DIEPTXF0_TX0FSA_Pos (0U)
1008#define DIEPTXF0_TX0FSA_Msk (0xFFFFUL << DIEPTXF0_TX0FSA_Pos) // 0x0000FFFF */
1009#define DIEPTXF0_TX0FSA DIEPTXF0_TX0FSA_Msk // Endpoint 0 transmit RAM start address */
1010#define DIEPTXF0_TX0FD_Pos (16U)
1011#define DIEPTXF0_TX0FD_Msk (0xFFFFUL << DIEPTXF0_TX0FD_Pos) // 0xFFFF0000 */
1012#define DIEPTXF0_TX0FD DIEPTXF0_TX0FD_Msk // Endpoint 0 TxFIFO depth */
1013
1014/******************** Bit definition for DVBUSPULSE register ********************/
1015#define DVBUSPULSE_DVBUSP_Pos (0U)
1016#define DVBUSPULSE_DVBUSP_Msk (0xFFFUL << DVBUSPULSE_DVBUSP_Pos) // 0x00000FFF */
1017#define DVBUSPULSE_DVBUSP DVBUSPULSE_DVBUSP_Msk // Device VBUS pulsing time */
1018
1019/******************** Bit definition for GNPTXSTS register ********************/
1020#define GNPTXSTS_NPTXFSAV_Pos (0U)
1021#define GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos) // 0x0000FFFF */
1022#define GNPTXSTS_NPTXFSAV GNPTXSTS_NPTXFSAV_Msk // Nonperiodic TxFIFO space available */
1023
1024#define GNPTXSTS_NPTQXSAV_Pos (16U)
1025#define GNPTXSTS_NPTQXSAV_Msk (0xFFUL << GNPTXSTS_NPTQXSAV_Pos) // 0x00FF0000 */
1026#define GNPTXSTS_NPTQXSAV GNPTXSTS_NPTQXSAV_Msk // Nonperiodic transmit request queue space available */
1027#define GNPTXSTS_NPTQXSAV_0 (0x01UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00010000 */
1028#define GNPTXSTS_NPTQXSAV_1 (0x02UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00020000 */
1029#define GNPTXSTS_NPTQXSAV_2 (0x04UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00040000 */
1030#define GNPTXSTS_NPTQXSAV_3 (0x08UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00080000 */
1031#define GNPTXSTS_NPTQXSAV_4 (0x10UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00100000 */
1032#define GNPTXSTS_NPTQXSAV_5 (0x20UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00200000 */
1033#define GNPTXSTS_NPTQXSAV_6 (0x40UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00400000 */
1034#define GNPTXSTS_NPTQXSAV_7 (0x80UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00800000 */
1035
1036#define GNPTXSTS_NPTXQTOP_Pos (24U)
1037#define GNPTXSTS_NPTXQTOP_Msk (0x7FUL << GNPTXSTS_NPTXQTOP_Pos) // 0x7F000000 */
1038#define GNPTXSTS_NPTXQTOP GNPTXSTS_NPTXQTOP_Msk // Top of the nonperiodic transmit request queue */
1039#define GNPTXSTS_NPTXQTOP_0 (0x01UL << GNPTXSTS_NPTXQTOP_Pos) // 0x01000000 */
1040#define GNPTXSTS_NPTXQTOP_1 (0x02UL << GNPTXSTS_NPTXQTOP_Pos) // 0x02000000 */
1041#define GNPTXSTS_NPTXQTOP_2 (0x04UL << GNPTXSTS_NPTXQTOP_Pos) // 0x04000000 */
1042#define GNPTXSTS_NPTXQTOP_3 (0x08UL << GNPTXSTS_NPTXQTOP_Pos) // 0x08000000 */
1043#define GNPTXSTS_NPTXQTOP_4 (0x10UL << GNPTXSTS_NPTXQTOP_Pos) // 0x10000000 */
1044#define GNPTXSTS_NPTXQTOP_5 (0x20UL << GNPTXSTS_NPTXQTOP_Pos) // 0x20000000 */
1045#define GNPTXSTS_NPTXQTOP_6 (0x40UL << GNPTXSTS_NPTXQTOP_Pos) // 0x40000000 */
1046
1047/******************** Bit definition for DTHRCTL register ********************/
1048#define DTHRCTL_NONISOTHREN_Pos (0U)
1049#define DTHRCTL_NONISOTHREN_Msk (0x1UL << DTHRCTL_NONISOTHREN_Pos) // 0x00000001 */
1050#define DTHRCTL_NONISOTHREN DTHRCTL_NONISOTHREN_Msk // Nonisochronous IN endpoints threshold enable */
1051#define DTHRCTL_ISOTHREN_Pos (1U)
1052#define DTHRCTL_ISOTHREN_Msk (0x1UL << DTHRCTL_ISOTHREN_Pos) // 0x00000002 */
1053#define DTHRCTL_ISOTHREN DTHRCTL_ISOTHREN_Msk // ISO IN endpoint threshold enable */
1054
1055#define DTHRCTL_TXTHRLEN_Pos (2U)
1056#define DTHRCTL_TXTHRLEN_Msk (0x1FFUL << DTHRCTL_TXTHRLEN_Pos) // 0x000007FC */
1057#define DTHRCTL_TXTHRLEN DTHRCTL_TXTHRLEN_Msk // Transmit threshold length */
1058#define DTHRCTL_TXTHRLEN_0 (0x001UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000004 */
1059#define DTHRCTL_TXTHRLEN_1 (0x002UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000008 */
1060#define DTHRCTL_TXTHRLEN_2 (0x004UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000010 */
1061#define DTHRCTL_TXTHRLEN_3 (0x008UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000020 */
1062#define DTHRCTL_TXTHRLEN_4 (0x010UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000040 */
1063#define DTHRCTL_TXTHRLEN_5 (0x020UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000080 */
1064#define DTHRCTL_TXTHRLEN_6 (0x040UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000100 */
1065#define DTHRCTL_TXTHRLEN_7 (0x080UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000200 */
1066#define DTHRCTL_TXTHRLEN_8 (0x100UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000400 */
1067#define DTHRCTL_RXTHREN_Pos (16U)
1068#define DTHRCTL_RXTHREN_Msk (0x1UL << DTHRCTL_RXTHREN_Pos) // 0x00010000 */
1069#define DTHRCTL_RXTHREN DTHRCTL_RXTHREN_Msk // Receive threshold enable */
1070
1071#define DTHRCTL_RXTHRLEN_Pos (17U)
1072#define DTHRCTL_RXTHRLEN_Msk (0x1FFUL << DTHRCTL_RXTHRLEN_Pos) // 0x03FE0000 */
1073#define DTHRCTL_RXTHRLEN DTHRCTL_RXTHRLEN_Msk // Receive threshold length */
1074#define DTHRCTL_RXTHRLEN_0 (0x001UL << DTHRCTL_RXTHRLEN_Pos) // 0x00020000 */
1075#define DTHRCTL_RXTHRLEN_1 (0x002UL << DTHRCTL_RXTHRLEN_Pos) // 0x00040000 */
1076#define DTHRCTL_RXTHRLEN_2 (0x004UL << DTHRCTL_RXTHRLEN_Pos) // 0x00080000 */
1077#define DTHRCTL_RXTHRLEN_3 (0x008UL << DTHRCTL_RXTHRLEN_Pos) // 0x00100000 */
1078#define DTHRCTL_RXTHRLEN_4 (0x010UL << DTHRCTL_RXTHRLEN_Pos) // 0x00200000 */
1079#define DTHRCTL_RXTHRLEN_5 (0x020UL << DTHRCTL_RXTHRLEN_Pos) // 0x00400000 */
1080#define DTHRCTL_RXTHRLEN_6 (0x040UL << DTHRCTL_RXTHRLEN_Pos) // 0x00800000 */
1081#define DTHRCTL_RXTHRLEN_7 (0x080UL << DTHRCTL_RXTHRLEN_Pos) // 0x01000000 */
1082#define DTHRCTL_RXTHRLEN_8 (0x100UL << DTHRCTL_RXTHRLEN_Pos) // 0x02000000 */
1083#define DTHRCTL_ARPEN_Pos (27U)
1084#define DTHRCTL_ARPEN_Msk (0x1UL << DTHRCTL_ARPEN_Pos) // 0x08000000 */
1085#define DTHRCTL_ARPEN DTHRCTL_ARPEN_Msk // Arbiter parking enable */
1086
1087/******************** Bit definition for DIEPEMPMSK register ********************/
1088#define DIEPEMPMSK_INEPTXFEM_Pos (0U)
1089#define DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos) // 0x0000FFFF */
1090#define DIEPEMPMSK_INEPTXFEM DIEPEMPMSK_INEPTXFEM_Msk // IN EP Tx FIFO empty interrupt mask bits */
1091
1092/******************** Bit definition for DEACHINT register ********************/
1093#define DEACHINT_IEP1INT_Pos (1U)
1094#define DEACHINT_IEP1INT_Msk (0x1UL << DEACHINT_IEP1INT_Pos) // 0x00000002 */
1095#define DEACHINT_IEP1INT DEACHINT_IEP1INT_Msk // IN endpoint 1interrupt bit */
1096#define DEACHINT_OEP1INT_Pos (17U)
1097#define DEACHINT_OEP1INT_Msk (0x1UL << DEACHINT_OEP1INT_Pos) // 0x00020000 */
1098#define DEACHINT_OEP1INT DEACHINT_OEP1INT_Msk // OUT endpoint 1 interrupt bit */
1099
1100/******************** Bit definition for GCCFG register ********************/
1101#define STM32_GCCFG_DCDET_Pos (0U)
1102#define STM32_GCCFG_DCDET_Msk (0x1UL << STM32_GCCFG_DCDET_Pos) // 0x00000001 */
1103#define STM32_GCCFG_DCDET STM32_GCCFG_DCDET_Msk // Data contact detection (DCD) status */
1104#define STM32_GCCFG_PDET_Pos (1U)
1105#define STM32_GCCFG_PDET_Msk (0x1UL << STM32_GCCFG_PDET_Pos) // 0x00000002 */
1106#define STM32_GCCFG_PDET STM32_GCCFG_PDET_Msk // Primary detection (PD) status */
1107#define STM32_GCCFG_SDET_Pos (2U)
1108#define STM32_GCCFG_SDET_Msk (0x1UL << STM32_GCCFG_SDET_Pos) // 0x00000004 */
1109#define STM32_GCCFG_SDET STM32_GCCFG_SDET_Msk // Secondary detection (SD) status */
1110#define STM32_GCCFG_PS2DET_Pos (3U)
1111#define STM32_GCCFG_PS2DET_Msk (0x1UL << STM32_GCCFG_PS2DET_Pos) // 0x00000008 */
1112#define STM32_GCCFG_PS2DET STM32_GCCFG_PS2DET_Msk // DM pull-up detection status */
1113#define STM32_GCCFG_PWRDWN_Pos (16U)
1114#define STM32_GCCFG_PWRDWN_Msk (0x1UL << STM32_GCCFG_PWRDWN_Pos) // 0x00010000 */
1115#define STM32_GCCFG_PWRDWN STM32_GCCFG_PWRDWN_Msk // Power down */
1116#define STM32_GCCFG_BCDEN_Pos (17U)
1117#define STM32_GCCFG_BCDEN_Msk (0x1UL << STM32_GCCFG_BCDEN_Pos) // 0x00020000 */
1118#define STM32_GCCFG_BCDEN STM32_GCCFG_BCDEN_Msk // Battery charging detector (BCD) enable */
1119#define STM32_GCCFG_DCDEN_Pos (18U)
1120#define STM32_GCCFG_DCDEN_Msk (0x1UL << STM32_GCCFG_DCDEN_Pos) // 0x00040000 */
1121#define STM32_GCCFG_DCDEN STM32_GCCFG_DCDEN_Msk // Data contact detection (DCD) mode enable*/
1122#define STM32_GCCFG_PDEN_Pos (19U)
1123#define STM32_GCCFG_PDEN_Msk (0x1UL << STM32_GCCFG_PDEN_Pos) // 0x00080000 */
1124#define STM32_GCCFG_PDEN STM32_GCCFG_PDEN_Msk // Primary detection (PD) mode enable*/
1125#define STM32_GCCFG_SDEN_Pos (20U)
1126#define STM32_GCCFG_SDEN_Msk (0x1UL << STM32_GCCFG_SDEN_Pos) // 0x00100000 */
1127#define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (SD) mode enable */
1128#define STM32_GCCFG_VBDEN_Pos (21U)
1129#define STM32_GCCFG_VBDEN_Msk (0x1UL << STM32_GCCFG_VBDEN_Pos) // 0x00200000 */
1130#define STM32_GCCFG_VBDEN STM32_GCCFG_VBDEN_Msk // VBUS mode enable */
1131#define STM32_GCCFG_OTGIDEN_Pos (22U)
1132#define STM32_GCCFG_OTGIDEN_Msk (0x1UL << STM32_GCCFG_OTGIDEN_Pos) // 0x00400000 */
1133#define STM32_GCCFG_OTGIDEN STM32_GCCFG_OTGIDEN_Msk // OTG Id enable */
1134#define STM32_GCCFG_PHYHSEN_Pos (23U)
1135#define STM32_GCCFG_PHYHSEN_Msk (0x1UL << STM32_GCCFG_PHYHSEN_Pos) // 0x00800000 */
1136#define STM32_GCCFG_PHYHSEN STM32_GCCFG_PHYHSEN_Msk // HS PHY enable */
1137
1138/******************** Bit definition for DEACHINTMSK register ********************/
1139#define DEACHINTMSK_IEP1INTM_Pos (1U)
1140#define DEACHINTMSK_IEP1INTM_Msk (0x1UL << DEACHINTMSK_IEP1INTM_Pos) // 0x00000002 */
1141#define DEACHINTMSK_IEP1INTM DEACHINTMSK_IEP1INTM_Msk // IN Endpoint 1 interrupt mask bit */
1142#define DEACHINTMSK_OEP1INTM_Pos (17U)
1143#define DEACHINTMSK_OEP1INTM_Msk (0x1UL << DEACHINTMSK_OEP1INTM_Pos) // 0x00020000 */
1144#define DEACHINTMSK_OEP1INTM DEACHINTMSK_OEP1INTM_Msk // OUT Endpoint 1 interrupt mask bit */
1145
1146/******************** Bit definition for CID register ********************/
1147#define CID_PRODUCT_ID_Pos (0U)
1148#define CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos) // 0xFFFFFFFF */
1149#define CID_PRODUCT_ID CID_PRODUCT_ID_Msk // Product ID field */
1150
1151/******************** Bit definition for GLPMCFG register ********************/
1152#define GLPMCFG_LPMEN_Pos (0U)
1153#define GLPMCFG_LPMEN_Msk (0x1UL << GLPMCFG_LPMEN_Pos) // 0x00000001 */
1154#define GLPMCFG_LPMEN GLPMCFG_LPMEN_Msk // LPM support enable */
1155#define GLPMCFG_LPMACK_Pos (1U)
1156#define GLPMCFG_LPMACK_Msk (0x1UL << GLPMCFG_LPMACK_Pos) // 0x00000002 */
1157#define GLPMCFG_LPMACK GLPMCFG_LPMACK_Msk // LPM Token acknowledge enable */
1158#define GLPMCFG_BESL_Pos (2U)
1159#define GLPMCFG_BESL_Msk (0xFUL << GLPMCFG_BESL_Pos) // 0x0000003C */
1160#define GLPMCFG_BESL GLPMCFG_BESL_Msk // BESL value received with last ACKed LPM Token */
1161#define GLPMCFG_REMWAKE_Pos (6U)
1162#define GLPMCFG_REMWAKE_Msk (0x1UL << GLPMCFG_REMWAKE_Pos) // 0x00000040 */
1163#define GLPMCFG_REMWAKE GLPMCFG_REMWAKE_Msk // bRemoteWake value received with last ACKed LPM Token */
1164#define GLPMCFG_L1SSEN_Pos (7U)
1165#define GLPMCFG_L1SSEN_Msk (0x1UL << GLPMCFG_L1SSEN_Pos) // 0x00000080 */
1166#define GLPMCFG_L1SSEN GLPMCFG_L1SSEN_Msk // L1 shallow sleep enable */
1167#define GLPMCFG_BESLTHRS_Pos (8U)
1168#define GLPMCFG_BESLTHRS_Msk (0xFUL << GLPMCFG_BESLTHRS_Pos) // 0x00000F00 */
1169#define GLPMCFG_BESLTHRS GLPMCFG_BESLTHRS_Msk // BESL threshold */
1170#define GLPMCFG_L1DSEN_Pos (12U)
1171#define GLPMCFG_L1DSEN_Msk (0x1UL << GLPMCFG_L1DSEN_Pos) // 0x00001000 */
1172#define GLPMCFG_L1DSEN GLPMCFG_L1DSEN_Msk // L1 deep sleep enable */
1173#define GLPMCFG_LPMRSP_Pos (13U)
1174#define GLPMCFG_LPMRSP_Msk (0x3UL << GLPMCFG_LPMRSP_Pos) // 0x00006000 */
1175#define GLPMCFG_LPMRSP GLPMCFG_LPMRSP_Msk // LPM response */
1176#define GLPMCFG_SLPSTS_Pos (15U)
1177#define GLPMCFG_SLPSTS_Msk (0x1UL << GLPMCFG_SLPSTS_Pos) // 0x00008000 */
1178#define GLPMCFG_SLPSTS GLPMCFG_SLPSTS_Msk // Port sleep status */
1179#define GLPMCFG_L1RSMOK_Pos (16U)
1180#define GLPMCFG_L1RSMOK_Msk (0x1UL << GLPMCFG_L1RSMOK_Pos) // 0x00010000 */
1181#define GLPMCFG_L1RSMOK GLPMCFG_L1RSMOK_Msk // Sleep State Resume OK */
1182#define GLPMCFG_LPMCHIDX_Pos (17U)
1183#define GLPMCFG_LPMCHIDX_Msk (0xFUL << GLPMCFG_LPMCHIDX_Pos) // 0x001E0000 */
1184#define GLPMCFG_LPMCHIDX GLPMCFG_LPMCHIDX_Msk // LPM Channel Index */
1185#define GLPMCFG_LPMRCNT_Pos (21U)
1186#define GLPMCFG_LPMRCNT_Msk (0x7UL << GLPMCFG_LPMRCNT_Pos) // 0x00E00000 */
1187#define GLPMCFG_LPMRCNT GLPMCFG_LPMRCNT_Msk // LPM retry count */
1188#define GLPMCFG_SNDLPM_Pos (24U)
1189#define GLPMCFG_SNDLPM_Msk (0x1UL << GLPMCFG_SNDLPM_Pos) // 0x01000000 */
1190#define GLPMCFG_SNDLPM GLPMCFG_SNDLPM_Msk // Send LPM transaction */
1191#define GLPMCFG_LPMRCNTSTS_Pos (25U)
1192#define GLPMCFG_LPMRCNTSTS_Msk (0x7UL << GLPMCFG_LPMRCNTSTS_Pos) // 0x0E000000 */
1193#define GLPMCFG_LPMRCNTSTS GLPMCFG_LPMRCNTSTS_Msk // LPM retry count status */
1194#define GLPMCFG_ENBESL_Pos (28U)
1195#define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) // 0x10000000 */
1196#define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk // Enable best effort service latency */
1197
1198/******************** Bit definition for DIEPEACHMSK1 register ********************/
1199#define DIEPEACHMSK1_XFRCM_Pos (0U)
1200#define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) // 0x00000001 */
1201#define DIEPEACHMSK1_XFRCM DIEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask */
1202#define DIEPEACHMSK1_EPDM_Pos (1U)
1203#define DIEPEACHMSK1_EPDM_Msk (0x1UL << DIEPEACHMSK1_EPDM_Pos) // 0x00000002 */
1204#define DIEPEACHMSK1_EPDM DIEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask */
1205#define DIEPEACHMSK1_TOM_Pos (3U)
1206#define DIEPEACHMSK1_TOM_Msk (0x1UL << DIEPEACHMSK1_TOM_Pos) // 0x00000008 */
1207#define DIEPEACHMSK1_TOM DIEPEACHMSK1_TOM_Msk // Timeout condition mask (nonisochronous endpoints) */
1208#define DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
1209#define DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010 */
1210#define DIEPEACHMSK1_ITTXFEMSK DIEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask */
1211#define DIEPEACHMSK1_INEPNMM_Pos (5U)
1212#define DIEPEACHMSK1_INEPNMM_Msk (0x1UL << DIEPEACHMSK1_INEPNMM_Pos) // 0x00000020 */
1213#define DIEPEACHMSK1_INEPNMM DIEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask */
1214#define DIEPEACHMSK1_INEPNEM_Pos (6U)
1215#define DIEPEACHMSK1_INEPNEM_Msk (0x1UL << DIEPEACHMSK1_INEPNEM_Pos) // 0x00000040 */
1216#define DIEPEACHMSK1_INEPNEM DIEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask */
1217#define DIEPEACHMSK1_TXFURM_Pos (8U)
1218#define DIEPEACHMSK1_TXFURM_Msk (0x1UL << DIEPEACHMSK1_TXFURM_Pos) // 0x00000100 */
1219#define DIEPEACHMSK1_TXFURM DIEPEACHMSK1_TXFURM_Msk // FIFO underrun mask */
1220#define DIEPEACHMSK1_BIM_Pos (9U)
1221#define DIEPEACHMSK1_BIM_Msk (0x1UL << DIEPEACHMSK1_BIM_Pos) // 0x00000200 */
1222#define DIEPEACHMSK1_BIM DIEPEACHMSK1_BIM_Msk // BNA interrupt mask */
1223#define DIEPEACHMSK1_NAKM_Pos (13U)
1224#define DIEPEACHMSK1_NAKM_Msk (0x1UL << DIEPEACHMSK1_NAKM_Pos) // 0x00002000 */
1225#define DIEPEACHMSK1_NAKM DIEPEACHMSK1_NAKM_Msk // NAK interrupt mask */
1226
1227/******************** Bit definition for HPRT register ********************/
1228#define HPRT_PCSTS_Pos (0U)
1229#define HPRT_PCSTS_Msk (0x1UL << HPRT_PCSTS_Pos) // 0x00000001 */
1230#define HPRT_PCSTS HPRT_PCSTS_Msk // Port connect status */
1231#define HPRT_PCDET_Pos (1U)
1232#define HPRT_PCDET_Msk (0x1UL << HPRT_PCDET_Pos) // 0x00000002 */
1233#define HPRT_PCDET HPRT_PCDET_Msk // Port connect detected */
1234#define HPRT_PENA_Pos (2U)
1235#define HPRT_PENA_Msk (0x1UL << HPRT_PENA_Pos) // 0x00000004 */
1236#define HPRT_PENA HPRT_PENA_Msk // Port enable */
1237#define HPRT_PENCHNG_Pos (3U)
1238#define HPRT_PENCHNG_Msk (0x1UL << HPRT_PENCHNG_Pos) // 0x00000008 */
1239#define HPRT_PENCHNG HPRT_PENCHNG_Msk // Port enable/disable change */
1240#define HPRT_POCA_Pos (4U)
1241#define HPRT_POCA_Msk (0x1UL << HPRT_POCA_Pos) // 0x00000010 */
1242#define HPRT_POCA HPRT_POCA_Msk // Port overcurrent active */
1243#define HPRT_POCCHNG_Pos (5U)
1244#define HPRT_POCCHNG_Msk (0x1UL << HPRT_POCCHNG_Pos) // 0x00000020 */
1245#define HPRT_POCCHNG HPRT_POCCHNG_Msk // Port overcurrent change */
1246#define HPRT_PRES_Pos (6U)
1247#define HPRT_PRES_Msk (0x1UL << HPRT_PRES_Pos) // 0x00000040 */
1248#define HPRT_PRES HPRT_PRES_Msk // Port resume */
1249#define HPRT_PSUSP_Pos (7U)
1250#define HPRT_PSUSP_Msk (0x1UL << HPRT_PSUSP_Pos) // 0x00000080 */
1251#define HPRT_PSUSP HPRT_PSUSP_Msk // Port suspend */
1252#define HPRT_PRST_Pos (8U)
1253#define HPRT_PRST_Msk (0x1UL << HPRT_PRST_Pos) // 0x00000100 */
1254#define HPRT_PRST HPRT_PRST_Msk // Port reset */
1255
1256#define HPRT_PLSTS_Pos (10U)
1257#define HPRT_PLSTS_Msk (0x3UL << HPRT_PLSTS_Pos) // 0x00000C00 */
1258#define HPRT_PLSTS HPRT_PLSTS_Msk // Port line status */
1259#define HPRT_PLSTS_0 (0x1UL << HPRT_PLSTS_Pos) // 0x00000400 */
1260#define HPRT_PLSTS_1 (0x2UL << HPRT_PLSTS_Pos) // 0x00000800 */
1261#define HPRT_PPWR_Pos (12U)
1262#define HPRT_PPWR_Msk (0x1UL << HPRT_PPWR_Pos) // 0x00001000 */
1263#define HPRT_PPWR HPRT_PPWR_Msk // Port power */
1264
1265#define HPRT_PTCTL_Pos (13U)
1266#define HPRT_PTCTL_Msk (0xFUL << HPRT_PTCTL_Pos) // 0x0001E000 */
1267#define HPRT_PTCTL HPRT_PTCTL_Msk // Port test control */
1268#define HPRT_PTCTL_0 (0x1UL << HPRT_PTCTL_Pos) // 0x00002000 */
1269#define HPRT_PTCTL_1 (0x2UL << HPRT_PTCTL_Pos) // 0x00004000 */
1270#define HPRT_PTCTL_2 (0x4UL << HPRT_PTCTL_Pos) // 0x00008000 */
1271#define HPRT_PTCTL_3 (0x8UL << HPRT_PTCTL_Pos) // 0x00010000 */
1272
1273#define HPRT_PSPD_Pos (17U)
1274#define HPRT_PSPD_Msk (0x3UL << HPRT_PSPD_Pos) // 0x00060000 */
1275#define HPRT_PSPD HPRT_PSPD_Msk // Port speed */
1276#define HPRT_PSPD_0 (0x1UL << HPRT_PSPD_Pos) // 0x00020000 */
1277#define HPRT_PSPD_1 (0x2UL << HPRT_PSPD_Pos) // 0x00040000 */
1278
1279/******************** Bit definition for DOEPEACHMSK1 register ********************/
1280#define DOEPEACHMSK1_XFRCM_Pos (0U)
1281#define DOEPEACHMSK1_XFRCM_Msk (0x1UL << DOEPEACHMSK1_XFRCM_Pos) // 0x00000001 */
1282#define DOEPEACHMSK1_XFRCM DOEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask */
1283#define DOEPEACHMSK1_EPDM_Pos (1U)
1284#define DOEPEACHMSK1_EPDM_Msk (0x1UL << DOEPEACHMSK1_EPDM_Pos) // 0x00000002 */
1285#define DOEPEACHMSK1_EPDM DOEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask */
1286#define DOEPEACHMSK1_TOM_Pos (3U)
1287#define DOEPEACHMSK1_TOM_Msk (0x1UL << DOEPEACHMSK1_TOM_Pos) // 0x00000008 */
1288#define DOEPEACHMSK1_TOM DOEPEACHMSK1_TOM_Msk // Timeout condition mask */
1289#define DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
1290#define DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010 */
1291#define DOEPEACHMSK1_ITTXFEMSK DOEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask */
1292#define DOEPEACHMSK1_INEPNMM_Pos (5U)
1293#define DOEPEACHMSK1_INEPNMM_Msk (0x1UL << DOEPEACHMSK1_INEPNMM_Pos) // 0x00000020 */
1294#define DOEPEACHMSK1_INEPNMM DOEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask */
1295#define DOEPEACHMSK1_INEPNEM_Pos (6U)
1296#define DOEPEACHMSK1_INEPNEM_Msk (0x1UL << DOEPEACHMSK1_INEPNEM_Pos) // 0x00000040 */
1297#define DOEPEACHMSK1_INEPNEM DOEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask */
1298#define DOEPEACHMSK1_TXFURM_Pos (8U)
1299#define DOEPEACHMSK1_TXFURM_Msk (0x1UL << DOEPEACHMSK1_TXFURM_Pos) // 0x00000100 */
1300#define DOEPEACHMSK1_TXFURM DOEPEACHMSK1_TXFURM_Msk // OUT packet error mask */
1301#define DOEPEACHMSK1_BIM_Pos (9U)
1302#define DOEPEACHMSK1_BIM_Msk (0x1UL << DOEPEACHMSK1_BIM_Pos) // 0x00000200 */
1303#define DOEPEACHMSK1_BIM DOEPEACHMSK1_BIM_Msk // BNA interrupt mask */
1304#define DOEPEACHMSK1_BERRM_Pos (12U)
1305#define DOEPEACHMSK1_BERRM_Msk (0x1UL << DOEPEACHMSK1_BERRM_Pos) // 0x00001000 */
1306#define DOEPEACHMSK1_BERRM DOEPEACHMSK1_BERRM_Msk // Bubble error interrupt mask */
1307#define DOEPEACHMSK1_NAKM_Pos (13U)
1308#define DOEPEACHMSK1_NAKM_Msk (0x1UL << DOEPEACHMSK1_NAKM_Pos) // 0x00002000 */
1309#define DOEPEACHMSK1_NAKM DOEPEACHMSK1_NAKM_Msk // NAK interrupt mask */
1310#define DOEPEACHMSK1_NYETM_Pos (14U)
1311#define DOEPEACHMSK1_NYETM_Msk (0x1UL << DOEPEACHMSK1_NYETM_Pos) // 0x00004000 */
1312#define DOEPEACHMSK1_NYETM DOEPEACHMSK1_NYETM_Msk // NYET interrupt mask */
1313
1314/******************** Bit definition for HPTXFSIZ register ********************/
1315#define HPTXFSIZ_PTXSA_Pos (0U)
1316#define HPTXFSIZ_PTXSA_Msk (0xFFFFUL << HPTXFSIZ_PTXSA_Pos) // 0x0000FFFF */
1317#define HPTXFSIZ_PTXSA HPTXFSIZ_PTXSA_Msk // Host periodic TxFIFO start address */
1318#define HPTXFSIZ_PTXFD_Pos (16U)
1319#define HPTXFSIZ_PTXFD_Msk (0xFFFFUL << HPTXFSIZ_PTXFD_Pos) // 0xFFFF0000 */
1320#define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk // Host periodic TxFIFO depth */
1321
1322/******************** Bit definition for DIEPCTL register ********************/
1323#define DIEPCTL_MPSIZ_Pos (0U)
1324#define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) // 0x000007FF */
1325#define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk // Maximum packet size */
1326#define DIEPCTL_USBAEP_Pos (15U)
1327#define DIEPCTL_USBAEP_Msk (0x1UL << DIEPCTL_USBAEP_Pos) // 0x00008000 */
1328#define DIEPCTL_USBAEP DIEPCTL_USBAEP_Msk // USB active endpoint */
1329#define DIEPCTL_EONUM_DPID_Pos (16U)
1330#define DIEPCTL_EONUM_DPID_Msk (0x1UL << DIEPCTL_EONUM_DPID_Pos) // 0x00010000 */
1331#define DIEPCTL_EONUM_DPID DIEPCTL_EONUM_DPID_Msk // Even/odd frame */
1332#define DIEPCTL_NAKSTS_Pos (17U)
1333#define DIEPCTL_NAKSTS_Msk (0x1UL << DIEPCTL_NAKSTS_Pos) // 0x00020000 */
1334#define DIEPCTL_NAKSTS DIEPCTL_NAKSTS_Msk // NAK status */
1335
1336#define DIEPCTL_EPTYP_Pos (18U)
1337#define DIEPCTL_EPTYP_Msk (0x3UL << DIEPCTL_EPTYP_Pos) // 0x000C0000 */
1338#define DIEPCTL_EPTYP DIEPCTL_EPTYP_Msk // Endpoint type */
1339#define DIEPCTL_EPTYP_0 (0x1UL << DIEPCTL_EPTYP_Pos) // 0x00040000 */
1340#define DIEPCTL_EPTYP_1 (0x2UL << DIEPCTL_EPTYP_Pos) // 0x00080000 */
1341#define DIEPCTL_STALL_Pos (21U)
1342#define DIEPCTL_STALL_Msk (0x1UL << DIEPCTL_STALL_Pos) // 0x00200000 */
1343#define DIEPCTL_STALL DIEPCTL_STALL_Msk // STALL handshake */
1344
1345#define DIEPCTL_TXFNUM_Pos (22U)
1346#define DIEPCTL_TXFNUM_Msk (0xFUL << DIEPCTL_TXFNUM_Pos) // 0x03C00000 */
1347#define DIEPCTL_TXFNUM DIEPCTL_TXFNUM_Msk // TxFIFO number */
1348#define DIEPCTL_TXFNUM_0 (0x1UL << DIEPCTL_TXFNUM_Pos) // 0x00400000 */
1349#define DIEPCTL_TXFNUM_1 (0x2UL << DIEPCTL_TXFNUM_Pos) // 0x00800000 */
1350#define DIEPCTL_TXFNUM_2 (0x4UL << DIEPCTL_TXFNUM_Pos) // 0x01000000 */
1351#define DIEPCTL_TXFNUM_3 (0x8UL << DIEPCTL_TXFNUM_Pos) // 0x02000000 */
1352#define DIEPCTL_CNAK_Pos (26U)
1353#define DIEPCTL_CNAK_Msk (0x1UL << DIEPCTL_CNAK_Pos) // 0x04000000 */
1354#define DIEPCTL_CNAK DIEPCTL_CNAK_Msk // Clear NAK */
1355#define DIEPCTL_SNAK_Pos (27U)
1356#define DIEPCTL_SNAK_Msk (0x1UL << DIEPCTL_SNAK_Pos) // 0x08000000 */
1357#define DIEPCTL_SNAK DIEPCTL_SNAK_Msk // Set NAK */
1358#define DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
1359#define DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000 */
1360#define DIEPCTL_SD0PID_SEVNFRM DIEPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID */
1361#define DIEPCTL_SODDFRM_Pos (29U)
1362#define DIEPCTL_SODDFRM_Msk (0x1UL << DIEPCTL_SODDFRM_Pos) // 0x20000000 */
1363#define DIEPCTL_SODDFRM DIEPCTL_SODDFRM_Msk // Set odd frame */
1364#define DIEPCTL_EPDIS_Pos (30U)
1365#define DIEPCTL_EPDIS_Msk (0x1UL << DIEPCTL_EPDIS_Pos) // 0x40000000 */
1366#define DIEPCTL_EPDIS DIEPCTL_EPDIS_Msk // Endpoint disable */
1367#define DIEPCTL_EPENA_Pos (31U)
1368#define DIEPCTL_EPENA_Msk (0x1UL << DIEPCTL_EPENA_Pos) // 0x80000000 */
1369#define DIEPCTL_EPENA DIEPCTL_EPENA_Msk // Endpoint enable */
1370
1371/******************** Bit definition for HCCHAR register ********************/
1372#define HCCHAR_MPSIZ_Pos (0U)
1373#define HCCHAR_MPSIZ_Msk (0x7FFUL << HCCHAR_MPSIZ_Pos) // 0x000007FF */
1374#define HCCHAR_MPSIZ HCCHAR_MPSIZ_Msk // Maximum packet size */
1375
1376#define HCCHAR_EPNUM_Pos (11U)
1377#define HCCHAR_EPNUM_Msk (0xFUL << HCCHAR_EPNUM_Pos) // 0x00007800 */
1378#define HCCHAR_EPNUM HCCHAR_EPNUM_Msk // Endpoint number */
1379#define HCCHAR_EPNUM_0 (0x1UL << HCCHAR_EPNUM_Pos) // 0x00000800 */
1380#define HCCHAR_EPNUM_1 (0x2UL << HCCHAR_EPNUM_Pos) // 0x00001000 */
1381#define HCCHAR_EPNUM_2 (0x4UL << HCCHAR_EPNUM_Pos) // 0x00002000 */
1382#define HCCHAR_EPNUM_3 (0x8UL << HCCHAR_EPNUM_Pos) // 0x00004000 */
1383#define HCCHAR_EPDIR_Pos (15U)
1384#define HCCHAR_EPDIR_Msk (0x1UL << HCCHAR_EPDIR_Pos) // 0x00008000 */
1385#define HCCHAR_EPDIR HCCHAR_EPDIR_Msk // Endpoint direction */
1386#define HCCHAR_LSDEV_Pos (17U)
1387#define HCCHAR_LSDEV_Msk (0x1UL << HCCHAR_LSDEV_Pos) // 0x00020000 */
1388#define HCCHAR_LSDEV HCCHAR_LSDEV_Msk // Low-speed device */
1389
1390#define HCCHAR_EPTYP_Pos (18U)
1391#define HCCHAR_EPTYP_Msk (0x3UL << HCCHAR_EPTYP_Pos) // 0x000C0000 */
1392#define HCCHAR_EPTYP HCCHAR_EPTYP_Msk // Endpoint type */
1393#define HCCHAR_EPTYP_0 (0x1UL << HCCHAR_EPTYP_Pos) // 0x00040000 */
1394#define HCCHAR_EPTYP_1 (0x2UL << HCCHAR_EPTYP_Pos) // 0x00080000 */
1395
1396#define HCCHAR_MC_Pos (20U)
1397#define HCCHAR_MC_Msk (0x3UL << HCCHAR_MC_Pos) // 0x00300000 */
1398#define HCCHAR_MC HCCHAR_MC_Msk // Multi Count (MC) / Error Count (EC) */
1399#define HCCHAR_MC_0 (0x1UL << HCCHAR_MC_Pos) // 0x00100000 */
1400#define HCCHAR_MC_1 (0x2UL << HCCHAR_MC_Pos) // 0x00200000 */
1401
1402#define HCCHAR_DAD_Pos (22U)
1403#define HCCHAR_DAD_Msk (0x7FUL << HCCHAR_DAD_Pos) // 0x1FC00000 */
1404#define HCCHAR_DAD HCCHAR_DAD_Msk // Device address */
1405#define HCCHAR_DAD_0 (0x01UL << HCCHAR_DAD_Pos) // 0x00400000 */
1406#define HCCHAR_DAD_1 (0x02UL << HCCHAR_DAD_Pos) // 0x00800000 */
1407#define HCCHAR_DAD_2 (0x04UL << HCCHAR_DAD_Pos) // 0x01000000 */
1408#define HCCHAR_DAD_3 (0x08UL << HCCHAR_DAD_Pos) // 0x02000000 */
1409#define HCCHAR_DAD_4 (0x10UL << HCCHAR_DAD_Pos) // 0x04000000 */
1410#define HCCHAR_DAD_5 (0x20UL << HCCHAR_DAD_Pos) // 0x08000000 */
1411#define HCCHAR_DAD_6 (0x40UL << HCCHAR_DAD_Pos) // 0x10000000 */
1412#define HCCHAR_ODDFRM_Pos (29U)
1413#define HCCHAR_ODDFRM_Msk (0x1UL << HCCHAR_ODDFRM_Pos) // 0x20000000 */
1414#define HCCHAR_ODDFRM HCCHAR_ODDFRM_Msk // Odd frame */
1415#define HCCHAR_CHDIS_Pos (30U)
1416#define HCCHAR_CHDIS_Msk (0x1UL << HCCHAR_CHDIS_Pos) // 0x40000000 */
1417#define HCCHAR_CHDIS HCCHAR_CHDIS_Msk // Channel disable */
1418#define HCCHAR_CHENA_Pos (31U)
1419#define HCCHAR_CHENA_Msk (0x1UL << HCCHAR_CHENA_Pos) // 0x80000000 */
1420#define HCCHAR_CHENA HCCHAR_CHENA_Msk // Channel enable */
1421
1422/******************** Bit definition for HCSPLT register ********************/
1423
1424#define HCSPLT_PRTADDR_Pos (0U)
1425#define HCSPLT_PRTADDR_Msk (0x7FUL << HCSPLT_PRTADDR_Pos) // 0x0000007F */
1426#define HCSPLT_PRTADDR HCSPLT_PRTADDR_Msk // Port address */
1427#define HCSPLT_PRTADDR_0 (0x01UL << HCSPLT_PRTADDR_Pos) // 0x00000001 */
1428#define HCSPLT_PRTADDR_1 (0x02UL << HCSPLT_PRTADDR_Pos) // 0x00000002 */
1429#define HCSPLT_PRTADDR_2 (0x04UL << HCSPLT_PRTADDR_Pos) // 0x00000004 */
1430#define HCSPLT_PRTADDR_3 (0x08UL << HCSPLT_PRTADDR_Pos) // 0x00000008 */
1431#define HCSPLT_PRTADDR_4 (0x10UL << HCSPLT_PRTADDR_Pos) // 0x00000010 */
1432#define HCSPLT_PRTADDR_5 (0x20UL << HCSPLT_PRTADDR_Pos) // 0x00000020 */
1433#define HCSPLT_PRTADDR_6 (0x40UL << HCSPLT_PRTADDR_Pos) // 0x00000040 */
1434
1435#define HCSPLT_HUBADDR_Pos (7U)
1436#define HCSPLT_HUBADDR_Msk (0x7FUL << HCSPLT_HUBADDR_Pos) // 0x00003F80 */
1437#define HCSPLT_HUBADDR HCSPLT_HUBADDR_Msk // Hub address */
1438#define HCSPLT_HUBADDR_0 (0x01UL << HCSPLT_HUBADDR_Pos) // 0x00000080 */
1439#define HCSPLT_HUBADDR_1 (0x02UL << HCSPLT_HUBADDR_Pos) // 0x00000100 */
1440#define HCSPLT_HUBADDR_2 (0x04UL << HCSPLT_HUBADDR_Pos) // 0x00000200 */
1441#define HCSPLT_HUBADDR_3 (0x08UL << HCSPLT_HUBADDR_Pos) // 0x00000400 */
1442#define HCSPLT_HUBADDR_4 (0x10UL << HCSPLT_HUBADDR_Pos) // 0x00000800 */
1443#define HCSPLT_HUBADDR_5 (0x20UL << HCSPLT_HUBADDR_Pos) // 0x00001000 */
1444#define HCSPLT_HUBADDR_6 (0x40UL << HCSPLT_HUBADDR_Pos) // 0x00002000 */
1445
1446#define HCSPLT_XACTPOS_Pos (14U)
1447#define HCSPLT_XACTPOS_Msk (0x3UL << HCSPLT_XACTPOS_Pos) // 0x0000C000 */
1448#define HCSPLT_XACTPOS HCSPLT_XACTPOS_Msk // XACTPOS */
1449#define HCSPLT_XACTPOS_0 (0x1UL << HCSPLT_XACTPOS_Pos) // 0x00004000 */
1450#define HCSPLT_XACTPOS_1 (0x2UL << HCSPLT_XACTPOS_Pos) // 0x00008000 */
1451#define HCSPLT_COMPLSPLT_Pos (16U)
1452#define HCSPLT_COMPLSPLT_Msk (0x1UL << HCSPLT_COMPLSPLT_Pos) // 0x00010000 */
1453#define HCSPLT_COMPLSPLT HCSPLT_COMPLSPLT_Msk // Do complete split */
1454#define HCSPLT_SPLITEN_Pos (31U)
1455#define HCSPLT_SPLITEN_Msk (0x1UL << HCSPLT_SPLITEN_Pos) // 0x80000000 */
1456#define HCSPLT_SPLITEN HCSPLT_SPLITEN_Msk // Split enable */
1457
1458/******************** Bit definition for HCINT register ********************/
1459#define HCINT_XFRC_Pos (0U)
1460#define HCINT_XFRC_Msk (0x1UL << HCINT_XFRC_Pos) // 0x00000001 */
1461#define HCINT_XFRC HCINT_XFRC_Msk // Transfer completed */
1462#define HCINT_CHH_Pos (1U)
1463#define HCINT_CHH_Msk (0x1UL << HCINT_CHH_Pos) // 0x00000002 */
1464#define HCINT_CHH HCINT_CHH_Msk // Channel halted */
1465#define HCINT_AHBERR_Pos (2U)
1466#define HCINT_AHBERR_Msk (0x1UL << HCINT_AHBERR_Pos) // 0x00000004 */
1467#define HCINT_AHBERR HCINT_AHBERR_Msk // AHB error */
1468#define HCINT_STALL_Pos (3U)
1469#define HCINT_STALL_Msk (0x1UL << HCINT_STALL_Pos) // 0x00000008 */
1470#define HCINT_STALL HCINT_STALL_Msk // STALL response received interrupt */
1471#define HCINT_NAK_Pos (4U)
1472#define HCINT_NAK_Msk (0x1UL << HCINT_NAK_Pos) // 0x00000010 */
1473#define HCINT_NAK HCINT_NAK_Msk // NAK response received interrupt */
1474#define HCINT_ACK_Pos (5U)
1475#define HCINT_ACK_Msk (0x1UL << HCINT_ACK_Pos) // 0x00000020 */
1476#define HCINT_ACK HCINT_ACK_Msk // ACK response received/transmitted interrupt */
1477#define HCINT_NYET_Pos (6U)
1478#define HCINT_NYET_Msk (0x1UL << HCINT_NYET_Pos) // 0x00000040 */
1479#define HCINT_NYET HCINT_NYET_Msk // Response received interrupt */
1480#define HCINT_TXERR_Pos (7U)
1481#define HCINT_TXERR_Msk (0x1UL << HCINT_TXERR_Pos) // 0x00000080 */
1482#define HCINT_TXERR HCINT_TXERR_Msk // Transaction error */
1483#define HCINT_BBERR_Pos (8U)
1484#define HCINT_BBERR_Msk (0x1UL << HCINT_BBERR_Pos) // 0x00000100 */
1485#define HCINT_BBERR HCINT_BBERR_Msk // Babble error */
1486#define HCINT_FRMOR_Pos (9U)
1487#define HCINT_FRMOR_Msk (0x1UL << HCINT_FRMOR_Pos) // 0x00000200 */
1488#define HCINT_FRMOR HCINT_FRMOR_Msk // Frame overrun */
1489#define HCINT_DTERR_Pos (10U)
1490#define HCINT_DTERR_Msk (0x1UL << HCINT_DTERR_Pos) // 0x00000400 */
1491#define HCINT_DTERR HCINT_DTERR_Msk // Data toggle error */
1492
1493/******************** Bit definition for DIEPINT register ********************/
1494#define DIEPINT_XFRC_Pos (0U)
1495#define DIEPINT_XFRC_Msk (0x1UL << DIEPINT_XFRC_Pos) // 0x00000001 */
1496#define DIEPINT_XFRC DIEPINT_XFRC_Msk // Transfer completed interrupt */
1497#define DIEPINT_EPDISD_Pos (1U)
1498#define DIEPINT_EPDISD_Msk (0x1UL << DIEPINT_EPDISD_Pos) // 0x00000002 */
1499#define DIEPINT_EPDISD DIEPINT_EPDISD_Msk // Endpoint disabled interrupt */
1500#define DIEPINT_AHBERR_Pos (2U)
1501#define DIEPINT_AHBERR_Msk (0x1UL << DIEPINT_AHBERR_Pos) // 0x00000004 */
1502#define DIEPINT_AHBERR DIEPINT_AHBERR_Msk // AHB Error (AHBErr) during an IN transaction */
1503#define DIEPINT_TOC_Pos (3U)
1504#define DIEPINT_TOC_Msk (0x1UL << DIEPINT_TOC_Pos) // 0x00000008 */
1505#define DIEPINT_TOC DIEPINT_TOC_Msk // Timeout condition */
1506#define DIEPINT_ITTXFE_Pos (4U)
1507#define DIEPINT_ITTXFE_Msk (0x1UL << DIEPINT_ITTXFE_Pos) // 0x00000010 */
1508#define DIEPINT_ITTXFE DIEPINT_ITTXFE_Msk // IN token received when TxFIFO is empty */
1509#define DIEPINT_INEPNM_Pos (5U)
1510#define DIEPINT_INEPNM_Msk (0x1UL << DIEPINT_INEPNM_Pos) // 0x00000020 */
1511#define DIEPINT_INEPNM DIEPINT_INEPNM_Msk // IN token received with EP mismatch */
1512#define DIEPINT_INEPNE_Pos (6U)
1513#define DIEPINT_INEPNE_Msk (0x1UL << DIEPINT_INEPNE_Pos) // 0x00000040 */
1514#define DIEPINT_INEPNE DIEPINT_INEPNE_Msk // IN endpoint NAK effective */
1515#define DIEPINT_TXFE_Pos (7U)
1516#define DIEPINT_TXFE_Msk (0x1UL << DIEPINT_TXFE_Pos) // 0x00000080 */
1517#define DIEPINT_TXFE DIEPINT_TXFE_Msk // Transmit FIFO empty */
1518#define DIEPINT_TXFIFOUDRN_Pos (8U)
1519#define DIEPINT_TXFIFOUDRN_Msk (0x1UL << DIEPINT_TXFIFOUDRN_Pos) // 0x00000100 */
1520#define DIEPINT_TXFIFOUDRN DIEPINT_TXFIFOUDRN_Msk // Transmit Fifo Underrun */
1521#define DIEPINT_BNA_Pos (9U)
1522#define DIEPINT_BNA_Msk (0x1UL << DIEPINT_BNA_Pos) // 0x00000200 */
1523#define DIEPINT_BNA DIEPINT_BNA_Msk // Buffer not available interrupt */
1524#define DIEPINT_PKTDRPSTS_Pos (11U)
1525#define DIEPINT_PKTDRPSTS_Msk (0x1UL << DIEPINT_PKTDRPSTS_Pos) // 0x00000800 */
1526#define DIEPINT_PKTDRPSTS DIEPINT_PKTDRPSTS_Msk // Packet dropped status */
1527#define DIEPINT_BERR_Pos (12U)
1528#define DIEPINT_BERR_Msk (0x1UL << DIEPINT_BERR_Pos) // 0x00001000 */
1529#define DIEPINT_BERR DIEPINT_BERR_Msk // Babble error interrupt */
1530#define DIEPINT_NAK_Pos (13U)
1531#define DIEPINT_NAK_Msk (0x1UL << DIEPINT_NAK_Pos) // 0x00002000 */
1532#define DIEPINT_NAK DIEPINT_NAK_Msk // NAK interrupt */
1533
1534/******************** Bit definition for HCINTMSK register ********************/
1535#define HCINTMSK_XFRCM_Pos (0U)
1536#define HCINTMSK_XFRCM_Msk (0x1UL << HCINTMSK_XFRCM_Pos) // 0x00000001 */
1537#define HCINTMSK_XFRCM HCINTMSK_XFRCM_Msk // Transfer completed mask */
1538#define HCINTMSK_CHHM_Pos (1U)
1539#define HCINTMSK_CHHM_Msk (0x1UL << HCINTMSK_CHHM_Pos) // 0x00000002 */
1540#define HCINTMSK_CHHM HCINTMSK_CHHM_Msk // Channel halted mask */
1541#define HCINTMSK_AHBERR_Pos (2U)
1542#define HCINTMSK_AHBERR_Msk (0x1UL << HCINTMSK_AHBERR_Pos) // 0x00000004 */
1543#define HCINTMSK_AHBERR HCINTMSK_AHBERR_Msk // AHB error */
1544#define HCINTMSK_STALLM_Pos (3U)
1545#define HCINTMSK_STALLM_Msk (0x1UL << HCINTMSK_STALLM_Pos) // 0x00000008 */
1546#define HCINTMSK_STALLM HCINTMSK_STALLM_Msk // STALL response received interrupt mask */
1547#define HCINTMSK_NAKM_Pos (4U)
1548#define HCINTMSK_NAKM_Msk (0x1UL << HCINTMSK_NAKM_Pos) // 0x00000010 */
1549#define HCINTMSK_NAKM HCINTMSK_NAKM_Msk // NAK response received interrupt mask */
1550#define HCINTMSK_ACKM_Pos (5U)
1551#define HCINTMSK_ACKM_Msk (0x1UL << HCINTMSK_ACKM_Pos) // 0x00000020 */
1552#define HCINTMSK_ACKM HCINTMSK_ACKM_Msk // ACK response received/transmitted interrupt mask */
1553#define HCINTMSK_NYET_Pos (6U)
1554#define HCINTMSK_NYET_Msk (0x1UL << HCINTMSK_NYET_Pos) // 0x00000040 */
1555#define HCINTMSK_NYET HCINTMSK_NYET_Msk // response received interrupt mask */
1556#define HCINTMSK_TXERRM_Pos (7U)
1557#define HCINTMSK_TXERRM_Msk (0x1UL << HCINTMSK_TXERRM_Pos) // 0x00000080 */
1558#define HCINTMSK_TXERRM HCINTMSK_TXERRM_Msk // Transaction error mask */
1559#define HCINTMSK_BBERRM_Pos (8U)
1560#define HCINTMSK_BBERRM_Msk (0x1UL << HCINTMSK_BBERRM_Pos) // 0x00000100 */
1561#define HCINTMSK_BBERRM HCINTMSK_BBERRM_Msk // Babble error mask */
1562#define HCINTMSK_FRMORM_Pos (9U)
1563#define HCINTMSK_FRMORM_Msk (0x1UL << HCINTMSK_FRMORM_Pos) // 0x00000200 */
1564#define HCINTMSK_FRMORM HCINTMSK_FRMORM_Msk // Frame overrun mask */
1565#define HCINTMSK_DTERRM_Pos (10U)
1566#define HCINTMSK_DTERRM_Msk (0x1UL << HCINTMSK_DTERRM_Pos) // 0x00000400 */
1567#define HCINTMSK_DTERRM HCINTMSK_DTERRM_Msk // Data toggle error mask */
1568
1569/******************** Bit definition for DIEPTSIZ register ********************/
1570
1571#define DIEPTSIZ_XFRSIZ_Pos (0U)
1572#define DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos) // 0x0007FFFF */
1573#define DIEPTSIZ_XFRSIZ DIEPTSIZ_XFRSIZ_Msk // Transfer size */
1574#define DIEPTSIZ_PKTCNT_Pos (19U)
1575#define DIEPTSIZ_PKTCNT_Msk (0x3FFUL << DIEPTSIZ_PKTCNT_Pos) // 0x1FF80000 */
1576#define DIEPTSIZ_PKTCNT DIEPTSIZ_PKTCNT_Msk // Packet count */
1577#define DIEPTSIZ_MULCNT_Pos (29U)
1578#define DIEPTSIZ_MULCNT_Msk (0x3UL << DIEPTSIZ_MULCNT_Pos) // 0x60000000 */
1579#define DIEPTSIZ_MULCNT DIEPTSIZ_MULCNT_Msk // Packet count */
1580 /******************** Bit definition for HCTSIZ register ********************/
1581#define HCTSIZ_XFRSIZ_Pos (0U)
1582#define HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) // 0x0007FFFF */
1583#define HCTSIZ_XFRSIZ HCTSIZ_XFRSIZ_Msk // Transfer size */
1584#define HCTSIZ_PKTCNT_Pos (19U)
1585#define HCTSIZ_PKTCNT_Msk (0x3FFUL << HCTSIZ_PKTCNT_Pos) // 0x1FF80000 */
1586#define HCTSIZ_PKTCNT HCTSIZ_PKTCNT_Msk // Packet count */
1587#define HCTSIZ_DOPING_Pos (31U)
1588#define HCTSIZ_DOPING_Msk (0x1UL << HCTSIZ_DOPING_Pos) // 0x80000000 */
1589#define HCTSIZ_DOPING HCTSIZ_DOPING_Msk // Do PING */
1590#define HCTSIZ_DPID_Pos (29U)
1591#define HCTSIZ_DPID_Msk (0x3UL << HCTSIZ_DPID_Pos) // 0x60000000 */
1592#define HCTSIZ_DPID HCTSIZ_DPID_Msk // Data PID */
1593#define HCTSIZ_DPID_0 (0x1UL << HCTSIZ_DPID_Pos) // 0x20000000 */
1594#define HCTSIZ_DPID_1 (0x2UL << HCTSIZ_DPID_Pos) // 0x40000000 */
1595
1596/******************** Bit definition for DIEPDMA register ********************/
1597#define DIEPDMA_DMAADDR_Pos (0U)
1598#define DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos) // 0xFFFFFFFF */
1599#define DIEPDMA_DMAADDR DIEPDMA_DMAADDR_Msk // DMA address */
1600
1601/******************** Bit definition for HCDMA register ********************/
1602#define HCDMA_DMAADDR_Pos (0U)
1603#define HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) // 0xFFFFFFFF */
1604#define HCDMA_DMAADDR HCDMA_DMAADDR_Msk // DMA address */
1605
1606 /******************** Bit definition for DTXFSTS register ********************/
1607#define DTXFSTS_INEPTFSAV_Pos (0U)
1608#define DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) // 0x0000FFFF */
1609#define DTXFSTS_INEPTFSAV DTXFSTS_INEPTFSAV_Msk // IN endpoint TxFIFO space available */
1610
1611 /******************** Bit definition for DIEPTXF register ********************/
1612#define DIEPTXF_INEPTXSA_Pos (0U)
1613#define DIEPTXF_INEPTXSA_Msk (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) // 0x0000FFFF */
1614#define DIEPTXF_INEPTXSA DIEPTXF_INEPTXSA_Msk // IN endpoint FIFOx transmit RAM start address */
1615#define DIEPTXF_INEPTXFD_Pos (16U)
1616#define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) // 0xFFFF0000 */
1617#define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk // IN endpoint TxFIFO depth */
1618
1619/******************** Bit definition for DOEPCTL register ********************/
1620#define DOEPCTL_MPSIZ_Pos (0U)
1621#define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) // 0x000007FF */
1622#define DOEPCTL_MPSIZ DOEPCTL_MPSIZ_Msk // Maximum packet size */ //Bit 1 */
1623#define DOEPCTL_USBAEP_Pos (15U)
1624#define DOEPCTL_USBAEP_Msk (0x1UL << DOEPCTL_USBAEP_Pos) // 0x00008000 */
1625#define DOEPCTL_USBAEP DOEPCTL_USBAEP_Msk // USB active endpoint */
1626#define DOEPCTL_NAKSTS_Pos (17U)
1627#define DOEPCTL_NAKSTS_Msk (0x1UL << DOEPCTL_NAKSTS_Pos) // 0x00020000 */
1628#define DOEPCTL_NAKSTS DOEPCTL_NAKSTS_Msk // NAK status */
1629#define DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
1630#define DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000 */
1631#define DOEPCTL_SD0PID_SEVNFRM DOEPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID */
1632#define DOEPCTL_SODDFRM_Pos (29U)
1633#define DOEPCTL_SODDFRM_Msk (0x1UL << DOEPCTL_SODDFRM_Pos) // 0x20000000 */
1634#define DOEPCTL_SODDFRM DOEPCTL_SODDFRM_Msk // Set odd frame */
1635#define DOEPCTL_EPTYP_Pos (18U)
1636#define DOEPCTL_EPTYP_Msk (0x3UL << DOEPCTL_EPTYP_Pos) // 0x000C0000 */
1637#define DOEPCTL_EPTYP DOEPCTL_EPTYP_Msk // Endpoint type */
1638#define DOEPCTL_EPTYP_0 (0x1UL << DOEPCTL_EPTYP_Pos) // 0x00040000 */
1639#define DOEPCTL_EPTYP_1 (0x2UL << DOEPCTL_EPTYP_Pos) // 0x00080000 */
1640#define DOEPCTL_SNPM_Pos (20U)
1641#define DOEPCTL_SNPM_Msk (0x1UL << DOEPCTL_SNPM_Pos) // 0x00100000 */
1642#define DOEPCTL_SNPM DOEPCTL_SNPM_Msk // Snoop mode */
1643#define DOEPCTL_STALL_Pos (21U)
1644#define DOEPCTL_STALL_Msk (0x1UL << DOEPCTL_STALL_Pos) // 0x00200000 */
1645#define DOEPCTL_STALL DOEPCTL_STALL_Msk // STALL handshake */
1646#define DOEPCTL_CNAK_Pos (26U)
1647#define DOEPCTL_CNAK_Msk (0x1UL << DOEPCTL_CNAK_Pos) // 0x04000000 */
1648#define DOEPCTL_CNAK DOEPCTL_CNAK_Msk // Clear NAK */
1649#define DOEPCTL_SNAK_Pos (27U)
1650#define DOEPCTL_SNAK_Msk (0x1UL << DOEPCTL_SNAK_Pos) // 0x08000000 */
1651#define DOEPCTL_SNAK DOEPCTL_SNAK_Msk // Set NAK */
1652#define DOEPCTL_EPDIS_Pos (30U)
1653#define DOEPCTL_EPDIS_Msk (0x1UL << DOEPCTL_EPDIS_Pos) // 0x40000000 */
1654#define DOEPCTL_EPDIS DOEPCTL_EPDIS_Msk // Endpoint disable */
1655#define DOEPCTL_EPENA_Pos (31U)
1656#define DOEPCTL_EPENA_Msk (0x1UL << DOEPCTL_EPENA_Pos) // 0x80000000 */
1657#define DOEPCTL_EPENA DOEPCTL_EPENA_Msk // Endpoint enable */
1658
1659/******************** Bit definition for DOEPINT register ********************/
1660#define DOEPINT_XFRC_Pos (0U)
1661#define DOEPINT_XFRC_Msk (0x1UL << DOEPINT_XFRC_Pos) // 0x00000001 */
1662#define DOEPINT_XFRC DOEPINT_XFRC_Msk // Transfer completed interrupt */
1663#define DOEPINT_EPDISD_Pos (1U)
1664#define DOEPINT_EPDISD_Msk (0x1UL << DOEPINT_EPDISD_Pos) // 0x00000002 */
1665#define DOEPINT_EPDISD DOEPINT_EPDISD_Msk // Endpoint disabled interrupt */
1666#define DOEPINT_AHBERR_Pos (2U)
1667#define DOEPINT_AHBERR_Msk (0x1UL << DOEPINT_AHBERR_Pos) // 0x00000004 */
1668#define DOEPINT_AHBERR DOEPINT_AHBERR_Msk // AHB Error (AHBErr) during an OUT transaction */
1669#define DOEPINT_STUP_Pos (3U)
1670#define DOEPINT_STUP_Msk (0x1UL << DOEPINT_STUP_Pos) // 0x00000008 */
1671#define DOEPINT_STUP DOEPINT_STUP_Msk // SETUP phase done */
1672#define DOEPINT_OTEPDIS_Pos (4U)
1673#define DOEPINT_OTEPDIS_Msk (0x1UL << DOEPINT_OTEPDIS_Pos) // 0x00000010 */
1674#define DOEPINT_OTEPDIS DOEPINT_OTEPDIS_Msk // OUT token received when endpoint disabled */
1675#define DOEPINT_OTEPSPR_Pos (5U)
1676#define DOEPINT_OTEPSPR_Msk (0x1UL << DOEPINT_OTEPSPR_Pos) // 0x00000020 */
1677#define DOEPINT_OTEPSPR DOEPINT_OTEPSPR_Msk // Status Phase Received For Control Write */
1678#define DOEPINT_B2BSTUP_Pos (6U)
1679#define DOEPINT_B2BSTUP_Msk (0x1UL << DOEPINT_B2BSTUP_Pos) // 0x00000040 */
1680#define DOEPINT_B2BSTUP DOEPINT_B2BSTUP_Msk // Back-to-back SETUP packets received */
1681#define DOEPINT_OUTPKTERR_Pos (8U)
1682#define DOEPINT_OUTPKTERR_Msk (0x1UL << DOEPINT_OUTPKTERR_Pos) // 0x00000100 */
1683#define DOEPINT_OUTPKTERR DOEPINT_OUTPKTERR_Msk // OUT packet error */
1684#define DOEPINT_NAK_Pos (13U)
1685#define DOEPINT_NAK_Msk (0x1UL << DOEPINT_NAK_Pos) // 0x00002000 */
1686#define DOEPINT_NAK DOEPINT_NAK_Msk // NAK Packet is transmitted by the device */
1687#define DOEPINT_NYET_Pos (14U)
1688#define DOEPINT_NYET_Msk (0x1UL << DOEPINT_NYET_Pos) // 0x00004000 */
1689#define DOEPINT_NYET DOEPINT_NYET_Msk // NYET interrupt */
1690#define DOEPINT_STPKTRX_Pos (15U)
1691#define DOEPINT_STPKTRX_Msk (0x1UL << DOEPINT_STPKTRX_Pos) // 0x00008000 */
1692#define DOEPINT_STPKTRX DOEPINT_STPKTRX_Msk // Setup Packet Received */
1693
1694/******************** Bit definition for DOEPTSIZ register ********************/
1695#define DOEPTSIZ_XFRSIZ_Pos (0U)
1696#define DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos) // 0x0007FFFF */
1697#define DOEPTSIZ_XFRSIZ DOEPTSIZ_XFRSIZ_Msk // Transfer size */
1698#define DOEPTSIZ_PKTCNT_Pos (19U)
1699#define DOEPTSIZ_PKTCNT_Msk (0x3FFUL << DOEPTSIZ_PKTCNT_Pos) // 0x1FF80000 */
1700#define DOEPTSIZ_PKTCNT DOEPTSIZ_PKTCNT_Msk // Packet count */
1701
1702#define DOEPTSIZ_STUPCNT_Pos (29U)
1703#define DOEPTSIZ_STUPCNT_Msk (0x3UL << DOEPTSIZ_STUPCNT_Pos) // 0x60000000 */
1704#define DOEPTSIZ_STUPCNT DOEPTSIZ_STUPCNT_Msk // SETUP packet count */
1705#define DOEPTSIZ_STUPCNT_0 (0x1UL << DOEPTSIZ_STUPCNT_Pos) // 0x20000000 */
1706#define DOEPTSIZ_STUPCNT_1 (0x2UL << DOEPTSIZ_STUPCNT_Pos) // 0x40000000 */
1707
1708/******************** Bit definition for PCGCTL register ********************/
1709#define PCGCTL_IF_DEV_MODE TU_BIT(31)
1710#define PCGCTL_P2HD_PRT_SPD_MASK (0x3ul << 29)
1711#define PCGCTL_P2HD_PRT_SPD_SHIFT 29
1712#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3ul << 27)
1713#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
1714#define PCGCTL_MAC_DEV_ADDR_MASK (0x7ful << 20)
1715#define PCGCTL_MAC_DEV_ADDR_SHIFT 20
1716#define PCGCTL_MAX_TERMSEL TU_BIT(19)
1717#define PCGCTL_MAX_XCVRSELECT_MASK (0x3ul << 17)
1718#define PCGCTL_MAX_XCVRSELECT_SHIFT 17
1719#define PCGCTL_PORT_POWER TU_BIT(16)
1720#define PCGCTL_PRT_CLK_SEL_MASK (0x3ul << 14)
1721#define PCGCTL_PRT_CLK_SEL_SHIFT 14
1722#define PCGCTL_ESS_REG_RESTORED TU_BIT(13)
1723#define PCGCTL_EXTND_HIBER_SWITCH TU_BIT(12)
1724#define PCGCTL_EXTND_HIBER_PWRCLMP TU_BIT(11)
1725#define PCGCTL_ENBL_EXTND_HIBER TU_BIT(10)
1726#define PCGCTL_RESTOREMODE TU_BIT(9)
1727#define PCGCTL_RESETAFTSUSP TU_BIT(8)
1728#define PCGCTL_DEEP_SLEEP TU_BIT(7)
1729#define PCGCTL_PHY_IN_SLEEP TU_BIT(6)
1730#define PCGCTL_ENBL_SLEEP_GATING TU_BIT(5)
1731#define PCGCTL_RSTPDWNMODULE TU_BIT(3)
1732#define PCGCTL_PWRCLMP TU_BIT(2)
1733#define PCGCTL_GATEHCLK TU_BIT(1)
1734#define PCGCTL_STOPPCLK TU_BIT(0)
1735
1736#define PCGCTL1_TIMER (0x3ul << 1)
1737#define PCGCTL1_GATEEN TU_BIT(0)
1738
1739#ifdef __cplusplus
1740 }
1741#endif
1742
1743#endif
TU_ATTR_PACKED
AUDIO Channel Cluster Descriptor (4.1)
Definition audio.h:647
dwc2_channel_t
Definition dwc2_type.h:154
dwc2_controller_t
Definition dwc2_type.h:28
dwc2_epin_t
Definition dwc2_type.h:167
dwc2_epout_t
Definition dwc2_type.h:180
dwc2_regs_t
Definition dwc2_type.h:191