31#ifndef _FM3_ETH1_DRIVER_H
32#define _FM3_ETH1_DRIVER_H
38#ifndef FM3_ETH1_TX_BUFFER_COUNT
39 #define FM3_ETH1_TX_BUFFER_COUNT 3
40#elif (FM3_ETH1_TX_BUFFER_COUNT < 1)
41 #error FM3_ETH1_TX_BUFFER_COUNT parameter is not valid
45#ifndef FM3_ETH1_TX_BUFFER_SIZE
46 #define FM3_ETH1_TX_BUFFER_SIZE 1536
47#elif (FM3_ETH1_TX_BUFFER_SIZE != 1536)
48 #error FM3_ETH1_TX_BUFFER_SIZE parameter is not valid
52#ifndef FM3_ETH1_RX_BUFFER_COUNT
53 #define FM3_ETH1_RX_BUFFER_COUNT 6
54#elif (FM3_ETH1_RX_BUFFER_COUNT < 1)
55 #error FM3_ETH1_RX_BUFFER_COUNT parameter is not valid
59#ifndef FM3_ETH1_RX_BUFFER_SIZE
60 #define FM3_ETH1_RX_BUFFER_SIZE 1536
61#elif (FM3_ETH1_RX_BUFFER_SIZE != 1536)
62 #error FM3_ETH1_RX_BUFFER_SIZE parameter is not valid
66#ifndef FM3_ETH1_IRQ_PRIORITY_GROUPING
67 #define FM3_ETH1_IRQ_PRIORITY_GROUPING 3
68#elif (FM3_ETH1_IRQ_PRIORITY_GROUPING < 0)
69 #error FM3_ETH1_IRQ_PRIORITY_GROUPING parameter is not valid
73#ifndef FM3_ETH1_IRQ_GROUP_PRIORITY
74 #define FM3_ETH1_IRQ_GROUP_PRIORITY 12
75#elif (FM3_ETH1_IRQ_GROUP_PRIORITY < 0)
76 #error FM3_ETH1_IRQ_GROUP_PRIORITY parameter is not valid
80#ifndef FM3_ETH1_IRQ_SUB_PRIORITY
81 #define FM3_ETH1_IRQ_SUB_PRIORITY 0
82#elif (FM3_ETH1_IRQ_SUB_PRIORITY < 0)
83 #error FM3_ETH1_IRQ_SUB_PRIORITY parameter is not valid
87#define ETH_SR_GLPII 0x40000000
88#define ETH_SR_TTI 0x20000000
89#define ETH_SR_GPI 0x10000000
90#define ETH_SR_GMI 0x08000000
91#define ETH_SR_GLI 0x04000000
92#define ETH_SR_EB 0x03800000
93#define ETH_SR_TS 0x00700000
94#define ETH_SR_RS 0x000E0000
95#define ETH_SR_NIS 0x00010000
96#define ETH_SR_AIS 0x00008000
97#define ETH_SR_ERI 0x00004000
98#define ETH_SR_FBI 0x00002000
99#define ETH_SR_ETI 0x00000400
100#define ETH_SR_RWT 0x00000200
101#define ETH_SR_RPS 0x00000100
102#define ETH_SR_RU 0x00000080
103#define ETH_SR_RI 0x00000040
104#define ETH_SR_UNF 0x00000020
105#define ETH_SR_OVF 0x00000010
106#define ETH_SR_TJT 0x00000008
107#define ETH_SR_TU 0x00000004
108#define ETH_SR_TPS 0x00000002
109#define ETH_SR_TI 0x00000001
112#define ETH_TDES0_OWN 0x80000000
113#define ETH_TDES0_IC 0x40000000
114#define ETH_TDES0_LS 0x20000000
115#define ETH_TDES0_FS 0x10000000
116#define ETH_TDES0_DC 0x08000000
117#define ETH_TDES0_DP 0x04000000
118#define ETH_TDES0_TTSE 0x02000000
119#define ETH_TDES0_CIC 0x00C00000
120#define ETH_TDES0_TER 0x00200000
121#define ETH_TDES0_TCH 0x00100000
122#define ETH_TDES0_TTSS 0x00020000
123#define ETH_TDES0_IHE 0x00010000
124#define ETH_TDES0_ES 0x00008000
125#define ETH_TDES0_JT 0x00004000
126#define ETH_TDES0_FF 0x00002000
127#define ETH_TDES0_IPE 0x00001000
128#define ETH_TDES0_LCA 0x00000800
129#define ETH_TDES0_NC 0x00000400
130#define ETH_TDES0_LCO 0x00000200
131#define ETH_TDES0_EC 0x00000100
132#define ETH_TDES0_VF 0x00000080
133#define ETH_TDES0_CC 0x00000078
134#define ETH_TDES0_ED 0x00000004
135#define ETH_TDES0_UF 0x00000002
136#define ETH_TDES0_DB 0x00000001
137#define ETH_TDES1_TBS2 0x1FFF0000
138#define ETH_TDES1_TBS1 0x00001FFF
139#define ETH_TDES2_B1AP 0xFFFFFFFF
140#define ETH_TDES3_B2AP 0xFFFFFFFF
141#define ETH_TDES6_TTSL 0xFFFFFFFF
142#define ETH_TDES7_TTSH 0xFFFFFFFF
145#define ETH_RDES0_OWN 0x80000000
146#define ETH_RDES0_AFM 0x40000000
147#define ETH_RDES0_FL 0x3FFF0000
148#define ETH_RDES0_ES 0x00008000
149#define ETH_RDES0_DE 0x00004000
150#define ETH_RDES0_SAF 0x00002000
151#define ETH_RDES0_LE 0x00001000
152#define ETH_RDES0_OE 0x00000800
153#define ETH_RDES0_VLAN 0x00000400
154#define ETH_RDES0_FS 0x00000200
155#define ETH_RDES0_LS 0x00000100
156#define ETH_RDES0_TS 0x00000080
157#define ETH_RDES0_LCO 0x00000040
158#define ETH_RDES0_FT 0x00000020
159#define ETH_RDES0_RWT 0x00000010
160#define ETH_RDES0_RE 0x00000008
161#define ETH_RDES0_DBE 0x00000004
162#define ETH_RDES0_CE 0x00000002
163#define ETH_RDES0_ESA 0x00000001
164#define ETH_RDES1_DIC 0x80000000
165#define ETH_RDES1_RBS2 0x1FFF0000
166#define ETH_RDES1_RER 0x00008000
167#define ETH_RDES1_RCH 0x00004000
168#define ETH_RDES1_RBS1 0x00001FFF
169#define ETH_RDES2_B1AP 0xFFFFFFFF
170#define ETH_RDES3_B2AP 0xFFFFFFFF
171#define ETH_RDES4_TD 0x00004000
172#define ETH_RDES4_PV 0x00002000
173#define ETH_RDES4_PFT 0x00001000
174#define ETH_RDES4_MT 0x00000F00
175#define ETH_RDES4_IP6R 0x00000080
176#define ETH_RDES4_IP4R 0x00000040
177#define ETH_RDES4_IPCB 0x00000020
178#define ETH_RDES4_IPE 0x00000010
179#define ETH_RDES4_IPHE 0x00000008
180#define ETH_RDES4_IPT 0x00000007
181#define ETH_RDES6_RTSL 0xFFFFFFFF
182#define ETH_RDES7_RTSH 0xFFFFFFFF
228error_t fm3Eth1Init(NetInterface *interface);
229void fm3Eth1InitGpio(NetInterface *interface);
230void fm3Eth1InitDmaDesc(NetInterface *interface);
232void fm3Eth1Tick(NetInterface *interface);
234void fm3Eth1EnableIrq(NetInterface *interface);
235void fm3Eth1DisableIrq(NetInterface *interface);
236void fm3Eth1EventHandler(NetInterface *interface);
238error_t fm3Eth1SendPacket(NetInterface *interface,
239 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
241error_t fm3Eth1ReceivePacket(NetInterface *interface);
243error_t fm3Eth1UpdateMacAddrFilter(NetInterface *interface);
244error_t fm3Eth1UpdateMacConfig(NetInterface *interface);
246void fm3Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr,
247 uint8_t regAddr, uint16_t data);
249uint16_t fm3Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
252uint32_t fm3Eth1CalcCrc(
const void *data,
size_t length);
error_t
Error codes.
Definition error.h:43
Network interface controller abstraction layer.
Enhanced RX DMA descriptor.
Definition fm3_eth1_driver.h:212
Enhanced TX DMA descriptor.
Definition fm3_eth1_driver.h:195
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283