31#ifndef _GD32F3XX_ETH_DRIVER_H
32#define _GD32F3XX_ETH_DRIVER_H
38#ifndef GD32F3XX_ETH_TX_BUFFER_COUNT
39 #define GD32F3XX_ETH_TX_BUFFER_COUNT 3
40#elif (GD32F3XX_ETH_TX_BUFFER_COUNT < 1)
41 #error GD32F3XX_ETH_TX_BUFFER_COUNT parameter is not valid
45#ifndef GD32F3XX_ETH_TX_BUFFER_SIZE
46 #define GD32F3XX_ETH_TX_BUFFER_SIZE 1536
47#elif (GD32F3XX_ETH_TX_BUFFER_SIZE != 1536)
48 #error GD32F3XX_ETH_TX_BUFFER_SIZE parameter is not valid
52#ifndef GD32F3XX_ETH_RX_BUFFER_COUNT
53 #define GD32F3XX_ETH_RX_BUFFER_COUNT 6
54#elif (GD32F3XX_ETH_RX_BUFFER_COUNT < 1)
55 #error GD32F3XX_ETH_RX_BUFFER_COUNT parameter is not valid
59#ifndef GD32F3XX_ETH_RX_BUFFER_SIZE
60 #define GD32F3XX_ETH_RX_BUFFER_SIZE 1536
61#elif (GD32F3XX_ETH_RX_BUFFER_SIZE != 1536)
62 #error GD32F3XX_ETH_RX_BUFFER_SIZE parameter is not valid
66#ifndef GD32F3XX_ETH_IRQ_PRIORITY_GROUPING
67 #define GD32F3XX_ETH_IRQ_PRIORITY_GROUPING 3
68#elif (GD32F3XX_ETH_IRQ_PRIORITY_GROUPING < 0)
69 #error GD32F3XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
73#ifndef GD32F3XX_ETH_IRQ_GROUP_PRIORITY
74 #define GD32F3XX_ETH_IRQ_GROUP_PRIORITY 12
75#elif (GD32F3XX_ETH_IRQ_GROUP_PRIORITY < 0)
76 #error GD32F3XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
80#ifndef GD32F3XX_ETH_IRQ_SUB_PRIORITY
81 #define GD32F3XX_ETH_IRQ_SUB_PRIORITY 0
82#elif (GD32F3XX_ETH_IRQ_SUB_PRIORITY < 0)
83 #error GD32F3XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
130error_t gd32f3xxEthInit(NetInterface *interface);
131void gd32f3xxEthInitGpio(NetInterface *interface);
132void gd32f3xxEthInitDmaDesc(NetInterface *interface);
134void gd32f3xxEthTick(NetInterface *interface);
136void gd32f3xxEthEnableIrq(NetInterface *interface);
137void gd32f3xxEthDisableIrq(NetInterface *interface);
138void gd32f3xxEthEventHandler(NetInterface *interface);
140error_t gd32f3xxEthSendPacket(NetInterface *interface,
141 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
143error_t gd32f3xxEthReceivePacket(NetInterface *interface);
145error_t gd32f3xxEthUpdateMacAddrFilter(NetInterface *interface);
146error_t gd32f3xxEthUpdateMacConfig(NetInterface *interface);
148void gd32f3xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
149 uint8_t regAddr, uint16_t data);
151uint16_t gd32f3xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
154uint32_t gd32f3xxEthCalcCrc(
const void *data,
size_t length);
error_t
Error codes.
Definition error.h:43
Network interface controller abstraction layer.
Enhanced RX DMA descriptor.
Definition gd32f3xx_eth_driver.h:114
Enhanced TX DMA descriptor.
Definition gd32f3xx_eth_driver.h:97
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283