mikroSDK Reference Manual
Macros
RCCEx Force Release Peripheral Reset
STM32F1xx_HAL_Driver | STM32F2xx_HAL_Driver | STM32F4xx_HAL_Driver | STM32F7xx_HAL_Driver | STM32H7xx_HAL_Driver » RCCEx » RCCEx Exported Macros

Forces or releases AHB/APB peripheral reset. More...

Macros

#define __HAL_RCC_DMA2_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
 Force or release AHB1 peripheral reset.
 
#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
 
#define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
 
#define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
 
#define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
 
#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
 
#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
 
#define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
 
#define __HAL_RCC_GPIOG_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
 
#define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
 
#define __HAL_RCC_GPIOI_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
 
#define __HAL_RCC_DMA2_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
 
#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
 
#define __HAL_RCC_GPIOA_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
 
#define __HAL_RCC_GPIOB_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
 
#define __HAL_RCC_GPIOC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
 
#define __HAL_RCC_GPIOD_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
 
#define __HAL_RCC_GPIOE_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
 
#define __HAL_RCC_GPIOF_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
 
#define __HAL_RCC_GPIOG_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
 
#define __HAL_RCC_GPIOH_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
 
#define __HAL_RCC_GPIOI_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
 
#define __HAL_RCC_AHB2_FORCE_RESET()   (RCC->AHB2RSTR = 0xFFFFFFFFU)
 Force or release AHB2 peripheral reset.
 
#define __HAL_RCC_RNG_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
 
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
 
#define __HAL_RCC_AHB2_RELEASE_RESET()   (RCC->AHB2RSTR = 0x00U)
 
#define __HAL_RCC_RNG_RELEASE_RESET()   (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
 
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()   (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
 
#define __HAL_RCC_AHB3_FORCE_RESET()   (RCC->AHB3RSTR = 0xFFFFFFFFU)
 Force or release AHB3 peripheral reset.
 
#define __HAL_RCC_FMC_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
 
#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
 
#define __HAL_RCC_AHB3_RELEASE_RESET()   (RCC->AHB3RSTR = 0x00U)
 
#define __HAL_RCC_FMC_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
 
#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
 
#define __HAL_RCC_TIM2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
 Force or release APB1 peripheral reset.
 
#define __HAL_RCC_TIM3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
 
#define __HAL_RCC_TIM4_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
 
#define __HAL_RCC_TIM5_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
 
#define __HAL_RCC_TIM6_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
 
#define __HAL_RCC_TIM7_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
 
#define __HAL_RCC_TIM12_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
 
#define __HAL_RCC_TIM13_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
 
#define __HAL_RCC_TIM14_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
 
#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
 
#define __HAL_RCC_SPI2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
 
#define __HAL_RCC_SPI3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
 
#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
 
#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
 
#define __HAL_RCC_UART4_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
 
#define __HAL_RCC_UART5_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
 
#define __HAL_RCC_I2C1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
 
#define __HAL_RCC_I2C2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
 
#define __HAL_RCC_I2C3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
 
#define __HAL_RCC_CAN1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
 
#define __HAL_RCC_DAC_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
 
#define __HAL_RCC_UART7_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
 
#define __HAL_RCC_UART8_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
 
#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
 
#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
 
#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
 
#define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
 
#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
 
#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
 
#define __HAL_RCC_TIM12_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
 
#define __HAL_RCC_TIM13_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
 
#define __HAL_RCC_TIM14_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
 
#define __HAL_RCC_LPTIM1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
 
#define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
 
#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
 
#define __HAL_RCC_USART2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
 
#define __HAL_RCC_USART3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
 
#define __HAL_RCC_UART4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
 
#define __HAL_RCC_UART5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
 
#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
 
#define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
 
#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
 
#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
 
#define __HAL_RCC_DAC_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
 
#define __HAL_RCC_UART7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
 
#define __HAL_RCC_UART8_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
 
#define __HAL_RCC_TIM1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
 Force or release APB2 peripheral reset.
 
#define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
 
#define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
 
#define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
 
#define __HAL_RCC_ADC_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
 
#define __HAL_RCC_SDMMC1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
 
#define __HAL_RCC_SPI1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
 
#define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
 
#define __HAL_RCC_TIM9_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
 
#define __HAL_RCC_TIM10_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
 
#define __HAL_RCC_TIM11_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
 
#define __HAL_RCC_SPI5_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
 
#define __HAL_RCC_SPI6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
 
#define __HAL_RCC_SAI1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
 
#define __HAL_RCC_SAI2_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
 
#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
 
#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
 
#define __HAL_RCC_USART1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
 
#define __HAL_RCC_USART6_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
 
#define __HAL_RCC_ADC_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
 
#define __HAL_RCC_SDMMC1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
 
#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
 
#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
 
#define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
 
#define __HAL_RCC_TIM10_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
 
#define __HAL_RCC_TIM11_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
 
#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
 
#define __HAL_RCC_SPI6_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
 
#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
 
#define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))