mikroSDK Reference Manual
Macros
Peripheral Clock Enable Disable
STM32F1xx_HAL_Driver | STM32F2xx_HAL_Driver | STM32F4xx_HAL_Driver | STM32F7xx_HAL_Driver | STM32H7xx_HAL_Driver » RCCEx » RCCEx Exported Macros

Enable or disable the AHB1 peripheral clock. More...

Macros

#define __HAL_RCC_BKPSRAM_CLK_ENABLE()
 Enables or disables the AHB1 peripheral clock.
 
#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE()
 
#define __HAL_RCC_DMA2_CLK_ENABLE()
 
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()
 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()
 
#define __HAL_RCC_GPIOA_CLK_ENABLE()
 
#define __HAL_RCC_GPIOB_CLK_ENABLE()
 
#define __HAL_RCC_GPIOC_CLK_ENABLE()
 
#define __HAL_RCC_GPIOD_CLK_ENABLE()
 
#define __HAL_RCC_GPIOE_CLK_ENABLE()
 
#define __HAL_RCC_GPIOF_CLK_ENABLE()
 
#define __HAL_RCC_GPIOG_CLK_ENABLE()
 
#define __HAL_RCC_GPIOH_CLK_ENABLE()
 
#define __HAL_RCC_GPIOI_CLK_ENABLE()
 
#define __HAL_RCC_BKPSRAM_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
 
#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
 
#define __HAL_RCC_DMA2_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
 
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
 
#define __HAL_RCC_GPIOA_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
 
#define __HAL_RCC_GPIOB_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
 
#define __HAL_RCC_GPIOC_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
 
#define __HAL_RCC_GPIOD_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
 
#define __HAL_RCC_GPIOE_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
 
#define __HAL_RCC_GPIOF_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
 
#define __HAL_RCC_GPIOG_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
 
#define __HAL_RCC_GPIOH_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
 
#define __HAL_RCC_GPIOI_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
 
#define __HAL_RCC_RNG_CLK_ENABLE()
 Enable or disable the AHB2 peripheral clock.
 
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
 
#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
 
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
 
#define __HAL_RCC_FMC_CLK_ENABLE()
 Enables or disables the AHB3 peripheral clock.
 
#define __HAL_RCC_QSPI_CLK_ENABLE()
 
#define __HAL_RCC_FMC_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
 
#define __HAL_RCC_QSPI_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
 
#define __HAL_RCC_TIM2_CLK_ENABLE()
 Enable or disable the Low Speed APB (APB1) peripheral clock.
 
#define __HAL_RCC_TIM3_CLK_ENABLE()
 
#define __HAL_RCC_TIM4_CLK_ENABLE()
 
#define __HAL_RCC_TIM5_CLK_ENABLE()
 
#define __HAL_RCC_TIM6_CLK_ENABLE()
 
#define __HAL_RCC_TIM7_CLK_ENABLE()
 
#define __HAL_RCC_TIM12_CLK_ENABLE()
 
#define __HAL_RCC_TIM13_CLK_ENABLE()
 
#define __HAL_RCC_TIM14_CLK_ENABLE()
 
#define __HAL_RCC_LPTIM1_CLK_ENABLE()
 
#define __HAL_RCC_SPI2_CLK_ENABLE()
 
#define __HAL_RCC_SPI3_CLK_ENABLE()
 
#define __HAL_RCC_USART2_CLK_ENABLE()
 
#define __HAL_RCC_USART3_CLK_ENABLE()
 
#define __HAL_RCC_UART4_CLK_ENABLE()
 
#define __HAL_RCC_UART5_CLK_ENABLE()
 
#define __HAL_RCC_I2C1_CLK_ENABLE()
 
#define __HAL_RCC_I2C2_CLK_ENABLE()
 
#define __HAL_RCC_I2C3_CLK_ENABLE()
 
#define __HAL_RCC_CAN1_CLK_ENABLE()
 
#define __HAL_RCC_DAC_CLK_ENABLE()
 
#define __HAL_RCC_UART7_CLK_ENABLE()
 
#define __HAL_RCC_UART8_CLK_ENABLE()
 
#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
 
#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
 
#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
 
#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
 
#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
 
#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
 
#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
 
#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
 
#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
 
#define __HAL_RCC_LPTIM1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
 
#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
 
#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
 
#define __HAL_RCC_USART2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 
#define __HAL_RCC_USART3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
 
#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
 
#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
 
#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
 
#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
 
#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
 
#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
 
#define __HAL_RCC_DAC_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
 
#define __HAL_RCC_UART7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
 
#define __HAL_RCC_UART8_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
 
#define __HAL_RCC_TIM1_CLK_ENABLE()
 Enable or disable the High Speed APB (APB2) peripheral clock.
 
#define __HAL_RCC_TIM8_CLK_ENABLE()
 
#define __HAL_RCC_USART1_CLK_ENABLE()
 
#define __HAL_RCC_USART6_CLK_ENABLE()
 
#define __HAL_RCC_ADC1_CLK_ENABLE()
 
#define __HAL_RCC_ADC2_CLK_ENABLE()
 
#define __HAL_RCC_ADC3_CLK_ENABLE()
 
#define __HAL_RCC_SDMMC1_CLK_ENABLE()
 
#define __HAL_RCC_SPI1_CLK_ENABLE()
 
#define __HAL_RCC_SPI4_CLK_ENABLE()
 
#define __HAL_RCC_TIM9_CLK_ENABLE()
 
#define __HAL_RCC_TIM10_CLK_ENABLE()
 
#define __HAL_RCC_TIM11_CLK_ENABLE()
 
#define __HAL_RCC_SPI5_CLK_ENABLE()
 
#define __HAL_RCC_SPI6_CLK_ENABLE()
 
#define __HAL_RCC_SAI1_CLK_ENABLE()
 
#define __HAL_RCC_SAI2_CLK_ENABLE()
 
#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
 
#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
 
#define __HAL_RCC_USART1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
 
#define __HAL_RCC_USART6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
 
#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 
#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
 
#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
 
#define __HAL_RCC_SDMMC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
 
#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 
#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
 
#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
 
#define __HAL_RCC_TIM10_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
 
#define __HAL_RCC_TIM11_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
 
#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
 
#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
 
#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
 
#define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
 

Macro Definition Documentation

◆ __HAL_RCC_ADC1_CLK_ENABLE

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0)
__IO
#define __IO
Definition core_cm3.h:170
RCC_APB2ENR_ADC1EN
#define RCC_APB2ENR_ADC1EN
Definition stm32f107xc.h:1789

◆ __HAL_RCC_ADC2_CLK_ENABLE

#define __HAL_RCC_ADC2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_ADC2EN
#define RCC_APB2ENR_ADC2EN
Definition stm32f107xc.h:1793

◆ __HAL_RCC_ADC3_CLK_ENABLE

#define __HAL_RCC_ADC3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_BKPSRAM_CLK_ENABLE

#define __HAL_RCC_BKPSRAM_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
UNUSED(tmpreg); \
} while(0)
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_CAN1_CLK_ENABLE

#define __HAL_RCC_CAN1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_CAN1EN
#define RCC_APB1ENR_CAN1EN
Definition stm32f107xc.h:1832

◆ __HAL_RCC_DAC_CLK_ENABLE

#define __HAL_RCC_DAC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_DACEN
#define RCC_APB1ENR_DACEN
Definition stm32f107xc.h:1882

◆ __HAL_RCC_DMA2_CLK_ENABLE

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_DTCMRAMEN_CLK_ENABLE

#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_FMC_CLK_ENABLE

#define __HAL_RCC_FMC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
UNUSED(tmpreg); \
} while(0)
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_GPIOA_CLK_ENABLE

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOB_CLK_ENABLE

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOC_CLK_ENABLE

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOD_CLK_ENABLE

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOE_CLK_ENABLE

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOF_CLK_ENABLE

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOG_CLK_ENABLE

#define __HAL_RCC_GPIOG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOH_CLK_ENABLE

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOI_CLK_ENABLE

#define __HAL_RCC_GPIOI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_I2C1_CLK_ENABLE

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_I2C1EN
#define RCC_APB1ENR_I2C1EN
Definition stm32f107xc.h:1828

◆ __HAL_RCC_I2C2_CLK_ENABLE

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_I2C2EN
#define RCC_APB1ENR_I2C2EN
Definition stm32f107xc.h:1852

◆ __HAL_RCC_I2C3_CLK_ENABLE

#define __HAL_RCC_I2C3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_LPTIM1_CLK_ENABLE

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_QSPI_CLK_ENABLE

#define __HAL_RCC_QSPI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_RNG_CLK_ENABLE

#define __HAL_RCC_RNG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
UNUSED(tmpreg); \
} while(0)
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_SAI1_CLK_ENABLE

#define __HAL_RCC_SAI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_SAI2_CLK_ENABLE

#define __HAL_RCC_SAI2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_SDMMC1_CLK_ENABLE

#define __HAL_RCC_SDMMC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_SPI1_CLK_ENABLE

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_SPI1EN
#define RCC_APB2ENR_SPI1EN
Definition stm32f107xc.h:1800

◆ __HAL_RCC_SPI2_CLK_ENABLE

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_SPI2EN
#define RCC_APB1ENR_SPI2EN
Definition stm32f107xc.h:1846

◆ __HAL_RCC_SPI3_CLK_ENABLE

#define __HAL_RCC_SPI3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_SPI3EN
#define RCC_APB1ENR_SPI3EN
Definition stm32f107xc.h:1866

◆ __HAL_RCC_SPI4_CLK_ENABLE

#define __HAL_RCC_SPI4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_SPI5_CLK_ENABLE

#define __HAL_RCC_SPI5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_SPI6_CLK_ENABLE

#define __HAL_RCC_SPI6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM10_CLK_ENABLE

#define __HAL_RCC_TIM10_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM11_CLK_ENABLE

#define __HAL_RCC_TIM11_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM12_CLK_ENABLE

#define __HAL_RCC_TIM12_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM13_CLK_ENABLE

#define __HAL_RCC_TIM13_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM14_CLK_ENABLE

#define __HAL_RCC_TIM14_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM1_CLK_ENABLE

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_TIM1EN
#define RCC_APB2ENR_TIM1EN
Definition stm32f107xc.h:1797
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_TIM2_CLK_ENABLE

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_TIM2EN
#define RCC_APB1ENR_TIM2EN
Definition stm32f107xc.h:1816
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_TIM3_CLK_ENABLE

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_TIM3EN
#define RCC_APB1ENR_TIM3EN
Definition stm32f107xc.h:1819

◆ __HAL_RCC_TIM4_CLK_ENABLE

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_TIM4EN
#define RCC_APB1ENR_TIM4EN
Definition stm32f107xc.h:1843

◆ __HAL_RCC_TIM5_CLK_ENABLE

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_TIM5EN
#define RCC_APB1ENR_TIM5EN
Definition stm32f107xc.h:1857

◆ __HAL_RCC_TIM6_CLK_ENABLE

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_TIM6EN
#define RCC_APB1ENR_TIM6EN
Definition stm32f107xc.h:1860

◆ __HAL_RCC_TIM7_CLK_ENABLE

#define __HAL_RCC_TIM7_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_TIM7EN
#define RCC_APB1ENR_TIM7EN
Definition stm32f107xc.h:1863

◆ __HAL_RCC_TIM8_CLK_ENABLE

#define __HAL_RCC_TIM8_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM9_CLK_ENABLE

#define __HAL_RCC_TIM9_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_UART4_CLK_ENABLE

#define __HAL_RCC_UART4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_UART4EN
#define RCC_APB1ENR_UART4EN
Definition stm32f107xc.h:1869

◆ __HAL_RCC_UART5_CLK_ENABLE

#define __HAL_RCC_UART5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_UART5EN
#define RCC_APB1ENR_UART5EN
Definition stm32f107xc.h:1872

◆ __HAL_RCC_UART7_CLK_ENABLE

#define __HAL_RCC_UART7_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_UART8_CLK_ENABLE

#define __HAL_RCC_UART8_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_USART1_CLK_ENABLE

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_USART1EN
#define RCC_APB2ENR_USART1EN
Definition stm32f107xc.h:1803

◆ __HAL_RCC_USART2_CLK_ENABLE

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_USART2EN
#define RCC_APB1ENR_USART2EN
Definition stm32f107xc.h:1825

◆ __HAL_RCC_USART3_CLK_ENABLE

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_USART3EN
#define RCC_APB1ENR_USART3EN
Definition stm32f107xc.h:1849

◆ __HAL_RCC_USART6_CLK_ENABLE

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_USB_OTG_FS_CLK_ENABLE

#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
UNUSED(tmpreg); \
__HAL_RCC_SYSCFG_CLK_ENABLE();\
} while(0)

◆ __HAL_RCC_USB_OTG_HS_CLK_ENABLE

#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE

#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
UNUSED(tmpreg); \
} while(0)