mikroSDK Reference Manual
Macros
Peripheral Clock Enable Disable Status
STM32F1xx_HAL_Driver | STM32F2xx_HAL_Driver | STM32F4xx_HAL_Driver | STM32F7xx_HAL_Driver | STM32H7xx_HAL_Driver » RCCEx » RCCEx Exported Macros

Get the enable or disable status of the AHB/APB peripheral clock. More...

Macros

#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
 Get the enable or disable status of the AHB1 peripheral clock.
 
#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
 
#define __HAL_RCC_DMA2_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
 
#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
 
#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
 
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
 
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
 
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
 
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
 
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
 
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
 
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
 
#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
 
#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
 
#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
 
#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
 
#define __HAL_RCC_DMA2_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
 
#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
 
#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
 
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
 
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
 
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
 
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
 
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
 
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
 
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
 
#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
 
#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
 
#define __HAL_RCC_RNG_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
 Get the enable or disable status of the AHB2 peripheral clock.
 
#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
 
#define __HAL_RCC_RNG_IS_CLK_DISABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
 
#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
 
#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
 Get the enable or disable status of the AHB3 peripheral clock.
 
#define __HAL_RCC_QSPI_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
 
#define __HAL_RCC_FMC_IS_CLK_DISABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
 
#define __HAL_RCC_QSPI_IS_CLK_DISABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
 
#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
 Get the enable or disable status of the APB1 peripheral clock.
 
#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
 
#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
 
#define __HAL_RCC_TIM5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
 
#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
 
#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
 
#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
 
#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
 
#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
 
#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
 
#define __HAL_RCC_SPI2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
 
#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
 
#define __HAL_RCC_USART2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
 
#define __HAL_RCC_USART3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
 
#define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
 
#define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
 
#define __HAL_RCC_I2C1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
 
#define __HAL_RCC_I2C2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
 
#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
 
#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
 
#define __HAL_RCC_DAC_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
 
#define __HAL_RCC_UART7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
 
#define __HAL_RCC_UART8_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
 
#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
 
#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
 
#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
 
#define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
 
#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
 
#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
 
#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
 
#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
 
#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
 
#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
 
#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
 
#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
 
#define __HAL_RCC_USART2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
 
#define __HAL_RCC_USART3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
 
#define __HAL_RCC_UART4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
 
#define __HAL_RCC_UART5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
 
#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
 
#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
 
#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
 
#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
 
#define __HAL_RCC_DAC_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
 
#define __HAL_RCC_UART7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
 
#define __HAL_RCC_UART8_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
 
#define __HAL_RCC_TIM1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
 Get the enable or disable status of the APB2 peripheral clock.
 
#define __HAL_RCC_TIM8_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
 
#define __HAL_RCC_USART1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
 
#define __HAL_RCC_USART6_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
 
#define __HAL_RCC_ADC1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
 
#define __HAL_RCC_ADC2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
 
#define __HAL_RCC_ADC3_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
 
#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
 
#define __HAL_RCC_SPI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
 
#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
 
#define __HAL_RCC_TIM9_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
 
#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
 
#define __HAL_RCC_TIM11_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
 
#define __HAL_RCC_SPI5_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
 
#define __HAL_RCC_SPI6_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
 
#define __HAL_RCC_SAI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
 
#define __HAL_RCC_SAI2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
 
#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
 
#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
 
#define __HAL_RCC_USART1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
 
#define __HAL_RCC_USART6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
 
#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
 
#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
 
#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
 
#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
 
#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
 
#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
 
#define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
 
#define __HAL_RCC_TIM10_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
 
#define __HAL_RCC_TIM11_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
 
#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
 
#define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
 
#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
 
#define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
 

Macro Definition Documentation

◆ __HAL_RCC_BKPSRAM_IS_CLK_ENABLED

#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED ( )    ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_FMC_IS_CLK_ENABLED

#define __HAL_RCC_FMC_IS_CLK_ENABLED ( )    ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_RNG_IS_CLK_ENABLED

#define __HAL_RCC_RNG_IS_CLK_ENABLED ( )    ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_TIM1_IS_CLK_ENABLED

#define __HAL_RCC_TIM1_IS_CLK_ENABLED ( )    ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_TIM2_IS_CLK_ENABLED

#define __HAL_RCC_TIM2_IS_CLK_ENABLED ( )    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.