Peripheral Configuration

Macros to configure clock source of different peripherals. More...

Macros
#define	__HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__)    MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
	Macro to configure the ADCx clock (x=1 to 3 depending on devices).
#define	__HAL_RCC_GET_ADC_SOURCE()   ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
	Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).

Macro Definition Documentation

__HAL_RCC_ADC_CONFIG

#define __HAL_RCC_ADC_CONFIG

(

__ADCCLKSOURCE__

)

MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))

Parameters

__ADCCLKSOURCE__

specifies the ADC clock source. This parameter can be one of the following values: RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock

__HAL_RCC_GET_ADC_SOURCE

#define __HAL_RCC_GET_ADC_SOURCE

(

)

((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))

Return values

The

clock source can be one of the following values: RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock