mikroSDK Reference Manual
Macros
AHB1 Peripheral Clock Enable Disable
STM32F1xx_HAL_Driver | STM32F2xx_HAL_Driver | STM32F4xx_HAL_Driver | STM32F7xx_HAL_Driver | STM32H7xx_HAL_Driver » RCC » RCC Exported Macros

Enable or disable the AHB1 peripheral clock. More...

Macros

#define __HAL_RCC_GPIOA_CLK_ENABLE()
 
#define __HAL_RCC_GPIOB_CLK_ENABLE()
 
#define __HAL_RCC_GPIOC_CLK_ENABLE()
 
#define __HAL_RCC_GPIOD_CLK_ENABLE()
 
#define __HAL_RCC_GPIOE_CLK_ENABLE()
 
#define __HAL_RCC_GPIOF_CLK_ENABLE()
 
#define __HAL_RCC_GPIOG_CLK_ENABLE()
 
#define __HAL_RCC_GPIOH_CLK_ENABLE()
 
#define __HAL_RCC_GPIOI_CLK_ENABLE()
 
#define __HAL_RCC_CRC_CLK_ENABLE()
 
#define __HAL_RCC_BKPSRAM_CLK_ENABLE()
 
#define __HAL_RCC_DMA1_CLK_ENABLE()
 
#define __HAL_RCC_DMA2_CLK_ENABLE()
 
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()
 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()
 
#define __HAL_RCC_GPIOA_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
 
#define __HAL_RCC_GPIOB_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
 
#define __HAL_RCC_GPIOC_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
 
#define __HAL_RCC_GPIOD_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
 
#define __HAL_RCC_GPIOE_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
 
#define __HAL_RCC_GPIOF_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
 
#define __HAL_RCC_GPIOG_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
 
#define __HAL_RCC_GPIOH_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
 
#define __HAL_RCC_GPIOI_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
 
#define __HAL_RCC_CRC_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
 
#define __HAL_RCC_BKPSRAM_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
 
#define __HAL_RCC_DMA1_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
 
#define __HAL_RCC_DMA2_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
 
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
 
#define __HAL_RCC_GPIOA_CLK_ENABLE()
 
#define __HAL_RCC_GPIOB_CLK_ENABLE()
 
#define __HAL_RCC_GPIOC_CLK_ENABLE()
 
#define __HAL_RCC_GPIOH_CLK_ENABLE()
 
#define __HAL_RCC_DMA1_CLK_ENABLE()
 
#define __HAL_RCC_DMA2_CLK_ENABLE()
 
#define __HAL_RCC_GPIOA_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
 
#define __HAL_RCC_GPIOB_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
 
#define __HAL_RCC_GPIOC_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
 
#define __HAL_RCC_GPIOH_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
 
#define __HAL_RCC_DMA1_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
 
#define __HAL_RCC_DMA2_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
 
#define __HAL_RCC_CRC_CLK_ENABLE()
 
#define __HAL_RCC_DMA1_CLK_ENABLE()
 
#define __HAL_RCC_CRC_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
 
#define __HAL_RCC_DMA1_CLK_DISABLE()   (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
 

Macro Definition Documentation

◆ __HAL_RCC_BKPSRAM_CLK_ENABLE

#define __HAL_RCC_BKPSRAM_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
UNUSED(tmpreg); \
} while(0)
__IO
#define __IO
Definition core_cm3.h:170

◆ __HAL_RCC_CRC_CLK_ENABLE [1/2]

#define __HAL_RCC_CRC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_CRC_CLK_ENABLE [2/2]

#define __HAL_RCC_CRC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_DMA1_CLK_ENABLE [1/3]

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_DMA1_CLK_ENABLE [2/3]

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_DMA1_CLK_ENABLE [3/3]

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_DMA2_CLK_ENABLE [1/2]

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_DMA2_CLK_ENABLE [2/2]

#define __HAL_RCC_DMA2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_GPIOA_CLK_ENABLE [1/2]

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOA_CLK_ENABLE [2/2]

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_GPIOB_CLK_ENABLE [1/2]

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOB_CLK_ENABLE [2/2]

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_GPIOC_CLK_ENABLE [1/2]

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOC_CLK_ENABLE [2/2]

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_GPIOD_CLK_ENABLE

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOE_CLK_ENABLE

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOF_CLK_ENABLE

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOG_CLK_ENABLE

#define __HAL_RCC_GPIOG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOH_CLK_ENABLE [1/2]

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_GPIOH_CLK_ENABLE [2/2]

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_GPIOI_CLK_ENABLE

#define __HAL_RCC_GPIOI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_USB_OTG_HS_CLK_ENABLE

#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE

#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
UNUSED(tmpreg); \
} while(0)