mikroSDK Reference Manual
Macros
APB1 Clock Enable Disable
STM32F1xx_HAL_Driver | STM32F2xx_HAL_Driver | STM32F4xx_HAL_Driver | STM32F7xx_HAL_Driver | STM32H7xx_HAL_Driver » RCC » RCC Exported Macros

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Macros

#define __HAL_RCC_TIM2_CLK_ENABLE()
 
#define __HAL_RCC_TIM3_CLK_ENABLE()
 
#define __HAL_RCC_WWDG_CLK_ENABLE()
 
#define __HAL_RCC_USART2_CLK_ENABLE()
 
#define __HAL_RCC_I2C1_CLK_ENABLE()
 
#define __HAL_RCC_BKP_CLK_ENABLE()
 
#define __HAL_RCC_PWR_CLK_ENABLE()
 
#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
 
#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
 
#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 
#define __HAL_RCC_USART2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 
#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
 
#define __HAL_RCC_BKP_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
 
#define __HAL_RCC_PWR_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
 
#define __HAL_RCC_TIM2_CLK_ENABLE()
 
#define __HAL_RCC_TIM3_CLK_ENABLE()
 
#define __HAL_RCC_TIM4_CLK_ENABLE()
 
#define __HAL_RCC_TIM5_CLK_ENABLE()
 
#define __HAL_RCC_TIM6_CLK_ENABLE()
 
#define __HAL_RCC_TIM7_CLK_ENABLE()
 
#define __HAL_RCC_TIM12_CLK_ENABLE()
 
#define __HAL_RCC_TIM13_CLK_ENABLE()
 
#define __HAL_RCC_TIM14_CLK_ENABLE()
 
#define __HAL_RCC_WWDG_CLK_ENABLE()
 
#define __HAL_RCC_SPI2_CLK_ENABLE()
 
#define __HAL_RCC_SPI3_CLK_ENABLE()
 
#define __HAL_RCC_USART2_CLK_ENABLE()
 
#define __HAL_RCC_USART3_CLK_ENABLE()
 
#define __HAL_RCC_UART4_CLK_ENABLE()
 
#define __HAL_RCC_UART5_CLK_ENABLE()
 
#define __HAL_RCC_I2C1_CLK_ENABLE()
 
#define __HAL_RCC_I2C2_CLK_ENABLE()
 
#define __HAL_RCC_I2C3_CLK_ENABLE()
 
#define __HAL_RCC_CAN1_CLK_ENABLE()
 
#define __HAL_RCC_CAN2_CLK_ENABLE()
 
#define __HAL_RCC_PWR_CLK_ENABLE()
 
#define __HAL_RCC_DAC_CLK_ENABLE()
 
#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
 
#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
 
#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
 
#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
 
#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
 
#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
 
#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
 
#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
 
#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
 
#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 
#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
 
#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
 
#define __HAL_RCC_USART2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 
#define __HAL_RCC_USART3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
 
#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
 
#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
 
#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
 
#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
 
#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
 
#define __HAL_RCC_PWR_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
 
#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
 
#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
 
#define __HAL_RCC_DAC_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
 
#define __HAL_RCC_TIM5_CLK_ENABLE()
 
#define __HAL_RCC_WWDG_CLK_ENABLE()
 
#define __HAL_RCC_SPI2_CLK_ENABLE()
 
#define __HAL_RCC_USART2_CLK_ENABLE()
 
#define __HAL_RCC_I2C1_CLK_ENABLE()
 
#define __HAL_RCC_I2C2_CLK_ENABLE()
 
#define __HAL_RCC_PWR_CLK_ENABLE()
 
#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
 
#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 
#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
 
#define __HAL_RCC_USART2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
 
#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
 
#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
 
#define __HAL_RCC_PWR_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
 
#define __HAL_RCC_WWDG_CLK_ENABLE()
 
#define __HAL_RCC_PWR_CLK_ENABLE()
 
#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
 
#define __HAL_RCC_PWR_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
 

Macro Definition Documentation

◆ __HAL_RCC_BKP_CLK_ENABLE

#define __HAL_RCC_BKP_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
UNUSED(tmpreg); \
} while(0U)
__IO
#define __IO
Definition core_cm3.h:170
RCC_APB1ENR_BKPEN
#define RCC_APB1ENR_BKPEN
Definition stm32f107xc.h:1836

◆ __HAL_RCC_CAN1_CLK_ENABLE

#define __HAL_RCC_CAN1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_CAN1EN
#define RCC_APB1ENR_CAN1EN
Definition stm32f107xc.h:1832

◆ __HAL_RCC_CAN2_CLK_ENABLE

#define __HAL_RCC_CAN2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_CAN2EN
#define RCC_APB1ENR_CAN2EN
Definition stm32f107xc.h:1878

◆ __HAL_RCC_DAC_CLK_ENABLE

#define __HAL_RCC_DAC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_DACEN
#define RCC_APB1ENR_DACEN
Definition stm32f107xc.h:1882

◆ __HAL_RCC_I2C1_CLK_ENABLE [1/3]

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB1ENR_I2C1EN
#define RCC_APB1ENR_I2C1EN
Definition stm32f107xc.h:1828

◆ __HAL_RCC_I2C1_CLK_ENABLE [2/3]

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_I2C1_CLK_ENABLE [3/3]

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_I2C2_CLK_ENABLE [1/2]

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_I2C2EN
#define RCC_APB1ENR_I2C2EN
Definition stm32f107xc.h:1852

◆ __HAL_RCC_I2C2_CLK_ENABLE [2/2]

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_I2C3_CLK_ENABLE

#define __HAL_RCC_I2C3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_PWR_CLK_ENABLE [1/4]

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB1ENR_PWREN
#define RCC_APB1ENR_PWREN
Definition stm32f107xc.h:1839

◆ __HAL_RCC_PWR_CLK_ENABLE [2/4]

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_PWR_CLK_ENABLE [3/4]

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_PWR_CLK_ENABLE [4/4]

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_SPI2_CLK_ENABLE [1/2]

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_SPI2EN
#define RCC_APB1ENR_SPI2EN
Definition stm32f107xc.h:1846

◆ __HAL_RCC_SPI2_CLK_ENABLE [2/2]

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_SPI3_CLK_ENABLE

#define __HAL_RCC_SPI3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_SPI3EN
#define RCC_APB1ENR_SPI3EN
Definition stm32f107xc.h:1866

◆ __HAL_RCC_TIM12_CLK_ENABLE

#define __HAL_RCC_TIM12_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM13_CLK_ENABLE

#define __HAL_RCC_TIM13_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM14_CLK_ENABLE

#define __HAL_RCC_TIM14_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM2_CLK_ENABLE [1/2]

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB1ENR_TIM2EN
#define RCC_APB1ENR_TIM2EN
Definition stm32f107xc.h:1816

◆ __HAL_RCC_TIM2_CLK_ENABLE [2/2]

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM3_CLK_ENABLE [1/2]

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB1ENR_TIM3EN
#define RCC_APB1ENR_TIM3EN
Definition stm32f107xc.h:1819

◆ __HAL_RCC_TIM3_CLK_ENABLE [2/2]

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM4_CLK_ENABLE

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_TIM4EN
#define RCC_APB1ENR_TIM4EN
Definition stm32f107xc.h:1843

◆ __HAL_RCC_TIM5_CLK_ENABLE [1/2]

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_TIM5EN
#define RCC_APB1ENR_TIM5EN
Definition stm32f107xc.h:1857

◆ __HAL_RCC_TIM5_CLK_ENABLE [2/2]

#define __HAL_RCC_TIM5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_TIM6_CLK_ENABLE

#define __HAL_RCC_TIM6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_TIM6EN
#define RCC_APB1ENR_TIM6EN
Definition stm32f107xc.h:1860

◆ __HAL_RCC_TIM7_CLK_ENABLE

#define __HAL_RCC_TIM7_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_TIM7EN
#define RCC_APB1ENR_TIM7EN
Definition stm32f107xc.h:1863

◆ __HAL_RCC_UART4_CLK_ENABLE

#define __HAL_RCC_UART4_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_UART4EN
#define RCC_APB1ENR_UART4EN
Definition stm32f107xc.h:1869

◆ __HAL_RCC_UART5_CLK_ENABLE

#define __HAL_RCC_UART5_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_UART5EN
#define RCC_APB1ENR_UART5EN
Definition stm32f107xc.h:1872

◆ __HAL_RCC_USART2_CLK_ENABLE [1/3]

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB1ENR_USART2EN
#define RCC_APB1ENR_USART2EN
Definition stm32f107xc.h:1825

◆ __HAL_RCC_USART2_CLK_ENABLE [2/3]

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_USART2_CLK_ENABLE [3/3]

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_USART3_CLK_ENABLE

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB1ENR_USART3EN
#define RCC_APB1ENR_USART3EN
Definition stm32f107xc.h:1849

◆ __HAL_RCC_WWDG_CLK_ENABLE [1/4]

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB1ENR_WWDGEN
#define RCC_APB1ENR_WWDGEN
Definition stm32f107xc.h:1822

◆ __HAL_RCC_WWDG_CLK_ENABLE [2/4]

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_WWDG_CLK_ENABLE [3/4]

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_WWDG_CLK_ENABLE [4/4]

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0)