mikroSDK Reference Manual
Macros
APB2 Clock Enable Disable
STM32F1xx_HAL_Driver | STM32F2xx_HAL_Driver | STM32F4xx_HAL_Driver | STM32F7xx_HAL_Driver | STM32H7xx_HAL_Driver » RCC » RCC Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Macros

#define __HAL_RCC_AFIO_CLK_ENABLE()
 
#define __HAL_RCC_GPIOA_CLK_ENABLE()
 
#define __HAL_RCC_GPIOB_CLK_ENABLE()
 
#define __HAL_RCC_GPIOC_CLK_ENABLE()
 
#define __HAL_RCC_GPIOD_CLK_ENABLE()
 
#define __HAL_RCC_ADC1_CLK_ENABLE()
 
#define __HAL_RCC_TIM1_CLK_ENABLE()
 
#define __HAL_RCC_SPI1_CLK_ENABLE()
 
#define __HAL_RCC_USART1_CLK_ENABLE()
 
#define __HAL_RCC_AFIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
 
#define __HAL_RCC_GPIOA_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
 
#define __HAL_RCC_GPIOB_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
 
#define __HAL_RCC_GPIOC_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
 
#define __HAL_RCC_GPIOD_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
 
#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 
#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
 
#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 
#define __HAL_RCC_USART1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
 
#define __HAL_RCC_TIM1_CLK_ENABLE()
 
#define __HAL_RCC_TIM8_CLK_ENABLE()
 
#define __HAL_RCC_USART1_CLK_ENABLE()
 
#define __HAL_RCC_USART6_CLK_ENABLE()
 
#define __HAL_RCC_ADC1_CLK_ENABLE()
 
#define __HAL_RCC_ADC2_CLK_ENABLE()
 
#define __HAL_RCC_ADC3_CLK_ENABLE()
 
#define __HAL_RCC_SDIO_CLK_ENABLE()
 
#define __HAL_RCC_SPI1_CLK_ENABLE()
 
#define __HAL_RCC_SYSCFG_CLK_ENABLE()
 
#define __HAL_RCC_TIM9_CLK_ENABLE()
 
#define __HAL_RCC_TIM10_CLK_ENABLE()
 
#define __HAL_RCC_TIM11_CLK_ENABLE()
 
#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
 
#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
 
#define __HAL_RCC_USART1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
 
#define __HAL_RCC_USART6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
 
#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 
#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
 
#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
 
#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
 
#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 
#define __HAL_RCC_SYSCFG_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
 
#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
 
#define __HAL_RCC_TIM10_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
 
#define __HAL_RCC_TIM11_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
 
#define __HAL_RCC_TIM1_CLK_ENABLE()
 
#define __HAL_RCC_USART1_CLK_ENABLE()
 
#define __HAL_RCC_USART6_CLK_ENABLE()
 
#define __HAL_RCC_ADC1_CLK_ENABLE()
 
#define __HAL_RCC_SPI1_CLK_ENABLE()
 
#define __HAL_RCC_SYSCFG_CLK_ENABLE()
 
#define __HAL_RCC_TIM9_CLK_ENABLE()
 
#define __HAL_RCC_TIM11_CLK_ENABLE()
 
#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
 
#define __HAL_RCC_USART1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
 
#define __HAL_RCC_USART6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
 
#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
 
#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
 
#define __HAL_RCC_SYSCFG_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
 
#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
 
#define __HAL_RCC_TIM11_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
 
#define __HAL_RCC_SYSCFG_CLK_ENABLE()
 
#define __HAL_RCC_SYSCFG_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
 

Macro Definition Documentation

◆ __HAL_RCC_ADC1_CLK_ENABLE [1/3]

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0U)
__IO
#define __IO
Definition core_cm3.h:170
RCC_APB2ENR_ADC1EN
#define RCC_APB2ENR_ADC1EN
Definition stm32f107xc.h:1789

◆ __HAL_RCC_ADC1_CLK_ENABLE [2/3]

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_ADC1_CLK_ENABLE [3/3]

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_ADC2_CLK_ENABLE

#define __HAL_RCC_ADC2_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
UNUSED(tmpreg); \
} while(0)
RCC_APB2ENR_ADC2EN
#define RCC_APB2ENR_ADC2EN
Definition stm32f107xc.h:1793

◆ __HAL_RCC_ADC3_CLK_ENABLE

#define __HAL_RCC_ADC3_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_AFIO_CLK_ENABLE

#define __HAL_RCC_AFIO_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB2ENR_AFIOEN
#define RCC_APB2ENR_AFIOEN
Definition stm32f107xc.h:1774

◆ __HAL_RCC_GPIOA_CLK_ENABLE

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB2ENR_IOPAEN
#define RCC_APB2ENR_IOPAEN
Definition stm32f107xc.h:1777

◆ __HAL_RCC_GPIOB_CLK_ENABLE

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB2ENR_IOPBEN
#define RCC_APB2ENR_IOPBEN
Definition stm32f107xc.h:1780

◆ __HAL_RCC_GPIOC_CLK_ENABLE

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB2ENR_IOPCEN
#define RCC_APB2ENR_IOPCEN
Definition stm32f107xc.h:1783

◆ __HAL_RCC_GPIOD_CLK_ENABLE

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB2ENR_IOPDEN
#define RCC_APB2ENR_IOPDEN
Definition stm32f107xc.h:1786

◆ __HAL_RCC_SDIO_CLK_ENABLE

#define __HAL_RCC_SDIO_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_SPI1_CLK_ENABLE [1/3]

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB2ENR_SPI1EN
#define RCC_APB2ENR_SPI1EN
Definition stm32f107xc.h:1800

◆ __HAL_RCC_SPI1_CLK_ENABLE [2/3]

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_SPI1_CLK_ENABLE [3/3]

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_SYSCFG_CLK_ENABLE [1/3]

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_SYSCFG_CLK_ENABLE [2/3]

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_SYSCFG_CLK_ENABLE [3/3]

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM10_CLK_ENABLE

#define __HAL_RCC_TIM10_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM11_CLK_ENABLE [1/2]

#define __HAL_RCC_TIM11_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM11_CLK_ENABLE [2/2]

#define __HAL_RCC_TIM11_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_TIM1_CLK_ENABLE [1/3]

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB2ENR_TIM1EN
#define RCC_APB2ENR_TIM1EN
Definition stm32f107xc.h:1797

◆ __HAL_RCC_TIM1_CLK_ENABLE [2/3]

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM1_CLK_ENABLE [3/3]

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_TIM8_CLK_ENABLE

#define __HAL_RCC_TIM8_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM9_CLK_ENABLE [1/2]

#define __HAL_RCC_TIM9_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_TIM9_CLK_ENABLE [2/2]

#define __HAL_RCC_TIM9_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_USART1_CLK_ENABLE [1/3]

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0U)
RCC_APB2ENR_USART1EN
#define RCC_APB2ENR_USART1EN
Definition stm32f107xc.h:1803

◆ __HAL_RCC_USART1_CLK_ENABLE [2/3]

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_USART1_CLK_ENABLE [3/3]

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0U)

◆ __HAL_RCC_USART6_CLK_ENABLE [1/2]

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0)

◆ __HAL_RCC_USART6_CLK_ENABLE [2/2]

#define __HAL_RCC_USART6_CLK_ENABLE ( )
Value:
do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
UNUSED(tmpreg); \
} while(0U)