PLL Clock Source

Macros
#define	RCC_PLLSOURCE_HSI_DIV2   0x00000000U
#define	RCC_PLLSOURCE_HSE   RCC_CFGR_PLLSRC
#define	RCC_PLLSOURCE_HSI   RCC_PLLCFGR_PLLSRC_HSI
#define	RCC_PLLSOURCE_HSE   RCC_PLLCFGR_PLLSRC_HSE
#define	RCC_PLLSOURCE_HSI   RCC_PLLCFGR_PLLSRC_HSI
#define	RCC_PLLSOURCE_HSE   RCC_PLLCFGR_PLLSRC_HSE
#define	RCC_PLLSOURCE_HSI   RCC_PLLCFGR_PLLSRC_HSI
#define	RCC_PLLSOURCE_HSE   RCC_PLLCFGR_PLLSRC_HSE
#define	RCC_PLLSOURCE_HSI   (0x00000000U)
#define	RCC_PLLSOURCE_CSI   (0x00000001U)
#define	RCC_PLLSOURCE_HSE   (0x00000002U)
#define	RCC_PLLSOURCE_NONE   (0x00000003U)

Macro Definition Documentation

RCC_PLLSOURCE_HSE

#define RCC_PLLSOURCE_HSE   RCC_CFGR_PLLSRC

HSE clock selected as PLL entry clock source

RCC_PLLSOURCE_HSI_DIV2

#define RCC_PLLSOURCE_HSI_DIV2   0x00000000U

HSI clock divided by 2 selected as PLL entry clock source