mikroSDK Reference Manual
hw_emac.h
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//*****************************************************************************
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//
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// hw_emac.h - Macros used when accessing the EMAC hardware.
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//
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// Copyright (c) 2012-2020 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_EMAC_H__
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#define __HW_EMAC_H__
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//*****************************************************************************
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//
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// The following are defines for the EMAC register offsets.
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//
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//*****************************************************************************
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#define EMAC_O_CFG 0x00000000
// Ethernet MAC Configuration
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#define EMAC_O_FRAMEFLTR 0x00000004
// Ethernet MAC Frame Filter
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#define EMAC_O_HASHTBLH 0x00000008
// Ethernet MAC Hash Table High
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#define EMAC_O_HASHTBLL 0x0000000C
// Ethernet MAC Hash Table Low
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#define EMAC_O_MIIADDR 0x00000010
// Ethernet MAC MII Address
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#define EMAC_O_MIIDATA 0x00000014
// Ethernet MAC MII Data Register
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#define EMAC_O_FLOWCTL 0x00000018
// Ethernet MAC Flow Control
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#define EMAC_O_VLANTG 0x0000001C
// Ethernet MAC VLAN Tag
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#define EMAC_O_STATUS 0x00000024
// Ethernet MAC Status
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#define EMAC_O_RWUFF 0x00000028
// Ethernet MAC Remote Wake-Up
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// Frame Filter
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#define EMAC_O_PMTCTLSTAT 0x0000002C
// Ethernet MAC PMT Control and
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// Status Register
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#define EMAC_O_LPICTLSTAT 0x00000030
// Ethernet MAC Low Power Idle
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// Control and Status Register
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#define EMAC_O_LPITIMERCTL 0x00000034
// Ethernet MAC Low Power Idle
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// Timer Control Register
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#define EMAC_O_RIS 0x00000038
// Ethernet MAC Raw Interrupt
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// Status
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#define EMAC_O_IM 0x0000003C
// Ethernet MAC Interrupt Mask
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#define EMAC_O_ADDR0H 0x00000040
// Ethernet MAC Address 0 High
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#define EMAC_O_ADDR0L 0x00000044
// Ethernet MAC Address 0 Low
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// Register
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#define EMAC_O_ADDR1H 0x00000048
// Ethernet MAC Address 1 High
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#define EMAC_O_ADDR1L 0x0000004C
// Ethernet MAC Address 1 Low
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#define EMAC_O_ADDR2H 0x00000050
// Ethernet MAC Address 2 High
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#define EMAC_O_ADDR2L 0x00000054
// Ethernet MAC Address 2 Low
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#define EMAC_O_ADDR3H 0x00000058
// Ethernet MAC Address 3 High
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#define EMAC_O_ADDR3L 0x0000005C
// Ethernet MAC Address 3 Low
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#define EMAC_O_WDOGTO 0x000000DC
// Ethernet MAC Watchdog Timeout
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#define EMAC_O_MMCCTRL 0x00000100
// Ethernet MAC MMC Control
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#define EMAC_O_MMCRXRIS 0x00000104
// Ethernet MAC MMC Receive Raw
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// Interrupt Status
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#define EMAC_O_MMCTXRIS 0x00000108
// Ethernet MAC MMC Transmit Raw
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// Interrupt Status
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#define EMAC_O_MMCRXIM 0x0000010C
// Ethernet MAC MMC Receive
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// Interrupt Mask
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#define EMAC_O_MMCTXIM 0x00000110
// Ethernet MAC MMC Transmit
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// Interrupt Mask
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#define EMAC_O_TXCNTGB 0x00000118
// Ethernet MAC Transmit Frame
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// Count for Good and Bad Frames
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#define EMAC_O_TXCNTSCOL 0x0000014C
// Ethernet MAC Transmit Frame
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// Count for Frames Transmitted
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// after Single Collision
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#define EMAC_O_TXCNTMCOL 0x00000150
// Ethernet MAC Transmit Frame
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// Count for Frames Transmitted
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// after Multiple Collisions
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#define EMAC_O_TXOCTCNTG 0x00000164
// Ethernet MAC Transmit Octet
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// Count Good
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#define EMAC_O_RXCNTGB 0x00000180
// Ethernet MAC Receive Frame Count
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// for Good and Bad Frames
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#define EMAC_O_RXCNTCRCERR 0x00000194
// Ethernet MAC Receive Frame Count
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// for CRC Error Frames
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#define EMAC_O_RXCNTALGNERR 0x00000198
// Ethernet MAC Receive Frame Count
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// for Alignment Error Frames
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#define EMAC_O_RXCNTGUNI 0x000001C4
// Ethernet MAC Receive Frame Count
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// for Good Unicast Frames
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#define EMAC_O_VLNINCREP 0x00000584
// Ethernet MAC VLAN Tag Inclusion
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// or Replacement
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#define EMAC_O_VLANHASH 0x00000588
// Ethernet MAC VLAN Hash Table
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#define EMAC_O_TIMSTCTRL 0x00000700
// Ethernet MAC Timestamp Control
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#define EMAC_O_SUBSECINC 0x00000704
// Ethernet MAC Sub-Second
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// Increment
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#define EMAC_O_TIMSEC 0x00000708
// Ethernet MAC System Time -
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// Seconds
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#define EMAC_O_TIMNANO 0x0000070C
// Ethernet MAC System Time -
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// Nanoseconds
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#define EMAC_O_TIMSECU 0x00000710
// Ethernet MAC System Time -
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// Seconds Update
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#define EMAC_O_TIMNANOU 0x00000714
// Ethernet MAC System Time -
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// Nanoseconds Update
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#define EMAC_O_TIMADD 0x00000718
// Ethernet MAC Timestamp Addend
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#define EMAC_O_TARGSEC 0x0000071C
// Ethernet MAC Target Time Seconds
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#define EMAC_O_TARGNANO 0x00000720
// Ethernet MAC Target Time
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// Nanoseconds
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#define EMAC_O_HWORDSEC 0x00000724
// Ethernet MAC System Time-Higher
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// Word Seconds
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#define EMAC_O_TIMSTAT 0x00000728
// Ethernet MAC Timestamp Status
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#define EMAC_O_PPSCTRL 0x0000072C
// Ethernet MAC PPS Control
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#define EMAC_O_PPS0INTVL 0x00000760
// Ethernet MAC PPS0 Interval
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#define EMAC_O_PPS0WIDTH 0x00000764
// Ethernet MAC PPS0 Width
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#define EMAC_O_DMABUSMOD 0x00000C00
// Ethernet MAC DMA Bus Mode
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#define EMAC_O_TXPOLLD 0x00000C04
// Ethernet MAC Transmit Poll
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// Demand
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#define EMAC_O_RXPOLLD 0x00000C08
// Ethernet MAC Receive Poll Demand
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#define EMAC_O_RXDLADDR 0x00000C0C
// Ethernet MAC Receive Descriptor
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// List Address
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#define EMAC_O_TXDLADDR 0x00000C10
// Ethernet MAC Transmit Descriptor
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// List Address
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#define EMAC_O_DMARIS 0x00000C14
// Ethernet MAC DMA Interrupt
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// Status
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#define EMAC_O_DMAOPMODE 0x00000C18
// Ethernet MAC DMA Operation Mode
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#define EMAC_O_DMAIM 0x00000C1C
// Ethernet MAC DMA Interrupt Mask
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// Register
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#define EMAC_O_MFBOC 0x00000C20
// Ethernet MAC Missed Frame and
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// Buffer Overflow Counter
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#define EMAC_O_RXINTWDT 0x00000C24
// Ethernet MAC Receive Interrupt
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// Watchdog Timer
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#define EMAC_O_HOSTXDESC 0x00000C48
// Ethernet MAC Current Host
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// Transmit Descriptor
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#define EMAC_O_HOSRXDESC 0x00000C4C
// Ethernet MAC Current Host
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// Receive Descriptor
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#define EMAC_O_HOSTXBA 0x00000C50
// Ethernet MAC Current Host
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// Transmit Buffer Address
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#define EMAC_O_HOSRXBA 0x00000C54
// Ethernet MAC Current Host
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// Receive Buffer Address
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#define EMAC_O_PP 0x00000FC0
// Ethernet MAC Peripheral Property
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// Register
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#define EMAC_O_PC 0x00000FC4
// Ethernet MAC Peripheral
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// Configuration Register
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#define EMAC_O_CC 0x00000FC8
// Ethernet MAC Clock Configuration
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// Register
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#define EMAC_O_EPHYRIS 0x00000FD0
// Ethernet PHY Raw Interrupt
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// Status
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#define EMAC_O_EPHYIM 0x00000FD4
// Ethernet PHY Interrupt Mask
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#define EMAC_O_EPHYMISC 0x00000FD8
// Ethernet PHY Masked Interrupt
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// Status and Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EMAC_O_CFG register.
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//
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//*****************************************************************************
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#define EMAC_CFG_TWOKPEN 0x08000000
// IEEE 802
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#define EMAC_CFG_CST 0x02000000
// CRC Stripping for Type Frames
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#define EMAC_CFG_WDDIS 0x00800000
// Watchdog Disable
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#define EMAC_CFG_JD 0x00400000
// Jabber Disable
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#define EMAC_CFG_JFEN 0x00100000
// Jumbo Frame Enable
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#define EMAC_CFG_IFG_M 0x000E0000
// Inter-Frame Gap (IFG)
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#define EMAC_CFG_IFG_96 0x00000000
// 96 bit times
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#define EMAC_CFG_IFG_88 0x00020000
// 88 bit times
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#define EMAC_CFG_IFG_80 0x00040000
// 80 bit times
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#define EMAC_CFG_IFG_72 0x00060000
// 72 bit times
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#define EMAC_CFG_IFG_64 0x00080000
// 64 bit times
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#define EMAC_CFG_IFG_56 0x000A0000
// 56 bit times
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#define EMAC_CFG_IFG_48 0x000C0000
// 48 bit times
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#define EMAC_CFG_IFG_40 0x000E0000
// 40 bit times
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#define EMAC_CFG_DISCRS 0x00010000
// Disable Carrier Sense During
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// Transmission
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#define EMAC_CFG_PS 0x00008000
// Port Select
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#define EMAC_CFG_FES 0x00004000
// Speed
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#define EMAC_CFG_DRO 0x00002000
// Disable Receive Own
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#define EMAC_CFG_LOOPBM 0x00001000
// Loopback Mode
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#define EMAC_CFG_DUPM 0x00000800
// Duplex Mode
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#define EMAC_CFG_IPC 0x00000400
// Checksum Offload
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#define EMAC_CFG_DR 0x00000200
// Disable Retry
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#define EMAC_CFG_ACS 0x00000080
// Automatic Pad or CRC Stripping
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#define EMAC_CFG_BL_M 0x00000060
// Back-Off Limit
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#define EMAC_CFG_BL_1024 0x00000000
// k = min (n,10)
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#define EMAC_CFG_BL_256 0x00000020
// k = min (n,8)
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#define EMAC_CFG_BL_8 0x00000040
// k = min (n,4)
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#define EMAC_CFG_BL_2 0x00000060
// k = min (n,1)
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#define EMAC_CFG_DC 0x00000010
// Deferral Check
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#define EMAC_CFG_TE 0x00000008
// Transmitter Enable
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#define EMAC_CFG_RE 0x00000004
// Receiver Enable
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#define EMAC_CFG_PRELEN_M 0x00000003
// Preamble Length for Transmit
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// Frames
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#define EMAC_CFG_PRELEN_7 0x00000000
// 7 bytes of preamble
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#define EMAC_CFG_PRELEN_5 0x00000001
// 5 bytes of preamble
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#define EMAC_CFG_PRELEN_3 0x00000002
// 3 bytes of preamble
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EMAC_O_FRAMEFLTR
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// register.
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//
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//*****************************************************************************
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#define EMAC_FRAMEFLTR_RA 0x80000000
// Receive All
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#define EMAC_FRAMEFLTR_VTFE 0x00010000
// VLAN Tag Filter Enable
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#define EMAC_FRAMEFLTR_HPF 0x00000400
// Hash or Perfect Filter
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#define EMAC_FRAMEFLTR_SAF 0x00000200
// Source Address Filter Enable
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#define EMAC_FRAMEFLTR_SAIF 0x00000100
// Source Address (SA) Inverse
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// Filtering
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#define EMAC_FRAMEFLTR_PCF_M 0x000000C0
// Pass Control Frames
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#define EMAC_FRAMEFLTR_PCF_ALL 0x00000000
// The MAC filters all control
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// frames from reaching application
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#define EMAC_FRAMEFLTR_PCF_PAUSE \
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0x00000040
// MAC forwards all control frames
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// except PAUSE control frames to
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// application even if they fail
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// the address filter
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#define EMAC_FRAMEFLTR_PCF_NONE 0x00000080
// MAC forwards all control frames
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// to application even if they fail
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// the address Filter
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#define EMAC_FRAMEFLTR_PCF_ADDR 0x000000C0
// MAC forwards control frames that
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// pass the address Filter
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#define EMAC_FRAMEFLTR_DBF 0x00000020
// Disable Broadcast Frames
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#define EMAC_FRAMEFLTR_PM 0x00000010
// Pass All Multicast
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#define EMAC_FRAMEFLTR_DAIF 0x00000008
// Destination Address (DA) Inverse
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// Filtering
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#define EMAC_FRAMEFLTR_HMC 0x00000004
// Hash Multicast
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#define EMAC_FRAMEFLTR_HUC 0x00000002
// Hash Unicast
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#define EMAC_FRAMEFLTR_PR 0x00000001
// Promiscuous Mode
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EMAC_O_HASHTBLH
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// register.
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//
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//*****************************************************************************
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#define EMAC_HASHTBLH_HTH_M 0xFFFFFFFF
// Hash Table High
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#define EMAC_HASHTBLH_HTH_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EMAC_O_HASHTBLL
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// register.
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//
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//*****************************************************************************
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#define EMAC_HASHTBLL_HTL_M 0xFFFFFFFF
// Hash Table Low
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#define EMAC_HASHTBLL_HTL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EMAC_O_MIIADDR register.
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//
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//*****************************************************************************
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#define EMAC_MIIADDR_PLA_M 0x0000F800
// Physical Layer Address
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#define EMAC_MIIADDR_MII_M 0x000007C0
// MII Register
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#define EMAC_MIIADDR_CR_M 0x0000003C
// Clock Reference Frequency
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// Selection
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#define EMAC_MIIADDR_CR_60_100 0x00000000
// The frequency of the System
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// Clock is 60 to 100 MHz providing
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// a MDIO clock of SYSCLK/42
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#define EMAC_MIIADDR_CR_100_150 0x00000004
// The frequency of the System
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// Clock is 100 to 150 MHz
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// providing a MDIO clock of
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// SYSCLK/62
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#define EMAC_MIIADDR_CR_20_35 0x00000008
// The frequency of the System
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// Clock is 20-35 MHz providing a
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// MDIO clock of System Clock/16
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#define EMAC_MIIADDR_CR_35_60 0x0000000C
// The frequency of the System
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// Clock is 35 to 60 MHz providing
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// a MDIO clock of System Clock/26
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#define EMAC_MIIADDR_MIIW 0x00000002
// MII Write
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#define EMAC_MIIADDR_MIIB 0x00000001
// MII Busy
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#define EMAC_MIIADDR_PLA_S 11
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#define EMAC_MIIADDR_MII_S 6
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EMAC_O_MIIDATA register.
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//
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//*****************************************************************************
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#define EMAC_MIIDATA_DATA_M 0x0000FFFF
// MII Data
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#define EMAC_MIIDATA_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EMAC_O_FLOWCTL register.
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//
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//*****************************************************************************
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#define EMAC_FLOWCTL_PT_M 0xFFFF0000
// Pause Time
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#define EMAC_FLOWCTL_DZQP 0x00000080
// Disable Zero-Quanta Pause
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#define EMAC_FLOWCTL_UP 0x00000008
// Unicast Pause Frame Detect
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#define EMAC_FLOWCTL_RFE 0x00000004
// Receive Flow Control Enable
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#define EMAC_FLOWCTL_TFE 0x00000002
// Transmit Flow Control Enable
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#define EMAC_FLOWCTL_FCBBPA 0x00000001
// Flow Control Busy or
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// Back-pressure Activate
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#define EMAC_FLOWCTL_PT_S 16
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EMAC_O_VLANTG register.
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//
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//*****************************************************************************
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#define EMAC_VLANTG_VTHM 0x00080000
// VLAN Tag Hash Table Match Enable
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#define EMAC_VLANTG_ESVL 0x00040000
// Enable S-VLAN
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#define EMAC_VLANTG_VTIM 0x00020000
// VLAN Tag Inverse Match Enable
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#define EMAC_VLANTG_ETV 0x00010000
// Enable 12-Bit VLAN Tag
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// Comparison
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#define EMAC_VLANTG_VL_M 0x0000FFFF
// VLAN Tag Identifier for Receive
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// Frames
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#define EMAC_VLANTG_VL_S 0
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323
//*****************************************************************************
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//
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// The following are defines for the bit fields in the EMAC_O_STATUS register.
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//
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//*****************************************************************************
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#define EMAC_STATUS_TXFF 0x02000000
// TX/RX Controller TX FIFO Full
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// Status
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#define EMAC_STATUS_TXFE 0x01000000
// TX/RX Controller TX FIFO Not
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// Empty Status
332
#define EMAC_STATUS_TWC 0x00400000
// TX/RX Controller TX FIFO Write
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// Controller Active Status
334
#define EMAC_STATUS_TRC_M 0x00300000
// TX/RX Controller's TX FIFO Read
335
// Controller Status
336
#define EMAC_STATUS_TRC_IDLE 0x00000000
// IDLE state
337
#define EMAC_STATUS_TRC_READ 0x00100000
// READ state (transferring data to
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// MAC transmitter)
339
#define EMAC_STATUS_TRC_WAIT 0x00200000
// Waiting for TX Status from MAC
340
// transmitter
341
#define EMAC_STATUS_TRC_WRFLUSH 0x00300000
// Writing the received TX Status
342
// or flushing the TX FIFO
343
#define EMAC_STATUS_TXPAUSED 0x00080000
// MAC Transmitter PAUSE
344
#define EMAC_STATUS_TFC_M 0x00060000
// MAC Transmit Frame Controller
345
// Status
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#define EMAC_STATUS_TFC_IDLE 0x00000000
// IDLE state
347
#define EMAC_STATUS_TFC_STATUS 0x00020000
// Waiting for status of previous
348
// frame or IFG or backoff period
349
// to be over
350
#define EMAC_STATUS_TFC_PAUSE 0x00040000
// Generating and transmitting a
351
// PAUSE control frame (in the
352
// full-duplex mode)
353
#define EMAC_STATUS_TFC_INPUT 0x00060000
// Transferring input frame for
354
// transmission
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#define EMAC_STATUS_TPE 0x00010000
// MAC MII Transmit Protocol Engine
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// Status
357
#define EMAC_STATUS_RXF_M 0x00000300
// TX/RX Controller RX FIFO
358
// Fill-level Status
359
#define EMAC_STATUS_RXF_EMPTY 0x00000000
// RX FIFO Empty
360
#define EMAC_STATUS_RXF_BELOW 0x00000100
// RX FIFO fill level is below the
361
// flow-control deactivate
362
// threshold
363
#define EMAC_STATUS_RXF_ABOVE 0x00000200
// RX FIFO fill level is above the
364
// flow-control activate threshold
365
#define EMAC_STATUS_RXF_FULL 0x00000300
// RX FIFO Full
366
#define EMAC_STATUS_RRC_M 0x00000060
// TX/RX Controller Read Controller
367
// State
368
#define EMAC_STATUS_RRC_IDLE 0x00000000
// IDLE state
369
#define EMAC_STATUS_RRC_STATUS 0x00000020
// Reading frame data
370
#define EMAC_STATUS_RRC_DATA 0x00000040
// Reading frame status (or
371
// timestamp)
372
#define EMAC_STATUS_RRC_FLUSH 0x00000060
// Flushing the frame data and
373
// status
374
#define EMAC_STATUS_RWC 0x00000010
// TX/RX Controller RX FIFO Write
375
// Controller Active Status
376
#define EMAC_STATUS_RFCFC_M 0x00000006
// MAC Receive Frame Controller
377
// FIFO Status
378
#define EMAC_STATUS_RPE 0x00000001
// MAC MII Receive Protocol Engine
379
// Status
380
#define EMAC_STATUS_RFCFC_S 1
381
382
//*****************************************************************************
383
//
384
// The following are defines for the bit fields in the EMAC_O_RWUFF register.
385
//
386
//*****************************************************************************
387
#define EMAC_RWUFF_WAKEUPFIL_M 0xFFFFFFFF
// Remote Wake-Up Frame Filter
388
#define EMAC_RWUFF_WAKEUPFIL_S 0
389
390
//*****************************************************************************
391
//
392
// The following are defines for the bit fields in the EMAC_O_PMTCTLSTAT
393
// register.
394
//
395
//*****************************************************************************
396
#define EMAC_PMTCTLSTAT_WUPFRRST \
397
0x80000000
// Wake-Up Frame Filter Register
398
// Pointer Reset
399
#define EMAC_PMTCTLSTAT_RWKPTR_M \
400
0x07000000
// Remote Wake-Up FIFO Pointer
401
#define EMAC_PMTCTLSTAT_GLBLUCAST \
402
0x00000200
// Global Unicast
403
#define EMAC_PMTCTLSTAT_WUPRX 0x00000040
// Wake-Up Frame Received
404
#define EMAC_PMTCTLSTAT_MGKPRX 0x00000020
// Magic Packet Received
405
#define EMAC_PMTCTLSTAT_WUPFREN 0x00000004
// Wake-Up Frame Enable
406
#define EMAC_PMTCTLSTAT_MGKPKTEN \
407
0x00000002
// Magic Packet Enable
408
#define EMAC_PMTCTLSTAT_PWRDWN 0x00000001
// Power Down
409
#define EMAC_PMTCTLSTAT_RWKPTR_S \
410
24
411
412
//*****************************************************************************
413
//
414
// The following are defines for the bit fields in the EMAC_O_LPICTLSTAT
415
// register.
416
//
417
//*****************************************************************************
418
#define EMAC_LPICTLSTAT_LPITXA 0x00080000
// LPI TX Automate
419
#define EMAC_LPICTLSTAT_PLSEN 0x00040000
// PHY Link Status Enable
420
#define EMAC_LPICTLSTAT_PLS 0x00020000
// PHY Link Status
421
#define EMAC_LPICTLSTAT_LPIEN 0x00010000
// LPI Enable
422
#define EMAC_LPICTLSTAT_RLPIST 0x00000200
// Receive LPI State
423
#define EMAC_LPICTLSTAT_TLPIST 0x00000100
// Transmit LPI State
424
#define EMAC_LPICTLSTAT_RLPIEX 0x00000008
// Receive LPI Exit
425
#define EMAC_LPICTLSTAT_RLPIEN 0x00000004
// Receive LPI Entry
426
#define EMAC_LPICTLSTAT_TLPIEX 0x00000002
// Transmit LPI Exit
427
#define EMAC_LPICTLSTAT_TLPIEN 0x00000001
// Transmit LPI Entry
428
429
//*****************************************************************************
430
//
431
// The following are defines for the bit fields in the EMAC_O_LPITIMERCTL
432
// register.
433
//
434
//*****************************************************************************
435
#define EMAC_LPITIMERCTL_LST_M 0x03FF0000
// Low Power Idle LS Timer
436
#define EMAC_LPITIMERCTL_LST_S 16
437
#define EMAC_LPITIMERCTL_TWT_M 0x0000FFFF
// Low Power Idle TW Timer
438
#define EMAC_LPITIMERCTL_TWT_S 0
439
440
//*****************************************************************************
441
//
442
// The following are defines for the bit fields in the EMAC_O_RIS register.
443
//
444
//*****************************************************************************
445
#define EMAC_RIS_LPI 0x00000400
// LPI Interrupt Status
446
#define EMAC_RIS_TS 0x00000200
// Timestamp Interrupt Status
447
#define EMAC_RIS_MMCTX 0x00000040
// MMC Transmit Interrupt Status
448
#define EMAC_RIS_MMCRX 0x00000020
// MMC Receive Interrupt Status
449
#define EMAC_RIS_MMC 0x00000010
// MMC Interrupt Status
450
#define EMAC_RIS_PMT 0x00000008
// PMT Interrupt Status
451
452
//*****************************************************************************
453
//
454
// The following are defines for the bit fields in the EMAC_O_IM register.
455
//
456
//*****************************************************************************
457
#define EMAC_IM_LPI 0x00000400
// LPI Interrupt Mask
458
#define EMAC_IM_TSI 0x00000200
// Timestamp Interrupt Mask
459
#define EMAC_IM_PMT 0x00000008
// PMT Interrupt Mask
460
461
//*****************************************************************************
462
//
463
// The following are defines for the bit fields in the EMAC_O_ADDR0H register.
464
//
465
//*****************************************************************************
466
#define EMAC_ADDR0H_AE 0x80000000
// Address Enable
467
#define EMAC_ADDR0H_ADDRHI_M 0x0000FFFF
// MAC Address0 [47:32]
468
#define EMAC_ADDR0H_ADDRHI_S 0
469
470
//*****************************************************************************
471
//
472
// The following are defines for the bit fields in the EMAC_O_ADDR0L register.
473
//
474
//*****************************************************************************
475
#define EMAC_ADDR0L_ADDRLO_M 0xFFFFFFFF
// MAC Address0 [31:0]
476
#define EMAC_ADDR0L_ADDRLO_S 0
477
478
//*****************************************************************************
479
//
480
// The following are defines for the bit fields in the EMAC_O_ADDR1H register.
481
//
482
//*****************************************************************************
483
#define EMAC_ADDR1H_AE 0x80000000
// Address Enable
484
#define EMAC_ADDR1H_SA 0x40000000
// Source Address
485
#define EMAC_ADDR1H_MBC_M 0x3F000000
// Mask Byte Control
486
#define EMAC_ADDR1H_ADDRHI_M 0x0000FFFF
// MAC Address1 [47:32]
487
#define EMAC_ADDR1H_MBC_S 24
488
#define EMAC_ADDR1H_ADDRHI_S 0
489
490
//*****************************************************************************
491
//
492
// The following are defines for the bit fields in the EMAC_O_ADDR1L register.
493
//
494
//*****************************************************************************
495
#define EMAC_ADDR1L_ADDRLO_M 0xFFFFFFFF
// MAC Address1 [31:0]
496
#define EMAC_ADDR1L_ADDRLO_S 0
497
498
//*****************************************************************************
499
//
500
// The following are defines for the bit fields in the EMAC_O_ADDR2H register.
501
//
502
//*****************************************************************************
503
#define EMAC_ADDR2H_AE 0x80000000
// Address Enable
504
#define EMAC_ADDR2H_SA 0x40000000
// Source Address
505
#define EMAC_ADDR2H_MBC_M 0x3F000000
// Mask Byte Control
506
#define EMAC_ADDR2H_ADDRHI_M 0x0000FFFF
// MAC Address2 [47:32]
507
#define EMAC_ADDR2H_MBC_S 24
508
#define EMAC_ADDR2H_ADDRHI_S 0
509
510
//*****************************************************************************
511
//
512
// The following are defines for the bit fields in the EMAC_O_ADDR2L register.
513
//
514
//*****************************************************************************
515
#define EMAC_ADDR2L_ADDRLO_M 0xFFFFFFFF
// MAC Address2 [31:0]
516
#define EMAC_ADDR2L_ADDRLO_S 0
517
518
//*****************************************************************************
519
//
520
// The following are defines for the bit fields in the EMAC_O_ADDR3H register.
521
//
522
//*****************************************************************************
523
#define EMAC_ADDR3H_AE 0x80000000
// Address Enable
524
#define EMAC_ADDR3H_SA 0x40000000
// Source Address
525
#define EMAC_ADDR3H_MBC_M 0x3F000000
// Mask Byte Control
526
#define EMAC_ADDR3H_ADDRHI_M 0x0000FFFF
// MAC Address3 [47:32]
527
#define EMAC_ADDR3H_MBC_S 24
528
#define EMAC_ADDR3H_ADDRHI_S 0
529
530
//*****************************************************************************
531
//
532
// The following are defines for the bit fields in the EMAC_O_ADDR3L register.
533
//
534
//*****************************************************************************
535
#define EMAC_ADDR3L_ADDRLO_M 0xFFFFFFFF
// MAC Address3 [31:0]
536
#define EMAC_ADDR3L_ADDRLO_S 0
537
538
//*****************************************************************************
539
//
540
// The following are defines for the bit fields in the EMAC_O_WDOGTO register.
541
//
542
//*****************************************************************************
543
#define EMAC_WDOGTO_PWE 0x00010000
// Programmable Watchdog Enable
544
#define EMAC_WDOGTO_WTO_M 0x00003FFF
// Watchdog Timeout
545
#define EMAC_WDOGTO_WTO_S 0
546
547
//*****************************************************************************
548
//
549
// The following are defines for the bit fields in the EMAC_O_MMCCTRL register.
550
//
551
//*****************************************************************************
552
#define EMAC_MMCCTRL_UCDBC 0x00000100
// Update MMC Counters for Dropped
553
// Broadcast Frames
554
#define EMAC_MMCCTRL_CNTPRSTLVL 0x00000020
// Full/Half Preset Level Value
555
#define EMAC_MMCCTRL_CNTPRST 0x00000010
// Counters Preset
556
#define EMAC_MMCCTRL_CNTFREEZ 0x00000008
// MMC Counter Freeze
557
#define EMAC_MMCCTRL_RSTONRD 0x00000004
// Reset on Read
558
#define EMAC_MMCCTRL_CNTSTPRO 0x00000002
// Counters Stop Rollover
559
#define EMAC_MMCCTRL_CNTRST 0x00000001
// Counters Reset
560
561
//*****************************************************************************
562
//
563
// The following are defines for the bit fields in the EMAC_O_MMCRXRIS
564
// register.
565
//
566
//*****************************************************************************
567
#define EMAC_MMCRXRIS_UCGF 0x00020000
// MMC Receive Unicast Good Frame
568
// Counter Interrupt Status
569
#define EMAC_MMCRXRIS_ALGNERR 0x00000040
// MMC Receive Alignment Error
570
// Frame Counter Interrupt Status
571
#define EMAC_MMCRXRIS_CRCERR 0x00000020
// MMC Receive CRC Error Frame
572
// Counter Interrupt Status
573
#define EMAC_MMCRXRIS_GBF 0x00000001
// MMC Receive Good Bad Frame
574
// Counter Interrupt Status
575
576
//*****************************************************************************
577
//
578
// The following are defines for the bit fields in the EMAC_O_MMCTXRIS
579
// register.
580
//
581
//*****************************************************************************
582
#define EMAC_MMCTXRIS_OCTCNT 0x00100000
// Octet Counter Interrupt Status
583
#define EMAC_MMCTXRIS_MCOLLGF 0x00008000
// MMC Transmit Multiple Collision
584
// Good Frame Counter Interrupt
585
// Status
586
#define EMAC_MMCTXRIS_SCOLLGF 0x00004000
// MMC Transmit Single Collision
587
// Good Frame Counter Interrupt
588
// Status
589
#define EMAC_MMCTXRIS_GBF 0x00000002
// MMC Transmit Good Bad Frame
590
// Counter Interrupt Status
591
592
//*****************************************************************************
593
//
594
// The following are defines for the bit fields in the EMAC_O_MMCRXIM register.
595
//
596
//*****************************************************************************
597
#define EMAC_MMCRXIM_UCGF 0x00020000
// MMC Receive Unicast Good Frame
598
// Counter Interrupt Mask
599
#define EMAC_MMCRXIM_ALGNERR 0x00000040
// MMC Receive Alignment Error
600
// Frame Counter Interrupt Mask
601
#define EMAC_MMCRXIM_CRCERR 0x00000020
// MMC Receive CRC Error Frame
602
// Counter Interrupt Mask
603
#define EMAC_MMCRXIM_GBF 0x00000001
// MMC Receive Good Bad Frame
604
// Counter Interrupt Mask
605
606
//*****************************************************************************
607
//
608
// The following are defines for the bit fields in the EMAC_O_MMCTXIM register.
609
//
610
//*****************************************************************************
611
#define EMAC_MMCTXIM_OCTCNT 0x00100000
// MMC Transmit Good Octet Counter
612
// Interrupt Mask
613
#define EMAC_MMCTXIM_MCOLLGF 0x00008000
// MMC Transmit Multiple Collision
614
// Good Frame Counter Interrupt
615
// Mask
616
#define EMAC_MMCTXIM_SCOLLGF 0x00004000
// MMC Transmit Single Collision
617
// Good Frame Counter Interrupt
618
// Mask
619
#define EMAC_MMCTXIM_GBF 0x00000002
// MMC Transmit Good Bad Frame
620
// Counter Interrupt Mask
621
622
//*****************************************************************************
623
//
624
// The following are defines for the bit fields in the EMAC_O_TXCNTGB register.
625
//
626
//*****************************************************************************
627
#define EMAC_TXCNTGB_TXFRMGB_M 0xFFFFFFFF
// This field indicates the number
628
// of good and bad frames
629
// transmitted, exclusive of
630
// retried frames
631
#define EMAC_TXCNTGB_TXFRMGB_S 0
632
633
//*****************************************************************************
634
//
635
// The following are defines for the bit fields in the EMAC_O_TXCNTSCOL
636
// register.
637
//
638
//*****************************************************************************
639
#define EMAC_TXCNTSCOL_TXSNGLCOLG_M \
640
0xFFFFFFFF
// This field indicates the number
641
// of successfully transmitted
642
// frames after a single collision
643
// in the half-duplex mode
644
#define EMAC_TXCNTSCOL_TXSNGLCOLG_S \
645
0
646
647
//*****************************************************************************
648
//
649
// The following are defines for the bit fields in the EMAC_O_TXCNTMCOL
650
// register.
651
//
652
//*****************************************************************************
653
#define EMAC_TXCNTMCOL_TXMULTCOLG_M \
654
0xFFFFFFFF
// This field indicates the number
655
// of successfully transmitted
656
// frames after multiple collisions
657
// in the half-duplex mode
658
#define EMAC_TXCNTMCOL_TXMULTCOLG_S \
659
0
660
661
//*****************************************************************************
662
//
663
// The following are defines for the bit fields in the EMAC_O_TXOCTCNTG
664
// register.
665
//
666
//*****************************************************************************
667
#define EMAC_TXOCTCNTG_TXOCTG_M 0xFFFFFFFF
// This field indicates the number
668
// of bytes transmitted, exclusive
669
// of preamble, in good frames
670
#define EMAC_TXOCTCNTG_TXOCTG_S 0
671
672
//*****************************************************************************
673
//
674
// The following are defines for the bit fields in the EMAC_O_RXCNTGB register.
675
//
676
//*****************************************************************************
677
#define EMAC_RXCNTGB_RXFRMGB_M 0xFFFFFFFF
// This field indicates the number
678
// of received good and bad frames
679
#define EMAC_RXCNTGB_RXFRMGB_S 0
680
681
//*****************************************************************************
682
//
683
// The following are defines for the bit fields in the EMAC_O_RXCNTCRCERR
684
// register.
685
//
686
//*****************************************************************************
687
#define EMAC_RXCNTCRCERR_RXCRCERR_M \
688
0xFFFFFFFF
// This field indicates the number
689
// of frames received with CRC
690
// error
691
#define EMAC_RXCNTCRCERR_RXCRCERR_S \
692
0
693
694
//*****************************************************************************
695
//
696
// The following are defines for the bit fields in the EMAC_O_RXCNTALGNERR
697
// register.
698
//
699
//*****************************************************************************
700
#define EMAC_RXCNTALGNERR_RXALGNERR_M \
701
0xFFFFFFFF
// This field indicates the number
702
// of frames received with
703
// alignment (dribble) error
704
#define EMAC_RXCNTALGNERR_RXALGNERR_S \
705
0
706
707
//*****************************************************************************
708
//
709
// The following are defines for the bit fields in the EMAC_O_RXCNTGUNI
710
// register.
711
//
712
//*****************************************************************************
713
#define EMAC_RXCNTGUNI_RXUCASTG_M \
714
0xFFFFFFFF
// This field indicates the number
715
// of received good unicast frames
716
#define EMAC_RXCNTGUNI_RXUCASTG_S \
717
0
718
719
//*****************************************************************************
720
//
721
// The following are defines for the bit fields in the EMAC_O_VLNINCREP
722
// register.
723
//
724
//*****************************************************************************
725
#define EMAC_VLNINCREP_CSVL 0x00080000
// C-VLAN or S-VLAN
726
#define EMAC_VLNINCREP_VLP 0x00040000
// VLAN Priority Control
727
#define EMAC_VLNINCREP_VLC_M 0x00030000
// VLAN Tag Control in Transmit
728
// Frames
729
#define EMAC_VLNINCREP_VLC_NONE 0x00000000
// No VLAN tag deletion, insertion,
730
// or replacement
731
#define EMAC_VLNINCREP_VLC_TAGDEL \
732
0x00010000
// VLAN tag deletion
733
#define EMAC_VLNINCREP_VLC_TAGINS \
734
0x00020000
// VLAN tag insertion
735
#define EMAC_VLNINCREP_VLC_TAGREP \
736
0x00030000
// VLAN tag replacement
737
#define EMAC_VLNINCREP_VLT_M 0x0000FFFF
// VLAN Tag for Transmit Frames
738
#define EMAC_VLNINCREP_VLT_S 0
739
740
//*****************************************************************************
741
//
742
// The following are defines for the bit fields in the EMAC_O_VLANHASH
743
// register.
744
//
745
//*****************************************************************************
746
#define EMAC_VLANHASH_VLHT_M 0x0000FFFF
// VLAN Hash Table
747
#define EMAC_VLANHASH_VLHT_S 0
748
749
//*****************************************************************************
750
//
751
// The following are defines for the bit fields in the EMAC_O_TIMSTCTRL
752
// register.
753
//
754
//*****************************************************************************
755
#define EMAC_TIMSTCTRL_PTPFLTR 0x00040000
// Enable MAC address for PTP Frame
756
// Filtering
757
#define EMAC_TIMSTCTRL_SELPTP_M 0x00030000
// Select PTP packets for Taking
758
// Snapshots
759
#define EMAC_TIMSTCTRL_TSMAST 0x00008000
// Enable Snapshot for Messages
760
// Relevant to Master
761
#define EMAC_TIMSTCTRL_TSEVNT 0x00004000
// Enable Timestamp Snapshot for
762
// Event Messages
763
#define EMAC_TIMSTCTRL_PTPIPV4 0x00002000
// Enable Processing of PTP Frames
764
// Sent over IPv4-UDP
765
#define EMAC_TIMSTCTRL_PTPIPV6 0x00001000
// Enable Processing of PTP Frames
766
// Sent Over IPv6-UDP
767
#define EMAC_TIMSTCTRL_PTPETH 0x00000800
// Enable Processing of PTP Over
768
// Ethernet Frames
769
#define EMAC_TIMSTCTRL_PTPVER2 0x00000400
// Enable PTP Packet Processing For
770
// Version 2 Format
771
#define EMAC_TIMSTCTRL_DGTLBIN 0x00000200
// Timestamp Digital or Binary
772
// Rollover Control
773
#define EMAC_TIMSTCTRL_ALLF 0x00000100
// Enable Timestamp For All Frames
774
#define EMAC_TIMSTCTRL_ADDREGUP 0x00000020
// Addend Register Update
775
#define EMAC_TIMSTCTRL_INTTRIG 0x00000010
// Timestamp Interrupt Trigger
776
// Enable
777
#define EMAC_TIMSTCTRL_TSUPDT 0x00000008
// Timestamp Update
778
#define EMAC_TIMSTCTRL_TSINIT 0x00000004
// Timestamp Initialize
779
#define EMAC_TIMSTCTRL_TSFCUPDT 0x00000002
// Timestamp Fine or Coarse Update
780
#define EMAC_TIMSTCTRL_TSEN 0x00000001
// Timestamp Enable
781
#define EMAC_TIMSTCTRL_SELPTP_S 16
782
783
//*****************************************************************************
784
//
785
// The following are defines for the bit fields in the EMAC_O_SUBSECINC
786
// register.
787
//
788
//*****************************************************************************
789
#define EMAC_SUBSECINC_SSINC_M 0x000000FF
// Sub-second Increment Value
790
#define EMAC_SUBSECINC_SSINC_S 0
791
792
//*****************************************************************************
793
//
794
// The following are defines for the bit fields in the EMAC_O_TIMSEC register.
795
//
796
//*****************************************************************************
797
#define EMAC_TIMSEC_TSS_M 0xFFFFFFFF
// Timestamp Second
798
#define EMAC_TIMSEC_TSS_S 0
799
800
//*****************************************************************************
801
//
802
// The following are defines for the bit fields in the EMAC_O_TIMNANO register.
803
//
804
//*****************************************************************************
805
#define EMAC_TIMNANO_TSSS_M 0x7FFFFFFF
// Timestamp Sub-Seconds
806
#define EMAC_TIMNANO_TSSS_S 0
807
808
//*****************************************************************************
809
//
810
// The following are defines for the bit fields in the EMAC_O_TIMSECU register.
811
//
812
//*****************************************************************************
813
#define EMAC_TIMSECU_TSS_M 0xFFFFFFFF
// Timestamp Second
814
#define EMAC_TIMSECU_TSS_S 0
815
816
//*****************************************************************************
817
//
818
// The following are defines for the bit fields in the EMAC_O_TIMNANOU
819
// register.
820
//
821
//*****************************************************************************
822
#define EMAC_TIMNANOU_ADDSUB 0x80000000
// Add or subtract time
823
#define EMAC_TIMNANOU_TSSS_M 0x7FFFFFFF
// Timestamp Sub-Second
824
#define EMAC_TIMNANOU_TSSS_S 0
825
826
//*****************************************************************************
827
//
828
// The following are defines for the bit fields in the EMAC_O_TIMADD register.
829
//
830
//*****************************************************************************
831
#define EMAC_TIMADD_TSAR_M 0xFFFFFFFF
// Timestamp Addend Register
832
#define EMAC_TIMADD_TSAR_S 0
833
834
//*****************************************************************************
835
//
836
// The following are defines for the bit fields in the EMAC_O_TARGSEC register.
837
//
838
//*****************************************************************************
839
#define EMAC_TARGSEC_TSTR_M 0xFFFFFFFF
// Target Time Seconds Register
840
#define EMAC_TARGSEC_TSTR_S 0
841
842
//*****************************************************************************
843
//
844
// The following are defines for the bit fields in the EMAC_O_TARGNANO
845
// register.
846
//
847
//*****************************************************************************
848
#define EMAC_TARGNANO_TRGTBUSY 0x80000000
// Target Time Register Busy
849
#define EMAC_TARGNANO_TTSLO_M 0x7FFFFFFF
// Target Timestamp Low Register
850
#define EMAC_TARGNANO_TTSLO_S 0
851
852
//*****************************************************************************
853
//
854
// The following are defines for the bit fields in the EMAC_O_HWORDSEC
855
// register.
856
//
857
//*****************************************************************************
858
#define EMAC_HWORDSEC_TSHWR_M 0x0000FFFF
// Target Timestamp Higher Word
859
// Register
860
#define EMAC_HWORDSEC_TSHWR_S 0
861
862
//*****************************************************************************
863
//
864
// The following are defines for the bit fields in the EMAC_O_TIMSTAT register.
865
//
866
//*****************************************************************************
867
#define EMAC_TIMSTAT_TSTARGT 0x00000002
// Timestamp Target Time Reached
868
#define EMAC_TIMSTAT_TSSOVF 0x00000001
// Timestamp Seconds Overflow
869
870
//*****************************************************************************
871
//
872
// The following are defines for the bit fields in the EMAC_O_PPSCTRL register.
873
//
874
//*****************************************************************************
875
#define EMAC_PPSCTRL_TRGMODS0_M 0x00000060
// Target Time Register Mode for
876
// PPS0 Output
877
#define EMAC_PPSCTRL_TRGMODS0_INTONLY \
878
0x00000000
// Indicates that the Target Time
879
// registers are programmed only
880
// for generating the interrupt
881
// event
882
#define EMAC_PPSCTRL_TRGMODS0_INTPPS0 \
883
0x00000040
// Indicates that the Target Time
884
// registers are programmed for
885
// generating the interrupt event
886
// and starting or stopping the
887
// generation of the EN0PPS output
888
// signal
889
#define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY \
890
0x00000060
// Indicates that the Target Time
891
// registers are programmed only
892
// for starting or stopping the
893
// generation of the EN0PPS output
894
// signal. No interrupt is asserted
895
#define EMAC_PPSCTRL_PPSEN0 0x00000010
// Flexible PPS Output Mode Enable
896
#define EMAC_PPSCTRL_PPSCTRL_M 0x0000000F
// EN0PPS Output Frequency Control
897
// (PPSCTRL) or Command Control
898
// (PPSCMD)
899
900
//*****************************************************************************
901
//
902
// The following are defines for the bit fields in the EMAC_O_PPS0INTVL
903
// register.
904
//
905
//*****************************************************************************
906
#define EMAC_PPS0INTVL_PPS0INT_M \
907
0xFFFFFFFF
// PPS0 Output Signal Interval
908
#define EMAC_PPS0INTVL_PPS0INT_S \
909
0
910
911
//*****************************************************************************
912
//
913
// The following are defines for the bit fields in the EMAC_O_PPS0WIDTH
914
// register.
915
//
916
//*****************************************************************************
917
#define EMAC_PPS0WIDTH_M 0xFFFFFFFF
// EN0PPS Output Signal Width
918
#define EMAC_PPS0WIDTH_S 0
919
920
//*****************************************************************************
921
//
922
// The following are defines for the bit fields in the EMAC_O_DMABUSMOD
923
// register.
924
//
925
//*****************************************************************************
926
#define EMAC_DMABUSMOD_RIB 0x80000000
// Rebuild Burst
927
#define EMAC_DMABUSMOD_TXPR 0x08000000
// Transmit Priority
928
#define EMAC_DMABUSMOD_MB 0x04000000
// Mixed Burst
929
#define EMAC_DMABUSMOD_AAL 0x02000000
// Address Aligned Beats
930
#define EMAC_DMABUSMOD_8XPBL 0x01000000
// 8 x Programmable Burst Length
931
// (PBL) Mode
932
#define EMAC_DMABUSMOD_USP 0x00800000
// Use Separate Programmable Burst
933
// Length (PBL)
934
#define EMAC_DMABUSMOD_RPBL_M 0x007E0000
// RX DMA Programmable Burst Length
935
// (PBL)
936
#define EMAC_DMABUSMOD_FB 0x00010000
// Fixed Burst
937
#define EMAC_DMABUSMOD_PR_M 0x0000C000
// Priority Ratio
938
#define EMAC_DMABUSMOD_PBL_M 0x00003F00
// Programmable Burst Length
939
#define EMAC_DMABUSMOD_ATDS 0x00000080
// Alternate Descriptor Size
940
#define EMAC_DMABUSMOD_DSL_M 0x0000007C
// Descriptor Skip Length
941
#define EMAC_DMABUSMOD_DA 0x00000002
// DMA Arbitration Scheme
942
#define EMAC_DMABUSMOD_SWR 0x00000001
// DMA Software Reset
943
#define EMAC_DMABUSMOD_RPBL_S 17
944
#define EMAC_DMABUSMOD_PR_S 14
945
#define EMAC_DMABUSMOD_PBL_S 8
946
#define EMAC_DMABUSMOD_DSL_S 2
947
948
//*****************************************************************************
949
//
950
// The following are defines for the bit fields in the EMAC_O_TXPOLLD register.
951
//
952
//*****************************************************************************
953
#define EMAC_TXPOLLD_TPD_M 0xFFFFFFFF
// Transmit Poll Demand
954
#define EMAC_TXPOLLD_TPD_S 0
955
956
//*****************************************************************************
957
//
958
// The following are defines for the bit fields in the EMAC_O_RXPOLLD register.
959
//
960
//*****************************************************************************
961
#define EMAC_RXPOLLD_RPD_M 0xFFFFFFFF
// Receive Poll Demand
962
#define EMAC_RXPOLLD_RPD_S 0
963
964
//*****************************************************************************
965
//
966
// The following are defines for the bit fields in the EMAC_O_RXDLADDR
967
// register.
968
//
969
//*****************************************************************************
970
#define EMAC_RXDLADDR_STRXLIST_M \
971
0xFFFFFFFC
// Start of Receive List
972
#define EMAC_RXDLADDR_STRXLIST_S \
973
2
974
975
//*****************************************************************************
976
//
977
// The following are defines for the bit fields in the EMAC_O_TXDLADDR
978
// register.
979
//
980
//*****************************************************************************
981
#define EMAC_TXDLADDR_TXDLADDR_M \
982
0xFFFFFFFC
// Start of Transmit List Base
983
// Address
984
#define EMAC_TXDLADDR_TXDLADDR_S \
985
2
986
987
//*****************************************************************************
988
//
989
// The following are defines for the bit fields in the EMAC_O_DMARIS register.
990
//
991
//*****************************************************************************
992
#define EMAC_DMARIS_LPI 0x40000000
// LPI Trigger Interrupt Status
993
#define EMAC_DMARIS_TT 0x20000000
// Timestamp Trigger Interrupt
994
// Status
995
#define EMAC_DMARIS_PMT 0x10000000
// MAC PMT Interrupt Status
996
#define EMAC_DMARIS_MMC 0x08000000
// MAC MMC Interrupt
997
#define EMAC_DMARIS_AE_M 0x03800000
// Access Error
998
#define EMAC_DMARIS_AE_RXDMAWD 0x00000000
// Error during RX DMA Write Data
999
// Transfer
1000
#define EMAC_DMARIS_AE_TXDMARD 0x01800000
// Error during TX DMA Read Data
1001
// Transfer
1002
#define EMAC_DMARIS_AE_RXDMADW 0x02000000
// Error during RX DMA Descriptor
1003
// Write Access
1004
#define EMAC_DMARIS_AE_TXDMADW 0x02800000
// Error during TX DMA Descriptor
1005
// Write Access
1006
#define EMAC_DMARIS_AE_RXDMADR 0x03000000
// Error during RX DMA Descriptor
1007
// Read Access
1008
#define EMAC_DMARIS_AE_TXDMADR 0x03800000
// Error during TX DMA Descriptor
1009
// Read Access
1010
#define EMAC_DMARIS_TS_M 0x00700000
// Transmit Process State
1011
#define EMAC_DMARIS_TS_STOP 0x00000000
// Stopped; Reset or Stop transmit
1012
// command processed
1013
#define EMAC_DMARIS_TS_RUNTXTD 0x00100000
// Running; Fetching transmit
1014
// transfer descriptor
1015
#define EMAC_DMARIS_TS_STATUS 0x00200000
// Running; Waiting for status
1016
#define EMAC_DMARIS_TS_RUNTX 0x00300000
// Running; Reading data from host
1017
// memory buffer and queuing it to
1018
// transmit buffer (TX FIFO)
1019
#define EMAC_DMARIS_TS_TSTAMP 0x00400000
// Writing Timestamp
1020
#define EMAC_DMARIS_TS_SUSPEND 0x00600000
// Suspended; Transmit descriptor
1021
// unavailable or transmit buffer
1022
// underflow
1023
#define EMAC_DMARIS_TS_RUNCTD 0x00700000
// Running; Closing transmit
1024
// descriptor
1025
#define EMAC_DMARIS_RS_M 0x000E0000
// Received Process State
1026
#define EMAC_DMARIS_RS_STOP 0x00000000
// Stopped: Reset or stop receive
1027
// command issued
1028
#define EMAC_DMARIS_RS_RUNRXTD 0x00020000
// Running: Fetching receive
1029
// transfer descriptor
1030
#define EMAC_DMARIS_RS_RUNRXD 0x00060000
// Running: Waiting for receive
1031
// packet
1032
#define EMAC_DMARIS_RS_SUSPEND 0x00080000
// Suspended: Receive descriptor
1033
// unavailable
1034
#define EMAC_DMARIS_RS_RUNCRD 0x000A0000
// Running: Closing receive
1035
// descriptor
1036
#define EMAC_DMARIS_RS_TSWS 0x000C0000
// Writing Timestamp
1037
#define EMAC_DMARIS_RS_RUNTXD 0x000E0000
// Running: Transferring the
1038
// receive packet data from receive
1039
// buffer to host memory
1040
#define EMAC_DMARIS_NIS 0x00010000
// Normal Interrupt Summary
1041
#define EMAC_DMARIS_AIS 0x00008000
// Abnormal Interrupt Summary
1042
#define EMAC_DMARIS_ERI 0x00004000
// Early Receive Interrupt
1043
#define EMAC_DMARIS_FBI 0x00002000
// Fatal Bus Error Interrupt
1044
#define EMAC_DMARIS_ETI 0x00000400
// Early Transmit Interrupt
1045
#define EMAC_DMARIS_RWT 0x00000200
// Receive Watchdog Timeout
1046
#define EMAC_DMARIS_RPS 0x00000100
// Receive Process Stopped
1047
#define EMAC_DMARIS_RU 0x00000080
// Receive Buffer Unavailable
1048
#define EMAC_DMARIS_RI 0x00000040
// Receive Interrupt
1049
#define EMAC_DMARIS_UNF 0x00000020
// Transmit Underflow
1050
#define EMAC_DMARIS_OVF 0x00000010
// Receive Overflow
1051
#define EMAC_DMARIS_TJT 0x00000008
// Transmit Jabber Timeout
1052
#define EMAC_DMARIS_TU 0x00000004
// Transmit Buffer Unavailable
1053
#define EMAC_DMARIS_TPS 0x00000002
// Transmit Process Stopped
1054
#define EMAC_DMARIS_TI 0x00000001
// Transmit Interrupt
1055
1056
//*****************************************************************************
1057
//
1058
// The following are defines for the bit fields in the EMAC_O_DMAOPMODE
1059
// register.
1060
//
1061
//*****************************************************************************
1062
#define EMAC_DMAOPMODE_DT 0x04000000
// Disable Dropping of TCP/IP
1063
// Checksum Error Frames
1064
#define EMAC_DMAOPMODE_RSF 0x02000000
// Receive Store and Forward
1065
#define EMAC_DMAOPMODE_DFF 0x01000000
// Disable Flushing of Received
1066
// Frames
1067
#define EMAC_DMAOPMODE_TSF 0x00200000
// Transmit Store and Forward
1068
#define EMAC_DMAOPMODE_FTF 0x00100000
// Flush Transmit FIFO
1069
#define EMAC_DMAOPMODE_TTC_M 0x0001C000
// Transmit Threshold Control
1070
#define EMAC_DMAOPMODE_TTC_64 0x00000000
// 64 bytes
1071
#define EMAC_DMAOPMODE_TTC_128 0x00004000
// 128 bytes
1072
#define EMAC_DMAOPMODE_TTC_192 0x00008000
// 192 bytes
1073
#define EMAC_DMAOPMODE_TTC_256 0x0000C000
// 256 bytes
1074
#define EMAC_DMAOPMODE_TTC_40 0x00010000
// 40 bytes
1075
#define EMAC_DMAOPMODE_TTC_32 0x00014000
// 32 bytes
1076
#define EMAC_DMAOPMODE_TTC_24 0x00018000
// 24 bytes
1077
#define EMAC_DMAOPMODE_TTC_16 0x0001C000
// 16 bytes
1078
#define EMAC_DMAOPMODE_ST 0x00002000
// Start or Stop Transmission
1079
// Command
1080
#define EMAC_DMAOPMODE_FEF 0x00000080
// Forward Error Frames
1081
#define EMAC_DMAOPMODE_FUF 0x00000040
// Forward Undersized Good Frames
1082
#define EMAC_DMAOPMODE_DGF 0x00000020
// Drop Giant Frame Enable
1083
#define EMAC_DMAOPMODE_RTC_M 0x00000018
// Receive Threshold Control
1084
#define EMAC_DMAOPMODE_RTC_64 0x00000000
// 64 bytes
1085
#define EMAC_DMAOPMODE_RTC_32 0x00000008
// 32 bytes
1086
#define EMAC_DMAOPMODE_RTC_96 0x00000010
// 96 bytes
1087
#define EMAC_DMAOPMODE_RTC_128 0x00000018
// 128 bytes
1088
#define EMAC_DMAOPMODE_OSF 0x00000004
// Operate on Second Frame
1089
#define EMAC_DMAOPMODE_SR 0x00000002
// Start or Stop Receive
1090
1091
//*****************************************************************************
1092
//
1093
// The following are defines for the bit fields in the EMAC_O_DMAIM register.
1094
//
1095
//*****************************************************************************
1096
#define EMAC_DMAIM_NIE 0x00010000
// Normal Interrupt Summary Enable
1097
#define EMAC_DMAIM_AIE 0x00008000
// Abnormal Interrupt Summary
1098
// Enable
1099
#define EMAC_DMAIM_ERE 0x00004000
// Early Receive Interrupt Enable
1100
#define EMAC_DMAIM_FBE 0x00002000
// Fatal Bus Error Enable
1101
#define EMAC_DMAIM_ETE 0x00000400
// Early Transmit Interrupt Enable
1102
#define EMAC_DMAIM_RWE 0x00000200
// Receive Watchdog Timeout Enable
1103
#define EMAC_DMAIM_RSE 0x00000100
// Receive Stopped Enable
1104
#define EMAC_DMAIM_RUE 0x00000080
// Receive Buffer Unavailable
1105
// Enable
1106
#define EMAC_DMAIM_RIE 0x00000040
// Receive Interrupt Enable
1107
#define EMAC_DMAIM_UNE 0x00000020
// Underflow Interrupt Enable
1108
#define EMAC_DMAIM_OVE 0x00000010
// Overflow Interrupt Enable
1109
#define EMAC_DMAIM_TJE 0x00000008
// Transmit Jabber Timeout Enable
1110
#define EMAC_DMAIM_TUE 0x00000004
// Transmit Buffer Unvailable
1111
// Enable
1112
#define EMAC_DMAIM_TSE 0x00000002
// Transmit Stopped Enable
1113
#define EMAC_DMAIM_TIE 0x00000001
// Transmit Interrupt Enable
1114
1115
//*****************************************************************************
1116
//
1117
// The following are defines for the bit fields in the EMAC_O_MFBOC register.
1118
//
1119
//*****************************************************************************
1120
#define EMAC_MFBOC_OVFCNTOVF 0x10000000
// Overflow Bit for FIFO Overflow
1121
// Counter
1122
#define EMAC_MFBOC_OVFFRMCNT_M 0x0FFE0000
// Overflow Frame Counter
1123
#define EMAC_MFBOC_MISCNTOVF 0x00010000
// Overflow bit for Missed Frame
1124
// Counter
1125
#define EMAC_MFBOC_MISFRMCNT_M 0x0000FFFF
// Missed Frame Counter
1126
#define EMAC_MFBOC_OVFFRMCNT_S 17
1127
#define EMAC_MFBOC_MISFRMCNT_S 0
1128
1129
//*****************************************************************************
1130
//
1131
// The following are defines for the bit fields in the EMAC_O_RXINTWDT
1132
// register.
1133
//
1134
//*****************************************************************************
1135
#define EMAC_RXINTWDT_RIWT_M 0x000000FF
// Receive Interrupt Watchdog Timer
1136
// Count
1137
#define EMAC_RXINTWDT_RIWT_S 0
1138
1139
//*****************************************************************************
1140
//
1141
// The following are defines for the bit fields in the EMAC_O_HOSTXDESC
1142
// register.
1143
//
1144
//*****************************************************************************
1145
#define EMAC_HOSTXDESC_CURTXDESC_M \
1146
0xFFFFFFFF
// Host Transmit Descriptor Address
1147
// Pointer
1148
#define EMAC_HOSTXDESC_CURTXDESC_S \
1149
0
1150
1151
//*****************************************************************************
1152
//
1153
// The following are defines for the bit fields in the EMAC_O_HOSRXDESC
1154
// register.
1155
//
1156
//*****************************************************************************
1157
#define EMAC_HOSRXDESC_CURRXDESC_M \
1158
0xFFFFFFFF
// Host Receive Descriptor Address
1159
// Pointer
1160
#define EMAC_HOSRXDESC_CURRXDESC_S \
1161
0
1162
1163
//*****************************************************************************
1164
//
1165
// The following are defines for the bit fields in the EMAC_O_HOSTXBA register.
1166
//
1167
//*****************************************************************************
1168
#define EMAC_HOSTXBA_CURTXBUFA_M \
1169
0xFFFFFFFF
// Host Transmit Buffer Address
1170
// Pointer
1171
#define EMAC_HOSTXBA_CURTXBUFA_S \
1172
0
1173
1174
//*****************************************************************************
1175
//
1176
// The following are defines for the bit fields in the EMAC_O_HOSRXBA register.
1177
//
1178
//*****************************************************************************
1179
#define EMAC_HOSRXBA_CURRXBUFA_M \
1180
0xFFFFFFFF
// Host Receive Buffer Address
1181
// Pointer
1182
#define EMAC_HOSRXBA_CURRXBUFA_S \
1183
0
1184
1185
//*****************************************************************************
1186
//
1187
// The following are defines for the bit fields in the EMAC_O_PP register.
1188
//
1189
//*****************************************************************************
1190
#define EMAC_PP_MACTYPE_M 0x00000700
// Ethernet MAC Type
1191
#define EMAC_PP_MACTYPE_1 0x00000100
// Tiva TM4E129x-class MAC
1192
#define EMAC_PP_PHYTYPE_M 0x00000007
// Ethernet PHY Type
1193
#define EMAC_PP_PHYTYPE_NONE 0x00000000
// No PHY
1194
#define EMAC_PP_PHYTYPE_1 0x00000003
// Snowflake class PHY
1195
1196
//*****************************************************************************
1197
//
1198
// The following are defines for the bit fields in the EMAC_O_PC register.
1199
//
1200
//*****************************************************************************
1201
#define EMAC_PC_PHYEXT 0x80000000
// PHY Select
1202
#define EMAC_PC_PINTFS_M 0x70000000
// Ethernet Interface Select
1203
#define EMAC_PC_PINTFS_IMII 0x00000000
// MII (default) Used for internal
1204
// PHY or external PHY connected
1205
// via MII
1206
#define EMAC_PC_PINTFS_RMII 0x40000000
// RMII: Used for external PHY
1207
// connected via RMII
1208
#define EMAC_PC_DIGRESTART 0x02000000
// PHY Soft Restart
1209
#define EMAC_PC_NIBDETDIS 0x01000000
// Odd Nibble TXER Detection
1210
// Disable
1211
#define EMAC_PC_RXERIDLE 0x00800000
// RXER Detection During Idle
1212
#define EMAC_PC_ISOMIILL 0x00400000
// Isolate MII in Link Loss
1213
#define EMAC_PC_LRR 0x00200000
// Link Loss Recovery
1214
#define EMAC_PC_TDRRUN 0x00100000
// TDR Auto Run
1215
#define EMAC_PC_FASTLDMODE_M 0x000F8000
// Fast Link Down Mode
1216
#define EMAC_PC_POLSWAP 0x00004000
// Polarity Swap
1217
#define EMAC_PC_MDISWAP 0x00002000
// MDI Swap
1218
#define EMAC_PC_RBSTMDIX 0x00001000
// Robust Auto MDI-X
1219
#define EMAC_PC_FASTMDIX 0x00000800
// Fast Auto MDI-X
1220
#define EMAC_PC_MDIXEN 0x00000400
// MDIX Enable
1221
#define EMAC_PC_FASTRXDV 0x00000200
// Fast RXDV Detection
1222
#define EMAC_PC_FASTLUPD 0x00000100
// FAST Link-Up in Parallel Detect
1223
#define EMAC_PC_EXTFD 0x00000080
// Extended Full Duplex Ability
1224
#define EMAC_PC_FASTANEN 0x00000040
// Fast Auto Negotiation Enable
1225
#define EMAC_PC_FASTANSEL_M 0x00000030
// Fast Auto Negotiation Select
1226
#define EMAC_PC_ANEN 0x00000008
// Auto Negotiation Enable
1227
#define EMAC_PC_ANMODE_M 0x00000006
// Auto Negotiation Mode
1228
#define EMAC_PC_ANMODE_10HD 0x00000000
// When ANEN = 0x0, the mode is
1229
// 10Base-T, Half-Duplex
1230
#define EMAC_PC_ANMODE_10FD 0x00000002
// When ANEN = 0x0, the mode is
1231
// 10Base-T, Full-Duplex
1232
#define EMAC_PC_ANMODE_100HD 0x00000004
// When ANEN = 0x0, the mode is
1233
// 100Base-TX, Half-Duplex
1234
#define EMAC_PC_ANMODE_100FD 0x00000006
// When ANEN = 0x0, the mode is
1235
// 100Base-TX, Full-Duplex
1236
#define EMAC_PC_PHYHOLD 0x00000001
// Ethernet PHY Hold
1237
#define EMAC_PC_FASTLDMODE_S 15
1238
#define EMAC_PC_FASTANSEL_S 4
1239
1240
//*****************************************************************************
1241
//
1242
// The following are defines for the bit fields in the EMAC_O_CC register.
1243
//
1244
//*****************************************************************************
1245
#define EMAC_CC_PTPCEN 0x00040000
// PTP Clock Reference Enable
1246
#define EMAC_CC_POL 0x00020000
// LED Polarity Control
1247
#define EMAC_CC_CLKEN 0x00010000
// EN0RREF_CLK Signal Enable
1248
1249
//*****************************************************************************
1250
//
1251
// The following are defines for the bit fields in the EMAC_O_EPHYRIS register.
1252
//
1253
//*****************************************************************************
1254
#define EMAC_EPHYRIS_INT 0x00000001
// Ethernet PHY Raw Interrupt
1255
// Status
1256
1257
//*****************************************************************************
1258
//
1259
// The following are defines for the bit fields in the EMAC_O_EPHYIM register.
1260
//
1261
//*****************************************************************************
1262
#define EMAC_EPHYIM_INT 0x00000001
// Ethernet PHY Interrupt Mask
1263
1264
//*****************************************************************************
1265
//
1266
// The following are defines for the bit fields in the EMAC_O_EPHYMISC
1267
// register.
1268
//
1269
//*****************************************************************************
1270
#define EMAC_EPHYMISC_INT 0x00000001
// Ethernet PHY Status and Clear
1271
// register
1272
1273
//*****************************************************************************
1274
//
1275
// The following are defines for the EPHY register offsets.
1276
//
1277
//*****************************************************************************
1278
#define EPHY_BMCR 0x00000000
// Ethernet PHY Basic Mode Control
1279
#define EPHY_BMSR 0x00000001
// Ethernet PHY Basic Mode Status
1280
#define EPHY_ID1 0x00000002
// Ethernet PHY Identifier Register
1281
// 1
1282
#define EPHY_ID2 0x00000003
// Ethernet PHY Identifier Register
1283
// 2
1284
#define EPHY_ANA 0x00000004
// Ethernet PHY Auto-Negotiation
1285
// Advertisement
1286
#define EPHY_ANLPA 0x00000005
// Ethernet PHY Auto-Negotiation
1287
// Link Partner Ability
1288
#define EPHY_ANER 0x00000006
// Ethernet PHY Auto-Negotiation
1289
// Expansion
1290
#define EPHY_ANNPTR 0x00000007
// Ethernet PHY Auto-Negotiation
1291
// Next Page TX
1292
#define EPHY_ANLNPTR 0x00000008
// Ethernet PHY Auto-Negotiation
1293
// Link Partner Ability Next Page
1294
#define EPHY_CFG1 0x00000009
// Ethernet PHY Configuration 1
1295
#define EPHY_CFG2 0x0000000A
// Ethernet PHY Configuration 2
1296
#define EPHY_CFG3 0x0000000B
// Ethernet PHY Configuration 3
1297
#define EPHY_REGCTL 0x0000000D
// Ethernet PHY Register Control
1298
#define EPHY_ADDAR 0x0000000E
// Ethernet PHY Address or Data
1299
#define EPHY_STS 0x00000010
// Ethernet PHY Status
1300
#define EPHY_SCR 0x00000011
// Ethernet PHY Specific Control
1301
#define EPHY_MISR1 0x00000012
// Ethernet PHY MII Interrupt
1302
// Status 1
1303
#define EPHY_MISR2 0x00000013
// Ethernet PHY MII Interrupt
1304
// Status 2
1305
#define EPHY_FCSCR 0x00000014
// Ethernet PHY False Carrier Sense
1306
// Counter
1307
#define EPHY_RXERCNT 0x00000015
// Ethernet PHY Receive Error Count
1308
#define EPHY_BISTCR 0x00000016
// Ethernet PHY BIST Control
1309
#define EPHY_LEDCR 0x00000018
// Ethernet PHY LED Control
1310
#define EPHY_CTL 0x00000019
// Ethernet PHY Control
1311
#define EPHY_10BTSC 0x0000001A
// Ethernet PHY 10Base-T
1312
// Status/Control - MR26
1313
#define EPHY_BICSR1 0x0000001B
// Ethernet PHY BIST Control and
1314
// Status 1
1315
#define EPHY_BICSR2 0x0000001C
// Ethernet PHY BIST Control and
1316
// Status 2
1317
#define EPHY_CDCR 0x0000001E
// Ethernet PHY Cable Diagnostic
1318
// Control
1319
#define EPHY_RCR 0x0000001F
// Ethernet PHY Reset Control
1320
#define EPHY_LEDCFG 0x00000025
// Ethernet PHY LED Configuration
1321
1322
//*****************************************************************************
1323
//
1324
// The following are defines for the bit fields in the EPHY_BMCR register.
1325
//
1326
//*****************************************************************************
1327
#define EPHY_BMCR_MIIRESET 0x00008000
// MII Register reset
1328
#define EPHY_BMCR_MIILOOPBK 0x00004000
// MII Loopback
1329
#define EPHY_BMCR_SPEED 0x00002000
// Speed Select
1330
#define EPHY_BMCR_ANEN 0x00001000
// Auto-Negotiate Enable
1331
#define EPHY_BMCR_PWRDWN 0x00000800
// Power Down
1332
#define EPHY_BMCR_ISOLATE 0x00000400
// Port Isolate
1333
#define EPHY_BMCR_RESTARTAN 0x00000200
// Restart Auto-Negotiation
1334
#define EPHY_BMCR_DUPLEXM 0x00000100
// Duplex Mode
1335
#define EPHY_BMCR_COLLTST 0x00000080
// Collision Test
1336
1337
//*****************************************************************************
1338
//
1339
// The following are defines for the bit fields in the EPHY_BMSR register.
1340
//
1341
//*****************************************************************************
1342
#define EPHY_BMSR_100BTXFD 0x00004000
// 100Base-TX Full Duplex Capable
1343
#define EPHY_BMSR_100BTXHD 0x00002000
// 100Base-TX Half Duplex Capable
1344
#define EPHY_BMSR_10BTFD 0x00001000
// 10 Base-T Full Duplex Capable
1345
#define EPHY_BMSR_10BTHD 0x00000800
// 10 Base-T Half Duplex Capable
1346
#define EPHY_BMSR_MFPRESUP 0x00000040
// Preamble Suppression Capable
1347
#define EPHY_BMSR_ANC 0x00000020
// Auto-Negotiation Complete
1348
#define EPHY_BMSR_RFAULT 0x00000010
// Remote Fault
1349
#define EPHY_BMSR_ANEN 0x00000008
// Auto Negotiation Enabled
1350
#define EPHY_BMSR_LINKSTAT 0x00000004
// Link Status
1351
#define EPHY_BMSR_JABBER 0x00000002
// Jabber Detect
1352
#define EPHY_BMSR_EXTEN 0x00000001
// Extended Capability Enable
1353
1354
//*****************************************************************************
1355
//
1356
// The following are defines for the bit fields in the EPHY_ID1 register.
1357
//
1358
//*****************************************************************************
1359
#define EPHY_ID1_OUIMSB_M 0x0000FFFF
// OUI Most Significant Bits
1360
#define EPHY_ID1_OUIMSB_S 0
1361
1362
//*****************************************************************************
1363
//
1364
// The following are defines for the bit fields in the EPHY_ID2 register.
1365
//
1366
//*****************************************************************************
1367
#define EPHY_ID2_OUILSB_M 0x0000FC00
// OUI Least Significant Bits
1368
#define EPHY_ID2_VNDRMDL_M 0x000003F0
// Vendor Model Number
1369
#define EPHY_ID2_MDLREV_M 0x0000000F
// Model Revision Number
1370
#define EPHY_ID2_OUILSB_S 10
1371
#define EPHY_ID2_VNDRMDL_S 4
1372
#define EPHY_ID2_MDLREV_S 0
1373
1374
//*****************************************************************************
1375
//
1376
// The following are defines for the bit fields in the EPHY_ANA register.
1377
//
1378
//*****************************************************************************
1379
#define EPHY_ANA_NP 0x00008000
// Next Page Indication
1380
#define EPHY_ANA_RF 0x00002000
// Remote Fault
1381
#define EPHY_ANA_ASMDUP 0x00000800
// Asymmetric PAUSE support for
1382
// Full Duplex Links
1383
#define EPHY_ANA_PAUSE 0x00000400
// PAUSE Support for Full Duplex
1384
// Links
1385
#define EPHY_ANA_100BT4 0x00000200
// 100Base-T4 Support
1386
#define EPHY_ANA_100BTXFD 0x00000100
// 100Base-TX Full Duplex Support
1387
#define EPHY_ANA_100BTX 0x00000080
// 100Base-TX Support
1388
#define EPHY_ANA_10BTFD 0x00000040
// 10Base-T Full Duplex Support
1389
#define EPHY_ANA_10BT 0x00000020
// 10Base-T Support
1390
#define EPHY_ANA_SELECT_M 0x0000001F
// Protocol Selection
1391
#define EPHY_ANA_SELECT_S 0
1392
1393
//*****************************************************************************
1394
//
1395
// The following are defines for the bit fields in the EPHY_ANLPA register.
1396
//
1397
//*****************************************************************************
1398
#define EPHY_ANLPA_NP 0x00008000
// Next Page Indication
1399
#define EPHY_ANLPA_ACK 0x00004000
// Acknowledge
1400
#define EPHY_ANLPA_RF 0x00002000
// Remote Fault
1401
#define EPHY_ANLPA_ASMDUP 0x00000800
// Asymmetric PAUSE
1402
#define EPHY_ANLPA_PAUSE 0x00000400
// PAUSE
1403
#define EPHY_ANLPA_100BT4 0x00000200
// 100Base-T4 Support
1404
#define EPHY_ANLPA_100BTXFD 0x00000100
// 100Base-TX Full Duplex Support
1405
#define EPHY_ANLPA_100BTX 0x00000080
// 100Base-TX Support
1406
#define EPHY_ANLPA_10BTFD 0x00000040
// 10Base-T Full Duplex Support
1407
#define EPHY_ANLPA_10BT 0x00000020
// 10Base-T Support
1408
#define EPHY_ANLPA_SELECT_M 0x0000001F
// Protocol Selection
1409
#define EPHY_ANLPA_SELECT_S 0
1410
1411
//*****************************************************************************
1412
//
1413
// The following are defines for the bit fields in the EPHY_ANER register.
1414
//
1415
//*****************************************************************************
1416
#define EPHY_ANER_PDF 0x00000010
// Parallel Detection Fault
1417
#define EPHY_ANER_LPNPABLE 0x00000008
// Link Partner Next Page Able
1418
#define EPHY_ANER_NPABLE 0x00000004
// Next Page Able
1419
#define EPHY_ANER_PAGERX 0x00000002
// Link Code Word Page Received
1420
#define EPHY_ANER_LPANABLE 0x00000001
// Link Partner Auto-Negotiation
1421
// Able
1422
1423
//*****************************************************************************
1424
//
1425
// The following are defines for the bit fields in the EPHY_ANNPTR register.
1426
//
1427
//*****************************************************************************
1428
#define EPHY_ANNPTR_NP 0x00008000
// Next Page Indication
1429
#define EPHY_ANNPTR_MP 0x00002000
// Message Page
1430
#define EPHY_ANNPTR_ACK2 0x00001000
// Acknowledge 2
1431
#define EPHY_ANNPTR_TOGTX 0x00000800
// Toggle
1432
#define EPHY_ANNPTR_CODE_M 0x000007FF
// Code
1433
#define EPHY_ANNPTR_CODE_S 0
1434
1435
//*****************************************************************************
1436
//
1437
// The following are defines for the bit fields in the EPHY_ANLNPTR register.
1438
//
1439
//*****************************************************************************
1440
#define EPHY_ANLNPTR_NP 0x00008000
// Next Page Indication
1441
#define EPHY_ANLNPTR_ACK 0x00004000
// Acknowledge
1442
#define EPHY_ANLNPTR_MP 0x00002000
// Message Page
1443
#define EPHY_ANLNPTR_ACK2 0x00001000
// Acknowledge 2
1444
#define EPHY_ANLNPTR_TOG 0x00000800
// Toggle
1445
#define EPHY_ANLNPTR_CODE_M 0x000007FF
// Code
1446
#define EPHY_ANLNPTR_CODE_S 0
1447
1448
//*****************************************************************************
1449
//
1450
// The following are defines for the bit fields in the EPHY_CFG1 register.
1451
//
1452
//*****************************************************************************
1453
#define EPHY_CFG1_DONE 0x00008000
// Configuration Done
1454
#define EPHY_CFG1_TDRAR 0x00000100
// TDR Auto-Run at Link Down
1455
#define EPHY_CFG1_LLR 0x00000080
// Link Loss Recovery
1456
#define EPHY_CFG1_FAMDIX 0x00000040
// Fast Auto MDI/MDIX
1457
#define EPHY_CFG1_RAMDIX 0x00000020
// Robust Auto MDI/MDIX
1458
#define EPHY_CFG1_FASTANEN 0x00000010
// Fast Auto Negotiation Enable
1459
#define EPHY_CFG1_FANSEL_M 0x0000000C
// Fast Auto-Negotiation Select
1460
// Configuration
1461
#define EPHY_CFG1_FANSEL_BLT80 0x00000000
// Break Link Timer: 80 ms
1462
#define EPHY_CFG1_FANSEL_BLT120 0x00000004
// Break Link Timer: 120 ms
1463
#define EPHY_CFG1_FANSEL_BLT240 0x00000008
// Break Link Timer: 240 ms
1464
#define EPHY_CFG1_FRXDVDET 0x00000002
// FAST RXDV Detection
1465
1466
//*****************************************************************************
1467
//
1468
// The following are defines for the bit fields in the EPHY_CFG2 register.
1469
//
1470
//*****************************************************************************
1471
#define EPHY_CFG2_FLUPPD 0x00000040
// Fast Link-Up in Parallel Detect
1472
// Mode
1473
#define EPHY_CFG2_EXTFD 0x00000020
// Extended Full-Duplex Ability
1474
#define EPHY_CFG2_ENLEDLINK 0x00000010
// Enhanced LED Functionality
1475
#define EPHY_CFG2_ISOMIILL 0x00000008
// Isolate MII outputs when
1476
// Enhanced Link is not Achievable
1477
#define EPHY_CFG2_RXERRIDLE 0x00000004
// Detection of Receive Symbol
1478
// Error During IDLE State
1479
#define EPHY_CFG2_ODDNDETDIS 0x00000002
// Detection of Transmit Error
1480
1481
//*****************************************************************************
1482
//
1483
// The following are defines for the bit fields in the EPHY_CFG3 register.
1484
//
1485
//*****************************************************************************
1486
#define EPHY_CFG3_POLSWAP 0x00000080
// Polarity Swap
1487
#define EPHY_CFG3_MDIMDIXS 0x00000040
// MDI/MDIX Swap
1488
#define EPHY_CFG3_FLDWNM_M 0x0000001F
// Fast Link Down Modes
1489
#define EPHY_CFG3_FLDWNM_S 0
1490
1491
//*****************************************************************************
1492
//
1493
// The following are defines for the bit fields in the EPHY_REGCTL register.
1494
//
1495
//*****************************************************************************
1496
#define EPHY_REGCTL_FUNC_M 0x0000C000
// Function
1497
#define EPHY_REGCTL_FUNC_ADDR 0x00000000
// Address
1498
#define EPHY_REGCTL_FUNC_DATANI 0x00004000
// Data, no post increment
1499
#define EPHY_REGCTL_FUNC_DATAPIRW \
1500
0x00008000
// Data, post increment on read and
1501
// write
1502
#define EPHY_REGCTL_FUNC_DATAPIWO \
1503
0x0000C000
// Data, post increment on write
1504
// only
1505
#define EPHY_REGCTL_DEVAD_M 0x0000001F
// Device Address
1506
#define EPHY_REGCTL_DEVAD_S 0
1507
1508
//*****************************************************************************
1509
//
1510
// The following are defines for the bit fields in the EPHY_ADDAR register.
1511
//
1512
//*****************************************************************************
1513
#define EPHY_ADDAR_ADDRDATA_M 0x0000FFFF
// Address or Data
1514
#define EPHY_ADDAR_ADDRDATA_S 0
1515
1516
//*****************************************************************************
1517
//
1518
// The following are defines for the bit fields in the EPHY_STS register.
1519
//
1520
//*****************************************************************************
1521
#define EPHY_STS_MDIXM 0x00004000
// MDI-X Mode
1522
#define EPHY_STS_RXLERR 0x00002000
// Receive Error Latch
1523
#define EPHY_STS_POLSTAT 0x00001000
// Polarity Status
1524
#define EPHY_STS_FCSL 0x00000800
// False Carrier Sense Latch
1525
#define EPHY_STS_SD 0x00000400
// Signal Detect
1526
#define EPHY_STS_DL 0x00000200
// Descrambler Lock
1527
#define EPHY_STS_PAGERX 0x00000100
// Link Code Page Received
1528
#define EPHY_STS_MIIREQ 0x00000080
// MII Interrupt Pending
1529
#define EPHY_STS_RF 0x00000040
// Remote Fault
1530
#define EPHY_STS_JD 0x00000020
// Jabber Detect
1531
#define EPHY_STS_ANS 0x00000010
// Auto-Negotiation Status
1532
#define EPHY_STS_MIILB 0x00000008
// MII Loopback Status
1533
#define EPHY_STS_DUPLEX 0x00000004
// Duplex Status
1534
#define EPHY_STS_SPEED 0x00000002
// Speed Status
1535
#define EPHY_STS_LINK 0x00000001
// Link Status
1536
1537
//*****************************************************************************
1538
//
1539
// The following are defines for the bit fields in the EPHY_SCR register.
1540
//
1541
//*****************************************************************************
1542
#define EPHY_SCR_DISCLK 0x00008000
// Disable CLK
1543
#define EPHY_SCR_PSEN 0x00004000
// Power Saving Modes Enable
1544
#define EPHY_SCR_PSMODE_M 0x00003000
// Power Saving Modes
1545
#define EPHY_SCR_PSMODE_NORMAL 0x00000000
// Normal: Normal operation mode.
1546
// PHY is fully functional
1547
#define EPHY_SCR_PSMODE_LOWPWR 0x00001000
// IEEE Power Down
1548
#define EPHY_SCR_PSMODE_ACTWOL 0x00002000
// Active Sleep
1549
#define EPHY_SCR_PSMODE_PASWOL 0x00003000
// Passive Sleep
1550
#define EPHY_SCR_SBPYASS 0x00000800
// Scrambler Bypass
1551
#define EPHY_SCR_LBFIFO_M 0x00000300
// Loopback FIFO Depth
1552
#define EPHY_SCR_LBFIFO_4 0x00000000
// Four nibble FIFO
1553
#define EPHY_SCR_LBFIFO_5 0x00000100
// Five nibble FIFO
1554
#define EPHY_SCR_LBFIFO_6 0x00000200
// Six nibble FIFO
1555
#define EPHY_SCR_LBFIFO_8 0x00000300
// Eight nibble FIFO
1556
#define EPHY_SCR_COLFDM 0x00000010
// Collision in Full-Duplex Mode
1557
#define EPHY_SCR_TINT 0x00000004
// Test Interrupt
1558
#define EPHY_SCR_INTEN 0x00000002
// Interrupt Enable
1559
1560
//*****************************************************************************
1561
//
1562
// The following are defines for the bit fields in the EPHY_MISR1 register.
1563
//
1564
//*****************************************************************************
1565
#define EPHY_MISR1_LINKSTAT 0x00002000
// Change of Link Status Interrupt
1566
#define EPHY_MISR1_SPEED 0x00001000
// Change of Speed Status Interrupt
1567
#define EPHY_MISR1_DUPLEXM 0x00000800
// Change of Duplex Status
1568
// Interrupt
1569
#define EPHY_MISR1_ANC 0x00000400
// Auto-Negotiation Complete
1570
// Interrupt
1571
#define EPHY_MISR1_FCHF 0x00000200
// False Carrier Counter Half-Full
1572
// Interrupt
1573
#define EPHY_MISR1_RXHF 0x00000100
// Receive Error Counter Half-Full
1574
// Interrupt
1575
#define EPHY_MISR1_LINKSTATEN 0x00000020
// Link Status Interrupt Enable
1576
#define EPHY_MISR1_SPEEDEN 0x00000010
// Speed Change Interrupt Enable
1577
#define EPHY_MISR1_DUPLEXMEN 0x00000008
// Duplex Status Interrupt Enable
1578
#define EPHY_MISR1_ANCEN 0x00000004
// Auto-Negotiation Complete
1579
// Interrupt Enable
1580
#define EPHY_MISR1_FCHFEN 0x00000002
// False Carrier Counter Register
1581
// half-full Interrupt Enable
1582
#define EPHY_MISR1_RXHFEN 0x00000001
// Receive Error Counter Register
1583
// Half-Full Event Interrupt
1584
1585
//*****************************************************************************
1586
//
1587
// The following are defines for the bit fields in the EPHY_MISR2 register.
1588
//
1589
//*****************************************************************************
1590
#define EPHY_MISR2_ANERR 0x00004000
// Auto-Negotiation Error Interrupt
1591
#define EPHY_MISR2_PAGERX 0x00002000
// Page Receive Interrupt
1592
#define EPHY_MISR2_LBFIFO 0x00001000
// Loopback FIFO Overflow/Underflow
1593
// Event Interrupt
1594
#define EPHY_MISR2_MDICO 0x00000800
// MDI/MDIX Crossover Status
1595
// Changed Interrupt
1596
#define EPHY_MISR2_SLEEP 0x00000400
// Sleep Mode Event Interrupt
1597
#define EPHY_MISR2_POLINT 0x00000200
// Polarity Changed Interrupt
1598
#define EPHY_MISR2_JABBER 0x00000100
// Jabber Detect Event Interrupt
1599
#define EPHY_MISR2_ANERREN 0x00000040
// Auto-Negotiation Error Interrupt
1600
// Enable
1601
#define EPHY_MISR2_PAGERXEN 0x00000020
// Page Receive Interrupt Enable
1602
#define EPHY_MISR2_LBFIFOEN 0x00000010
// Loopback FIFO Overflow/Underflow
1603
// Interrupt Enable
1604
#define EPHY_MISR2_MDICOEN 0x00000008
// MDI/MDIX Crossover Status
1605
// Changed Interrupt Enable
1606
#define EPHY_MISR2_SLEEPEN 0x00000004
// Sleep Mode Event Interrupt
1607
// Enable
1608
#define EPHY_MISR2_POLINTEN 0x00000002
// Polarity Changed Interrupt
1609
// Enable
1610
#define EPHY_MISR2_JABBEREN 0x00000001
// Jabber Detect Event Interrupt
1611
// Enable
1612
1613
//*****************************************************************************
1614
//
1615
// The following are defines for the bit fields in the EPHY_FCSCR register.
1616
//
1617
//*****************************************************************************
1618
#define EPHY_FCSCR_FCSCNT_M 0x000000FF
// False Carrier Event Counter
1619
#define EPHY_FCSCR_FCSCNT_S 0
1620
1621
//*****************************************************************************
1622
//
1623
// The following are defines for the bit fields in the EPHY_RXERCNT register.
1624
//
1625
//*****************************************************************************
1626
#define EPHY_RXERCNT_RXERRCNT_M 0x0000FFFF
// Receive Error Count
1627
#define EPHY_RXERCNT_RXERRCNT_S 0
1628
1629
//*****************************************************************************
1630
//
1631
// The following are defines for the bit fields in the EPHY_BISTCR register.
1632
//
1633
//*****************************************************************************
1634
#define EPHY_BISTCR_PRBSM 0x00004000
// PRBS Single/Continuous Mode
1635
#define EPHY_BISTCR_PRBSPKT 0x00002000
// Generated PRBS Packets
1636
#define EPHY_BISTCR_PKTEN 0x00001000
// Packet Generation Enable
1637
#define EPHY_BISTCR_PRBSCHKLK 0x00000800
// PRBS Checker Lock Indication
1638
#define EPHY_BISTCR_PRBSCHKSYNC 0x00000400
// PRBS Checker Lock Sync Loss
1639
// Indication
1640
#define EPHY_BISTCR_PKTGENSTAT 0x00000200
// Packet Generator Status
1641
// Indication
1642
#define EPHY_BISTCR_PWRMODE 0x00000100
// Power Mode Indication
1643
#define EPHY_BISTCR_TXMIILB 0x00000040
// Transmit Data in MII Loopback
1644
// Mode
1645
#define EPHY_BISTCR_LBMODE_M 0x0000001F
// Loopback Mode Select
1646
#define EPHY_BISTCR_LBMODE_NPCSIN \
1647
0x00000001
// Near-end loopback: PCS Input
1648
// Loopback
1649
#define EPHY_BISTCR_LBMODE_NPCSOUT \
1650
0x00000002
// Near-end loopback: PCS Output
1651
// Loopback (In 100Base-TX only)
1652
#define EPHY_BISTCR_LBMODE_NDIG 0x00000004
// Near-end loopback: Digital
1653
// Loopback
1654
#define EPHY_BISTCR_LBMODE_NANA 0x00000008
// Near-end loopback: Analog
1655
// Loopback (requires 100 Ohm
1656
// termination)
1657
#define EPHY_BISTCR_LBMODE_FREV 0x00000010
// Far-end Loopback: Reverse
1658
// Loopback
1659
1660
//*****************************************************************************
1661
//
1662
// The following are defines for the bit fields in the EPHY_LEDCR register.
1663
//
1664
//*****************************************************************************
1665
#define EPHY_LEDCR_BLINKRATE_M 0x00000600
// LED Blinking Rate (ON/OFF
1666
// duration):
1667
#define EPHY_LEDCR_BLINKRATE_20HZ \
1668
0x00000000
// 20 Hz (50 ms)
1669
#define EPHY_LEDCR_BLINKRATE_10HZ \
1670
0x00000200
// 10 Hz (100 ms)
1671
#define EPHY_LEDCR_BLINKRATE_5HZ \
1672
0x00000400
// 5 Hz (200 ms)
1673
#define EPHY_LEDCR_BLINKRATE_2HZ \
1674
0x00000600
// 2 Hz (500 ms)
1675
1676
//*****************************************************************************
1677
//
1678
// The following are defines for the bit fields in the EPHY_CTL register.
1679
//
1680
//*****************************************************************************
1681
#define EPHY_CTL_AUTOMDI 0x00008000
// Auto-MDIX Enable
1682
#define EPHY_CTL_FORCEMDI 0x00004000
// Force MDIX
1683
#define EPHY_CTL_PAUSERX 0x00002000
// Pause Receive Negotiated Status
1684
#define EPHY_CTL_PAUSETX 0x00001000
// Pause Transmit Negotiated Status
1685
#define EPHY_CTL_MIILNKSTAT 0x00000800
// MII Link Status
1686
#define EPHY_CTL_BYPLEDSTRCH 0x00000080
// Bypass LED Stretching
1687
1688
//*****************************************************************************
1689
//
1690
// The following are defines for the bit fields in the EPHY_10BTSC register.
1691
//
1692
//*****************************************************************************
1693
#define EPHY_10BTSC_RXTHEN 0x00002000
// Lower Receiver Threshold Enable
1694
#define EPHY_10BTSC_SQUELCH_M 0x00001E00
// Squelch Configuration
1695
#define EPHY_10BTSC_NLPDIS 0x00000080
// Normal Link Pulse (NLP)
1696
// Transmission Control
1697
#define EPHY_10BTSC_POLSTAT 0x00000010
// 10 Mb Polarity Status
1698
#define EPHY_10BTSC_JABBERD 0x00000001
// Jabber Disable
1699
#define EPHY_10BTSC_SQUELCH_S 9
1700
1701
//*****************************************************************************
1702
//
1703
// The following are defines for the bit fields in the EPHY_BICSR1 register.
1704
//
1705
//*****************************************************************************
1706
#define EPHY_BICSR1_ERRCNT_M 0x0000FF00
// BIST Error Count
1707
#define EPHY_BICSR1_IPGLENGTH_M 0x000000FF
// BIST IPG Length
1708
#define EPHY_BICSR1_ERRCNT_S 8
1709
#define EPHY_BICSR1_IPGLENGTH_S 0
1710
1711
//*****************************************************************************
1712
//
1713
// The following are defines for the bit fields in the EPHY_BICSR2 register.
1714
//
1715
//*****************************************************************************
1716
#define EPHY_BICSR2_PKTLENGTH_M 0x000007FF
// BIST Packet Length
1717
#define EPHY_BICSR2_PKTLENGTH_S 0
1718
1719
//*****************************************************************************
1720
//
1721
// The following are defines for the bit fields in the EPHY_CDCR register.
1722
//
1723
//*****************************************************************************
1724
#define EPHY_CDCR_START 0x00008000
// Cable Diagnostic Process Start
1725
#define EPHY_CDCR_LINKQUAL_M 0x00000300
// Link Quality Indication
1726
#define EPHY_CDCR_LINKQUAL_GOOD 0x00000100
// Good Quality Link Indication
1727
#define EPHY_CDCR_LINKQUAL_MILD 0x00000200
// Mid- Quality Link Indication
1728
#define EPHY_CDCR_LINKQUAL_POOR 0x00000300
// Poor Quality Link Indication
1729
#define EPHY_CDCR_DONE 0x00000002
// Cable Diagnostic Process Done
1730
#define EPHY_CDCR_FAIL 0x00000001
// Cable Diagnostic Process Fail
1731
1732
//*****************************************************************************
1733
//
1734
// The following are defines for the bit fields in the EPHY_RCR register.
1735
//
1736
//*****************************************************************************
1737
#define EPHY_RCR_SWRST 0x00008000
// Software Reset
1738
#define EPHY_RCR_SWRESTART 0x00004000
// Software Restart
1739
1740
//*****************************************************************************
1741
//
1742
// The following are defines for the bit fields in the EPHY_LEDCFG register.
1743
//
1744
//*****************************************************************************
1745
#define EPHY_LEDCFG_LED2_M 0x00000F00
// LED2 Configuration
1746
#define EPHY_LEDCFG_LED2_LINK 0x00000000
// Link OK
1747
#define EPHY_LEDCFG_LED2_RXTX 0x00000100
// RX/TX Activity
1748
#define EPHY_LEDCFG_LED2_TX 0x00000200
// TX Activity
1749
#define EPHY_LEDCFG_LED2_RX 0x00000300
// RX Activity
1750
#define EPHY_LEDCFG_LED2_COL 0x00000400
// Collision
1751
#define EPHY_LEDCFG_LED2_100BT 0x00000500
// 100-Base TX
1752
#define EPHY_LEDCFG_LED2_10BT 0x00000600
// 10-Base TX
1753
#define EPHY_LEDCFG_LED2_FD 0x00000700
// Full Duplex
1754
#define EPHY_LEDCFG_LED2_LINKTXRX \
1755
0x00000800
// Link OK/Blink on TX/RX Activity
1756
#define EPHY_LEDCFG_LED1_M 0x000000F0
// LED1 Configuration
1757
#define EPHY_LEDCFG_LED1_LINK 0x00000000
// Link OK
1758
#define EPHY_LEDCFG_LED1_RXTX 0x00000010
// RX/TX Activity
1759
#define EPHY_LEDCFG_LED1_TX 0x00000020
// TX Activity
1760
#define EPHY_LEDCFG_LED1_RX 0x00000030
// RX Activity
1761
#define EPHY_LEDCFG_LED1_COL 0x00000040
// Collision
1762
#define EPHY_LEDCFG_LED1_100BT 0x00000050
// 100-Base TX
1763
#define EPHY_LEDCFG_LED1_10BT 0x00000060
// 10-Base TX
1764
#define EPHY_LEDCFG_LED1_FD 0x00000070
// Full Duplex
1765
#define EPHY_LEDCFG_LED1_LINKTXRX \
1766
0x00000080
// Link OK/Blink on TX/RX Activity
1767
#define EPHY_LEDCFG_LED0_M 0x0000000F
// LED0 Configuration
1768
#define EPHY_LEDCFG_LED0_LINK 0x00000000
// Link OK
1769
#define EPHY_LEDCFG_LED0_RXTX 0x00000001
// RX/TX Activity
1770
#define EPHY_LEDCFG_LED0_TX 0x00000002
// TX Activity
1771
#define EPHY_LEDCFG_LED0_RX 0x00000003
// RX Activity
1772
#define EPHY_LEDCFG_LED0_COL 0x00000004
// Collision
1773
#define EPHY_LEDCFG_LED0_100BT 0x00000005
// 100-Base TX
1774
#define EPHY_LEDCFG_LED0_10BT 0x00000006
// 10-Base TX
1775
#define EPHY_LEDCFG_LED0_FD 0x00000007
// Full Duplex
1776
#define EPHY_LEDCFG_LED0_LINKTXRX \
1777
0x00000008
// Link OK/Blink on TX/RX Activity
1778
1779
//*****************************************************************************
1780
//
1781
// The following definitions are deprecated.
1782
//
1783
//*****************************************************************************
1784
#ifndef DEPRECATED
1785
1786
//*****************************************************************************
1787
//
1788
// The following are deprecated defines for the bit fields in the
1789
// EMAC_O_PPSCTRL register.
1790
//
1791
//*****************************************************************************
1792
#define EMAC_PPSCTRL_PPSCTRL_1HZ \
1793
0x00000000
// When the PPSEN0 bit = 0x0, the
1794
// EN0PPS signal is 1 pulse of the
1795
// PTP reference clock.(of width
1796
// clk_ptp_i) every second
1797
#define EMAC_PPSCTRL_PPSCTRL_2HZ \
1798
0x00000001
// When the PPSEN0 bit = 0x0, the
1799
// binary rollover is 2 Hz, and the
1800
// digital rollover is 1 Hz
1801
#define EMAC_PPSCTRL_PPSCTRL_4HZ \
1802
0x00000002
// When the PPSEN0 bit = 0x0, the
1803
// binary rollover is 4 Hz, and the
1804
// digital rollover is 2 Hz
1805
#define EMAC_PPSCTRL_PPSCTRL_8HZ \
1806
0x00000003
// When thePPSEN0 bit = 0x0, the
1807
// binary rollover is 8 Hz, and the
1808
// digital rollover is 4 Hz,
1809
#define EMAC_PPSCTRL_PPSCTRL_16HZ \
1810
0x00000004
// When thePPSEN0 bit = 0x0, the
1811
// binary rollover is 16 Hz, and
1812
// the digital rollover is 8 Hz
1813
#define EMAC_PPSCTRL_PPSCTRL_32HZ \
1814
0x00000005
// When thePPSEN0 bit = 0x0, the
1815
// binary rollover is 32 Hz, and
1816
// the digital rollover is 16 Hz
1817
#define EMAC_PPSCTRL_PPSCTRL_64HZ \
1818
0x00000006
// When thePPSEN0 bit = 0x0, the
1819
// binary rollover is 64 Hz, and
1820
// the digital rollover is 32 Hz
1821
#define EMAC_PPSCTRL_PPSCTRL_128HZ \
1822
0x00000007
// When thePPSEN0 bit = 0x0, the
1823
// binary rollover is 128 Hz, and
1824
// the digital rollover is 64 Hz
1825
#define EMAC_PPSCTRL_PPSCTRL_256HZ \
1826
0x00000008
// When thePPSEN0 bit = 0x0, the
1827
// binary rollover is 256 Hz, and
1828
// the digital rollover is 128 Hz
1829
#define EMAC_PPSCTRL_PPSCTRL_512HZ \
1830
0x00000009
// When thePPSEN0 bit = 0x0, the
1831
// binary rollover is 512 Hz, and
1832
// the digital rollover is 256 Hz
1833
#define EMAC_PPSCTRL_PPSCTRL_1024HZ \
1834
0x0000000A
// When the PPSEN0 bit = 0x0, the
1835
// binary rollover is 1.024 kHz,
1836
// and the digital rollover is 512
1837
// Hz
1838
#define EMAC_PPSCTRL_PPSCTRL_2048HZ \
1839
0x0000000B
// When thePPSEN0 bit = 0x0, the
1840
// binary rollover is 2.048 kHz,
1841
// and the digital rollover is
1842
// 1.024 kHz
1843
#define EMAC_PPSCTRL_PPSCTRL_4096HZ \
1844
0x0000000C
// When thePPSEN0 bit = 0x0, the
1845
// binary rollover is 4.096 kHz,
1846
// and the digital rollover is
1847
// 2.048 kHz
1848
#define EMAC_PPSCTRL_PPSCTRL_8192HZ \
1849
0x0000000D
// When thePPSEN0 bit = 0x0, the
1850
// binary rollover is 8.192 kHz,
1851
// and the digital rollover is
1852
// 4.096 kHz
1853
#define EMAC_PPSCTRL_PPSCTRL_16384HZ \
1854
0x0000000E
// When thePPSEN0 bit = 0x0, the
1855
// binary rollover is 16.384 kHz,
1856
// and the digital rollover is
1857
// 8.092 kHz
1858
#define EMAC_PPSCTRL_PPSCTRL_32768HZ \
1859
0x0000000F
// When thePPSEN0 bit = 0x0, the
1860
// binary rollover is 32.768 KHz,
1861
// and the digital rollover is
1862
// 16.384 KHz
1863
1864
//*****************************************************************************
1865
//
1866
// The following are deprecated defines for the bit fields in the EMAC_O_CC
1867
// register.
1868
//
1869
//*****************************************************************************
1870
#define EMAC_CC_CS_PA7 0x00000001
// GPIO
1871
1872
#endif
1873
1874
#endif
// __HW_EMAC_H__