mikroSDK Reference Manual
hw_sysctl.h
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//*****************************************************************************
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//
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// hw_sysctl.h - Macros used when accessing the system control hardware.
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//
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// Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_SYSCTL_H__
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#define __HW_SYSCTL_H__
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//*****************************************************************************
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//
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// The following are defines for the System Control register addresses.
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//
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//*****************************************************************************
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#define SYSCTL_DID0 0x400FE000
// Device Identification 0
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#define SYSCTL_DID1 0x400FE004
// Device Identification 1
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#define SYSCTL_DC0 0x400FE008
// Device Capabilities 0
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#define SYSCTL_DC1 0x400FE010
// Device Capabilities 1
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#define SYSCTL_DC2 0x400FE014
// Device Capabilities 2
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#define SYSCTL_DC3 0x400FE018
// Device Capabilities 3
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#define SYSCTL_DC4 0x400FE01C
// Device Capabilities 4
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#define SYSCTL_DC5 0x400FE020
// Device Capabilities 5
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#define SYSCTL_DC6 0x400FE024
// Device Capabilities 6
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#define SYSCTL_DC7 0x400FE028
// Device Capabilities 7
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#define SYSCTL_DC8 0x400FE02C
// Device Capabilities 8
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#define SYSCTL_PBORCTL 0x400FE030
// Brown-Out Reset Control
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#define SYSCTL_PTBOCTL 0x400FE038
// Power-Temp Brown Out Control
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#define SYSCTL_SRCR0 0x400FE040
// Software Reset Control 0
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#define SYSCTL_SRCR1 0x400FE044
// Software Reset Control 1
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#define SYSCTL_SRCR2 0x400FE048
// Software Reset Control 2
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#define SYSCTL_RIS 0x400FE050
// Raw Interrupt Status
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#define SYSCTL_IMC 0x400FE054
// Interrupt Mask Control
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#define SYSCTL_MISC 0x400FE058
// Masked Interrupt Status and
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// Clear
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#define SYSCTL_RESC 0x400FE05C
// Reset Cause
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#define SYSCTL_PWRTC 0x400FE060
// Power-Temperature Cause
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#define SYSCTL_RCC 0x400FE060
// Run-Mode Clock Configuration
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#define SYSCTL_NMIC 0x400FE064
// NMI Cause Register
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#define SYSCTL_GPIOHBCTL 0x400FE06C
// GPIO High-Performance Bus
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// Control
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#define SYSCTL_RCC2 0x400FE070
// Run-Mode Clock Configuration 2
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#define SYSCTL_MOSCCTL 0x400FE07C
// Main Oscillator Control
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#define SYSCTL_RSCLKCFG 0x400FE0B0
// Run and Sleep Mode Configuration
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// Register
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#define SYSCTL_MEMTIM0 0x400FE0C0
// Memory Timing Parameter Register
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// 0 for Main Flash and EEPROM
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#define SYSCTL_RCGC0 0x400FE100
// Run Mode Clock Gating Control
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// Register 0
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#define SYSCTL_RCGC1 0x400FE104
// Run Mode Clock Gating Control
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// Register 1
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#define SYSCTL_RCGC2 0x400FE108
// Run Mode Clock Gating Control
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// Register 2
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#define SYSCTL_SCGC0 0x400FE110
// Sleep Mode Clock Gating Control
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// Register 0
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#define SYSCTL_SCGC1 0x400FE114
// Sleep Mode Clock Gating Control
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// Register 1
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#define SYSCTL_SCGC2 0x400FE118
// Sleep Mode Clock Gating Control
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// Register 2
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#define SYSCTL_DCGC0 0x400FE120
// Deep Sleep Mode Clock Gating
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// Control Register 0
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#define SYSCTL_DCGC1 0x400FE124
// Deep-Sleep Mode Clock Gating
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// Control Register 1
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#define SYSCTL_DCGC2 0x400FE128
// Deep Sleep Mode Clock Gating
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// Control Register 2
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#define SYSCTL_ALTCLKCFG 0x400FE138
// Alternate Clock Configuration
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#define SYSCTL_DSLPCLKCFG 0x400FE144
// Deep Sleep Clock Configuration
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#define SYSCTL_DSCLKCFG 0x400FE144
// Deep Sleep Clock Configuration
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// Register
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#define SYSCTL_DIVSCLK 0x400FE148
// Divisor and Source Clock
103
// Configuration
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#define SYSCTL_SYSPROP 0x400FE14C
// System Properties
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#define SYSCTL_PIOSCCAL 0x400FE150
// Precision Internal Oscillator
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// Calibration
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#define SYSCTL_PIOSCSTAT 0x400FE154
// Precision Internal Oscillator
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// Statistics
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#define SYSCTL_PLLFREQ0 0x400FE160
// PLL Frequency 0
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#define SYSCTL_PLLFREQ1 0x400FE164
// PLL Frequency 1
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#define SYSCTL_PLLSTAT 0x400FE168
// PLL Status
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#define SYSCTL_SLPPWRCFG 0x400FE188
// Sleep Power Configuration
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#define SYSCTL_DSLPPWRCFG 0x400FE18C
// Deep-Sleep Power Configuration
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#define SYSCTL_DC9 0x400FE190
// Device Capabilities 9
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#define SYSCTL_NVMSTAT 0x400FE1A0
// Non-Volatile Memory Information
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#define SYSCTL_LDOSPCTL 0x400FE1B4
// LDO Sleep Power Control
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#define SYSCTL_LDODPCTL 0x400FE1BC
// LDO Deep-Sleep Power Control
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#define SYSCTL_RESBEHAVCTL 0x400FE1D8
// Reset Behavior Control Register
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#define SYSCTL_HSSR 0x400FE1F4
// Hardware System Service Request
120
#define SYSCTL_USBPDS 0x400FE280
// USB Power Domain Status
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#define SYSCTL_USBMPC 0x400FE284
// USB Memory Power Control
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#define SYSCTL_EMACPDS 0x400FE288
// Ethernet MAC Power Domain Status
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#define SYSCTL_EMACMPC 0x400FE28C
// Ethernet MAC Memory Power
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// Control
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#define SYSCTL_LCDMPC 0x400FE294
// LCD Memory Power Control
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#define SYSCTL_PPWD 0x400FE300
// Watchdog Timer Peripheral
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// Present
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#define SYSCTL_PPTIMER 0x400FE304
// 16/32-Bit General-Purpose Timer
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// Peripheral Present
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#define SYSCTL_PPGPIO 0x400FE308
// General-Purpose Input/Output
131
// Peripheral Present
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#define SYSCTL_PPDMA 0x400FE30C
// Micro Direct Memory Access
133
// Peripheral Present
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#define SYSCTL_PPEPI 0x400FE310
// EPI Peripheral Present
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#define SYSCTL_PPHIB 0x400FE314
// Hibernation Peripheral Present
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#define SYSCTL_PPUART 0x400FE318
// Universal Asynchronous
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// Receiver/Transmitter Peripheral
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// Present
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#define SYSCTL_PPSSI 0x400FE31C
// Synchronous Serial Interface
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// Peripheral Present
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#define SYSCTL_PPI2C 0x400FE320
// Inter-Integrated Circuit
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// Peripheral Present
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#define SYSCTL_PPUSB 0x400FE328
// Universal Serial Bus Peripheral
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// Present
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#define SYSCTL_PPEPHY 0x400FE330
// Ethernet PHY Peripheral Present
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#define SYSCTL_PPCAN 0x400FE334
// Controller Area Network
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// Peripheral Present
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#define SYSCTL_PPADC 0x400FE338
// Analog-to-Digital Converter
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// Peripheral Present
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#define SYSCTL_PPACMP 0x400FE33C
// Analog Comparator Peripheral
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// Present
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#define SYSCTL_PPPWM 0x400FE340
// Pulse Width Modulator Peripheral
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// Present
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#define SYSCTL_PPQEI 0x400FE344
// Quadrature Encoder Interface
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// Peripheral Present
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#define SYSCTL_PPLPC 0x400FE348
// Low Pin Count Interface
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// Peripheral Present
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#define SYSCTL_PPPECI 0x400FE350
// Platform Environment Control
159
// Interface Peripheral Present
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#define SYSCTL_PPFAN 0x400FE354
// Fan Control Peripheral Present
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#define SYSCTL_PPEEPROM 0x400FE358
// EEPROM Peripheral Present
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#define SYSCTL_PPWTIMER 0x400FE35C
// 32/64-Bit Wide General-Purpose
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// Timer Peripheral Present
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#define SYSCTL_PPRTS 0x400FE370
// Remote Temperature Sensor
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// Peripheral Present
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#define SYSCTL_PPCCM 0x400FE374
// CRC and Cryptographic Modules
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// Peripheral Present
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#define SYSCTL_PPLCD 0x400FE390
// LCD Peripheral Present
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#define SYSCTL_PPOWIRE 0x400FE398
// 1-Wire Peripheral Present
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#define SYSCTL_PPEMAC 0x400FE39C
// Ethernet MAC Peripheral Present
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#define SYSCTL_PPHIM 0x400FE3A4
// Human Interface Master
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// Peripheral Present
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#define SYSCTL_SRWD 0x400FE500
// Watchdog Timer Software Reset
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#define SYSCTL_SRTIMER 0x400FE504
// 16/32-Bit General-Purpose Timer
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// Software Reset
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#define SYSCTL_SRGPIO 0x400FE508
// General-Purpose Input/Output
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// Software Reset
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#define SYSCTL_SRDMA 0x400FE50C
// Micro Direct Memory Access
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// Software Reset
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#define SYSCTL_SREPI 0x400FE510
// EPI Software Reset
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#define SYSCTL_SRHIB 0x400FE514
// Hibernation Software Reset
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#define SYSCTL_SRUART 0x400FE518
// Universal Asynchronous
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// Receiver/Transmitter Software
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// Reset
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#define SYSCTL_SRSSI 0x400FE51C
// Synchronous Serial Interface
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// Software Reset
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#define SYSCTL_SRI2C 0x400FE520
// Inter-Integrated Circuit
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// Software Reset
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#define SYSCTL_SRUSB 0x400FE528
// Universal Serial Bus Software
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// Reset
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#define SYSCTL_SREPHY 0x400FE530
// Ethernet PHY Software Reset
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#define SYSCTL_SRCAN 0x400FE534
// Controller Area Network Software
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// Reset
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#define SYSCTL_SRADC 0x400FE538
// Analog-to-Digital Converter
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// Software Reset
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#define SYSCTL_SRACMP 0x400FE53C
// Analog Comparator Software Reset
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#define SYSCTL_SRPWM 0x400FE540
// Pulse Width Modulator Software
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// Reset
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#define SYSCTL_SRQEI 0x400FE544
// Quadrature Encoder Interface
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// Software Reset
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#define SYSCTL_SREEPROM 0x400FE558
// EEPROM Software Reset
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#define SYSCTL_SRWTIMER 0x400FE55C
// 32/64-Bit Wide General-Purpose
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// Timer Software Reset
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#define SYSCTL_SRCCM 0x400FE574
// CRC and Cryptographic Modules
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// Software Reset
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#define SYSCTL_SRLCD 0x400FE590
// LCD Controller Software Reset
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#define SYSCTL_SROWIRE 0x400FE598
// 1-Wire Software Reset
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#define SYSCTL_SREMAC 0x400FE59C
// Ethernet MAC Software Reset
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#define SYSCTL_RCGCWD 0x400FE600
// Watchdog Timer Run Mode Clock
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// Gating Control
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#define SYSCTL_RCGCTIMER 0x400FE604
// 16/32-Bit General-Purpose Timer
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// Run Mode Clock Gating Control
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#define SYSCTL_RCGCGPIO 0x400FE608
// General-Purpose Input/Output Run
214
// Mode Clock Gating Control
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#define SYSCTL_RCGCDMA 0x400FE60C
// Micro Direct Memory Access Run
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// Mode Clock Gating Control
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#define SYSCTL_RCGCEPI 0x400FE610
// EPI Run Mode Clock Gating
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// Control
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#define SYSCTL_RCGCHIB 0x400FE614
// Hibernation Run Mode Clock
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// Gating Control
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#define SYSCTL_RCGCUART 0x400FE618
// Universal Asynchronous
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// Receiver/Transmitter Run Mode
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// Clock Gating Control
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#define SYSCTL_RCGCSSI 0x400FE61C
// Synchronous Serial Interface Run
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// Mode Clock Gating Control
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#define SYSCTL_RCGCI2C 0x400FE620
// Inter-Integrated Circuit Run
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// Mode Clock Gating Control
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#define SYSCTL_RCGCUSB 0x400FE628
// Universal Serial Bus Run Mode
229
// Clock Gating Control
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#define SYSCTL_RCGCEPHY 0x400FE630
// Ethernet PHY Run Mode Clock
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// Gating Control
232
#define SYSCTL_RCGCCAN 0x400FE634
// Controller Area Network Run Mode
233
// Clock Gating Control
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#define SYSCTL_RCGCADC 0x400FE638
// Analog-to-Digital Converter Run
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// Mode Clock Gating Control
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#define SYSCTL_RCGCACMP 0x400FE63C
// Analog Comparator Run Mode Clock
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// Gating Control
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#define SYSCTL_RCGCPWM 0x400FE640
// Pulse Width Modulator Run Mode
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// Clock Gating Control
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#define SYSCTL_RCGCQEI 0x400FE644
// Quadrature Encoder Interface Run
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// Mode Clock Gating Control
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#define SYSCTL_RCGCEEPROM 0x400FE658
// EEPROM Run Mode Clock Gating
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// Control
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#define SYSCTL_RCGCWTIMER 0x400FE65C
// 32/64-Bit Wide General-Purpose
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// Timer Run Mode Clock Gating
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// Control
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#define SYSCTL_RCGCCCM 0x400FE674
// CRC and Cryptographic Modules
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// Run Mode Clock Gating Control
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#define SYSCTL_RCGCLCD 0x400FE690
// LCD Controller Run Mode Clock
250
// Gating Control
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#define SYSCTL_RCGCOWIRE 0x400FE698
// 1-Wire Run Mode Clock Gating
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// Control
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#define SYSCTL_RCGCEMAC 0x400FE69C
// Ethernet MAC Run Mode Clock
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// Gating Control
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#define SYSCTL_SCGCWD 0x400FE700
// Watchdog Timer Sleep Mode Clock
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// Gating Control
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#define SYSCTL_SCGCTIMER 0x400FE704
// 16/32-Bit General-Purpose Timer
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// Sleep Mode Clock Gating Control
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#define SYSCTL_SCGCGPIO 0x400FE708
// General-Purpose Input/Output
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// Sleep Mode Clock Gating Control
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#define SYSCTL_SCGCDMA 0x400FE70C
// Micro Direct Memory Access Sleep
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// Mode Clock Gating Control
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#define SYSCTL_SCGCEPI 0x400FE710
// EPI Sleep Mode Clock Gating
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// Control
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#define SYSCTL_SCGCHIB 0x400FE714
// Hibernation Sleep Mode Clock
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// Gating Control
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#define SYSCTL_SCGCUART 0x400FE718
// Universal Asynchronous
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// Receiver/Transmitter Sleep Mode
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// Clock Gating Control
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#define SYSCTL_SCGCSSI 0x400FE71C
// Synchronous Serial Interface
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// Sleep Mode Clock Gating Control
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#define SYSCTL_SCGCI2C 0x400FE720
// Inter-Integrated Circuit Sleep
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// Mode Clock Gating Control
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#define SYSCTL_SCGCUSB 0x400FE728
// Universal Serial Bus Sleep Mode
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// Clock Gating Control
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#define SYSCTL_SCGCEPHY 0x400FE730
// Ethernet PHY Sleep Mode Clock
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// Gating Control
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#define SYSCTL_SCGCCAN 0x400FE734
// Controller Area Network Sleep
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// Mode Clock Gating Control
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#define SYSCTL_SCGCADC 0x400FE738
// Analog-to-Digital Converter
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// Sleep Mode Clock Gating Control
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#define SYSCTL_SCGCACMP 0x400FE73C
// Analog Comparator Sleep Mode
283
// Clock Gating Control
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#define SYSCTL_SCGCPWM 0x400FE740
// Pulse Width Modulator Sleep Mode
285
// Clock Gating Control
286
#define SYSCTL_SCGCQEI 0x400FE744
// Quadrature Encoder Interface
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// Sleep Mode Clock Gating Control
288
#define SYSCTL_SCGCEEPROM 0x400FE758
// EEPROM Sleep Mode Clock Gating
289
// Control
290
#define SYSCTL_SCGCWTIMER 0x400FE75C
// 32/64-Bit Wide General-Purpose
291
// Timer Sleep Mode Clock Gating
292
// Control
293
#define SYSCTL_SCGCCCM 0x400FE774
// CRC and Cryptographic Modules
294
// Sleep Mode Clock Gating Control
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#define SYSCTL_SCGCLCD 0x400FE790
// LCD Controller Sleep Mode Clock
296
// Gating Control
297
#define SYSCTL_SCGCOWIRE 0x400FE798
// 1-Wire Sleep Mode Clock Gating
298
// Control
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#define SYSCTL_SCGCEMAC 0x400FE79C
// Ethernet MAC Sleep Mode Clock
300
// Gating Control
301
#define SYSCTL_DCGCWD 0x400FE800
// Watchdog Timer Deep-Sleep Mode
302
// Clock Gating Control
303
#define SYSCTL_DCGCTIMER 0x400FE804
// 16/32-Bit General-Purpose Timer
304
// Deep-Sleep Mode Clock Gating
305
// Control
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#define SYSCTL_DCGCGPIO 0x400FE808
// General-Purpose Input/Output
307
// Deep-Sleep Mode Clock Gating
308
// Control
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#define SYSCTL_DCGCDMA 0x400FE80C
// Micro Direct Memory Access
310
// Deep-Sleep Mode Clock Gating
311
// Control
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#define SYSCTL_DCGCEPI 0x400FE810
// EPI Deep-Sleep Mode Clock Gating
313
// Control
314
#define SYSCTL_DCGCHIB 0x400FE814
// Hibernation Deep-Sleep Mode
315
// Clock Gating Control
316
#define SYSCTL_DCGCUART 0x400FE818
// Universal Asynchronous
317
// Receiver/Transmitter Deep-Sleep
318
// Mode Clock Gating Control
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#define SYSCTL_DCGCSSI 0x400FE81C
// Synchronous Serial Interface
320
// Deep-Sleep Mode Clock Gating
321
// Control
322
#define SYSCTL_DCGCI2C 0x400FE820
// Inter-Integrated Circuit
323
// Deep-Sleep Mode Clock Gating
324
// Control
325
#define SYSCTL_DCGCUSB 0x400FE828
// Universal Serial Bus Deep-Sleep
326
// Mode Clock Gating Control
327
#define SYSCTL_DCGCEPHY 0x400FE830
// Ethernet PHY Deep-Sleep Mode
328
// Clock Gating Control
329
#define SYSCTL_DCGCCAN 0x400FE834
// Controller Area Network
330
// Deep-Sleep Mode Clock Gating
331
// Control
332
#define SYSCTL_DCGCADC 0x400FE838
// Analog-to-Digital Converter
333
// Deep-Sleep Mode Clock Gating
334
// Control
335
#define SYSCTL_DCGCACMP 0x400FE83C
// Analog Comparator Deep-Sleep
336
// Mode Clock Gating Control
337
#define SYSCTL_DCGCPWM 0x400FE840
// Pulse Width Modulator Deep-Sleep
338
// Mode Clock Gating Control
339
#define SYSCTL_DCGCQEI 0x400FE844
// Quadrature Encoder Interface
340
// Deep-Sleep Mode Clock Gating
341
// Control
342
#define SYSCTL_DCGCEEPROM 0x400FE858
// EEPROM Deep-Sleep Mode Clock
343
// Gating Control
344
#define SYSCTL_DCGCWTIMER 0x400FE85C
// 32/64-Bit Wide General-Purpose
345
// Timer Deep-Sleep Mode Clock
346
// Gating Control
347
#define SYSCTL_DCGCCCM 0x400FE874
// CRC and Cryptographic Modules
348
// Deep-Sleep Mode Clock Gating
349
// Control
350
#define SYSCTL_DCGCLCD 0x400FE890
// LCD Controller Deep-Sleep Mode
351
// Clock Gating Control
352
#define SYSCTL_DCGCOWIRE 0x400FE898
// 1-Wire Deep-Sleep Mode Clock
353
// Gating Control
354
#define SYSCTL_DCGCEMAC 0x400FE89C
// Ethernet MAC Deep-Sleep Mode
355
// Clock Gating Control
356
#define SYSCTL_PCWD 0x400FE900
// Watchdog Timer Power Control
357
#define SYSCTL_PCTIMER 0x400FE904
// 16/32-Bit General-Purpose Timer
358
// Power Control
359
#define SYSCTL_PCGPIO 0x400FE908
// General-Purpose Input/Output
360
// Power Control
361
#define SYSCTL_PCDMA 0x400FE90C
// Micro Direct Memory Access Power
362
// Control
363
#define SYSCTL_PCEPI 0x400FE910
// External Peripheral Interface
364
// Power Control
365
#define SYSCTL_PCHIB 0x400FE914
// Hibernation Power Control
366
#define SYSCTL_PCUART 0x400FE918
// Universal Asynchronous
367
// Receiver/Transmitter Power
368
// Control
369
#define SYSCTL_PCSSI 0x400FE91C
// Synchronous Serial Interface
370
// Power Control
371
#define SYSCTL_PCI2C 0x400FE920
// Inter-Integrated Circuit Power
372
// Control
373
#define SYSCTL_PCUSB 0x400FE928
// Universal Serial Bus Power
374
// Control
375
#define SYSCTL_PCEPHY 0x400FE930
// Ethernet PHY Power Control
376
#define SYSCTL_PCCAN 0x400FE934
// Controller Area Network Power
377
// Control
378
#define SYSCTL_PCADC 0x400FE938
// Analog-to-Digital Converter
379
// Power Control
380
#define SYSCTL_PCACMP 0x400FE93C
// Analog Comparator Power Control
381
#define SYSCTL_PCPWM 0x400FE940
// Pulse Width Modulator Power
382
// Control
383
#define SYSCTL_PCQEI 0x400FE944
// Quadrature Encoder Interface
384
// Power Control
385
#define SYSCTL_PCEEPROM 0x400FE958
// EEPROM Power Control
386
#define SYSCTL_PCCCM 0x400FE974
// CRC and Cryptographic Modules
387
// Power Control
388
#define SYSCTL_PCLCD 0x400FE990
// LCD Controller Power Control
389
#define SYSCTL_PCOWIRE 0x400FE998
// 1-Wire Power Control
390
#define SYSCTL_PCEMAC 0x400FE99C
// Ethernet MAC Power Control
391
#define SYSCTL_PRWD 0x400FEA00
// Watchdog Timer Peripheral Ready
392
#define SYSCTL_PRTIMER 0x400FEA04
// 16/32-Bit General-Purpose Timer
393
// Peripheral Ready
394
#define SYSCTL_PRGPIO 0x400FEA08
// General-Purpose Input/Output
395
// Peripheral Ready
396
#define SYSCTL_PRDMA 0x400FEA0C
// Micro Direct Memory Access
397
// Peripheral Ready
398
#define SYSCTL_PREPI 0x400FEA10
// EPI Peripheral Ready
399
#define SYSCTL_PRHIB 0x400FEA14
// Hibernation Peripheral Ready
400
#define SYSCTL_PRUART 0x400FEA18
// Universal Asynchronous
401
// Receiver/Transmitter Peripheral
402
// Ready
403
#define SYSCTL_PRSSI 0x400FEA1C
// Synchronous Serial Interface
404
// Peripheral Ready
405
#define SYSCTL_PRI2C 0x400FEA20
// Inter-Integrated Circuit
406
// Peripheral Ready
407
#define SYSCTL_PRUSB 0x400FEA28
// Universal Serial Bus Peripheral
408
// Ready
409
#define SYSCTL_PREPHY 0x400FEA30
// Ethernet PHY Peripheral Ready
410
#define SYSCTL_PRCAN 0x400FEA34
// Controller Area Network
411
// Peripheral Ready
412
#define SYSCTL_PRADC 0x400FEA38
// Analog-to-Digital Converter
413
// Peripheral Ready
414
#define SYSCTL_PRACMP 0x400FEA3C
// Analog Comparator Peripheral
415
// Ready
416
#define SYSCTL_PRPWM 0x400FEA40
// Pulse Width Modulator Peripheral
417
// Ready
418
#define SYSCTL_PRQEI 0x400FEA44
// Quadrature Encoder Interface
419
// Peripheral Ready
420
#define SYSCTL_PREEPROM 0x400FEA58
// EEPROM Peripheral Ready
421
#define SYSCTL_PRWTIMER 0x400FEA5C
// 32/64-Bit Wide General-Purpose
422
// Timer Peripheral Ready
423
#define SYSCTL_PRCCM 0x400FEA74
// CRC and Cryptographic Modules
424
// Peripheral Ready
425
#define SYSCTL_PRLCD 0x400FEA90
// LCD Controller Peripheral Ready
426
#define SYSCTL_PROWIRE 0x400FEA98
// 1-Wire Peripheral Ready
427
#define SYSCTL_PREMAC 0x400FEA9C
// Ethernet MAC Peripheral Ready
428
#define SYSCTL_UNIQUEID0 0x400FEF20
// Unique ID 0
429
#define SYSCTL_UNIQUEID1 0x400FEF24
// Unique ID 1
430
#define SYSCTL_UNIQUEID2 0x400FEF28
// Unique ID 2
431
#define SYSCTL_UNIQUEID3 0x400FEF2C
// Unique ID 3
432
#define SYSCTL_CCMCGREQ 0x44030204
// Cryptographic Modules Clock
433
// Gating Request
434
435
//*****************************************************************************
436
//
437
// The following are defines for the bit fields in the SYSCTL_DID0 register.
438
//
439
//*****************************************************************************
440
#define SYSCTL_DID0_VER_M 0x70000000
// DID0 Version
441
#define SYSCTL_DID0_VER_1 0x10000000
// Second version of the DID0
442
// register format.
443
#define SYSCTL_DID0_CLASS_M 0x00FF0000
// Device Class
444
#define SYSCTL_DID0_CLASS_TM4C123 \
445
0x00050000
// Tiva TM4C123x and TM4E123x
446
// microcontrollers
447
#define SYSCTL_DID0_CLASS_TM4C129 \
448
0x000A0000
// Tiva(TM) TM4C129-class
449
// microcontrollers
450
#define SYSCTL_DID0_MAJ_M 0x0000FF00
// Major Revision
451
#define SYSCTL_DID0_MAJ_REVA 0x00000000
// Revision A (initial device)
452
#define SYSCTL_DID0_MAJ_REVB 0x00000100
// Revision B (first base layer
453
// revision)
454
#define SYSCTL_DID0_MAJ_REVC 0x00000200
// Revision C (second base layer
455
// revision)
456
#define SYSCTL_DID0_MIN_M 0x000000FF
// Minor Revision
457
#define SYSCTL_DID0_MIN_0 0x00000000
// Initial device, or a major
458
// revision update
459
#define SYSCTL_DID0_MIN_1 0x00000001
// First metal layer change
460
#define SYSCTL_DID0_MIN_2 0x00000002
// Second metal layer change
461
462
//*****************************************************************************
463
//
464
// The following are defines for the bit fields in the SYSCTL_DID1 register.
465
//
466
//*****************************************************************************
467
#define SYSCTL_DID1_VER_M 0xF0000000
// DID1 Version
468
#define SYSCTL_DID1_VER_1 0x10000000
// fury_ib
469
#define SYSCTL_DID1_FAM_M 0x0F000000
// Family
470
#define SYSCTL_DID1_FAM_TIVA 0x00000000
// Tiva family of microcontollers
471
#define SYSCTL_DID1_PRTNO_M 0x00FF0000
// Part Number
472
#define SYSCTL_DID1_PRTNO_TM4C1230C3PM \
473
0x00220000
// TM4C1230C3PM
474
#define SYSCTL_DID1_PRTNO_TM4C1230D5PM \
475
0x00230000
// TM4C1230D5PM
476
#define SYSCTL_DID1_PRTNO_TM4C1230E6PM \
477
0x00200000
// TM4C1230E6PM
478
#define SYSCTL_DID1_PRTNO_TM4C1230H6PM \
479
0x00210000
// TM4C1230H6PM
480
#define SYSCTL_DID1_PRTNO_TM4C1231C3PM \
481
0x00180000
// TM4C1231C3PM
482
#define SYSCTL_DID1_PRTNO_TM4C1231D5PM \
483
0x00190000
// TM4C1231D5PM
484
#define SYSCTL_DID1_PRTNO_TM4C1231D5PZ \
485
0x00360000
// TM4C1231D5PZ
486
#define SYSCTL_DID1_PRTNO_TM4C1231E6PM \
487
0x00100000
// TM4C1231E6PM
488
#define SYSCTL_DID1_PRTNO_TM4C1231E6PZ \
489
0x00300000
// TM4C1231E6PZ
490
#define SYSCTL_DID1_PRTNO_TM4C1231H6PGE \
491
0x00350000
// TM4C1231H6PGE
492
#define SYSCTL_DID1_PRTNO_TM4C1231H6PM \
493
0x00110000
// TM4C1231H6PM
494
#define SYSCTL_DID1_PRTNO_TM4C1231H6PZ \
495
0x00310000
// TM4C1231H6PZ
496
#define SYSCTL_DID1_PRTNO_TM4C1232C3PM \
497
0x00080000
// TM4C1232C3PM
498
#define SYSCTL_DID1_PRTNO_TM4C1232D5PM \
499
0x00090000
// TM4C1232D5PM
500
#define SYSCTL_DID1_PRTNO_TM4C1232E6PM \
501
0x000A0000
// TM4C1232E6PM
502
#define SYSCTL_DID1_PRTNO_TM4C1232H6PM \
503
0x000B0000
// TM4C1232H6PM
504
#define SYSCTL_DID1_PRTNO_TM4C1233C3PM \
505
0x00010000
// TM4C1233C3PM
506
#define SYSCTL_DID1_PRTNO_TM4C1233D5PM \
507
0x00020000
// TM4C1233D5PM
508
#define SYSCTL_DID1_PRTNO_TM4C1233D5PZ \
509
0x00D00000
// TM4C1233D5PZ
510
#define SYSCTL_DID1_PRTNO_TM4C1233E6PM \
511
0x00030000
// TM4C1233E6PM
512
#define SYSCTL_DID1_PRTNO_TM4C1233E6PZ \
513
0x00D10000
// TM4C1233E6PZ
514
#define SYSCTL_DID1_PRTNO_TM4C1233H6PGE \
515
0x00D60000
// TM4C1233H6PGE
516
#define SYSCTL_DID1_PRTNO_TM4C1233H6PM \
517
0x00040000
// TM4C1233H6PM
518
#define SYSCTL_DID1_PRTNO_TM4C1233H6PZ \
519
0x00D20000
// TM4C1233H6PZ
520
#define SYSCTL_DID1_PRTNO_TM4C1236D5PM \
521
0x00520000
// TM4C1236D5PM
522
#define SYSCTL_DID1_PRTNO_TM4C1236E6PM \
523
0x00500000
// TM4C1236E6PM
524
#define SYSCTL_DID1_PRTNO_TM4C1236H6PM \
525
0x00510000
// TM4C1236H6PM
526
#define SYSCTL_DID1_PRTNO_TM4C1237D5PM \
527
0x00480000
// TM4C1237D5PM
528
#define SYSCTL_DID1_PRTNO_TM4C1237D5PZ \
529
0x00660000
// TM4C1237D5PZ
530
#define SYSCTL_DID1_PRTNO_TM4C1237E6PM \
531
0x00400000
// TM4C1237E6PM
532
#define SYSCTL_DID1_PRTNO_TM4C1237E6PZ \
533
0x00600000
// TM4C1237E6PZ
534
#define SYSCTL_DID1_PRTNO_TM4C1237H6PGE \
535
0x00650000
// TM4C1237H6PGE
536
#define SYSCTL_DID1_PRTNO_TM4C1237H6PM \
537
0x00410000
// TM4C1237H6PM
538
#define SYSCTL_DID1_PRTNO_TM4C1237H6PZ \
539
0x00610000
// TM4C1237H6PZ
540
#define SYSCTL_DID1_PRTNO_TM4C123AE6PM \
541
0x00800000
// TM4C123AE6PM
542
#define SYSCTL_DID1_PRTNO_TM4C123AH6PM \
543
0x00830000
// TM4C123AH6PM
544
#define SYSCTL_DID1_PRTNO_TM4C123BE6PM \
545
0x00700000
// TM4C123BE6PM
546
#define SYSCTL_DID1_PRTNO_TM4C123BE6PZ \
547
0x00C30000
// TM4C123BE6PZ
548
#define SYSCTL_DID1_PRTNO_TM4C123BH6PGE \
549
0x00C60000
// TM4C123BH6PGE
550
#define SYSCTL_DID1_PRTNO_TM4C123BH6PM \
551
0x00730000
// TM4C123BH6PM
552
#define SYSCTL_DID1_PRTNO_TM4C123BH6PZ \
553
0x00C40000
// TM4C123BH6PZ
554
#define SYSCTL_DID1_PRTNO_TM4C123BH6ZRB \
555
0x00E90000
// TM4C123BH6ZRB
556
#define SYSCTL_DID1_PRTNO_TM4C123FE6PM \
557
0x00B00000
// TM4C123FE6PM
558
#define SYSCTL_DID1_PRTNO_TM4C123FH6PM \
559
0x00B10000
// TM4C123FH6PM
560
#define SYSCTL_DID1_PRTNO_TM4C123GE6PM \
561
0x00A00000
// TM4C123GE6PM
562
#define SYSCTL_DID1_PRTNO_TM4C123GE6PZ \
563
0x00C00000
// TM4C123GE6PZ
564
#define SYSCTL_DID1_PRTNO_TM4C123GH6PGE \
565
0x00C50000
// TM4C123GH6PGE
566
#define SYSCTL_DID1_PRTNO_TM4C123GH6PM \
567
0x00A10000
// TM4C123GH6PM
568
#define SYSCTL_DID1_PRTNO_TM4C123GH6PZ \
569
0x00C10000
// TM4C123GH6PZ
570
#define SYSCTL_DID1_PRTNO_TM4C123GH6ZRB \
571
0x00E30000
// TM4C123GH6ZRB
572
#define SYSCTL_DID1_PRTNO_TM4C1290NCPDT \
573
0x00190000
// TM4C1290NCPDT
574
#define SYSCTL_DID1_PRTNO_TM4C1290NCZAD \
575
0x001B0000
// TM4C1290NCZAD
576
#define SYSCTL_DID1_PRTNO_TM4C1292NCPDT \
577
0x001C0000
// TM4C1292NCPDT
578
#define SYSCTL_DID1_PRTNO_TM4C1292NCZAD \
579
0x001E0000
// TM4C1292NCZAD
580
#define SYSCTL_DID1_PRTNO_TM4C1294KCPDT \
581
0x00340000
// TM4C1294KCPDT
582
#define SYSCTL_DID1_PRTNO_TM4C1294NCPDT \
583
0x001F0000
// TM4C1294NCPDT
584
#define SYSCTL_DID1_PRTNO_TM4C1294NCZAD \
585
0x00210000
// TM4C1294NCZAD
586
#define SYSCTL_DID1_PRTNO_TM4C1297NCZAD \
587
0x00220000
// TM4C1297NCZAD
588
#define SYSCTL_DID1_PRTNO_TM4C1299KCZAD \
589
0x00360000
// TM4C1299KCZAD
590
#define SYSCTL_DID1_PRTNO_TM4C1299NCZAD \
591
0x00230000
// TM4C1299NCZAD
592
#define SYSCTL_DID1_PRTNO_TM4C129CNCPDT \
593
0x00240000
// TM4C129CNCPDT
594
#define SYSCTL_DID1_PRTNO_TM4C129CNCZAD \
595
0x00260000
// TM4C129CNCZAD
596
#define SYSCTL_DID1_PRTNO_TM4C129DNCPDT \
597
0x00270000
// TM4C129DNCPDT
598
#define SYSCTL_DID1_PRTNO_TM4C129DNCZAD \
599
0x00290000
// TM4C129DNCZAD
600
#define SYSCTL_DID1_PRTNO_TM4C129EKCPDT \
601
0x00350000
// TM4C129EKCPDT
602
#define SYSCTL_DID1_PRTNO_TM4C129ENCPDT \
603
0x002D0000
// TM4C129ENCPDT
604
#define SYSCTL_DID1_PRTNO_TM4C129ENCZAD \
605
0x002F0000
// TM4C129ENCZAD
606
#define SYSCTL_DID1_PRTNO_TM4C129LNCZAD \
607
0x00300000
// TM4C129LNCZAD
608
#define SYSCTL_DID1_PRTNO_TM4C129XKCZAD \
609
0x00370000
// TM4C129XKCZAD
610
#define SYSCTL_DID1_PRTNO_TM4C129XNCZAD \
611
0x00320000
// TM4C129XNCZAD
612
#define SYSCTL_DID1_PINCNT_M 0x0000E000
// Package Pin Count
613
#define SYSCTL_DID1_PINCNT_100 0x00004000
// 100-pin LQFP package
614
#define SYSCTL_DID1_PINCNT_64 0x00006000
// 64-pin LQFP package
615
#define SYSCTL_DID1_PINCNT_144 0x00008000
// 144-pin LQFP package
616
#define SYSCTL_DID1_PINCNT_157 0x0000A000
// 157-pin BGA package
617
#define SYSCTL_DID1_PINCNT_128 0x0000C000
// 128-pin TQFP package
618
#define SYSCTL_DID1_TEMP_M 0x000000E0
// Temperature Range
619
#define SYSCTL_DID1_TEMP_C 0x00000000
// Commercial temperature range
620
#define SYSCTL_DID1_TEMP_I 0x00000020
// Industrial temperature range
621
#define SYSCTL_DID1_TEMP_E 0x00000040
// Extended temperature range
622
#define SYSCTL_DID1_TEMP_IE 0x00000060
// Available in both industrial
623
// temperature range (-40C to 85C)
624
// and extended temperature range
625
// (-40C to 105C) devices. See
626
#define SYSCTL_DID1_PKG_M 0x00000018
// Package Type
627
#define SYSCTL_DID1_PKG_QFP 0x00000008
// QFP package
628
#define SYSCTL_DID1_PKG_BGA 0x00000010
// BGA package
629
#define SYSCTL_DID1_ROHS 0x00000004
// RoHS-Compliance
630
#define SYSCTL_DID1_QUAL_M 0x00000003
// Qualification Status
631
#define SYSCTL_DID1_QUAL_ES 0x00000000
// Engineering Sample (unqualified)
632
#define SYSCTL_DID1_QUAL_PP 0x00000001
// Pilot Production (unqualified)
633
#define SYSCTL_DID1_QUAL_FQ 0x00000002
// Fully Qualified
634
635
//*****************************************************************************
636
//
637
// The following are defines for the bit fields in the SYSCTL_DC0 register.
638
//
639
//*****************************************************************************
640
#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000
// SRAM Size
641
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000
// 2 KB of SRAM
642
#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000
// 4 KB of SRAM
643
#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000
// 6 KB of SRAM
644
#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000
// 8 KB of SRAM
645
#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000
// 12 KB of SRAM
646
#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000
// 16 KB of SRAM
647
#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000
// 20 KB of SRAM
648
#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000
// 24 KB of SRAM
649
#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000
// 32 KB of SRAM
650
#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF
// Flash Size
651
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003
// 8 KB of Flash
652
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007
// 16 KB of Flash
653
#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F
// 32 KB of Flash
654
#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F
// 64 KB of Flash
655
#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F
// 96 KB of Flash
656
#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F
// 128 KB of Flash
657
#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F
// 192 KB of Flash
658
#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F
// 256 KB of Flash
659
660
//*****************************************************************************
661
//
662
// The following are defines for the bit fields in the SYSCTL_DC1 register.
663
//
664
//*****************************************************************************
665
#define SYSCTL_DC1_WDT1 0x10000000
// Watchdog Timer1 Present
666
#define SYSCTL_DC1_CAN1 0x02000000
// CAN Module 1 Present
667
#define SYSCTL_DC1_CAN0 0x01000000
// CAN Module 0 Present
668
#define SYSCTL_DC1_PWM1 0x00200000
// PWM Module 1 Present
669
#define SYSCTL_DC1_PWM0 0x00100000
// PWM Module 0 Present
670
#define SYSCTL_DC1_ADC1 0x00020000
// ADC Module 1 Present
671
#define SYSCTL_DC1_ADC0 0x00010000
// ADC Module 0 Present
672
#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000
// System Clock Divider
673
#define SYSCTL_DC1_MINSYSDIV_80 0x00002000
// Specifies an 80-MHz CPU clock
674
// with a PLL divider of 2.5
675
#define SYSCTL_DC1_MINSYSDIV_50 0x00003000
// Specifies a 50-MHz CPU clock
676
// with a PLL divider of 4
677
#define SYSCTL_DC1_MINSYSDIV_40 0x00004000
// Specifies a 40-MHz CPU clock
678
// with a PLL divider of 5
679
#define SYSCTL_DC1_MINSYSDIV_25 0x00007000
// Specifies a 25-MHz clock with a
680
// PLL divider of 8
681
#define SYSCTL_DC1_MINSYSDIV_20 0x00009000
// Specifies a 20-MHz clock with a
682
// PLL divider of 10
683
#define SYSCTL_DC1_ADC1SPD_M 0x00000C00
// Max ADC1 Speed
684
#define SYSCTL_DC1_ADC1SPD_125K 0x00000000
// 125K samples/second
685
#define SYSCTL_DC1_ADC1SPD_250K 0x00000400
// 250K samples/second
686
#define SYSCTL_DC1_ADC1SPD_500K 0x00000800
// 500K samples/second
687
#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00
// 1M samples/second
688
#define SYSCTL_DC1_ADC0SPD_M 0x00000300
// Max ADC0 Speed
689
#define SYSCTL_DC1_ADC0SPD_125K 0x00000000
// 125K samples/second
690
#define SYSCTL_DC1_ADC0SPD_250K 0x00000100
// 250K samples/second
691
#define SYSCTL_DC1_ADC0SPD_500K 0x00000200
// 500K samples/second
692
#define SYSCTL_DC1_ADC0SPD_1M 0x00000300
// 1M samples/second
693
#define SYSCTL_DC1_MPU 0x00000080
// MPU Present
694
#define SYSCTL_DC1_HIB 0x00000040
// Hibernation Module Present
695
#define SYSCTL_DC1_TEMP 0x00000020
// Temp Sensor Present
696
#define SYSCTL_DC1_PLL 0x00000010
// PLL Present
697
#define SYSCTL_DC1_WDT0 0x00000008
// Watchdog Timer 0 Present
698
#define SYSCTL_DC1_SWO 0x00000004
// SWO Trace Port Present
699
#define SYSCTL_DC1_SWD 0x00000002
// SWD Present
700
#define SYSCTL_DC1_JTAG 0x00000001
// JTAG Present
701
702
//*****************************************************************************
703
//
704
// The following are defines for the bit fields in the SYSCTL_DC2 register.
705
//
706
//*****************************************************************************
707
#define SYSCTL_DC2_EPI0 0x40000000
// EPI Module 0 Present
708
#define SYSCTL_DC2_I2S0 0x10000000
// I2S Module 0 Present
709
#define SYSCTL_DC2_COMP2 0x04000000
// Analog Comparator 2 Present
710
#define SYSCTL_DC2_COMP1 0x02000000
// Analog Comparator 1 Present
711
#define SYSCTL_DC2_COMP0 0x01000000
// Analog Comparator 0 Present
712
#define SYSCTL_DC2_TIMER3 0x00080000
// Timer Module 3 Present
713
#define SYSCTL_DC2_TIMER2 0x00040000
// Timer Module 2 Present
714
#define SYSCTL_DC2_TIMER1 0x00020000
// Timer Module 1 Present
715
#define SYSCTL_DC2_TIMER0 0x00010000
// Timer Module 0 Present
716
#define SYSCTL_DC2_I2C1HS 0x00008000
// I2C Module 1 Speed
717
#define SYSCTL_DC2_I2C1 0x00004000
// I2C Module 1 Present
718
#define SYSCTL_DC2_I2C0HS 0x00002000
// I2C Module 0 Speed
719
#define SYSCTL_DC2_I2C0 0x00001000
// I2C Module 0 Present
720
#define SYSCTL_DC2_QEI1 0x00000200
// QEI Module 1 Present
721
#define SYSCTL_DC2_QEI0 0x00000100
// QEI Module 0 Present
722
#define SYSCTL_DC2_SSI1 0x00000020
// SSI Module 1 Present
723
#define SYSCTL_DC2_SSI0 0x00000010
// SSI Module 0 Present
724
#define SYSCTL_DC2_UART2 0x00000004
// UART Module 2 Present
725
#define SYSCTL_DC2_UART1 0x00000002
// UART Module 1 Present
726
#define SYSCTL_DC2_UART0 0x00000001
// UART Module 0 Present
727
728
//*****************************************************************************
729
//
730
// The following are defines for the bit fields in the SYSCTL_DC3 register.
731
//
732
//*****************************************************************************
733
#define SYSCTL_DC3_32KHZ 0x80000000
// 32KHz Input Clock Available
734
#define SYSCTL_DC3_CCP5 0x20000000
// T2CCP1 Pin Present
735
#define SYSCTL_DC3_CCP4 0x10000000
// T2CCP0 Pin Present
736
#define SYSCTL_DC3_CCP3 0x08000000
// T1CCP1 Pin Present
737
#define SYSCTL_DC3_CCP2 0x04000000
// T1CCP0 Pin Present
738
#define SYSCTL_DC3_CCP1 0x02000000
// T0CCP1 Pin Present
739
#define SYSCTL_DC3_CCP0 0x01000000
// T0CCP0 Pin Present
740
#define SYSCTL_DC3_ADC0AIN7 0x00800000
// ADC Module 0 AIN7 Pin Present
741
#define SYSCTL_DC3_ADC0AIN6 0x00400000
// ADC Module 0 AIN6 Pin Present
742
#define SYSCTL_DC3_ADC0AIN5 0x00200000
// ADC Module 0 AIN5 Pin Present
743
#define SYSCTL_DC3_ADC0AIN4 0x00100000
// ADC Module 0 AIN4 Pin Present
744
#define SYSCTL_DC3_ADC0AIN3 0x00080000
// ADC Module 0 AIN3 Pin Present
745
#define SYSCTL_DC3_ADC0AIN2 0x00040000
// ADC Module 0 AIN2 Pin Present
746
#define SYSCTL_DC3_ADC0AIN1 0x00020000
// ADC Module 0 AIN1 Pin Present
747
#define SYSCTL_DC3_ADC0AIN0 0x00010000
// ADC Module 0 AIN0 Pin Present
748
#define SYSCTL_DC3_PWMFAULT 0x00008000
// PWM Fault Pin Present
749
#define SYSCTL_DC3_C2O 0x00004000
// C2o Pin Present
750
#define SYSCTL_DC3_C2PLUS 0x00002000
// C2+ Pin Present
751
#define SYSCTL_DC3_C2MINUS 0x00001000
// C2- Pin Present
752
#define SYSCTL_DC3_C1O 0x00000800
// C1o Pin Present
753
#define SYSCTL_DC3_C1PLUS 0x00000400
// C1+ Pin Present
754
#define SYSCTL_DC3_C1MINUS 0x00000200
// C1- Pin Present
755
#define SYSCTL_DC3_C0O 0x00000100
// C0o Pin Present
756
#define SYSCTL_DC3_C0PLUS 0x00000080
// C0+ Pin Present
757
#define SYSCTL_DC3_C0MINUS 0x00000040
// C0- Pin Present
758
#define SYSCTL_DC3_PWM5 0x00000020
// PWM5 Pin Present
759
#define SYSCTL_DC3_PWM4 0x00000010
// PWM4 Pin Present
760
#define SYSCTL_DC3_PWM3 0x00000008
// PWM3 Pin Present
761
#define SYSCTL_DC3_PWM2 0x00000004
// PWM2 Pin Present
762
#define SYSCTL_DC3_PWM1 0x00000002
// PWM1 Pin Present
763
#define SYSCTL_DC3_PWM0 0x00000001
// PWM0 Pin Present
764
765
//*****************************************************************************
766
//
767
// The following are defines for the bit fields in the SYSCTL_DC4 register.
768
//
769
//*****************************************************************************
770
#define SYSCTL_DC4_EPHY0 0x40000000
// Ethernet PHY Layer 0 Present
771
#define SYSCTL_DC4_EMAC0 0x10000000
// Ethernet MAC Layer 0 Present
772
#define SYSCTL_DC4_E1588 0x01000000
// 1588 Capable
773
#define SYSCTL_DC4_PICAL 0x00040000
// PIOSC Calibrate
774
#define SYSCTL_DC4_CCP7 0x00008000
// T3CCP1 Pin Present
775
#define SYSCTL_DC4_CCP6 0x00004000
// T3CCP0 Pin Present
776
#define SYSCTL_DC4_UDMA 0x00002000
// Micro-DMA Module Present
777
#define SYSCTL_DC4_ROM 0x00001000
// Internal Code ROM Present
778
#define SYSCTL_DC4_GPIOJ 0x00000100
// GPIO Port J Present
779
#define SYSCTL_DC4_GPIOH 0x00000080
// GPIO Port H Present
780
#define SYSCTL_DC4_GPIOG 0x00000040
// GPIO Port G Present
781
#define SYSCTL_DC4_GPIOF 0x00000020
// GPIO Port F Present
782
#define SYSCTL_DC4_GPIOE 0x00000010
// GPIO Port E Present
783
#define SYSCTL_DC4_GPIOD 0x00000008
// GPIO Port D Present
784
#define SYSCTL_DC4_GPIOC 0x00000004
// GPIO Port C Present
785
#define SYSCTL_DC4_GPIOB 0x00000002
// GPIO Port B Present
786
#define SYSCTL_DC4_GPIOA 0x00000001
// GPIO Port A Present
787
788
//*****************************************************************************
789
//
790
// The following are defines for the bit fields in the SYSCTL_DC5 register.
791
//
792
//*****************************************************************************
793
#define SYSCTL_DC5_PWMFAULT3 0x08000000
// PWM Fault 3 Pin Present
794
#define SYSCTL_DC5_PWMFAULT2 0x04000000
// PWM Fault 2 Pin Present
795
#define SYSCTL_DC5_PWMFAULT1 0x02000000
// PWM Fault 1 Pin Present
796
#define SYSCTL_DC5_PWMFAULT0 0x01000000
// PWM Fault 0 Pin Present
797
#define SYSCTL_DC5_PWMEFLT 0x00200000
// PWM Extended Fault Active
798
#define SYSCTL_DC5_PWMESYNC 0x00100000
// PWM Extended SYNC Active
799
#define SYSCTL_DC5_PWM7 0x00000080
// PWM7 Pin Present
800
#define SYSCTL_DC5_PWM6 0x00000040
// PWM6 Pin Present
801
#define SYSCTL_DC5_PWM5 0x00000020
// PWM5 Pin Present
802
#define SYSCTL_DC5_PWM4 0x00000010
// PWM4 Pin Present
803
#define SYSCTL_DC5_PWM3 0x00000008
// PWM3 Pin Present
804
#define SYSCTL_DC5_PWM2 0x00000004
// PWM2 Pin Present
805
#define SYSCTL_DC5_PWM1 0x00000002
// PWM1 Pin Present
806
#define SYSCTL_DC5_PWM0 0x00000001
// PWM0 Pin Present
807
808
//*****************************************************************************
809
//
810
// The following are defines for the bit fields in the SYSCTL_DC6 register.
811
//
812
//*****************************************************************************
813
#define SYSCTL_DC6_USB0PHY 0x00000010
// USB Module 0 PHY Present
814
#define SYSCTL_DC6_USB0_M 0x00000003
// USB Module 0 Present
815
#define SYSCTL_DC6_USB0_DEV 0x00000001
// USB0 is Device Only
816
#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002
// USB is Device or Host
817
#define SYSCTL_DC6_USB0_OTG 0x00000003
// USB0 is OTG
818
819
//*****************************************************************************
820
//
821
// The following are defines for the bit fields in the SYSCTL_DC7 register.
822
//
823
//*****************************************************************************
824
#define SYSCTL_DC7_DMACH30 0x40000000
// DMA Channel 30
825
#define SYSCTL_DC7_DMACH29 0x20000000
// DMA Channel 29
826
#define SYSCTL_DC7_DMACH28 0x10000000
// DMA Channel 28
827
#define SYSCTL_DC7_DMACH27 0x08000000
// DMA Channel 27
828
#define SYSCTL_DC7_DMACH26 0x04000000
// DMA Channel 26
829
#define SYSCTL_DC7_DMACH25 0x02000000
// DMA Channel 25
830
#define SYSCTL_DC7_DMACH24 0x01000000
// DMA Channel 24
831
#define SYSCTL_DC7_DMACH23 0x00800000
// DMA Channel 23
832
#define SYSCTL_DC7_DMACH22 0x00400000
// DMA Channel 22
833
#define SYSCTL_DC7_DMACH21 0x00200000
// DMA Channel 21
834
#define SYSCTL_DC7_DMACH20 0x00100000
// DMA Channel 20
835
#define SYSCTL_DC7_DMACH19 0x00080000
// DMA Channel 19
836
#define SYSCTL_DC7_DMACH18 0x00040000
// DMA Channel 18
837
#define SYSCTL_DC7_DMACH17 0x00020000
// DMA Channel 17
838
#define SYSCTL_DC7_DMACH16 0x00010000
// DMA Channel 16
839
#define SYSCTL_DC7_DMACH15 0x00008000
// DMA Channel 15
840
#define SYSCTL_DC7_DMACH14 0x00004000
// DMA Channel 14
841
#define SYSCTL_DC7_DMACH13 0x00002000
// DMA Channel 13
842
#define SYSCTL_DC7_DMACH12 0x00001000
// DMA Channel 12
843
#define SYSCTL_DC7_DMACH11 0x00000800
// DMA Channel 11
844
#define SYSCTL_DC7_DMACH10 0x00000400
// DMA Channel 10
845
#define SYSCTL_DC7_DMACH9 0x00000200
// DMA Channel 9
846
#define SYSCTL_DC7_DMACH8 0x00000100
// DMA Channel 8
847
#define SYSCTL_DC7_DMACH7 0x00000080
// DMA Channel 7
848
#define SYSCTL_DC7_DMACH6 0x00000040
// DMA Channel 6
849
#define SYSCTL_DC7_DMACH5 0x00000020
// DMA Channel 5
850
#define SYSCTL_DC7_DMACH4 0x00000010
// DMA Channel 4
851
#define SYSCTL_DC7_DMACH3 0x00000008
// DMA Channel 3
852
#define SYSCTL_DC7_DMACH2 0x00000004
// DMA Channel 2
853
#define SYSCTL_DC7_DMACH1 0x00000002
// DMA Channel 1
854
#define SYSCTL_DC7_DMACH0 0x00000001
// DMA Channel 0
855
856
//*****************************************************************************
857
//
858
// The following are defines for the bit fields in the SYSCTL_DC8 register.
859
//
860
//*****************************************************************************
861
#define SYSCTL_DC8_ADC1AIN15 0x80000000
// ADC Module 1 AIN15 Pin Present
862
#define SYSCTL_DC8_ADC1AIN14 0x40000000
// ADC Module 1 AIN14 Pin Present
863
#define SYSCTL_DC8_ADC1AIN13 0x20000000
// ADC Module 1 AIN13 Pin Present
864
#define SYSCTL_DC8_ADC1AIN12 0x10000000
// ADC Module 1 AIN12 Pin Present
865
#define SYSCTL_DC8_ADC1AIN11 0x08000000
// ADC Module 1 AIN11 Pin Present
866
#define SYSCTL_DC8_ADC1AIN10 0x04000000
// ADC Module 1 AIN10 Pin Present
867
#define SYSCTL_DC8_ADC1AIN9 0x02000000
// ADC Module 1 AIN9 Pin Present
868
#define SYSCTL_DC8_ADC1AIN8 0x01000000
// ADC Module 1 AIN8 Pin Present
869
#define SYSCTL_DC8_ADC1AIN7 0x00800000
// ADC Module 1 AIN7 Pin Present
870
#define SYSCTL_DC8_ADC1AIN6 0x00400000
// ADC Module 1 AIN6 Pin Present
871
#define SYSCTL_DC8_ADC1AIN5 0x00200000
// ADC Module 1 AIN5 Pin Present
872
#define SYSCTL_DC8_ADC1AIN4 0x00100000
// ADC Module 1 AIN4 Pin Present
873
#define SYSCTL_DC8_ADC1AIN3 0x00080000
// ADC Module 1 AIN3 Pin Present
874
#define SYSCTL_DC8_ADC1AIN2 0x00040000
// ADC Module 1 AIN2 Pin Present
875
#define SYSCTL_DC8_ADC1AIN1 0x00020000
// ADC Module 1 AIN1 Pin Present
876
#define SYSCTL_DC8_ADC1AIN0 0x00010000
// ADC Module 1 AIN0 Pin Present
877
#define SYSCTL_DC8_ADC0AIN15 0x00008000
// ADC Module 0 AIN15 Pin Present
878
#define SYSCTL_DC8_ADC0AIN14 0x00004000
// ADC Module 0 AIN14 Pin Present
879
#define SYSCTL_DC8_ADC0AIN13 0x00002000
// ADC Module 0 AIN13 Pin Present
880
#define SYSCTL_DC8_ADC0AIN12 0x00001000
// ADC Module 0 AIN12 Pin Present
881
#define SYSCTL_DC8_ADC0AIN11 0x00000800
// ADC Module 0 AIN11 Pin Present
882
#define SYSCTL_DC8_ADC0AIN10 0x00000400
// ADC Module 0 AIN10 Pin Present
883
#define SYSCTL_DC8_ADC0AIN9 0x00000200
// ADC Module 0 AIN9 Pin Present
884
#define SYSCTL_DC8_ADC0AIN8 0x00000100
// ADC Module 0 AIN8 Pin Present
885
#define SYSCTL_DC8_ADC0AIN7 0x00000080
// ADC Module 0 AIN7 Pin Present
886
#define SYSCTL_DC8_ADC0AIN6 0x00000040
// ADC Module 0 AIN6 Pin Present
887
#define SYSCTL_DC8_ADC0AIN5 0x00000020
// ADC Module 0 AIN5 Pin Present
888
#define SYSCTL_DC8_ADC0AIN4 0x00000010
// ADC Module 0 AIN4 Pin Present
889
#define SYSCTL_DC8_ADC0AIN3 0x00000008
// ADC Module 0 AIN3 Pin Present
890
#define SYSCTL_DC8_ADC0AIN2 0x00000004
// ADC Module 0 AIN2 Pin Present
891
#define SYSCTL_DC8_ADC0AIN1 0x00000002
// ADC Module 0 AIN1 Pin Present
892
#define SYSCTL_DC8_ADC0AIN0 0x00000001
// ADC Module 0 AIN0 Pin Present
893
894
//*****************************************************************************
895
//
896
// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
897
//
898
//*****************************************************************************
899
#define SYSCTL_PBORCTL_BOR0 0x00000004
// VDD under BOR0 Event Action
900
#define SYSCTL_PBORCTL_BOR1 0x00000002
// VDD under BOR1 Event Action
901
902
//*****************************************************************************
903
//
904
// The following are defines for the bit fields in the SYSCTL_PTBOCTL register.
905
//
906
//*****************************************************************************
907
#define SYSCTL_PTBOCTL_VDDA_UBOR_M \
908
0x00000300
// VDDA under BOR Event Action
909
#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE \
910
0x00000000
// No Action
911
#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT \
912
0x00000100
// System control interrupt
913
#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI \
914
0x00000200
// NMI
915
#define SYSCTL_PTBOCTL_VDDA_UBOR_RST \
916
0x00000300
// Reset
917
#define SYSCTL_PTBOCTL_VDD_UBOR_M \
918
0x00000003
// VDD (VDDS) under BOR Event
919
// Action
920
#define SYSCTL_PTBOCTL_VDD_UBOR_NONE \
921
0x00000000
// No Action
922
#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT \
923
0x00000001
// System control interrupt
924
#define SYSCTL_PTBOCTL_VDD_UBOR_NMI \
925
0x00000002
// NMI
926
#define SYSCTL_PTBOCTL_VDD_UBOR_RST \
927
0x00000003
// Reset
928
929
//*****************************************************************************
930
//
931
// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
932
//
933
//*****************************************************************************
934
#define SYSCTL_SRCR0_WDT1 0x10000000
// WDT1 Reset Control
935
#define SYSCTL_SRCR0_CAN1 0x02000000
// CAN1 Reset Control
936
#define SYSCTL_SRCR0_CAN0 0x01000000
// CAN0 Reset Control
937
#define SYSCTL_SRCR0_PWM0 0x00100000
// PWM Reset Control
938
#define SYSCTL_SRCR0_ADC1 0x00020000
// ADC1 Reset Control
939
#define SYSCTL_SRCR0_ADC0 0x00010000
// ADC0 Reset Control
940
#define SYSCTL_SRCR0_HIB 0x00000040
// HIB Reset Control
941
#define SYSCTL_SRCR0_WDT0 0x00000008
// WDT0 Reset Control
942
943
//*****************************************************************************
944
//
945
// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
946
//
947
//*****************************************************************************
948
#define SYSCTL_SRCR1_COMP2 0x04000000
// Analog Comp 2 Reset Control
949
#define SYSCTL_SRCR1_COMP1 0x02000000
// Analog Comp 1 Reset Control
950
#define SYSCTL_SRCR1_COMP0 0x01000000
// Analog Comp 0 Reset Control
951
#define SYSCTL_SRCR1_TIMER3 0x00080000
// Timer 3 Reset Control
952
#define SYSCTL_SRCR1_TIMER2 0x00040000
// Timer 2 Reset Control
953
#define SYSCTL_SRCR1_TIMER1 0x00020000
// Timer 1 Reset Control
954
#define SYSCTL_SRCR1_TIMER0 0x00010000
// Timer 0 Reset Control
955
#define SYSCTL_SRCR1_I2C1 0x00004000
// I2C1 Reset Control
956
#define SYSCTL_SRCR1_I2C0 0x00001000
// I2C0 Reset Control
957
#define SYSCTL_SRCR1_QEI1 0x00000200
// QEI1 Reset Control
958
#define SYSCTL_SRCR1_QEI0 0x00000100
// QEI0 Reset Control
959
#define SYSCTL_SRCR1_SSI1 0x00000020
// SSI1 Reset Control
960
#define SYSCTL_SRCR1_SSI0 0x00000010
// SSI0 Reset Control
961
#define SYSCTL_SRCR1_UART2 0x00000004
// UART2 Reset Control
962
#define SYSCTL_SRCR1_UART1 0x00000002
// UART1 Reset Control
963
#define SYSCTL_SRCR1_UART0 0x00000001
// UART0 Reset Control
964
965
//*****************************************************************************
966
//
967
// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
968
//
969
//*****************************************************************************
970
#define SYSCTL_SRCR2_USB0 0x00010000
// USB0 Reset Control
971
#define SYSCTL_SRCR2_UDMA 0x00002000
// Micro-DMA Reset Control
972
#define SYSCTL_SRCR2_GPIOJ 0x00000100
// Port J Reset Control
973
#define SYSCTL_SRCR2_GPIOH 0x00000080
// Port H Reset Control
974
#define SYSCTL_SRCR2_GPIOG 0x00000040
// Port G Reset Control
975
#define SYSCTL_SRCR2_GPIOF 0x00000020
// Port F Reset Control
976
#define SYSCTL_SRCR2_GPIOE 0x00000010
// Port E Reset Control
977
#define SYSCTL_SRCR2_GPIOD 0x00000008
// Port D Reset Control
978
#define SYSCTL_SRCR2_GPIOC 0x00000004
// Port C Reset Control
979
#define SYSCTL_SRCR2_GPIOB 0x00000002
// Port B Reset Control
980
#define SYSCTL_SRCR2_GPIOA 0x00000001
// Port A Reset Control
981
982
//*****************************************************************************
983
//
984
// The following are defines for the bit fields in the SYSCTL_RIS register.
985
//
986
//*****************************************************************************
987
#define SYSCTL_RIS_BOR0RIS 0x00000800
// VDD under BOR0 Raw Interrupt
988
// Status
989
#define SYSCTL_RIS_VDDARIS 0x00000400
// VDDA Power OK Event Raw
990
// Interrupt Status
991
#define SYSCTL_RIS_MOSCPUPRIS 0x00000100
// MOSC Power Up Raw Interrupt
992
// Status
993
#define SYSCTL_RIS_USBPLLLRIS 0x00000080
// USB PLL Lock Raw Interrupt
994
// Status
995
#define SYSCTL_RIS_PLLLRIS 0x00000040
// PLL Lock Raw Interrupt Status
996
#define SYSCTL_RIS_MOFRIS 0x00000008
// Main Oscillator Failure Raw
997
// Interrupt Status
998
#define SYSCTL_RIS_BOR1RIS 0x00000002
// VDD under BOR1 Raw Interrupt
999
// Status
1000
#define SYSCTL_RIS_BORRIS 0x00000002
// Brown-Out Reset Raw Interrupt
1001
// Status
1002
1003
//*****************************************************************************
1004
//
1005
// The following are defines for the bit fields in the SYSCTL_IMC register.
1006
//
1007
//*****************************************************************************
1008
#define SYSCTL_IMC_BOR0IM 0x00000800
// VDD under BOR0 Interrupt Mask
1009
#define SYSCTL_IMC_VDDAIM 0x00000400
// VDDA Power OK Interrupt Mask
1010
#define SYSCTL_IMC_MOSCPUPIM 0x00000100
// MOSC Power Up Interrupt Mask
1011
#define SYSCTL_IMC_USBPLLLIM 0x00000080
// USB PLL Lock Interrupt Mask
1012
#define SYSCTL_IMC_PLLLIM 0x00000040
// PLL Lock Interrupt Mask
1013
#define SYSCTL_IMC_MOFIM 0x00000008
// Main Oscillator Failure
1014
// Interrupt Mask
1015
#define SYSCTL_IMC_BORIM 0x00000002
// Brown-Out Reset Interrupt Mask
1016
#define SYSCTL_IMC_BOR1IM 0x00000002
// VDD under BOR1 Interrupt Mask
1017
1018
//*****************************************************************************
1019
//
1020
// The following are defines for the bit fields in the SYSCTL_MISC register.
1021
//
1022
//*****************************************************************************
1023
#define SYSCTL_MISC_BOR0MIS 0x00000800
// VDD under BOR0 Masked Interrupt
1024
// Status
1025
#define SYSCTL_MISC_VDDAMIS 0x00000400
// VDDA Power OK Masked Interrupt
1026
// Status
1027
#define SYSCTL_MISC_MOSCPUPMIS 0x00000100
// MOSC Power Up Masked Interrupt
1028
// Status
1029
#define SYSCTL_MISC_USBPLLLMIS 0x00000080
// USB PLL Lock Masked Interrupt
1030
// Status
1031
#define SYSCTL_MISC_PLLLMIS 0x00000040
// PLL Lock Masked Interrupt Status
1032
#define SYSCTL_MISC_MOFMIS 0x00000008
// Main Oscillator Failure Masked
1033
// Interrupt Status
1034
#define SYSCTL_MISC_BORMIS 0x00000002
// BOR Masked Interrupt Status
1035
#define SYSCTL_MISC_BOR1MIS 0x00000002
// VDD under BOR1 Masked Interrupt
1036
// Status
1037
1038
//*****************************************************************************
1039
//
1040
// The following are defines for the bit fields in the SYSCTL_RESC register.
1041
//
1042
//*****************************************************************************
1043
#define SYSCTL_RESC_MOSCFAIL 0x00010000
// MOSC Failure Reset
1044
#define SYSCTL_RESC_HSSR 0x00001000
// HSSR Reset
1045
#define SYSCTL_RESC_WDT1 0x00000020
// Watchdog Timer 1 Reset
1046
#define SYSCTL_RESC_SW 0x00000010
// Software Reset
1047
#define SYSCTL_RESC_WDT0 0x00000008
// Watchdog Timer 0 Reset
1048
#define SYSCTL_RESC_BOR 0x00000004
// Brown-Out Reset
1049
#define SYSCTL_RESC_POR 0x00000002
// Power-On Reset
1050
#define SYSCTL_RESC_EXT 0x00000001
// External Reset
1051
1052
//*****************************************************************************
1053
//
1054
// The following are defines for the bit fields in the SYSCTL_PWRTC register.
1055
//
1056
//*****************************************************************************
1057
#define SYSCTL_PWRTC_VDDA_UBOR 0x00000010
// VDDA Under BOR Status
1058
#define SYSCTL_PWRTC_VDD_UBOR 0x00000001
// VDD Under BOR Status
1059
1060
//*****************************************************************************
1061
//
1062
// The following are defines for the bit fields in the SYSCTL_RCC register.
1063
//
1064
//*****************************************************************************
1065
#define SYSCTL_RCC_ACG 0x08000000
// Auto Clock Gating
1066
#define SYSCTL_RCC_SYSDIV_M 0x07800000
// System Clock Divisor
1067
#define SYSCTL_RCC_USESYSDIV 0x00400000
// Enable System Clock Divider
1068
#define SYSCTL_RCC_USEPWMDIV 0x00100000
// Enable PWM Clock Divisor
1069
#define SYSCTL_RCC_PWMDIV_M 0x000E0000
// PWM Unit Clock Divisor
1070
#define SYSCTL_RCC_PWMDIV_2 0x00000000
// PWM clock /2
1071
#define SYSCTL_RCC_PWMDIV_4 0x00020000
// PWM clock /4
1072
#define SYSCTL_RCC_PWMDIV_8 0x00040000
// PWM clock /8
1073
#define SYSCTL_RCC_PWMDIV_16 0x00060000
// PWM clock /16
1074
#define SYSCTL_RCC_PWMDIV_32 0x00080000
// PWM clock /32
1075
#define SYSCTL_RCC_PWMDIV_64 0x000A0000
// PWM clock /64
1076
#define SYSCTL_RCC_PWRDN 0x00002000
// PLL Power Down
1077
#define SYSCTL_RCC_BYPASS 0x00000800
// PLL Bypass
1078
#define SYSCTL_RCC_XTAL_M 0x000007C0
// Crystal Value
1079
#define SYSCTL_RCC_XTAL_4MHZ 0x00000180
// 4 MHz
1080
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0
// 4.096 MHz
1081
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200
// 4.9152 MHz
1082
#define SYSCTL_RCC_XTAL_5MHZ 0x00000240
// 5 MHz
1083
#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280
// 5.12 MHz
1084
#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0
// 6 MHz
1085
#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300
// 6.144 MHz
1086
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340
// 7.3728 MHz
1087
#define SYSCTL_RCC_XTAL_8MHZ 0x00000380
// 8 MHz
1088
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0
// 8.192 MHz
1089
#define SYSCTL_RCC_XTAL_10MHZ 0x00000400
// 10 MHz
1090
#define SYSCTL_RCC_XTAL_12MHZ 0x00000440
// 12 MHz
1091
#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480
// 12.288 MHz
1092
#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0
// 13.56 MHz
1093
#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500
// 14.31818 MHz
1094
#define SYSCTL_RCC_XTAL_16MHZ 0x00000540
// 16 MHz
1095
#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580
// 16.384 MHz
1096
#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0
// 18.0 MHz (USB)
1097
#define SYSCTL_RCC_XTAL_20MHZ 0x00000600
// 20.0 MHz (USB)
1098
#define SYSCTL_RCC_XTAL_24MHZ 0x00000640
// 24.0 MHz (USB)
1099
#define SYSCTL_RCC_XTAL_25MHZ 0x00000680
// 25.0 MHz (USB)
1100
#define SYSCTL_RCC_OSCSRC_M 0x00000030
// Oscillator Source
1101
#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000
// MOSC
1102
#define SYSCTL_RCC_OSCSRC_INT 0x00000010
// IOSC
1103
#define SYSCTL_RCC_OSCSRC_INT4 0x00000020
// IOSC/4
1104
#define SYSCTL_RCC_OSCSRC_30 0x00000030
// LFIOSC
1105
#define SYSCTL_RCC_MOSCDIS 0x00000001
// Main Oscillator Disable
1106
#define SYSCTL_RCC_SYSDIV_S 23
1107
#define SYSCTL_RCC_XTAL_S 6
// Shift to the XTAL field
1108
1109
//*****************************************************************************
1110
//
1111
// The following are defines for the bit fields in the SYSCTL_NMIC register.
1112
//
1113
//*****************************************************************************
1114
#define SYSCTL_NMIC_MOSCFAIL 0x00010000
// MOSC Failure NMI
1115
#define SYSCTL_NMIC_TAMPER 0x00000200
// Tamper Event NMI
1116
#define SYSCTL_NMIC_WDT1 0x00000020
// Watch Dog Timer (WDT) 1 NMI
1117
#define SYSCTL_NMIC_WDT0 0x00000008
// Watch Dog Timer (WDT) 0 NMI
1118
#define SYSCTL_NMIC_POWER 0x00000004
// Power/Brown Out Event NMI
1119
#define SYSCTL_NMIC_EXTERNAL 0x00000001
// External Pin NMI
1120
1121
//*****************************************************************************
1122
//
1123
// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
1124
// register.
1125
//
1126
//*****************************************************************************
1127
#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100
// Port J Advanced High-Performance
1128
// Bus
1129
#define SYSCTL_GPIOHBCTL_PORTH 0x00000080
// Port H Advanced High-Performance
1130
// Bus
1131
#define SYSCTL_GPIOHBCTL_PORTG 0x00000040
// Port G Advanced High-Performance
1132
// Bus
1133
#define SYSCTL_GPIOHBCTL_PORTF 0x00000020
// Port F Advanced High-Performance
1134
// Bus
1135
#define SYSCTL_GPIOHBCTL_PORTE 0x00000010
// Port E Advanced High-Performance
1136
// Bus
1137
#define SYSCTL_GPIOHBCTL_PORTD 0x00000008
// Port D Advanced High-Performance
1138
// Bus
1139
#define SYSCTL_GPIOHBCTL_PORTC 0x00000004
// Port C Advanced High-Performance
1140
// Bus
1141
#define SYSCTL_GPIOHBCTL_PORTB 0x00000002
// Port B Advanced High-Performance
1142
// Bus
1143
#define SYSCTL_GPIOHBCTL_PORTA 0x00000001
// Port A Advanced High-Performance
1144
// Bus
1145
1146
//*****************************************************************************
1147
//
1148
// The following are defines for the bit fields in the SYSCTL_RCC2 register.
1149
//
1150
//*****************************************************************************
1151
#define SYSCTL_RCC2_USERCC2 0x80000000
// Use RCC2
1152
#define SYSCTL_RCC2_DIV400 0x40000000
// Divide PLL as 400 MHz vs. 200
1153
// MHz
1154
#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000
// System Clock Divisor 2
1155
#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000
// Additional LSB for SYSDIV2
1156
#define SYSCTL_RCC2_USBPWRDN 0x00004000
// Power-Down USB PLL
1157
#define SYSCTL_RCC2_PWRDN2 0x00002000
// Power-Down PLL 2
1158
#define SYSCTL_RCC2_BYPASS2 0x00000800
// PLL Bypass 2
1159
#define SYSCTL_RCC2_OSCSRC2_M 0x00000070
// Oscillator Source 2
1160
#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000
// MOSC
1161
#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010
// PIOSC
1162
#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020
// PIOSC/4
1163
#define SYSCTL_RCC2_OSCSRC2_30 0x00000030
// LFIOSC
1164
#define SYSCTL_RCC2_OSCSRC2_32 0x00000070
// 32.768 kHz
1165
#define SYSCTL_RCC2_SYSDIV2_S 23
1166
1167
//*****************************************************************************
1168
//
1169
// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
1170
//
1171
//*****************************************************************************
1172
#define SYSCTL_MOSCCTL_OSCRNG 0x00000010
// Oscillator Range
1173
#define SYSCTL_MOSCCTL_PWRDN 0x00000008
// Power Down
1174
#define SYSCTL_MOSCCTL_NOXTAL 0x00000004
// No Crystal Connected
1175
#define SYSCTL_MOSCCTL_MOSCIM 0x00000002
// MOSC Failure Action
1176
#define SYSCTL_MOSCCTL_CVAL 0x00000001
// Clock Validation for MOSC
1177
1178
//*****************************************************************************
1179
//
1180
// The following are defines for the bit fields in the SYSCTL_RSCLKCFG
1181
// register.
1182
//
1183
//*****************************************************************************
1184
#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000
// Memory Timing Register Update
1185
#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000
// New PLLFREQ Accept
1186
#define SYSCTL_RSCLKCFG_ACG 0x20000000
// Auto Clock Gating
1187
#define SYSCTL_RSCLKCFG_USEPLL 0x10000000
// Use PLL
1188
#define SYSCTL_RSCLKCFG_PLLSRC_M \
1189
0x0F000000
// PLL Source
1190
#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC \
1191
0x00000000
// PIOSC is PLL input clock source
1192
#define SYSCTL_RSCLKCFG_PLLSRC_MOSC \
1193
0x03000000
// MOSC is the PLL input clock
1194
// source
1195
#define SYSCTL_RSCLKCFG_OSCSRC_M \
1196
0x00F00000
// Oscillator Source
1197
#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC \
1198
0x00000000
// PIOSC is oscillator source
1199
#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC \
1200
0x00200000
// LFIOSC is oscillator source
1201
#define SYSCTL_RSCLKCFG_OSCSRC_MOSC \
1202
0x00300000
// MOSC is oscillator source
1203
#define SYSCTL_RSCLKCFG_OSCSRC_RTC \
1204
0x00400000
// Hibernation Module RTC
1205
// Oscillator (RTCOSC)
1206
#define SYSCTL_RSCLKCFG_OSYSDIV_M \
1207
0x000FFC00
// Oscillator System Clock Divisor
1208
#define SYSCTL_RSCLKCFG_PSYSDIV_M \
1209
0x000003FF
// PLL System Clock Divisor
1210
#define SYSCTL_RSCLKCFG_OSYSDIV_S \
1211
10
1212
#define SYSCTL_RSCLKCFG_PSYSDIV_S \
1213
0
1214
1215
//*****************************************************************************
1216
//
1217
// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register.
1218
//
1219
//*****************************************************************************
1220
#define SYSCTL_MEMTIM0_EBCHT_M 0x03C00000
// EEPROM Clock High Time
1221
#define SYSCTL_MEMTIM0_EBCHT_0_5 \
1222
0x00000000
// 1/2 system clock period
1223
#define SYSCTL_MEMTIM0_EBCHT_1 0x00400000
// 1 system clock period
1224
#define SYSCTL_MEMTIM0_EBCHT_1_5 \
1225
0x00800000
// 1.5 system clock periods
1226
#define SYSCTL_MEMTIM0_EBCHT_2 0x00C00000
// 2 system clock periods
1227
#define SYSCTL_MEMTIM0_EBCHT_2_5 \
1228
0x01000000
// 2.5 system clock periods
1229
#define SYSCTL_MEMTIM0_EBCHT_3 0x01400000
// 3 system clock periods
1230
#define SYSCTL_MEMTIM0_EBCHT_3_5 \
1231
0x01800000
// 3.5 system clock periods
1232
#define SYSCTL_MEMTIM0_EBCHT_4 0x01C00000
// 4 system clock periods
1233
#define SYSCTL_MEMTIM0_EBCHT_4_5 \
1234
0x02000000
// 4.5 system clock periods
1235
#define SYSCTL_MEMTIM0_EBCE 0x00200000
// EEPROM Bank Clock Edge
1236
#define SYSCTL_MEMTIM0_MB1 0x00100010
// Must be one
1237
#define SYSCTL_MEMTIM0_EWS_M 0x000F0000
// EEPROM Wait States
1238
#define SYSCTL_MEMTIM0_FBCHT_M 0x000003C0
// Flash Bank Clock High Time
1239
#define SYSCTL_MEMTIM0_FBCHT_0_5 \
1240
0x00000000
// 1/2 system clock period
1241
#define SYSCTL_MEMTIM0_FBCHT_1 0x00000040
// 1 system clock period
1242
#define SYSCTL_MEMTIM0_FBCHT_1_5 \
1243
0x00000080
// 1.5 system clock periods
1244
#define SYSCTL_MEMTIM0_FBCHT_2 0x000000C0
// 2 system clock periods
1245
#define SYSCTL_MEMTIM0_FBCHT_2_5 \
1246
0x00000100
// 2.5 system clock periods
1247
#define SYSCTL_MEMTIM0_FBCHT_3 0x00000140
// 3 system clock periods
1248
#define SYSCTL_MEMTIM0_FBCHT_3_5 \
1249
0x00000180
// 3.5 system clock periods
1250
#define SYSCTL_MEMTIM0_FBCHT_4 0x000001C0
// 4 system clock periods
1251
#define SYSCTL_MEMTIM0_FBCHT_4_5 \
1252
0x00000200
// 4.5 system clock periods
1253
#define SYSCTL_MEMTIM0_FBCE 0x00000020
// Flash Bank Clock Edge
1254
#define SYSCTL_MEMTIM0_FWS_M 0x0000000F
// Flash Wait State
1255
#define SYSCTL_MEMTIM0_EWS_S 16
1256
#define SYSCTL_MEMTIM0_FWS_S 0
1257
1258
//*****************************************************************************
1259
//
1260
// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
1261
//
1262
//*****************************************************************************
1263
#define SYSCTL_RCGC0_WDT1 0x10000000
// WDT1 Clock Gating Control
1264
#define SYSCTL_RCGC0_CAN1 0x02000000
// CAN1 Clock Gating Control
1265
#define SYSCTL_RCGC0_CAN0 0x01000000
// CAN0 Clock Gating Control
1266
#define SYSCTL_RCGC0_PWM0 0x00100000
// PWM Clock Gating Control
1267
#define SYSCTL_RCGC0_ADC1 0x00020000
// ADC1 Clock Gating Control
1268
#define SYSCTL_RCGC0_ADC0 0x00010000
// ADC0 Clock Gating Control
1269
#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00
// ADC1 Sample Speed
1270
#define SYSCTL_RCGC0_ADC1SPD_125K \
1271
0x00000000
// 125K samples/second
1272
#define SYSCTL_RCGC0_ADC1SPD_250K \
1273
0x00000400
// 250K samples/second
1274
#define SYSCTL_RCGC0_ADC1SPD_500K \
1275
0x00000800
// 500K samples/second
1276
#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00
// 1M samples/second
1277
#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300
// ADC0 Sample Speed
1278
#define SYSCTL_RCGC0_ADC0SPD_125K \
1279
0x00000000
// 125K samples/second
1280
#define SYSCTL_RCGC0_ADC0SPD_250K \
1281
0x00000100
// 250K samples/second
1282
#define SYSCTL_RCGC0_ADC0SPD_500K \
1283
0x00000200
// 500K samples/second
1284
#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300
// 1M samples/second
1285
#define SYSCTL_RCGC0_HIB 0x00000040
// HIB Clock Gating Control
1286
#define SYSCTL_RCGC0_WDT0 0x00000008
// WDT0 Clock Gating Control
1287
1288
//*****************************************************************************
1289
//
1290
// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
1291
//
1292
//*****************************************************************************
1293
#define SYSCTL_RCGC1_COMP2 0x04000000
// Analog Comparator 2 Clock Gating
1294
#define SYSCTL_RCGC1_COMP1 0x02000000
// Analog Comparator 1 Clock Gating
1295
#define SYSCTL_RCGC1_COMP0 0x01000000
// Analog Comparator 0 Clock Gating
1296
#define SYSCTL_RCGC1_TIMER3 0x00080000
// Timer 3 Clock Gating Control
1297
#define SYSCTL_RCGC1_TIMER2 0x00040000
// Timer 2 Clock Gating Control
1298
#define SYSCTL_RCGC1_TIMER1 0x00020000
// Timer 1 Clock Gating Control
1299
#define SYSCTL_RCGC1_TIMER0 0x00010000
// Timer 0 Clock Gating Control
1300
#define SYSCTL_RCGC1_I2C1 0x00004000
// I2C1 Clock Gating Control
1301
#define SYSCTL_RCGC1_I2C0 0x00001000
// I2C0 Clock Gating Control
1302
#define SYSCTL_RCGC1_QEI1 0x00000200
// QEI1 Clock Gating Control
1303
#define SYSCTL_RCGC1_QEI0 0x00000100
// QEI0 Clock Gating Control
1304
#define SYSCTL_RCGC1_SSI1 0x00000020
// SSI1 Clock Gating Control
1305
#define SYSCTL_RCGC1_SSI0 0x00000010
// SSI0 Clock Gating Control
1306
#define SYSCTL_RCGC1_UART2 0x00000004
// UART2 Clock Gating Control
1307
#define SYSCTL_RCGC1_UART1 0x00000002
// UART1 Clock Gating Control
1308
#define SYSCTL_RCGC1_UART0 0x00000001
// UART0 Clock Gating Control
1309
1310
//*****************************************************************************
1311
//
1312
// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
1313
//
1314
//*****************************************************************************
1315
#define SYSCTL_RCGC2_USB0 0x00010000
// USB0 Clock Gating Control
1316
#define SYSCTL_RCGC2_UDMA 0x00002000
// Micro-DMA Clock Gating Control
1317
#define SYSCTL_RCGC2_GPIOJ 0x00000100
// Port J Clock Gating Control
1318
#define SYSCTL_RCGC2_GPIOH 0x00000080
// Port H Clock Gating Control
1319
#define SYSCTL_RCGC2_GPIOG 0x00000040
// Port G Clock Gating Control
1320
#define SYSCTL_RCGC2_GPIOF 0x00000020
// Port F Clock Gating Control
1321
#define SYSCTL_RCGC2_GPIOE 0x00000010
// Port E Clock Gating Control
1322
#define SYSCTL_RCGC2_GPIOD 0x00000008
// Port D Clock Gating Control
1323
#define SYSCTL_RCGC2_GPIOC 0x00000004
// Port C Clock Gating Control
1324
#define SYSCTL_RCGC2_GPIOB 0x00000002
// Port B Clock Gating Control
1325
#define SYSCTL_RCGC2_GPIOA 0x00000001
// Port A Clock Gating Control
1326
1327
//*****************************************************************************
1328
//
1329
// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
1330
//
1331
//*****************************************************************************
1332
#define SYSCTL_SCGC0_WDT1 0x10000000
// WDT1 Clock Gating Control
1333
#define SYSCTL_SCGC0_CAN1 0x02000000
// CAN1 Clock Gating Control
1334
#define SYSCTL_SCGC0_CAN0 0x01000000
// CAN0 Clock Gating Control
1335
#define SYSCTL_SCGC0_PWM0 0x00100000
// PWM Clock Gating Control
1336
#define SYSCTL_SCGC0_ADC1 0x00020000
// ADC1 Clock Gating Control
1337
#define SYSCTL_SCGC0_ADC0 0x00010000
// ADC0 Clock Gating Control
1338
#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00
// ADC Sample Speed
1339
#define SYSCTL_SCGC0_HIB 0x00000040
// HIB Clock Gating Control
1340
#define SYSCTL_SCGC0_WDT0 0x00000008
// WDT0 Clock Gating Control
1341
1342
//*****************************************************************************
1343
//
1344
// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
1345
//
1346
//*****************************************************************************
1347
#define SYSCTL_SCGC1_COMP2 0x04000000
// Analog Comparator 2 Clock Gating
1348
#define SYSCTL_SCGC1_COMP1 0x02000000
// Analog Comparator 1 Clock Gating
1349
#define SYSCTL_SCGC1_COMP0 0x01000000
// Analog Comparator 0 Clock Gating
1350
#define SYSCTL_SCGC1_TIMER3 0x00080000
// Timer 3 Clock Gating Control
1351
#define SYSCTL_SCGC1_TIMER2 0x00040000
// Timer 2 Clock Gating Control
1352
#define SYSCTL_SCGC1_TIMER1 0x00020000
// Timer 1 Clock Gating Control
1353
#define SYSCTL_SCGC1_TIMER0 0x00010000
// Timer 0 Clock Gating Control
1354
#define SYSCTL_SCGC1_I2C1 0x00004000
// I2C1 Clock Gating Control
1355
#define SYSCTL_SCGC1_I2C0 0x00001000
// I2C0 Clock Gating Control
1356
#define SYSCTL_SCGC1_QEI1 0x00000200
// QEI1 Clock Gating Control
1357
#define SYSCTL_SCGC1_QEI0 0x00000100
// QEI0 Clock Gating Control
1358
#define SYSCTL_SCGC1_SSI1 0x00000020
// SSI1 Clock Gating Control
1359
#define SYSCTL_SCGC1_SSI0 0x00000010
// SSI0 Clock Gating Control
1360
#define SYSCTL_SCGC1_UART2 0x00000004
// UART2 Clock Gating Control
1361
#define SYSCTL_SCGC1_UART1 0x00000002
// UART1 Clock Gating Control
1362
#define SYSCTL_SCGC1_UART0 0x00000001
// UART0 Clock Gating Control
1363
1364
//*****************************************************************************
1365
//
1366
// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
1367
//
1368
//*****************************************************************************
1369
#define SYSCTL_SCGC2_USB0 0x00010000
// USB0 Clock Gating Control
1370
#define SYSCTL_SCGC2_UDMA 0x00002000
// Micro-DMA Clock Gating Control
1371
#define SYSCTL_SCGC2_GPIOJ 0x00000100
// Port J Clock Gating Control
1372
#define SYSCTL_SCGC2_GPIOH 0x00000080
// Port H Clock Gating Control
1373
#define SYSCTL_SCGC2_GPIOG 0x00000040
// Port G Clock Gating Control
1374
#define SYSCTL_SCGC2_GPIOF 0x00000020
// Port F Clock Gating Control
1375
#define SYSCTL_SCGC2_GPIOE 0x00000010
// Port E Clock Gating Control
1376
#define SYSCTL_SCGC2_GPIOD 0x00000008
// Port D Clock Gating Control
1377
#define SYSCTL_SCGC2_GPIOC 0x00000004
// Port C Clock Gating Control
1378
#define SYSCTL_SCGC2_GPIOB 0x00000002
// Port B Clock Gating Control
1379
#define SYSCTL_SCGC2_GPIOA 0x00000001
// Port A Clock Gating Control
1380
1381
//*****************************************************************************
1382
//
1383
// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
1384
//
1385
//*****************************************************************************
1386
#define SYSCTL_DCGC0_WDT1 0x10000000
// WDT1 Clock Gating Control
1387
#define SYSCTL_DCGC0_CAN1 0x02000000
// CAN1 Clock Gating Control
1388
#define SYSCTL_DCGC0_CAN0 0x01000000
// CAN0 Clock Gating Control
1389
#define SYSCTL_DCGC0_PWM0 0x00100000
// PWM Clock Gating Control
1390
#define SYSCTL_DCGC0_ADC1 0x00020000
// ADC1 Clock Gating Control
1391
#define SYSCTL_DCGC0_ADC0 0x00010000
// ADC0 Clock Gating Control
1392
#define SYSCTL_DCGC0_HIB 0x00000040
// HIB Clock Gating Control
1393
#define SYSCTL_DCGC0_WDT0 0x00000008
// WDT0 Clock Gating Control
1394
1395
//*****************************************************************************
1396
//
1397
// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
1398
//
1399
//*****************************************************************************
1400
#define SYSCTL_DCGC1_COMP2 0x04000000
// Analog Comparator 2 Clock Gating
1401
#define SYSCTL_DCGC1_COMP1 0x02000000
// Analog Comparator 1 Clock Gating
1402
#define SYSCTL_DCGC1_COMP0 0x01000000
// Analog Comparator 0 Clock Gating
1403
#define SYSCTL_DCGC1_TIMER3 0x00080000
// Timer 3 Clock Gating Control
1404
#define SYSCTL_DCGC1_TIMER2 0x00040000
// Timer 2 Clock Gating Control
1405
#define SYSCTL_DCGC1_TIMER1 0x00020000
// Timer 1 Clock Gating Control
1406
#define SYSCTL_DCGC1_TIMER0 0x00010000
// Timer 0 Clock Gating Control
1407
#define SYSCTL_DCGC1_I2C1 0x00004000
// I2C1 Clock Gating Control
1408
#define SYSCTL_DCGC1_I2C0 0x00001000
// I2C0 Clock Gating Control
1409
#define SYSCTL_DCGC1_QEI1 0x00000200
// QEI1 Clock Gating Control
1410
#define SYSCTL_DCGC1_QEI0 0x00000100
// QEI0 Clock Gating Control
1411
#define SYSCTL_DCGC1_SSI1 0x00000020
// SSI1 Clock Gating Control
1412
#define SYSCTL_DCGC1_SSI0 0x00000010
// SSI0 Clock Gating Control
1413
#define SYSCTL_DCGC1_UART2 0x00000004
// UART2 Clock Gating Control
1414
#define SYSCTL_DCGC1_UART1 0x00000002
// UART1 Clock Gating Control
1415
#define SYSCTL_DCGC1_UART0 0x00000001
// UART0 Clock Gating Control
1416
1417
//*****************************************************************************
1418
//
1419
// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
1420
//
1421
//*****************************************************************************
1422
#define SYSCTL_DCGC2_USB0 0x00010000
// USB0 Clock Gating Control
1423
#define SYSCTL_DCGC2_UDMA 0x00002000
// Micro-DMA Clock Gating Control
1424
#define SYSCTL_DCGC2_GPIOJ 0x00000100
// Port J Clock Gating Control
1425
#define SYSCTL_DCGC2_GPIOH 0x00000080
// Port H Clock Gating Control
1426
#define SYSCTL_DCGC2_GPIOG 0x00000040
// Port G Clock Gating Control
1427
#define SYSCTL_DCGC2_GPIOF 0x00000020
// Port F Clock Gating Control
1428
#define SYSCTL_DCGC2_GPIOE 0x00000010
// Port E Clock Gating Control
1429
#define SYSCTL_DCGC2_GPIOD 0x00000008
// Port D Clock Gating Control
1430
#define SYSCTL_DCGC2_GPIOC 0x00000004
// Port C Clock Gating Control
1431
#define SYSCTL_DCGC2_GPIOB 0x00000002
// Port B Clock Gating Control
1432
#define SYSCTL_DCGC2_GPIOA 0x00000001
// Port A Clock Gating Control
1433
1434
//*****************************************************************************
1435
//
1436
// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG
1437
// register.
1438
//
1439
//*****************************************************************************
1440
#define SYSCTL_ALTCLKCFG_ALTCLK_M \
1441
0x0000000F
// Alternate Clock Source
1442
#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC \
1443
0x00000000
// PIOSC
1444
#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC \
1445
0x00000003
// Hibernation Module Real-time
1446
// clock output (RTCOSC)
1447
#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC \
1448
0x00000004
// Low-frequency internal
1449
// oscillator (LFIOSC)
1450
1451
//*****************************************************************************
1452
//
1453
// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
1454
// register.
1455
//
1456
//*****************************************************************************
1457
#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000
// Divider Field Override
1458
#define SYSCTL_DSLPCLKCFG_O_M 0x00000070
// Clock Source
1459
#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000
// MOSC
1460
#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010
// PIOSC
1461
#define SYSCTL_DSLPCLKCFG_O_30 0x00000030
// LFIOSC
1462
#define SYSCTL_DSLPCLKCFG_O_32 0x00000070
// 32.768 kHz
1463
#define SYSCTL_DSLPCLKCFG_PIOSCPD \
1464
0x00000002
// PIOSC Power Down Request
1465
#define SYSCTL_DSLPCLKCFG_D_S 23
1466
1467
//*****************************************************************************
1468
//
1469
// The following are defines for the bit fields in the SYSCTL_DSCLKCFG
1470
// register.
1471
//
1472
//*****************************************************************************
1473
#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000
// PIOSC Power Down
1474
#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000
// MOSC Disable Power Down
1475
#define SYSCTL_DSCLKCFG_DSOSCSRC_M \
1476
0x00F00000
// Deep Sleep Oscillator Source
1477
#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC \
1478
0x00000000
// PIOSC
1479
#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC \
1480
0x00200000
// LFIOSC
1481
#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC \
1482
0x00300000
// MOSC
1483
#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC \
1484
0x00400000
// Hibernation Module RTCOSC
1485
#define SYSCTL_DSCLKCFG_DSSYSDIV_M \
1486
0x000003FF
// Deep Sleep Clock Divisor
1487
#define SYSCTL_DSCLKCFG_DSSYSDIV_S \
1488
0
1489
1490
//*****************************************************************************
1491
//
1492
// The following are defines for the bit fields in the SYSCTL_DIVSCLK register.
1493
//
1494
//*****************************************************************************
1495
#define SYSCTL_DIVSCLK_EN 0x80000000
// DIVSCLK Enable
1496
#define SYSCTL_DIVSCLK_SRC_M 0x00030000
// Clock Source
1497
#define SYSCTL_DIVSCLK_SRC_SYSCLK \
1498
0x00000000
// System Clock
1499
#define SYSCTL_DIVSCLK_SRC_PIOSC \
1500
0x00010000
// PIOSC
1501
#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000
// MOSC
1502
#define SYSCTL_DIVSCLK_DIV_M 0x000000FF
// Divisor Value
1503
#define SYSCTL_DIVSCLK_DIV_S 0
1504
1505
//*****************************************************************************
1506
//
1507
// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
1508
//
1509
//*****************************************************************************
1510
#define SYSCTL_SYSPROP_FPU 0x00000001
// FPU Present
1511
1512
//*****************************************************************************
1513
//
1514
// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
1515
// register.
1516
//
1517
//*****************************************************************************
1518
#define SYSCTL_PIOSCCAL_UTEN 0x80000000
// Use User Trim Value
1519
#define SYSCTL_PIOSCCAL_CAL 0x00000200
// Start Calibration
1520
#define SYSCTL_PIOSCCAL_UPDATE 0x00000100
// Update Trim
1521
#define SYSCTL_PIOSCCAL_UT_M 0x0000007F
// User Trim Value
1522
#define SYSCTL_PIOSCCAL_UT_S 0
1523
1524
//*****************************************************************************
1525
//
1526
// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
1527
// register.
1528
//
1529
//*****************************************************************************
1530
#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000
// Default Trim Value
1531
#define SYSCTL_PIOSCSTAT_CR_M 0x00000300
// Calibration Result
1532
#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000
// Calibration has not been
1533
// attempted
1534
#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100
// The last calibration operation
1535
// completed to meet 1% accuracy
1536
#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200
// The last calibration operation
1537
// failed to meet 1% accuracy
1538
#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F
// Calibration Trim Value
1539
#define SYSCTL_PIOSCSTAT_DT_S 16
1540
#define SYSCTL_PIOSCSTAT_CT_S 0
1541
1542
//*****************************************************************************
1543
//
1544
// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
1545
// register.
1546
//
1547
//*****************************************************************************
1548
#define SYSCTL_PLLFREQ0_PLLPWR 0x00800000
// PLL Power
1549
#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00
// PLL M Fractional Value
1550
#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF
// PLL M Integer Value
1551
#define SYSCTL_PLLFREQ0_MFRAC_S 10
1552
#define SYSCTL_PLLFREQ0_MINT_S 0
1553
1554
//*****************************************************************************
1555
//
1556
// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
1557
// register.
1558
//
1559
//*****************************************************************************
1560
#define SYSCTL_PLLFREQ1_Q_M 0x00001F00
// PLL Q Value
1561
#define SYSCTL_PLLFREQ1_N_M 0x0000001F
// PLL N Value
1562
#define SYSCTL_PLLFREQ1_Q_S 8
1563
#define SYSCTL_PLLFREQ1_N_S 0
1564
1565
//*****************************************************************************
1566
//
1567
// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
1568
//
1569
//*****************************************************************************
1570
#define SYSCTL_PLLSTAT_LOCK 0x00000001
// PLL Lock
1571
1572
//*****************************************************************************
1573
//
1574
// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG
1575
// register.
1576
//
1577
//*****************************************************************************
1578
#define SYSCTL_SLPPWRCFG_FLASHPM_M \
1579
0x00000030
// Flash Power Modes
1580
#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \
1581
0x00000000
// Active Mode
1582
#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \
1583
0x00000020
// Low Power Mode
1584
#define SYSCTL_SLPPWRCFG_SRAMPM_M \
1585
0x00000003
// SRAM Power Modes
1586
#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \
1587
0x00000000
// Active Mode
1588
#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \
1589
0x00000001
// Standby Mode
1590
#define SYSCTL_SLPPWRCFG_SRAMPM_LP \
1591
0x00000003
// Low Power Mode
1592
1593
//*****************************************************************************
1594
//
1595
// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG
1596
// register.
1597
//
1598
//*****************************************************************************
1599
#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200
// LDO Sleep Mode
1600
#define SYSCTL_DSLPPWRCFG_TSPD 0x00000100
// Temperature Sense Power Down
1601
#define SYSCTL_DSLPPWRCFG_FLASHPM_M \
1602
0x00000030
// Flash Power Modes
1603
#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \
1604
0x00000000
// Active Mode
1605
#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \
1606
0x00000020
// Low Power Mode
1607
#define SYSCTL_DSLPPWRCFG_SRAMPM_M \
1608
0x00000003
// SRAM Power Modes
1609
#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \
1610
0x00000000
// Active Mode
1611
#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \
1612
0x00000001
// Standby Mode
1613
#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \
1614
0x00000003
// Low Power Mode
1615
1616
//*****************************************************************************
1617
//
1618
// The following are defines for the bit fields in the SYSCTL_DC9 register.
1619
//
1620
//*****************************************************************************
1621
#define SYSCTL_DC9_ADC1DC7 0x00800000
// ADC1 DC7 Present
1622
#define SYSCTL_DC9_ADC1DC6 0x00400000
// ADC1 DC6 Present
1623
#define SYSCTL_DC9_ADC1DC5 0x00200000
// ADC1 DC5 Present
1624
#define SYSCTL_DC9_ADC1DC4 0x00100000
// ADC1 DC4 Present
1625
#define SYSCTL_DC9_ADC1DC3 0x00080000
// ADC1 DC3 Present
1626
#define SYSCTL_DC9_ADC1DC2 0x00040000
// ADC1 DC2 Present
1627
#define SYSCTL_DC9_ADC1DC1 0x00020000
// ADC1 DC1 Present
1628
#define SYSCTL_DC9_ADC1DC0 0x00010000
// ADC1 DC0 Present
1629
#define SYSCTL_DC9_ADC0DC7 0x00000080
// ADC0 DC7 Present
1630
#define SYSCTL_DC9_ADC0DC6 0x00000040
// ADC0 DC6 Present
1631
#define SYSCTL_DC9_ADC0DC5 0x00000020
// ADC0 DC5 Present
1632
#define SYSCTL_DC9_ADC0DC4 0x00000010
// ADC0 DC4 Present
1633
#define SYSCTL_DC9_ADC0DC3 0x00000008
// ADC0 DC3 Present
1634
#define SYSCTL_DC9_ADC0DC2 0x00000004
// ADC0 DC2 Present
1635
#define SYSCTL_DC9_ADC0DC1 0x00000002
// ADC0 DC1 Present
1636
#define SYSCTL_DC9_ADC0DC0 0x00000001
// ADC0 DC0 Present
1637
1638
//*****************************************************************************
1639
//
1640
// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
1641
//
1642
//*****************************************************************************
1643
#define SYSCTL_NVMSTAT_FWB 0x00000001
// 32 Word Flash Write Buffer
1644
// Available
1645
1646
//*****************************************************************************
1647
//
1648
// The following are defines for the bit fields in the SYSCTL_LDOSPCTL
1649
// register.
1650
//
1651
//*****************************************************************************
1652
#define SYSCTL_LDOSPCTL_VADJEN 0x80000000
// Voltage Adjust Enable
1653
#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF
// LDO Output Voltage
1654
#define SYSCTL_LDOSPCTL_VLDO_0_90V \
1655
0x00000012
// 0.90 V
1656
#define SYSCTL_LDOSPCTL_VLDO_0_95V \
1657
0x00000013
// 0.95 V
1658
#define SYSCTL_LDOSPCTL_VLDO_1_00V \
1659
0x00000014
// 1.00 V
1660
#define SYSCTL_LDOSPCTL_VLDO_1_05V \
1661
0x00000015
// 1.05 V
1662
#define SYSCTL_LDOSPCTL_VLDO_1_10V \
1663
0x00000016
// 1.10 V
1664
#define SYSCTL_LDOSPCTL_VLDO_1_15V \
1665
0x00000017
// 1.15 V
1666
#define SYSCTL_LDOSPCTL_VLDO_1_20V \
1667
0x00000018
// 1.20 V
1668
1669
//*****************************************************************************
1670
//
1671
// The following are defines for the bit fields in the SYSCTL_LDODPCTL
1672
// register.
1673
//
1674
//*****************************************************************************
1675
#define SYSCTL_LDODPCTL_VADJEN 0x80000000
// Voltage Adjust Enable
1676
#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF
// LDO Output Voltage
1677
#define SYSCTL_LDODPCTL_VLDO_0_90V \
1678
0x00000012
// 0.90 V
1679
#define SYSCTL_LDODPCTL_VLDO_0_95V \
1680
0x00000013
// 0.95 V
1681
#define SYSCTL_LDODPCTL_VLDO_1_00V \
1682
0x00000014
// 1.00 V
1683
#define SYSCTL_LDODPCTL_VLDO_1_05V \
1684
0x00000015
// 1.05 V
1685
#define SYSCTL_LDODPCTL_VLDO_1_10V \
1686
0x00000016
// 1.10 V
1687
#define SYSCTL_LDODPCTL_VLDO_1_15V \
1688
0x00000017
// 1.15 V
1689
#define SYSCTL_LDODPCTL_VLDO_1_20V \
1690
0x00000018
// 1.20 V
1691
#define SYSCTL_LDODPCTL_VLDO_1_25V \
1692
0x00000019
// 1.25 V
1693
#define SYSCTL_LDODPCTL_VLDO_1_30V \
1694
0x0000001A
// 1.30 V
1695
#define SYSCTL_LDODPCTL_VLDO_1_35V \
1696
0x0000001B
// 1.35 V
1697
1698
//*****************************************************************************
1699
//
1700
// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL
1701
// register.
1702
//
1703
//*****************************************************************************
1704
#define SYSCTL_RESBEHAVCTL_WDOG1_M \
1705
0x000000C0
// Watchdog 1 Reset Operation
1706
#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST \
1707
0x00000080
// Watchdog 1 issues a system
1708
// reset. The application starts
1709
// within 10 us
1710
#define SYSCTL_RESBEHAVCTL_WDOG1_POR \
1711
0x000000C0
// Watchdog 1 issues a simulated
1712
// POR sequence. Application starts
1713
// less than 500 us after
1714
// deassertion (Default)
1715
#define SYSCTL_RESBEHAVCTL_WDOG0_M \
1716
0x00000030
// Watchdog 0 Reset Operation
1717
#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST \
1718
0x00000020
// Watchdog 0 issues a system
1719
// reset. The application starts
1720
// within 10 us
1721
#define SYSCTL_RESBEHAVCTL_WDOG0_POR \
1722
0x00000030
// Watchdog 0 issues a simulated
1723
// POR sequence. Application starts
1724
// less than 500 us after
1725
// deassertion (Default)
1726
#define SYSCTL_RESBEHAVCTL_BOR_M \
1727
0x0000000C
// BOR Reset operation
1728
#define SYSCTL_RESBEHAVCTL_BOR_SYSRST \
1729
0x00000008
// Brown Out Reset issues system
1730
// reset. The application starts
1731
// within 10 us
1732
#define SYSCTL_RESBEHAVCTL_BOR_POR \
1733
0x0000000C
// Brown Out Reset issues a
1734
// simulated POR sequence. The
1735
// application starts less than 500
1736
// us after deassertion (Default)
1737
#define SYSCTL_RESBEHAVCTL_EXTRES_M \
1738
0x00000003
// External RST Pin Operation
1739
#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST \
1740
0x00000002
// External RST assertion issues a
1741
// system reset. The application
1742
// starts within 10 us
1743
#define SYSCTL_RESBEHAVCTL_EXTRES_POR \
1744
0x00000003
// External RST assertion issues a
1745
// simulated POR sequence.
1746
// Application starts less than 500
1747
// us after deassertion (Default)
1748
1749
//*****************************************************************************
1750
//
1751
// The following are defines for the bit fields in the SYSCTL_HSSR register.
1752
//
1753
//*****************************************************************************
1754
#define SYSCTL_HSSR_KEY_M 0xFF000000
// Write Key
1755
#define SYSCTL_HSSR_CDOFF_M 0x00FFFFFF
// Command Descriptor Pointer
1756
#define SYSCTL_HSSR_KEY_S 24
1757
#define SYSCTL_HSSR_CDOFF_S 0
1758
1759
//*****************************************************************************
1760
//
1761
// The following are defines for the bit fields in the SYSCTL_USBPDS register.
1762
//
1763
//*****************************************************************************
1764
#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C
// Memory Array Power Status
1765
#define SYSCTL_USBPDS_MEMSTAT_OFF \
1766
0x00000000
// Array OFF
1767
#define SYSCTL_USBPDS_MEMSTAT_RETAIN \
1768
0x00000004
// SRAM Retention
1769
#define SYSCTL_USBPDS_MEMSTAT_ON \
1770
0x0000000C
// Array On
1771
#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003
// Power Domain Status
1772
#define SYSCTL_USBPDS_PWRSTAT_OFF \
1773
0x00000000
// OFF
1774
#define SYSCTL_USBPDS_PWRSTAT_ON \
1775
0x00000003
// ON
1776
1777
//*****************************************************************************
1778
//
1779
// The following are defines for the bit fields in the SYSCTL_USBMPC register.
1780
//
1781
//*****************************************************************************
1782
#define SYSCTL_USBMPC_PWRCTL_M 0x00000003
// Memory Array Power Control
1783
#define SYSCTL_USBMPC_PWRCTL_OFF \
1784
0x00000000
// Array OFF
1785
#define SYSCTL_USBMPC_PWRCTL_RETAIN \
1786
0x00000001
// SRAM Retention
1787
#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003
// Array On
1788
1789
//*****************************************************************************
1790
//
1791
// The following are defines for the bit fields in the SYSCTL_EMACPDS register.
1792
//
1793
//*****************************************************************************
1794
#define SYSCTL_EMACPDS_MEMSTAT_M \
1795
0x0000000C
// Memory Array Power Status
1796
#define SYSCTL_EMACPDS_MEMSTAT_OFF \
1797
0x00000000
// Array OFF
1798
#define SYSCTL_EMACPDS_MEMSTAT_ON \
1799
0x0000000C
// Array On
1800
#define SYSCTL_EMACPDS_PWRSTAT_M \
1801
0x00000003
// Power Domain Status
1802
#define SYSCTL_EMACPDS_PWRSTAT_OFF \
1803
0x00000000
// OFF
1804
#define SYSCTL_EMACPDS_PWRSTAT_ON \
1805
0x00000003
// ON
1806
1807
//*****************************************************************************
1808
//
1809
// The following are defines for the bit fields in the SYSCTL_EMACMPC register.
1810
//
1811
//*****************************************************************************
1812
#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003
// Memory Array Power Control
1813
#define SYSCTL_EMACMPC_PWRCTL_OFF \
1814
0x00000000
// Array OFF
1815
#define SYSCTL_EMACMPC_PWRCTL_ON \
1816
0x00000003
// Array On
1817
1818
//*****************************************************************************
1819
//
1820
// The following are defines for the bit fields in the SYSCTL_LCDMPC register.
1821
//
1822
//*****************************************************************************
1823
#define SYSCTL_LCDMPC_PWRCTL_M 0x00000003
// Memory Array Power Control
1824
#define SYSCTL_LCDMPC_PWRCTL_OFF \
1825
0x00000000
// Array OFF
1826
#define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003
// Array On
1827
1828
//*****************************************************************************
1829
//
1830
// The following are defines for the bit fields in the SYSCTL_PPWD register.
1831
//
1832
//*****************************************************************************
1833
#define SYSCTL_PPWD_P1 0x00000002
// Watchdog Timer 1 Present
1834
#define SYSCTL_PPWD_P0 0x00000001
// Watchdog Timer 0 Present
1835
1836
//*****************************************************************************
1837
//
1838
// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
1839
//
1840
//*****************************************************************************
1841
#define SYSCTL_PPTIMER_P7 0x00000080
// 16/32-Bit General-Purpose Timer
1842
// 7 Present
1843
#define SYSCTL_PPTIMER_P6 0x00000040
// 16/32-Bit General-Purpose Timer
1844
// 6 Present
1845
#define SYSCTL_PPTIMER_P5 0x00000020
// 16/32-Bit General-Purpose Timer
1846
// 5 Present
1847
#define SYSCTL_PPTIMER_P4 0x00000010
// 16/32-Bit General-Purpose Timer
1848
// 4 Present
1849
#define SYSCTL_PPTIMER_P3 0x00000008
// 16/32-Bit General-Purpose Timer
1850
// 3 Present
1851
#define SYSCTL_PPTIMER_P2 0x00000004
// 16/32-Bit General-Purpose Timer
1852
// 2 Present
1853
#define SYSCTL_PPTIMER_P1 0x00000002
// 16/32-Bit General-Purpose Timer
1854
// 1 Present
1855
#define SYSCTL_PPTIMER_P0 0x00000001
// 16/32-Bit General-Purpose Timer
1856
// 0 Present
1857
1858
//*****************************************************************************
1859
//
1860
// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
1861
//
1862
//*****************************************************************************
1863
#define SYSCTL_PPGPIO_P17 0x00020000
// GPIO Port T Present
1864
#define SYSCTL_PPGPIO_P16 0x00010000
// GPIO Port S Present
1865
#define SYSCTL_PPGPIO_P15 0x00008000
// GPIO Port R Present
1866
#define SYSCTL_PPGPIO_P14 0x00004000
// GPIO Port Q Present
1867
#define SYSCTL_PPGPIO_P13 0x00002000
// GPIO Port P Present
1868
#define SYSCTL_PPGPIO_P12 0x00001000
// GPIO Port N Present
1869
#define SYSCTL_PPGPIO_P11 0x00000800
// GPIO Port M Present
1870
#define SYSCTL_PPGPIO_P10 0x00000400
// GPIO Port L Present
1871
#define SYSCTL_PPGPIO_P9 0x00000200
// GPIO Port K Present
1872
#define SYSCTL_PPGPIO_P8 0x00000100
// GPIO Port J Present
1873
#define SYSCTL_PPGPIO_P7 0x00000080
// GPIO Port H Present
1874
#define SYSCTL_PPGPIO_P6 0x00000040
// GPIO Port G Present
1875
#define SYSCTL_PPGPIO_P5 0x00000020
// GPIO Port F Present
1876
#define SYSCTL_PPGPIO_P4 0x00000010
// GPIO Port E Present
1877
#define SYSCTL_PPGPIO_P3 0x00000008
// GPIO Port D Present
1878
#define SYSCTL_PPGPIO_P2 0x00000004
// GPIO Port C Present
1879
#define SYSCTL_PPGPIO_P1 0x00000002
// GPIO Port B Present
1880
#define SYSCTL_PPGPIO_P0 0x00000001
// GPIO Port A Present
1881
1882
//*****************************************************************************
1883
//
1884
// The following are defines for the bit fields in the SYSCTL_PPDMA register.
1885
//
1886
//*****************************************************************************
1887
#define SYSCTL_PPDMA_P0 0x00000001
// uDMA Module Present
1888
1889
//*****************************************************************************
1890
//
1891
// The following are defines for the bit fields in the SYSCTL_PPEPI register.
1892
//
1893
//*****************************************************************************
1894
#define SYSCTL_PPEPI_P0 0x00000001
// EPI Module Present
1895
1896
//*****************************************************************************
1897
//
1898
// The following are defines for the bit fields in the SYSCTL_PPHIB register.
1899
//
1900
//*****************************************************************************
1901
#define SYSCTL_PPHIB_P0 0x00000001
// Hibernation Module Present
1902
1903
//*****************************************************************************
1904
//
1905
// The following are defines for the bit fields in the SYSCTL_PPUART register.
1906
//
1907
//*****************************************************************************
1908
#define SYSCTL_PPUART_P7 0x00000080
// UART Module 7 Present
1909
#define SYSCTL_PPUART_P6 0x00000040
// UART Module 6 Present
1910
#define SYSCTL_PPUART_P5 0x00000020
// UART Module 5 Present
1911
#define SYSCTL_PPUART_P4 0x00000010
// UART Module 4 Present
1912
#define SYSCTL_PPUART_P3 0x00000008
// UART Module 3 Present
1913
#define SYSCTL_PPUART_P2 0x00000004
// UART Module 2 Present
1914
#define SYSCTL_PPUART_P1 0x00000002
// UART Module 1 Present
1915
#define SYSCTL_PPUART_P0 0x00000001
// UART Module 0 Present
1916
1917
//*****************************************************************************
1918
//
1919
// The following are defines for the bit fields in the SYSCTL_PPSSI register.
1920
//
1921
//*****************************************************************************
1922
#define SYSCTL_PPSSI_P3 0x00000008
// SSI Module 3 Present
1923
#define SYSCTL_PPSSI_P2 0x00000004
// SSI Module 2 Present
1924
#define SYSCTL_PPSSI_P1 0x00000002
// SSI Module 1 Present
1925
#define SYSCTL_PPSSI_P0 0x00000001
// SSI Module 0 Present
1926
1927
//*****************************************************************************
1928
//
1929
// The following are defines for the bit fields in the SYSCTL_PPI2C register.
1930
//
1931
//*****************************************************************************
1932
#define SYSCTL_PPI2C_P9 0x00000200
// I2C Module 9 Present
1933
#define SYSCTL_PPI2C_P8 0x00000100
// I2C Module 8 Present
1934
#define SYSCTL_PPI2C_P7 0x00000080
// I2C Module 7 Present
1935
#define SYSCTL_PPI2C_P6 0x00000040
// I2C Module 6 Present
1936
#define SYSCTL_PPI2C_P5 0x00000020
// I2C Module 5 Present
1937
#define SYSCTL_PPI2C_P4 0x00000010
// I2C Module 4 Present
1938
#define SYSCTL_PPI2C_P3 0x00000008
// I2C Module 3 Present
1939
#define SYSCTL_PPI2C_P2 0x00000004
// I2C Module 2 Present
1940
#define SYSCTL_PPI2C_P1 0x00000002
// I2C Module 1 Present
1941
#define SYSCTL_PPI2C_P0 0x00000001
// I2C Module 0 Present
1942
1943
//*****************************************************************************
1944
//
1945
// The following are defines for the bit fields in the SYSCTL_PPUSB register.
1946
//
1947
//*****************************************************************************
1948
#define SYSCTL_PPUSB_P0 0x00000001
// USB Module Present
1949
1950
//*****************************************************************************
1951
//
1952
// The following are defines for the bit fields in the SYSCTL_PPEPHY register.
1953
//
1954
//*****************************************************************************
1955
#define SYSCTL_PPEPHY_P0 0x00000001
// Ethernet PHY Module Present
1956
1957
//*****************************************************************************
1958
//
1959
// The following are defines for the bit fields in the SYSCTL_PPCAN register.
1960
//
1961
//*****************************************************************************
1962
#define SYSCTL_PPCAN_P1 0x00000002
// CAN Module 1 Present
1963
#define SYSCTL_PPCAN_P0 0x00000001
// CAN Module 0 Present
1964
1965
//*****************************************************************************
1966
//
1967
// The following are defines for the bit fields in the SYSCTL_PPADC register.
1968
//
1969
//*****************************************************************************
1970
#define SYSCTL_PPADC_P1 0x00000002
// ADC Module 1 Present
1971
#define SYSCTL_PPADC_P0 0x00000001
// ADC Module 0 Present
1972
1973
//*****************************************************************************
1974
//
1975
// The following are defines for the bit fields in the SYSCTL_PPACMP register.
1976
//
1977
//*****************************************************************************
1978
#define SYSCTL_PPACMP_P0 0x00000001
// Analog Comparator Module Present
1979
1980
//*****************************************************************************
1981
//
1982
// The following are defines for the bit fields in the SYSCTL_PPPWM register.
1983
//
1984
//*****************************************************************************
1985
#define SYSCTL_PPPWM_P1 0x00000002
// PWM Module 1 Present
1986
#define SYSCTL_PPPWM_P0 0x00000001
// PWM Module 0 Present
1987
1988
//*****************************************************************************
1989
//
1990
// The following are defines for the bit fields in the SYSCTL_PPQEI register.
1991
//
1992
//*****************************************************************************
1993
#define SYSCTL_PPQEI_P1 0x00000002
// QEI Module 1 Present
1994
#define SYSCTL_PPQEI_P0 0x00000001
// QEI Module 0 Present
1995
1996
//*****************************************************************************
1997
//
1998
// The following are defines for the bit fields in the SYSCTL_PPLPC register.
1999
//
2000
//*****************************************************************************
2001
#define SYSCTL_PPLPC_P0 0x00000001
// LPC Module Present
2002
2003
//*****************************************************************************
2004
//
2005
// The following are defines for the bit fields in the SYSCTL_PPPECI register.
2006
//
2007
//*****************************************************************************
2008
#define SYSCTL_PPPECI_P0 0x00000001
// PECI Module Present
2009
2010
//*****************************************************************************
2011
//
2012
// The following are defines for the bit fields in the SYSCTL_PPFAN register.
2013
//
2014
//*****************************************************************************
2015
#define SYSCTL_PPFAN_P0 0x00000001
// FAN Module 0 Present
2016
2017
//*****************************************************************************
2018
//
2019
// The following are defines for the bit fields in the SYSCTL_PPEEPROM
2020
// register.
2021
//
2022
//*****************************************************************************
2023
#define SYSCTL_PPEEPROM_P0 0x00000001
// EEPROM Module Present
2024
2025
//*****************************************************************************
2026
//
2027
// The following are defines for the bit fields in the SYSCTL_PPWTIMER
2028
// register.
2029
//
2030
//*****************************************************************************
2031
#define SYSCTL_PPWTIMER_P5 0x00000020
// 32/64-Bit Wide General-Purpose
2032
// Timer 5 Present
2033
#define SYSCTL_PPWTIMER_P4 0x00000010
// 32/64-Bit Wide General-Purpose
2034
// Timer 4 Present
2035
#define SYSCTL_PPWTIMER_P3 0x00000008
// 32/64-Bit Wide General-Purpose
2036
// Timer 3 Present
2037
#define SYSCTL_PPWTIMER_P2 0x00000004
// 32/64-Bit Wide General-Purpose
2038
// Timer 2 Present
2039
#define SYSCTL_PPWTIMER_P1 0x00000002
// 32/64-Bit Wide General-Purpose
2040
// Timer 1 Present
2041
#define SYSCTL_PPWTIMER_P0 0x00000001
// 32/64-Bit Wide General-Purpose
2042
// Timer 0 Present
2043
2044
//*****************************************************************************
2045
//
2046
// The following are defines for the bit fields in the SYSCTL_PPRTS register.
2047
//
2048
//*****************************************************************************
2049
#define SYSCTL_PPRTS_P0 0x00000001
// RTS Module Present
2050
2051
//*****************************************************************************
2052
//
2053
// The following are defines for the bit fields in the SYSCTL_PPCCM register.
2054
//
2055
//*****************************************************************************
2056
#define SYSCTL_PPCCM_P0 0x00000001
// CRC and Cryptographic Modules
2057
// Present
2058
2059
//*****************************************************************************
2060
//
2061
// The following are defines for the bit fields in the SYSCTL_PPLCD register.
2062
//
2063
//*****************************************************************************
2064
#define SYSCTL_PPLCD_P0 0x00000001
// LCD Module Present
2065
2066
//*****************************************************************************
2067
//
2068
// The following are defines for the bit fields in the SYSCTL_PPOWIRE register.
2069
//
2070
//*****************************************************************************
2071
#define SYSCTL_PPOWIRE_P0 0x00000001
// 1-Wire Module Present
2072
2073
//*****************************************************************************
2074
//
2075
// The following are defines for the bit fields in the SYSCTL_PPEMAC register.
2076
//
2077
//*****************************************************************************
2078
#define SYSCTL_PPEMAC_P0 0x00000001
// Ethernet Controller Module
2079
// Present
2080
2081
//*****************************************************************************
2082
//
2083
// The following are defines for the bit fields in the SYSCTL_PPHIM register.
2084
//
2085
//*****************************************************************************
2086
#define SYSCTL_PPHIM_P0 0x00000001
// HIM Module Present
2087
2088
//*****************************************************************************
2089
//
2090
// The following are defines for the bit fields in the SYSCTL_SRWD register.
2091
//
2092
//*****************************************************************************
2093
#define SYSCTL_SRWD_R1 0x00000002
// Watchdog Timer 1 Software Reset
2094
#define SYSCTL_SRWD_R0 0x00000001
// Watchdog Timer 0 Software Reset
2095
2096
//*****************************************************************************
2097
//
2098
// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
2099
//
2100
//*****************************************************************************
2101
#define SYSCTL_SRTIMER_R7 0x00000080
// 16/32-Bit General-Purpose Timer
2102
// 7 Software Reset
2103
#define SYSCTL_SRTIMER_R6 0x00000040
// 16/32-Bit General-Purpose Timer
2104
// 6 Software Reset
2105
#define SYSCTL_SRTIMER_R5 0x00000020
// 16/32-Bit General-Purpose Timer
2106
// 5 Software Reset
2107
#define SYSCTL_SRTIMER_R4 0x00000010
// 16/32-Bit General-Purpose Timer
2108
// 4 Software Reset
2109
#define SYSCTL_SRTIMER_R3 0x00000008
// 16/32-Bit General-Purpose Timer
2110
// 3 Software Reset
2111
#define SYSCTL_SRTIMER_R2 0x00000004
// 16/32-Bit General-Purpose Timer
2112
// 2 Software Reset
2113
#define SYSCTL_SRTIMER_R1 0x00000002
// 16/32-Bit General-Purpose Timer
2114
// 1 Software Reset
2115
#define SYSCTL_SRTIMER_R0 0x00000001
// 16/32-Bit General-Purpose Timer
2116
// 0 Software Reset
2117
2118
//*****************************************************************************
2119
//
2120
// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
2121
//
2122
//*****************************************************************************
2123
#define SYSCTL_SRGPIO_R17 0x00020000
// GPIO Port T Software Reset
2124
#define SYSCTL_SRGPIO_R16 0x00010000
// GPIO Port S Software Reset
2125
#define SYSCTL_SRGPIO_R15 0x00008000
// GPIO Port R Software Reset
2126
#define SYSCTL_SRGPIO_R14 0x00004000
// GPIO Port Q Software Reset
2127
#define SYSCTL_SRGPIO_R13 0x00002000
// GPIO Port P Software Reset
2128
#define SYSCTL_SRGPIO_R12 0x00001000
// GPIO Port N Software Reset
2129
#define SYSCTL_SRGPIO_R11 0x00000800
// GPIO Port M Software Reset
2130
#define SYSCTL_SRGPIO_R10 0x00000400
// GPIO Port L Software Reset
2131
#define SYSCTL_SRGPIO_R9 0x00000200
// GPIO Port K Software Reset
2132
#define SYSCTL_SRGPIO_R8 0x00000100
// GPIO Port J Software Reset
2133
#define SYSCTL_SRGPIO_R7 0x00000080
// GPIO Port H Software Reset
2134
#define SYSCTL_SRGPIO_R6 0x00000040
// GPIO Port G Software Reset
2135
#define SYSCTL_SRGPIO_R5 0x00000020
// GPIO Port F Software Reset
2136
#define SYSCTL_SRGPIO_R4 0x00000010
// GPIO Port E Software Reset
2137
#define SYSCTL_SRGPIO_R3 0x00000008
// GPIO Port D Software Reset
2138
#define SYSCTL_SRGPIO_R2 0x00000004
// GPIO Port C Software Reset
2139
#define SYSCTL_SRGPIO_R1 0x00000002
// GPIO Port B Software Reset
2140
#define SYSCTL_SRGPIO_R0 0x00000001
// GPIO Port A Software Reset
2141
2142
//*****************************************************************************
2143
//
2144
// The following are defines for the bit fields in the SYSCTL_SRDMA register.
2145
//
2146
//*****************************************************************************
2147
#define SYSCTL_SRDMA_R0 0x00000001
// uDMA Module Software Reset
2148
2149
//*****************************************************************************
2150
//
2151
// The following are defines for the bit fields in the SYSCTL_SREPI register.
2152
//
2153
//*****************************************************************************
2154
#define SYSCTL_SREPI_R0 0x00000001
// EPI Module Software Reset
2155
2156
//*****************************************************************************
2157
//
2158
// The following are defines for the bit fields in the SYSCTL_SRHIB register.
2159
//
2160
//*****************************************************************************
2161
#define SYSCTL_SRHIB_R0 0x00000001
// Hibernation Module Software
2162
// Reset
2163
2164
//*****************************************************************************
2165
//
2166
// The following are defines for the bit fields in the SYSCTL_SRUART register.
2167
//
2168
//*****************************************************************************
2169
#define SYSCTL_SRUART_R7 0x00000080
// UART Module 7 Software Reset
2170
#define SYSCTL_SRUART_R6 0x00000040
// UART Module 6 Software Reset
2171
#define SYSCTL_SRUART_R5 0x00000020
// UART Module 5 Software Reset
2172
#define SYSCTL_SRUART_R4 0x00000010
// UART Module 4 Software Reset
2173
#define SYSCTL_SRUART_R3 0x00000008
// UART Module 3 Software Reset
2174
#define SYSCTL_SRUART_R2 0x00000004
// UART Module 2 Software Reset
2175
#define SYSCTL_SRUART_R1 0x00000002
// UART Module 1 Software Reset
2176
#define SYSCTL_SRUART_R0 0x00000001
// UART Module 0 Software Reset
2177
2178
//*****************************************************************************
2179
//
2180
// The following are defines for the bit fields in the SYSCTL_SRSSI register.
2181
//
2182
//*****************************************************************************
2183
#define SYSCTL_SRSSI_R3 0x00000008
// SSI Module 3 Software Reset
2184
#define SYSCTL_SRSSI_R2 0x00000004
// SSI Module 2 Software Reset
2185
#define SYSCTL_SRSSI_R1 0x00000002
// SSI Module 1 Software Reset
2186
#define SYSCTL_SRSSI_R0 0x00000001
// SSI Module 0 Software Reset
2187
2188
//*****************************************************************************
2189
//
2190
// The following are defines for the bit fields in the SYSCTL_SRI2C register.
2191
//
2192
//*****************************************************************************
2193
#define SYSCTL_SRI2C_R9 0x00000200
// I2C Module 9 Software Reset
2194
#define SYSCTL_SRI2C_R8 0x00000100
// I2C Module 8 Software Reset
2195
#define SYSCTL_SRI2C_R7 0x00000080
// I2C Module 7 Software Reset
2196
#define SYSCTL_SRI2C_R6 0x00000040
// I2C Module 6 Software Reset
2197
#define SYSCTL_SRI2C_R5 0x00000020
// I2C Module 5 Software Reset
2198
#define SYSCTL_SRI2C_R4 0x00000010
// I2C Module 4 Software Reset
2199
#define SYSCTL_SRI2C_R3 0x00000008
// I2C Module 3 Software Reset
2200
#define SYSCTL_SRI2C_R2 0x00000004
// I2C Module 2 Software Reset
2201
#define SYSCTL_SRI2C_R1 0x00000002
// I2C Module 1 Software Reset
2202
#define SYSCTL_SRI2C_R0 0x00000001
// I2C Module 0 Software Reset
2203
2204
//*****************************************************************************
2205
//
2206
// The following are defines for the bit fields in the SYSCTL_SRUSB register.
2207
//
2208
//*****************************************************************************
2209
#define SYSCTL_SRUSB_R0 0x00000001
// USB Module Software Reset
2210
2211
//*****************************************************************************
2212
//
2213
// The following are defines for the bit fields in the SYSCTL_SREPHY register.
2214
//
2215
//*****************************************************************************
2216
#define SYSCTL_SREPHY_R0 0x00000001
// Ethernet PHY Module Software
2217
// Reset
2218
2219
//*****************************************************************************
2220
//
2221
// The following are defines for the bit fields in the SYSCTL_SRCAN register.
2222
//
2223
//*****************************************************************************
2224
#define SYSCTL_SRCAN_R1 0x00000002
// CAN Module 1 Software Reset
2225
#define SYSCTL_SRCAN_R0 0x00000001
// CAN Module 0 Software Reset
2226
2227
//*****************************************************************************
2228
//
2229
// The following are defines for the bit fields in the SYSCTL_SRADC register.
2230
//
2231
//*****************************************************************************
2232
#define SYSCTL_SRADC_R1 0x00000002
// ADC Module 1 Software Reset
2233
#define SYSCTL_SRADC_R0 0x00000001
// ADC Module 0 Software Reset
2234
2235
//*****************************************************************************
2236
//
2237
// The following are defines for the bit fields in the SYSCTL_SRACMP register.
2238
//
2239
//*****************************************************************************
2240
#define SYSCTL_SRACMP_R0 0x00000001
// Analog Comparator Module 0
2241
// Software Reset
2242
2243
//*****************************************************************************
2244
//
2245
// The following are defines for the bit fields in the SYSCTL_SRPWM register.
2246
//
2247
//*****************************************************************************
2248
#define SYSCTL_SRPWM_R1 0x00000002
// PWM Module 1 Software Reset
2249
#define SYSCTL_SRPWM_R0 0x00000001
// PWM Module 0 Software Reset
2250
2251
//*****************************************************************************
2252
//
2253
// The following are defines for the bit fields in the SYSCTL_SRQEI register.
2254
//
2255
//*****************************************************************************
2256
#define SYSCTL_SRQEI_R1 0x00000002
// QEI Module 1 Software Reset
2257
#define SYSCTL_SRQEI_R0 0x00000001
// QEI Module 0 Software Reset
2258
2259
//*****************************************************************************
2260
//
2261
// The following are defines for the bit fields in the SYSCTL_SREEPROM
2262
// register.
2263
//
2264
//*****************************************************************************
2265
#define SYSCTL_SREEPROM_R0 0x00000001
// EEPROM Module Software Reset
2266
2267
//*****************************************************************************
2268
//
2269
// The following are defines for the bit fields in the SYSCTL_SRWTIMER
2270
// register.
2271
//
2272
//*****************************************************************************
2273
#define SYSCTL_SRWTIMER_R5 0x00000020
// 32/64-Bit Wide General-Purpose
2274
// Timer 5 Software Reset
2275
#define SYSCTL_SRWTIMER_R4 0x00000010
// 32/64-Bit Wide General-Purpose
2276
// Timer 4 Software Reset
2277
#define SYSCTL_SRWTIMER_R3 0x00000008
// 32/64-Bit Wide General-Purpose
2278
// Timer 3 Software Reset
2279
#define SYSCTL_SRWTIMER_R2 0x00000004
// 32/64-Bit Wide General-Purpose
2280
// Timer 2 Software Reset
2281
#define SYSCTL_SRWTIMER_R1 0x00000002
// 32/64-Bit Wide General-Purpose
2282
// Timer 1 Software Reset
2283
#define SYSCTL_SRWTIMER_R0 0x00000001
// 32/64-Bit Wide General-Purpose
2284
// Timer 0 Software Reset
2285
2286
//*****************************************************************************
2287
//
2288
// The following are defines for the bit fields in the SYSCTL_SRCCM register.
2289
//
2290
//*****************************************************************************
2291
#define SYSCTL_SRCCM_R0 0x00000001
// CRC and Cryptographic Modules
2292
// Software Reset
2293
2294
//*****************************************************************************
2295
//
2296
// The following are defines for the bit fields in the SYSCTL_SRLCD register.
2297
//
2298
//*****************************************************************************
2299
#define SYSCTL_SRLCD_R0 0x00000001
// LCD Module 0 Software Reset
2300
2301
//*****************************************************************************
2302
//
2303
// The following are defines for the bit fields in the SYSCTL_SROWIRE register.
2304
//
2305
//*****************************************************************************
2306
#define SYSCTL_SROWIRE_R0 0x00000001
// 1-Wire Module Software Reset
2307
2308
//*****************************************************************************
2309
//
2310
// The following are defines for the bit fields in the SYSCTL_SREMAC register.
2311
//
2312
//*****************************************************************************
2313
#define SYSCTL_SREMAC_R0 0x00000001
// Ethernet Controller MAC Module 0
2314
// Software Reset
2315
2316
//*****************************************************************************
2317
//
2318
// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
2319
//
2320
//*****************************************************************************
2321
#define SYSCTL_RCGCWD_R1 0x00000002
// Watchdog Timer 1 Run Mode Clock
2322
// Gating Control
2323
#define SYSCTL_RCGCWD_R0 0x00000001
// Watchdog Timer 0 Run Mode Clock
2324
// Gating Control
2325
2326
//*****************************************************************************
2327
//
2328
// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
2329
// register.
2330
//
2331
//*****************************************************************************
2332
#define SYSCTL_RCGCTIMER_R7 0x00000080
// 16/32-Bit General-Purpose Timer
2333
// 7 Run Mode Clock Gating Control
2334
#define SYSCTL_RCGCTIMER_R6 0x00000040
// 16/32-Bit General-Purpose Timer
2335
// 6 Run Mode Clock Gating Control
2336
#define SYSCTL_RCGCTIMER_R5 0x00000020
// 16/32-Bit General-Purpose Timer
2337
// 5 Run Mode Clock Gating Control
2338
#define SYSCTL_RCGCTIMER_R4 0x00000010
// 16/32-Bit General-Purpose Timer
2339
// 4 Run Mode Clock Gating Control
2340
#define SYSCTL_RCGCTIMER_R3 0x00000008
// 16/32-Bit General-Purpose Timer
2341
// 3 Run Mode Clock Gating Control
2342
#define SYSCTL_RCGCTIMER_R2 0x00000004
// 16/32-Bit General-Purpose Timer
2343
// 2 Run Mode Clock Gating Control
2344
#define SYSCTL_RCGCTIMER_R1 0x00000002
// 16/32-Bit General-Purpose Timer
2345
// 1 Run Mode Clock Gating Control
2346
#define SYSCTL_RCGCTIMER_R0 0x00000001
// 16/32-Bit General-Purpose Timer
2347
// 0 Run Mode Clock Gating Control
2348
2349
//*****************************************************************************
2350
//
2351
// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
2352
// register.
2353
//
2354
//*****************************************************************************
2355
#define SYSCTL_RCGCGPIO_R17 0x00020000
// GPIO Port T Run Mode Clock
2356
// Gating Control
2357
#define SYSCTL_RCGCGPIO_R16 0x00010000
// GPIO Port S Run Mode Clock
2358
// Gating Control
2359
#define SYSCTL_RCGCGPIO_R15 0x00008000
// GPIO Port R Run Mode Clock
2360
// Gating Control
2361
#define SYSCTL_RCGCGPIO_R14 0x00004000
// GPIO Port Q Run Mode Clock
2362
// Gating Control
2363
#define SYSCTL_RCGCGPIO_R13 0x00002000
// GPIO Port P Run Mode Clock
2364
// Gating Control
2365
#define SYSCTL_RCGCGPIO_R12 0x00001000
// GPIO Port N Run Mode Clock
2366
// Gating Control
2367
#define SYSCTL_RCGCGPIO_R11 0x00000800
// GPIO Port M Run Mode Clock
2368
// Gating Control
2369
#define SYSCTL_RCGCGPIO_R10 0x00000400
// GPIO Port L Run Mode Clock
2370
// Gating Control
2371
#define SYSCTL_RCGCGPIO_R9 0x00000200
// GPIO Port K Run Mode Clock
2372
// Gating Control
2373
#define SYSCTL_RCGCGPIO_R8 0x00000100
// GPIO Port J Run Mode Clock
2374
// Gating Control
2375
#define SYSCTL_RCGCGPIO_R7 0x00000080
// GPIO Port H Run Mode Clock
2376
// Gating Control
2377
#define SYSCTL_RCGCGPIO_R6 0x00000040
// GPIO Port G Run Mode Clock
2378
// Gating Control
2379
#define SYSCTL_RCGCGPIO_R5 0x00000020
// GPIO Port F Run Mode Clock
2380
// Gating Control
2381
#define SYSCTL_RCGCGPIO_R4 0x00000010
// GPIO Port E Run Mode Clock
2382
// Gating Control
2383
#define SYSCTL_RCGCGPIO_R3 0x00000008
// GPIO Port D Run Mode Clock
2384
// Gating Control
2385
#define SYSCTL_RCGCGPIO_R2 0x00000004
// GPIO Port C Run Mode Clock
2386
// Gating Control
2387
#define SYSCTL_RCGCGPIO_R1 0x00000002
// GPIO Port B Run Mode Clock
2388
// Gating Control
2389
#define SYSCTL_RCGCGPIO_R0 0x00000001
// GPIO Port A Run Mode Clock
2390
// Gating Control
2391
2392
//*****************************************************************************
2393
//
2394
// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
2395
//
2396
//*****************************************************************************
2397
#define SYSCTL_RCGCDMA_R0 0x00000001
// uDMA Module Run Mode Clock
2398
// Gating Control
2399
2400
//*****************************************************************************
2401
//
2402
// The following are defines for the bit fields in the SYSCTL_RCGCEPI register.
2403
//
2404
//*****************************************************************************
2405
#define SYSCTL_RCGCEPI_R0 0x00000001
// EPI Module Run Mode Clock Gating
2406
// Control
2407
2408
//*****************************************************************************
2409
//
2410
// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
2411
//
2412
//*****************************************************************************
2413
#define SYSCTL_RCGCHIB_R0 0x00000001
// Hibernation Module Run Mode
2414
// Clock Gating Control
2415
2416
//*****************************************************************************
2417
//
2418
// The following are defines for the bit fields in the SYSCTL_RCGCUART
2419
// register.
2420
//
2421
//*****************************************************************************
2422
#define SYSCTL_RCGCUART_R7 0x00000080
// UART Module 7 Run Mode Clock
2423
// Gating Control
2424
#define SYSCTL_RCGCUART_R6 0x00000040
// UART Module 6 Run Mode Clock
2425
// Gating Control
2426
#define SYSCTL_RCGCUART_R5 0x00000020
// UART Module 5 Run Mode Clock
2427
// Gating Control
2428
#define SYSCTL_RCGCUART_R4 0x00000010
// UART Module 4 Run Mode Clock
2429
// Gating Control
2430
#define SYSCTL_RCGCUART_R3 0x00000008
// UART Module 3 Run Mode Clock
2431
// Gating Control
2432
#define SYSCTL_RCGCUART_R2 0x00000004
// UART Module 2 Run Mode Clock
2433
// Gating Control
2434
#define SYSCTL_RCGCUART_R1 0x00000002
// UART Module 1 Run Mode Clock
2435
// Gating Control
2436
#define SYSCTL_RCGCUART_R0 0x00000001
// UART Module 0 Run Mode Clock
2437
// Gating Control
2438
2439
//*****************************************************************************
2440
//
2441
// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
2442
//
2443
//*****************************************************************************
2444
#define SYSCTL_RCGCSSI_R3 0x00000008
// SSI Module 3 Run Mode Clock
2445
// Gating Control
2446
#define SYSCTL_RCGCSSI_R2 0x00000004
// SSI Module 2 Run Mode Clock
2447
// Gating Control
2448
#define SYSCTL_RCGCSSI_R1 0x00000002
// SSI Module 1 Run Mode Clock
2449
// Gating Control
2450
#define SYSCTL_RCGCSSI_R0 0x00000001
// SSI Module 0 Run Mode Clock
2451
// Gating Control
2452
2453
//*****************************************************************************
2454
//
2455
// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
2456
//
2457
//*****************************************************************************
2458
#define SYSCTL_RCGCI2C_R9 0x00000200
// I2C Module 9 Run Mode Clock
2459
// Gating Control
2460
#define SYSCTL_RCGCI2C_R8 0x00000100
// I2C Module 8 Run Mode Clock
2461
// Gating Control
2462
#define SYSCTL_RCGCI2C_R7 0x00000080
// I2C Module 7 Run Mode Clock
2463
// Gating Control
2464
#define SYSCTL_RCGCI2C_R6 0x00000040
// I2C Module 6 Run Mode Clock
2465
// Gating Control
2466
#define SYSCTL_RCGCI2C_R5 0x00000020
// I2C Module 5 Run Mode Clock
2467
// Gating Control
2468
#define SYSCTL_RCGCI2C_R4 0x00000010
// I2C Module 4 Run Mode Clock
2469
// Gating Control
2470
#define SYSCTL_RCGCI2C_R3 0x00000008
// I2C Module 3 Run Mode Clock
2471
// Gating Control
2472
#define SYSCTL_RCGCI2C_R2 0x00000004
// I2C Module 2 Run Mode Clock
2473
// Gating Control
2474
#define SYSCTL_RCGCI2C_R1 0x00000002
// I2C Module 1 Run Mode Clock
2475
// Gating Control
2476
#define SYSCTL_RCGCI2C_R0 0x00000001
// I2C Module 0 Run Mode Clock
2477
// Gating Control
2478
2479
//*****************************************************************************
2480
//
2481
// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
2482
//
2483
//*****************************************************************************
2484
#define SYSCTL_RCGCUSB_R0 0x00000001
// USB Module Run Mode Clock Gating
2485
// Control
2486
2487
//*****************************************************************************
2488
//
2489
// The following are defines for the bit fields in the SYSCTL_RCGCEPHY
2490
// register.
2491
//
2492
//*****************************************************************************
2493
#define SYSCTL_RCGCEPHY_R0 0x00000001
// Ethernet PHY Module Run Mode
2494
// Clock Gating Control
2495
2496
//*****************************************************************************
2497
//
2498
// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
2499
//
2500
//*****************************************************************************
2501
#define SYSCTL_RCGCCAN_R1 0x00000002
// CAN Module 1 Run Mode Clock
2502
// Gating Control
2503
#define SYSCTL_RCGCCAN_R0 0x00000001
// CAN Module 0 Run Mode Clock
2504
// Gating Control
2505
2506
//*****************************************************************************
2507
//
2508
// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
2509
//
2510
//*****************************************************************************
2511
#define SYSCTL_RCGCADC_R1 0x00000002
// ADC Module 1 Run Mode Clock
2512
// Gating Control
2513
#define SYSCTL_RCGCADC_R0 0x00000001
// ADC Module 0 Run Mode Clock
2514
// Gating Control
2515
2516
//*****************************************************************************
2517
//
2518
// The following are defines for the bit fields in the SYSCTL_RCGCACMP
2519
// register.
2520
//
2521
//*****************************************************************************
2522
#define SYSCTL_RCGCACMP_R0 0x00000001
// Analog Comparator Module 0 Run
2523
// Mode Clock Gating Control
2524
2525
//*****************************************************************************
2526
//
2527
// The following are defines for the bit fields in the SYSCTL_RCGCPWM register.
2528
//
2529
//*****************************************************************************
2530
#define SYSCTL_RCGCPWM_R1 0x00000002
// PWM Module 1 Run Mode Clock
2531
// Gating Control
2532
#define SYSCTL_RCGCPWM_R0 0x00000001
// PWM Module 0 Run Mode Clock
2533
// Gating Control
2534
2535
//*****************************************************************************
2536
//
2537
// The following are defines for the bit fields in the SYSCTL_RCGCQEI register.
2538
//
2539
//*****************************************************************************
2540
#define SYSCTL_RCGCQEI_R1 0x00000002
// QEI Module 1 Run Mode Clock
2541
// Gating Control
2542
#define SYSCTL_RCGCQEI_R0 0x00000001
// QEI Module 0 Run Mode Clock
2543
// Gating Control
2544
2545
//*****************************************************************************
2546
//
2547
// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
2548
// register.
2549
//
2550
//*****************************************************************************
2551
#define SYSCTL_RCGCEEPROM_R0 0x00000001
// EEPROM Module Run Mode Clock
2552
// Gating Control
2553
2554
//*****************************************************************************
2555
//
2556
// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
2557
// register.
2558
//
2559
//*****************************************************************************
2560
#define SYSCTL_RCGCWTIMER_R5 0x00000020
// 32/64-Bit Wide General-Purpose
2561
// Timer 5 Run Mode Clock Gating
2562
// Control
2563
#define SYSCTL_RCGCWTIMER_R4 0x00000010
// 32/64-Bit Wide General-Purpose
2564
// Timer 4 Run Mode Clock Gating
2565
// Control
2566
#define SYSCTL_RCGCWTIMER_R3 0x00000008
// 32/64-Bit Wide General-Purpose
2567
// Timer 3 Run Mode Clock Gating
2568
// Control
2569
#define SYSCTL_RCGCWTIMER_R2 0x00000004
// 32/64-Bit Wide General-Purpose
2570
// Timer 2 Run Mode Clock Gating
2571
// Control
2572
#define SYSCTL_RCGCWTIMER_R1 0x00000002
// 32/64-Bit Wide General-Purpose
2573
// Timer 1 Run Mode Clock Gating
2574
// Control
2575
#define SYSCTL_RCGCWTIMER_R0 0x00000001
// 32/64-Bit Wide General-Purpose
2576
// Timer 0 Run Mode Clock Gating
2577
// Control
2578
2579
//*****************************************************************************
2580
//
2581
// The following are defines for the bit fields in the SYSCTL_RCGCCCM register.
2582
//
2583
//*****************************************************************************
2584
#define SYSCTL_RCGCCCM_R0 0x00000001
// CRC and Cryptographic Modules
2585
// Run Mode Clock Gating Control
2586
2587
//*****************************************************************************
2588
//
2589
// The following are defines for the bit fields in the SYSCTL_RCGCLCD register.
2590
//
2591
//*****************************************************************************
2592
#define SYSCTL_RCGCLCD_R0 0x00000001
// LCD Controller Module 0 Run Mode
2593
// Clock Gating Control
2594
2595
//*****************************************************************************
2596
//
2597
// The following are defines for the bit fields in the SYSCTL_RCGCOWIRE
2598
// register.
2599
//
2600
//*****************************************************************************
2601
#define SYSCTL_RCGCOWIRE_R0 0x00000001
// 1-Wire Module 0 Run Mode Clock
2602
// Gating Control
2603
2604
//*****************************************************************************
2605
//
2606
// The following are defines for the bit fields in the SYSCTL_RCGCEMAC
2607
// register.
2608
//
2609
//*****************************************************************************
2610
#define SYSCTL_RCGCEMAC_R0 0x00000001
// Ethernet MAC Module 0 Run Mode
2611
// Clock Gating Control
2612
2613
//*****************************************************************************
2614
//
2615
// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
2616
//
2617
//*****************************************************************************
2618
#define SYSCTL_SCGCWD_S1 0x00000002
// Watchdog Timer 1 Sleep Mode
2619
// Clock Gating Control
2620
#define SYSCTL_SCGCWD_S0 0x00000001
// Watchdog Timer 0 Sleep Mode
2621
// Clock Gating Control
2622
2623
//*****************************************************************************
2624
//
2625
// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
2626
// register.
2627
//
2628
//*****************************************************************************
2629
#define SYSCTL_SCGCTIMER_S7 0x00000080
// 16/32-Bit General-Purpose Timer
2630
// 7 Sleep Mode Clock Gating
2631
// Control
2632
#define SYSCTL_SCGCTIMER_S6 0x00000040
// 16/32-Bit General-Purpose Timer
2633
// 6 Sleep Mode Clock Gating
2634
// Control
2635
#define SYSCTL_SCGCTIMER_S5 0x00000020
// 16/32-Bit General-Purpose Timer
2636
// 5 Sleep Mode Clock Gating
2637
// Control
2638
#define SYSCTL_SCGCTIMER_S4 0x00000010
// 16/32-Bit General-Purpose Timer
2639
// 4 Sleep Mode Clock Gating
2640
// Control
2641
#define SYSCTL_SCGCTIMER_S3 0x00000008
// 16/32-Bit General-Purpose Timer
2642
// 3 Sleep Mode Clock Gating
2643
// Control
2644
#define SYSCTL_SCGCTIMER_S2 0x00000004
// 16/32-Bit General-Purpose Timer
2645
// 2 Sleep Mode Clock Gating
2646
// Control
2647
#define SYSCTL_SCGCTIMER_S1 0x00000002
// 16/32-Bit General-Purpose Timer
2648
// 1 Sleep Mode Clock Gating
2649
// Control
2650
#define SYSCTL_SCGCTIMER_S0 0x00000001
// 16/32-Bit General-Purpose Timer
2651
// 0 Sleep Mode Clock Gating
2652
// Control
2653
2654
//*****************************************************************************
2655
//
2656
// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
2657
// register.
2658
//
2659
//*****************************************************************************
2660
#define SYSCTL_SCGCGPIO_S17 0x00020000
// GPIO Port T Sleep Mode Clock
2661
// Gating Control
2662
#define SYSCTL_SCGCGPIO_S16 0x00010000
// GPIO Port S Sleep Mode Clock
2663
// Gating Control
2664
#define SYSCTL_SCGCGPIO_S15 0x00008000
// GPIO Port R Sleep Mode Clock
2665
// Gating Control
2666
#define SYSCTL_SCGCGPIO_S14 0x00004000
// GPIO Port Q Sleep Mode Clock
2667
// Gating Control
2668
#define SYSCTL_SCGCGPIO_S13 0x00002000
// GPIO Port P Sleep Mode Clock
2669
// Gating Control
2670
#define SYSCTL_SCGCGPIO_S12 0x00001000
// GPIO Port N Sleep Mode Clock
2671
// Gating Control
2672
#define SYSCTL_SCGCGPIO_S11 0x00000800
// GPIO Port M Sleep Mode Clock
2673
// Gating Control
2674
#define SYSCTL_SCGCGPIO_S10 0x00000400
// GPIO Port L Sleep Mode Clock
2675
// Gating Control
2676
#define SYSCTL_SCGCGPIO_S9 0x00000200
// GPIO Port K Sleep Mode Clock
2677
// Gating Control
2678
#define SYSCTL_SCGCGPIO_S8 0x00000100
// GPIO Port J Sleep Mode Clock
2679
// Gating Control
2680
#define SYSCTL_SCGCGPIO_S7 0x00000080
// GPIO Port H Sleep Mode Clock
2681
// Gating Control
2682
#define SYSCTL_SCGCGPIO_S6 0x00000040
// GPIO Port G Sleep Mode Clock
2683
// Gating Control
2684
#define SYSCTL_SCGCGPIO_S5 0x00000020
// GPIO Port F Sleep Mode Clock
2685
// Gating Control
2686
#define SYSCTL_SCGCGPIO_S4 0x00000010
// GPIO Port E Sleep Mode Clock
2687
// Gating Control
2688
#define SYSCTL_SCGCGPIO_S3 0x00000008
// GPIO Port D Sleep Mode Clock
2689
// Gating Control
2690
#define SYSCTL_SCGCGPIO_S2 0x00000004
// GPIO Port C Sleep Mode Clock
2691
// Gating Control
2692
#define SYSCTL_SCGCGPIO_S1 0x00000002
// GPIO Port B Sleep Mode Clock
2693
// Gating Control
2694
#define SYSCTL_SCGCGPIO_S0 0x00000001
// GPIO Port A Sleep Mode Clock
2695
// Gating Control
2696
2697
//*****************************************************************************
2698
//
2699
// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
2700
//
2701
//*****************************************************************************
2702
#define SYSCTL_SCGCDMA_S0 0x00000001
// uDMA Module Sleep Mode Clock
2703
// Gating Control
2704
2705
//*****************************************************************************
2706
//
2707
// The following are defines for the bit fields in the SYSCTL_SCGCEPI register.
2708
//
2709
//*****************************************************************************
2710
#define SYSCTL_SCGCEPI_S0 0x00000001
// EPI Module Sleep Mode Clock
2711
// Gating Control
2712
2713
//*****************************************************************************
2714
//
2715
// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
2716
//
2717
//*****************************************************************************
2718
#define SYSCTL_SCGCHIB_S0 0x00000001
// Hibernation Module Sleep Mode
2719
// Clock Gating Control
2720
2721
//*****************************************************************************
2722
//
2723
// The following are defines for the bit fields in the SYSCTL_SCGCUART
2724
// register.
2725
//
2726
//*****************************************************************************
2727
#define SYSCTL_SCGCUART_S7 0x00000080
// UART Module 7 Sleep Mode Clock
2728
// Gating Control
2729
#define SYSCTL_SCGCUART_S6 0x00000040
// UART Module 6 Sleep Mode Clock
2730
// Gating Control
2731
#define SYSCTL_SCGCUART_S5 0x00000020
// UART Module 5 Sleep Mode Clock
2732
// Gating Control
2733
#define SYSCTL_SCGCUART_S4 0x00000010
// UART Module 4 Sleep Mode Clock
2734
// Gating Control
2735
#define SYSCTL_SCGCUART_S3 0x00000008
// UART Module 3 Sleep Mode Clock
2736
// Gating Control
2737
#define SYSCTL_SCGCUART_S2 0x00000004
// UART Module 2 Sleep Mode Clock
2738
// Gating Control
2739
#define SYSCTL_SCGCUART_S1 0x00000002
// UART Module 1 Sleep Mode Clock
2740
// Gating Control
2741
#define SYSCTL_SCGCUART_S0 0x00000001
// UART Module 0 Sleep Mode Clock
2742
// Gating Control
2743
2744
//*****************************************************************************
2745
//
2746
// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
2747
//
2748
//*****************************************************************************
2749
#define SYSCTL_SCGCSSI_S3 0x00000008
// SSI Module 3 Sleep Mode Clock
2750
// Gating Control
2751
#define SYSCTL_SCGCSSI_S2 0x00000004
// SSI Module 2 Sleep Mode Clock
2752
// Gating Control
2753
#define SYSCTL_SCGCSSI_S1 0x00000002
// SSI Module 1 Sleep Mode Clock
2754
// Gating Control
2755
#define SYSCTL_SCGCSSI_S0 0x00000001
// SSI Module 0 Sleep Mode Clock
2756
// Gating Control
2757
2758
//*****************************************************************************
2759
//
2760
// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
2761
//
2762
//*****************************************************************************
2763
#define SYSCTL_SCGCI2C_S9 0x00000200
// I2C Module 9 Sleep Mode Clock
2764
// Gating Control
2765
#define SYSCTL_SCGCI2C_S8 0x00000100
// I2C Module 8 Sleep Mode Clock
2766
// Gating Control
2767
#define SYSCTL_SCGCI2C_S7 0x00000080
// I2C Module 7 Sleep Mode Clock
2768
// Gating Control
2769
#define SYSCTL_SCGCI2C_S6 0x00000040
// I2C Module 6 Sleep Mode Clock
2770
// Gating Control
2771
#define SYSCTL_SCGCI2C_S5 0x00000020
// I2C Module 5 Sleep Mode Clock
2772
// Gating Control
2773
#define SYSCTL_SCGCI2C_S4 0x00000010
// I2C Module 4 Sleep Mode Clock
2774
// Gating Control
2775
#define SYSCTL_SCGCI2C_S3 0x00000008
// I2C Module 3 Sleep Mode Clock
2776
// Gating Control
2777
#define SYSCTL_SCGCI2C_S2 0x00000004
// I2C Module 2 Sleep Mode Clock
2778
// Gating Control
2779
#define SYSCTL_SCGCI2C_S1 0x00000002
// I2C Module 1 Sleep Mode Clock
2780
// Gating Control
2781
#define SYSCTL_SCGCI2C_S0 0x00000001
// I2C Module 0 Sleep Mode Clock
2782
// Gating Control
2783
2784
//*****************************************************************************
2785
//
2786
// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
2787
//
2788
//*****************************************************************************
2789
#define SYSCTL_SCGCUSB_S0 0x00000001
// USB Module Sleep Mode Clock
2790
// Gating Control
2791
2792
//*****************************************************************************
2793
//
2794
// The following are defines for the bit fields in the SYSCTL_SCGCEPHY
2795
// register.
2796
//
2797
//*****************************************************************************
2798
#define SYSCTL_SCGCEPHY_S0 0x00000001
// PHY Module Sleep Mode Clock
2799
// Gating Control
2800
2801
//*****************************************************************************
2802
//
2803
// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
2804
//
2805
//*****************************************************************************
2806
#define SYSCTL_SCGCCAN_S1 0x00000002
// CAN Module 1 Sleep Mode Clock
2807
// Gating Control
2808
#define SYSCTL_SCGCCAN_S0 0x00000001
// CAN Module 0 Sleep Mode Clock
2809
// Gating Control
2810
2811
//*****************************************************************************
2812
//
2813
// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
2814
//
2815
//*****************************************************************************
2816
#define SYSCTL_SCGCADC_S1 0x00000002
// ADC Module 1 Sleep Mode Clock
2817
// Gating Control
2818
#define SYSCTL_SCGCADC_S0 0x00000001
// ADC Module 0 Sleep Mode Clock
2819
// Gating Control
2820
2821
//*****************************************************************************
2822
//
2823
// The following are defines for the bit fields in the SYSCTL_SCGCACMP
2824
// register.
2825
//
2826
//*****************************************************************************
2827
#define SYSCTL_SCGCACMP_S0 0x00000001
// Analog Comparator Module 0 Sleep
2828
// Mode Clock Gating Control
2829
2830
//*****************************************************************************
2831
//
2832
// The following are defines for the bit fields in the SYSCTL_SCGCPWM register.
2833
//
2834
//*****************************************************************************
2835
#define SYSCTL_SCGCPWM_S1 0x00000002
// PWM Module 1 Sleep Mode Clock
2836
// Gating Control
2837
#define SYSCTL_SCGCPWM_S0 0x00000001
// PWM Module 0 Sleep Mode Clock
2838
// Gating Control
2839
2840
//*****************************************************************************
2841
//
2842
// The following are defines for the bit fields in the SYSCTL_SCGCQEI register.
2843
//
2844
//*****************************************************************************
2845
#define SYSCTL_SCGCQEI_S1 0x00000002
// QEI Module 1 Sleep Mode Clock
2846
// Gating Control
2847
#define SYSCTL_SCGCQEI_S0 0x00000001
// QEI Module 0 Sleep Mode Clock
2848
// Gating Control
2849
2850
//*****************************************************************************
2851
//
2852
// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
2853
// register.
2854
//
2855
//*****************************************************************************
2856
#define SYSCTL_SCGCEEPROM_S0 0x00000001
// EEPROM Module Sleep Mode Clock
2857
// Gating Control
2858
2859
//*****************************************************************************
2860
//
2861
// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
2862
// register.
2863
//
2864
//*****************************************************************************
2865
#define SYSCTL_SCGCWTIMER_S5 0x00000020
// 32/64-Bit Wide General-Purpose
2866
// Timer 5 Sleep Mode Clock Gating
2867
// Control
2868
#define SYSCTL_SCGCWTIMER_S4 0x00000010
// 32/64-Bit Wide General-Purpose
2869
// Timer 4 Sleep Mode Clock Gating
2870
// Control
2871
#define SYSCTL_SCGCWTIMER_S3 0x00000008
// 32/64-Bit Wide General-Purpose
2872
// Timer 3 Sleep Mode Clock Gating
2873
// Control
2874
#define SYSCTL_SCGCWTIMER_S2 0x00000004
// 32/64-Bit Wide General-Purpose
2875
// Timer 2 Sleep Mode Clock Gating
2876
// Control
2877
#define SYSCTL_SCGCWTIMER_S1 0x00000002
// 32/64-Bit Wide General-Purpose
2878
// Timer 1 Sleep Mode Clock Gating
2879
// Control
2880
#define SYSCTL_SCGCWTIMER_S0 0x00000001
// 32/64-Bit Wide General-Purpose
2881
// Timer 0 Sleep Mode Clock Gating
2882
// Control
2883
2884
//*****************************************************************************
2885
//
2886
// The following are defines for the bit fields in the SYSCTL_SCGCCCM register.
2887
//
2888
//*****************************************************************************
2889
#define SYSCTL_SCGCCCM_S0 0x00000001
// CRC and Cryptographic Modules
2890
// Sleep Mode Clock Gating Control
2891
2892
//*****************************************************************************
2893
//
2894
// The following are defines for the bit fields in the SYSCTL_SCGCLCD register.
2895
//
2896
//*****************************************************************************
2897
#define SYSCTL_SCGCLCD_S0 0x00000001
// LCD Controller Module 0 Sleep
2898
// Mode Clock Gating Control
2899
2900
//*****************************************************************************
2901
//
2902
// The following are defines for the bit fields in the SYSCTL_SCGCOWIRE
2903
// register.
2904
//
2905
//*****************************************************************************
2906
#define SYSCTL_SCGCOWIRE_S0 0x00000001
// 1-Wire Module 0 Sleep Mode Clock
2907
// Gating Control
2908
2909
//*****************************************************************************
2910
//
2911
// The following are defines for the bit fields in the SYSCTL_SCGCEMAC
2912
// register.
2913
//
2914
//*****************************************************************************
2915
#define SYSCTL_SCGCEMAC_S0 0x00000001
// Ethernet MAC Module 0 Sleep Mode
2916
// Clock Gating Control
2917
2918
//*****************************************************************************
2919
//
2920
// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
2921
//
2922
//*****************************************************************************
2923
#define SYSCTL_DCGCWD_D1 0x00000002
// Watchdog Timer 1 Deep-Sleep Mode
2924
// Clock Gating Control
2925
#define SYSCTL_DCGCWD_D0 0x00000001
// Watchdog Timer 0 Deep-Sleep Mode
2926
// Clock Gating Control
2927
2928
//*****************************************************************************
2929
//
2930
// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
2931
// register.
2932
//
2933
//*****************************************************************************
2934
#define SYSCTL_DCGCTIMER_D7 0x00000080
// 16/32-Bit General-Purpose Timer
2935
// 7 Deep-Sleep Mode Clock Gating
2936
// Control
2937
#define SYSCTL_DCGCTIMER_D6 0x00000040
// 16/32-Bit General-Purpose Timer
2938
// 6 Deep-Sleep Mode Clock Gating
2939
// Control
2940
#define SYSCTL_DCGCTIMER_D5 0x00000020
// 16/32-Bit General-Purpose Timer
2941
// 5 Deep-Sleep Mode Clock Gating
2942
// Control
2943
#define SYSCTL_DCGCTIMER_D4 0x00000010
// 16/32-Bit General-Purpose Timer
2944
// 4 Deep-Sleep Mode Clock Gating
2945
// Control
2946
#define SYSCTL_DCGCTIMER_D3 0x00000008
// 16/32-Bit General-Purpose Timer
2947
// 3 Deep-Sleep Mode Clock Gating
2948
// Control
2949
#define SYSCTL_DCGCTIMER_D2 0x00000004
// 16/32-Bit General-Purpose Timer
2950
// 2 Deep-Sleep Mode Clock Gating
2951
// Control
2952
#define SYSCTL_DCGCTIMER_D1 0x00000002
// 16/32-Bit General-Purpose Timer
2953
// 1 Deep-Sleep Mode Clock Gating
2954
// Control
2955
#define SYSCTL_DCGCTIMER_D0 0x00000001
// 16/32-Bit General-Purpose Timer
2956
// 0 Deep-Sleep Mode Clock Gating
2957
// Control
2958
2959
//*****************************************************************************
2960
//
2961
// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
2962
// register.
2963
//
2964
//*****************************************************************************
2965
#define SYSCTL_DCGCGPIO_D17 0x00020000
// GPIO Port T Deep-Sleep Mode
2966
// Clock Gating Control
2967
#define SYSCTL_DCGCGPIO_D16 0x00010000
// GPIO Port S Deep-Sleep Mode
2968
// Clock Gating Control
2969
#define SYSCTL_DCGCGPIO_D15 0x00008000
// GPIO Port R Deep-Sleep Mode
2970
// Clock Gating Control
2971
#define SYSCTL_DCGCGPIO_D14 0x00004000
// GPIO Port Q Deep-Sleep Mode
2972
// Clock Gating Control
2973
#define SYSCTL_DCGCGPIO_D13 0x00002000
// GPIO Port P Deep-Sleep Mode
2974
// Clock Gating Control
2975
#define SYSCTL_DCGCGPIO_D12 0x00001000
// GPIO Port N Deep-Sleep Mode
2976
// Clock Gating Control
2977
#define SYSCTL_DCGCGPIO_D11 0x00000800
// GPIO Port M Deep-Sleep Mode
2978
// Clock Gating Control
2979
#define SYSCTL_DCGCGPIO_D10 0x00000400
// GPIO Port L Deep-Sleep Mode
2980
// Clock Gating Control
2981
#define SYSCTL_DCGCGPIO_D9 0x00000200
// GPIO Port K Deep-Sleep Mode
2982
// Clock Gating Control
2983
#define SYSCTL_DCGCGPIO_D8 0x00000100
// GPIO Port J Deep-Sleep Mode
2984
// Clock Gating Control
2985
#define SYSCTL_DCGCGPIO_D7 0x00000080
// GPIO Port H Deep-Sleep Mode
2986
// Clock Gating Control
2987
#define SYSCTL_DCGCGPIO_D6 0x00000040
// GPIO Port G Deep-Sleep Mode
2988
// Clock Gating Control
2989
#define SYSCTL_DCGCGPIO_D5 0x00000020
// GPIO Port F Deep-Sleep Mode
2990
// Clock Gating Control
2991
#define SYSCTL_DCGCGPIO_D4 0x00000010
// GPIO Port E Deep-Sleep Mode
2992
// Clock Gating Control
2993
#define SYSCTL_DCGCGPIO_D3 0x00000008
// GPIO Port D Deep-Sleep Mode
2994
// Clock Gating Control
2995
#define SYSCTL_DCGCGPIO_D2 0x00000004
// GPIO Port C Deep-Sleep Mode
2996
// Clock Gating Control
2997
#define SYSCTL_DCGCGPIO_D1 0x00000002
// GPIO Port B Deep-Sleep Mode
2998
// Clock Gating Control
2999
#define SYSCTL_DCGCGPIO_D0 0x00000001
// GPIO Port A Deep-Sleep Mode
3000
// Clock Gating Control
3001
3002
//*****************************************************************************
3003
//
3004
// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
3005
//
3006
//*****************************************************************************
3007
#define SYSCTL_DCGCDMA_D0 0x00000001
// uDMA Module Deep-Sleep Mode
3008
// Clock Gating Control
3009
3010
//*****************************************************************************
3011
//
3012
// The following are defines for the bit fields in the SYSCTL_DCGCEPI register.
3013
//
3014
//*****************************************************************************
3015
#define SYSCTL_DCGCEPI_D0 0x00000001
// EPI Module Deep-Sleep Mode Clock
3016
// Gating Control
3017
3018
//*****************************************************************************
3019
//
3020
// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
3021
//
3022
//*****************************************************************************
3023
#define SYSCTL_DCGCHIB_D0 0x00000001
// Hibernation Module Deep-Sleep
3024
// Mode Clock Gating Control
3025
3026
//*****************************************************************************
3027
//
3028
// The following are defines for the bit fields in the SYSCTL_DCGCUART
3029
// register.
3030
//
3031
//*****************************************************************************
3032
#define SYSCTL_DCGCUART_D7 0x00000080
// UART Module 7 Deep-Sleep Mode
3033
// Clock Gating Control
3034
#define SYSCTL_DCGCUART_D6 0x00000040
// UART Module 6 Deep-Sleep Mode
3035
// Clock Gating Control
3036
#define SYSCTL_DCGCUART_D5 0x00000020
// UART Module 5 Deep-Sleep Mode
3037
// Clock Gating Control
3038
#define SYSCTL_DCGCUART_D4 0x00000010
// UART Module 4 Deep-Sleep Mode
3039
// Clock Gating Control
3040
#define SYSCTL_DCGCUART_D3 0x00000008
// UART Module 3 Deep-Sleep Mode
3041
// Clock Gating Control
3042
#define SYSCTL_DCGCUART_D2 0x00000004
// UART Module 2 Deep-Sleep Mode
3043
// Clock Gating Control
3044
#define SYSCTL_DCGCUART_D1 0x00000002
// UART Module 1 Deep-Sleep Mode
3045
// Clock Gating Control
3046
#define SYSCTL_DCGCUART_D0 0x00000001
// UART Module 0 Deep-Sleep Mode
3047
// Clock Gating Control
3048
3049
//*****************************************************************************
3050
//
3051
// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
3052
//
3053
//*****************************************************************************
3054
#define SYSCTL_DCGCSSI_D3 0x00000008
// SSI Module 3 Deep-Sleep Mode
3055
// Clock Gating Control
3056
#define SYSCTL_DCGCSSI_D2 0x00000004
// SSI Module 2 Deep-Sleep Mode
3057
// Clock Gating Control
3058
#define SYSCTL_DCGCSSI_D1 0x00000002
// SSI Module 1 Deep-Sleep Mode
3059
// Clock Gating Control
3060
#define SYSCTL_DCGCSSI_D0 0x00000001
// SSI Module 0 Deep-Sleep Mode
3061
// Clock Gating Control
3062
3063
//*****************************************************************************
3064
//
3065
// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
3066
//
3067
//*****************************************************************************
3068
#define SYSCTL_DCGCI2C_D9 0x00000200
// I2C Module 9 Deep-Sleep Mode
3069
// Clock Gating Control
3070
#define SYSCTL_DCGCI2C_D8 0x00000100
// I2C Module 8 Deep-Sleep Mode
3071
// Clock Gating Control
3072
#define SYSCTL_DCGCI2C_D7 0x00000080
// I2C Module 7 Deep-Sleep Mode
3073
// Clock Gating Control
3074
#define SYSCTL_DCGCI2C_D6 0x00000040
// I2C Module 6 Deep-Sleep Mode
3075
// Clock Gating Control
3076
#define SYSCTL_DCGCI2C_D5 0x00000020
// I2C Module 5 Deep-Sleep Mode
3077
// Clock Gating Control
3078
#define SYSCTL_DCGCI2C_D4 0x00000010
// I2C Module 4 Deep-Sleep Mode
3079
// Clock Gating Control
3080
#define SYSCTL_DCGCI2C_D3 0x00000008
// I2C Module 3 Deep-Sleep Mode
3081
// Clock Gating Control
3082
#define SYSCTL_DCGCI2C_D2 0x00000004
// I2C Module 2 Deep-Sleep Mode
3083
// Clock Gating Control
3084
#define SYSCTL_DCGCI2C_D1 0x00000002
// I2C Module 1 Deep-Sleep Mode
3085
// Clock Gating Control
3086
#define SYSCTL_DCGCI2C_D0 0x00000001
// I2C Module 0 Deep-Sleep Mode
3087
// Clock Gating Control
3088
3089
//*****************************************************************************
3090
//
3091
// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
3092
//
3093
//*****************************************************************************
3094
#define SYSCTL_DCGCUSB_D0 0x00000001
// USB Module Deep-Sleep Mode Clock
3095
// Gating Control
3096
3097
//*****************************************************************************
3098
//
3099
// The following are defines for the bit fields in the SYSCTL_DCGCEPHY
3100
// register.
3101
//
3102
//*****************************************************************************
3103
#define SYSCTL_DCGCEPHY_D0 0x00000001
// PHY Module Deep-Sleep Mode Clock
3104
// Gating Control
3105
3106
//*****************************************************************************
3107
//
3108
// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
3109
//
3110
//*****************************************************************************
3111
#define SYSCTL_DCGCCAN_D1 0x00000002
// CAN Module 1 Deep-Sleep Mode
3112
// Clock Gating Control
3113
#define SYSCTL_DCGCCAN_D0 0x00000001
// CAN Module 0 Deep-Sleep Mode
3114
// Clock Gating Control
3115
3116
//*****************************************************************************
3117
//
3118
// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
3119
//
3120
//*****************************************************************************
3121
#define SYSCTL_DCGCADC_D1 0x00000002
// ADC Module 1 Deep-Sleep Mode
3122
// Clock Gating Control
3123
#define SYSCTL_DCGCADC_D0 0x00000001
// ADC Module 0 Deep-Sleep Mode
3124
// Clock Gating Control
3125
3126
//*****************************************************************************
3127
//
3128
// The following are defines for the bit fields in the SYSCTL_DCGCACMP
3129
// register.
3130
//
3131
//*****************************************************************************
3132
#define SYSCTL_DCGCACMP_D0 0x00000001
// Analog Comparator Module 0
3133
// Deep-Sleep Mode Clock Gating
3134
// Control
3135
3136
//*****************************************************************************
3137
//
3138
// The following are defines for the bit fields in the SYSCTL_DCGCPWM register.
3139
//
3140
//*****************************************************************************
3141
#define SYSCTL_DCGCPWM_D1 0x00000002
// PWM Module 1 Deep-Sleep Mode
3142
// Clock Gating Control
3143
#define SYSCTL_DCGCPWM_D0 0x00000001
// PWM Module 0 Deep-Sleep Mode
3144
// Clock Gating Control
3145
3146
//*****************************************************************************
3147
//
3148
// The following are defines for the bit fields in the SYSCTL_DCGCQEI register.
3149
//
3150
//*****************************************************************************
3151
#define SYSCTL_DCGCQEI_D1 0x00000002
// QEI Module 1 Deep-Sleep Mode
3152
// Clock Gating Control
3153
#define SYSCTL_DCGCQEI_D0 0x00000001
// QEI Module 0 Deep-Sleep Mode
3154
// Clock Gating Control
3155
3156
//*****************************************************************************
3157
//
3158
// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
3159
// register.
3160
//
3161
//*****************************************************************************
3162
#define SYSCTL_DCGCEEPROM_D0 0x00000001
// EEPROM Module Deep-Sleep Mode
3163
// Clock Gating Control
3164
3165
//*****************************************************************************
3166
//
3167
// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
3168
// register.
3169
//
3170
//*****************************************************************************
3171
#define SYSCTL_DCGCWTIMER_D5 0x00000020
// 32/64-Bit Wide General-Purpose
3172
// Timer 5 Deep-Sleep Mode Clock
3173
// Gating Control
3174
#define SYSCTL_DCGCWTIMER_D4 0x00000010
// 32/64-Bit Wide General-Purpose
3175
// Timer 4 Deep-Sleep Mode Clock
3176
// Gating Control
3177
#define SYSCTL_DCGCWTIMER_D3 0x00000008
// 32/64-Bit Wide General-Purpose
3178
// Timer 3 Deep-Sleep Mode Clock
3179
// Gating Control
3180
#define SYSCTL_DCGCWTIMER_D2 0x00000004
// 32/64-Bit Wide General-Purpose
3181
// Timer 2 Deep-Sleep Mode Clock
3182
// Gating Control
3183
#define SYSCTL_DCGCWTIMER_D1 0x00000002
// 32/64-Bit Wide General-Purpose
3184
// Timer 1 Deep-Sleep Mode Clock
3185
// Gating Control
3186
#define SYSCTL_DCGCWTIMER_D0 0x00000001
// 32/64-Bit Wide General-Purpose
3187
// Timer 0 Deep-Sleep Mode Clock
3188
// Gating Control
3189
3190
//*****************************************************************************
3191
//
3192
// The following are defines for the bit fields in the SYSCTL_DCGCCCM register.
3193
//
3194
//*****************************************************************************
3195
#define SYSCTL_DCGCCCM_D0 0x00000001
// CRC and Cryptographic Modules
3196
// Deep-Sleep Mode Clock Gating
3197
// Control
3198
3199
//*****************************************************************************
3200
//
3201
// The following are defines for the bit fields in the SYSCTL_DCGCLCD register.
3202
//
3203
//*****************************************************************************
3204
#define SYSCTL_DCGCLCD_D0 0x00000001
// LCD Controller Module 0
3205
// Deep-Sleep Mode Clock Gating
3206
// Control
3207
3208
//*****************************************************************************
3209
//
3210
// The following are defines for the bit fields in the SYSCTL_DCGCOWIRE
3211
// register.
3212
//
3213
//*****************************************************************************
3214
#define SYSCTL_DCGCOWIRE_D0 0x00000001
// 1-Wire Module 0 Deep-Sleep Mode
3215
// Clock Gating Control
3216
3217
//*****************************************************************************
3218
//
3219
// The following are defines for the bit fields in the SYSCTL_DCGCEMAC
3220
// register.
3221
//
3222
//*****************************************************************************
3223
#define SYSCTL_DCGCEMAC_D0 0x00000001
// Ethernet MAC Module 0 Deep-Sleep
3224
// Mode Clock Gating Control
3225
3226
//*****************************************************************************
3227
//
3228
// The following are defines for the bit fields in the SYSCTL_PCWD register.
3229
//
3230
//*****************************************************************************
3231
#define SYSCTL_PCWD_P1 0x00000002
// Watchdog Timer 1 Power Control
3232
#define SYSCTL_PCWD_P0 0x00000001
// Watchdog Timer 0 Power Control
3233
3234
//*****************************************************************************
3235
//
3236
// The following are defines for the bit fields in the SYSCTL_PCTIMER register.
3237
//
3238
//*****************************************************************************
3239
#define SYSCTL_PCTIMER_P7 0x00000080
// General-Purpose Timer 7 Power
3240
// Control
3241
#define SYSCTL_PCTIMER_P6 0x00000040
// General-Purpose Timer 6 Power
3242
// Control
3243
#define SYSCTL_PCTIMER_P5 0x00000020
// General-Purpose Timer 5 Power
3244
// Control
3245
#define SYSCTL_PCTIMER_P4 0x00000010
// General-Purpose Timer 4 Power
3246
// Control
3247
#define SYSCTL_PCTIMER_P3 0x00000008
// General-Purpose Timer 3 Power
3248
// Control
3249
#define SYSCTL_PCTIMER_P2 0x00000004
// General-Purpose Timer 2 Power
3250
// Control
3251
#define SYSCTL_PCTIMER_P1 0x00000002
// General-Purpose Timer 1 Power
3252
// Control
3253
#define SYSCTL_PCTIMER_P0 0x00000001
// General-Purpose Timer 0 Power
3254
// Control
3255
3256
//*****************************************************************************
3257
//
3258
// The following are defines for the bit fields in the SYSCTL_PCGPIO register.
3259
//
3260
//*****************************************************************************
3261
#define SYSCTL_PCGPIO_P17 0x00020000
// GPIO Port T Power Control
3262
#define SYSCTL_PCGPIO_P16 0x00010000
// GPIO Port S Power Control
3263
#define SYSCTL_PCGPIO_P15 0x00008000
// GPIO Port R Power Control
3264
#define SYSCTL_PCGPIO_P14 0x00004000
// GPIO Port Q Power Control
3265
#define SYSCTL_PCGPIO_P13 0x00002000
// GPIO Port P Power Control
3266
#define SYSCTL_PCGPIO_P12 0x00001000
// GPIO Port N Power Control
3267
#define SYSCTL_PCGPIO_P11 0x00000800
// GPIO Port M Power Control
3268
#define SYSCTL_PCGPIO_P10 0x00000400
// GPIO Port L Power Control
3269
#define SYSCTL_PCGPIO_P9 0x00000200
// GPIO Port K Power Control
3270
#define SYSCTL_PCGPIO_P8 0x00000100
// GPIO Port J Power Control
3271
#define SYSCTL_PCGPIO_P7 0x00000080
// GPIO Port H Power Control
3272
#define SYSCTL_PCGPIO_P6 0x00000040
// GPIO Port G Power Control
3273
#define SYSCTL_PCGPIO_P5 0x00000020
// GPIO Port F Power Control
3274
#define SYSCTL_PCGPIO_P4 0x00000010
// GPIO Port E Power Control
3275
#define SYSCTL_PCGPIO_P3 0x00000008
// GPIO Port D Power Control
3276
#define SYSCTL_PCGPIO_P2 0x00000004
// GPIO Port C Power Control
3277
#define SYSCTL_PCGPIO_P1 0x00000002
// GPIO Port B Power Control
3278
#define SYSCTL_PCGPIO_P0 0x00000001
// GPIO Port A Power Control
3279
3280
//*****************************************************************************
3281
//
3282
// The following are defines for the bit fields in the SYSCTL_PCDMA register.
3283
//
3284
//*****************************************************************************
3285
#define SYSCTL_PCDMA_P0 0x00000001
// uDMA Module Power Control
3286
3287
//*****************************************************************************
3288
//
3289
// The following are defines for the bit fields in the SYSCTL_PCEPI register.
3290
//
3291
//*****************************************************************************
3292
#define SYSCTL_PCEPI_P0 0x00000001
// EPI Module Power Control
3293
3294
//*****************************************************************************
3295
//
3296
// The following are defines for the bit fields in the SYSCTL_PCHIB register.
3297
//
3298
//*****************************************************************************
3299
#define SYSCTL_PCHIB_P0 0x00000001
// Hibernation Module Power Control
3300
3301
//*****************************************************************************
3302
//
3303
// The following are defines for the bit fields in the SYSCTL_PCUART register.
3304
//
3305
//*****************************************************************************
3306
#define SYSCTL_PCUART_P7 0x00000080
// UART Module 7 Power Control
3307
#define SYSCTL_PCUART_P6 0x00000040
// UART Module 6 Power Control
3308
#define SYSCTL_PCUART_P5 0x00000020
// UART Module 5 Power Control
3309
#define SYSCTL_PCUART_P4 0x00000010
// UART Module 4 Power Control
3310
#define SYSCTL_PCUART_P3 0x00000008
// UART Module 3 Power Control
3311
#define SYSCTL_PCUART_P2 0x00000004
// UART Module 2 Power Control
3312
#define SYSCTL_PCUART_P1 0x00000002
// UART Module 1 Power Control
3313
#define SYSCTL_PCUART_P0 0x00000001
// UART Module 0 Power Control
3314
3315
//*****************************************************************************
3316
//
3317
// The following are defines for the bit fields in the SYSCTL_PCSSI register.
3318
//
3319
//*****************************************************************************
3320
#define SYSCTL_PCSSI_P3 0x00000008
// SSI Module 3 Power Control
3321
#define SYSCTL_PCSSI_P2 0x00000004
// SSI Module 2 Power Control
3322
#define SYSCTL_PCSSI_P1 0x00000002
// SSI Module 1 Power Control
3323
#define SYSCTL_PCSSI_P0 0x00000001
// SSI Module 0 Power Control
3324
3325
//*****************************************************************************
3326
//
3327
// The following are defines for the bit fields in the SYSCTL_PCI2C register.
3328
//
3329
//*****************************************************************************
3330
#define SYSCTL_PCI2C_P9 0x00000200
// I2C Module 9 Power Control
3331
#define SYSCTL_PCI2C_P8 0x00000100
// I2C Module 8 Power Control
3332
#define SYSCTL_PCI2C_P7 0x00000080
// I2C Module 7 Power Control
3333
#define SYSCTL_PCI2C_P6 0x00000040
// I2C Module 6 Power Control
3334
#define SYSCTL_PCI2C_P5 0x00000020
// I2C Module 5 Power Control
3335
#define SYSCTL_PCI2C_P4 0x00000010
// I2C Module 4 Power Control
3336
#define SYSCTL_PCI2C_P3 0x00000008
// I2C Module 3 Power Control
3337
#define SYSCTL_PCI2C_P2 0x00000004
// I2C Module 2 Power Control
3338
#define SYSCTL_PCI2C_P1 0x00000002
// I2C Module 1 Power Control
3339
#define SYSCTL_PCI2C_P0 0x00000001
// I2C Module 0 Power Control
3340
3341
//*****************************************************************************
3342
//
3343
// The following are defines for the bit fields in the SYSCTL_PCUSB register.
3344
//
3345
//*****************************************************************************
3346
#define SYSCTL_PCUSB_P0 0x00000001
// USB Module Power Control
3347
3348
//*****************************************************************************
3349
//
3350
// The following are defines for the bit fields in the SYSCTL_PCEPHY register.
3351
//
3352
//*****************************************************************************
3353
#define SYSCTL_PCEPHY_P0 0x00000001
// Ethernet PHY Module Power
3354
// Control
3355
3356
//*****************************************************************************
3357
//
3358
// The following are defines for the bit fields in the SYSCTL_PCCAN register.
3359
//
3360
//*****************************************************************************
3361
#define SYSCTL_PCCAN_P1 0x00000002
// CAN Module 1 Power Control
3362
#define SYSCTL_PCCAN_P0 0x00000001
// CAN Module 0 Power Control
3363
3364
//*****************************************************************************
3365
//
3366
// The following are defines for the bit fields in the SYSCTL_PCADC register.
3367
//
3368
//*****************************************************************************
3369
#define SYSCTL_PCADC_P1 0x00000002
// ADC Module 1 Power Control
3370
#define SYSCTL_PCADC_P0 0x00000001
// ADC Module 0 Power Control
3371
3372
//*****************************************************************************
3373
//
3374
// The following are defines for the bit fields in the SYSCTL_PCACMP register.
3375
//
3376
//*****************************************************************************
3377
#define SYSCTL_PCACMP_P0 0x00000001
// Analog Comparator Module 0 Power
3378
// Control
3379
3380
//*****************************************************************************
3381
//
3382
// The following are defines for the bit fields in the SYSCTL_PCPWM register.
3383
//
3384
//*****************************************************************************
3385
#define SYSCTL_PCPWM_P0 0x00000001
// PWM Module 0 Power Control
3386
3387
//*****************************************************************************
3388
//
3389
// The following are defines for the bit fields in the SYSCTL_PCQEI register.
3390
//
3391
//*****************************************************************************
3392
#define SYSCTL_PCQEI_P0 0x00000001
// QEI Module 0 Power Control
3393
3394
//*****************************************************************************
3395
//
3396
// The following are defines for the bit fields in the SYSCTL_PCEEPROM
3397
// register.
3398
//
3399
//*****************************************************************************
3400
#define SYSCTL_PCEEPROM_P0 0x00000001
// EEPROM Module 0 Power Control
3401
3402
//*****************************************************************************
3403
//
3404
// The following are defines for the bit fields in the SYSCTL_PCCCM register.
3405
//
3406
//*****************************************************************************
3407
#define SYSCTL_PCCCM_P0 0x00000001
// CRC and Cryptographic Modules
3408
// Power Control
3409
3410
//*****************************************************************************
3411
//
3412
// The following are defines for the bit fields in the SYSCTL_PCLCD register.
3413
//
3414
//*****************************************************************************
3415
#define SYSCTL_PCLCD_P0 0x00000001
// LCD Controller Module 0 Power
3416
// Control
3417
3418
//*****************************************************************************
3419
//
3420
// The following are defines for the bit fields in the SYSCTL_PCOWIRE register.
3421
//
3422
//*****************************************************************************
3423
#define SYSCTL_PCOWIRE_P0 0x00000001
// 1-Wire Module 0 Power Control
3424
3425
//*****************************************************************************
3426
//
3427
// The following are defines for the bit fields in the SYSCTL_PCEMAC register.
3428
//
3429
//*****************************************************************************
3430
#define SYSCTL_PCEMAC_P0 0x00000001
// Ethernet MAC Module 0 Power
3431
// Control
3432
3433
//*****************************************************************************
3434
//
3435
// The following are defines for the bit fields in the SYSCTL_PRWD register.
3436
//
3437
//*****************************************************************************
3438
#define SYSCTL_PRWD_R1 0x00000002
// Watchdog Timer 1 Peripheral
3439
// Ready
3440
#define SYSCTL_PRWD_R0 0x00000001
// Watchdog Timer 0 Peripheral
3441
// Ready
3442
3443
//*****************************************************************************
3444
//
3445
// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
3446
//
3447
//*****************************************************************************
3448
#define SYSCTL_PRTIMER_R7 0x00000080
// 16/32-Bit General-Purpose Timer
3449
// 7 Peripheral Ready
3450
#define SYSCTL_PRTIMER_R6 0x00000040
// 16/32-Bit General-Purpose Timer
3451
// 6 Peripheral Ready
3452
#define SYSCTL_PRTIMER_R5 0x00000020
// 16/32-Bit General-Purpose Timer
3453
// 5 Peripheral Ready
3454
#define SYSCTL_PRTIMER_R4 0x00000010
// 16/32-Bit General-Purpose Timer
3455
// 4 Peripheral Ready
3456
#define SYSCTL_PRTIMER_R3 0x00000008
// 16/32-Bit General-Purpose Timer
3457
// 3 Peripheral Ready
3458
#define SYSCTL_PRTIMER_R2 0x00000004
// 16/32-Bit General-Purpose Timer
3459
// 2 Peripheral Ready
3460
#define SYSCTL_PRTIMER_R1 0x00000002
// 16/32-Bit General-Purpose Timer
3461
// 1 Peripheral Ready
3462
#define SYSCTL_PRTIMER_R0 0x00000001
// 16/32-Bit General-Purpose Timer
3463
// 0 Peripheral Ready
3464
3465
//*****************************************************************************
3466
//
3467
// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
3468
//
3469
//*****************************************************************************
3470
#define SYSCTL_PRGPIO_R17 0x00020000
// GPIO Port T Peripheral Ready
3471
#define SYSCTL_PRGPIO_R16 0x00010000
// GPIO Port S Peripheral Ready
3472
#define SYSCTL_PRGPIO_R15 0x00008000
// GPIO Port R Peripheral Ready
3473
#define SYSCTL_PRGPIO_R14 0x00004000
// GPIO Port Q Peripheral Ready
3474
#define SYSCTL_PRGPIO_R13 0x00002000
// GPIO Port P Peripheral Ready
3475
#define SYSCTL_PRGPIO_R12 0x00001000
// GPIO Port N Peripheral Ready
3476
#define SYSCTL_PRGPIO_R11 0x00000800
// GPIO Port M Peripheral Ready
3477
#define SYSCTL_PRGPIO_R10 0x00000400
// GPIO Port L Peripheral Ready
3478
#define SYSCTL_PRGPIO_R9 0x00000200
// GPIO Port K Peripheral Ready
3479
#define SYSCTL_PRGPIO_R8 0x00000100
// GPIO Port J Peripheral Ready
3480
#define SYSCTL_PRGPIO_R7 0x00000080
// GPIO Port H Peripheral Ready
3481
#define SYSCTL_PRGPIO_R6 0x00000040
// GPIO Port G Peripheral Ready
3482
#define SYSCTL_PRGPIO_R5 0x00000020
// GPIO Port F Peripheral Ready
3483
#define SYSCTL_PRGPIO_R4 0x00000010
// GPIO Port E Peripheral Ready
3484
#define SYSCTL_PRGPIO_R3 0x00000008
// GPIO Port D Peripheral Ready
3485
#define SYSCTL_PRGPIO_R2 0x00000004
// GPIO Port C Peripheral Ready
3486
#define SYSCTL_PRGPIO_R1 0x00000002
// GPIO Port B Peripheral Ready
3487
#define SYSCTL_PRGPIO_R0 0x00000001
// GPIO Port A Peripheral Ready
3488
3489
//*****************************************************************************
3490
//
3491
// The following are defines for the bit fields in the SYSCTL_PRDMA register.
3492
//
3493
//*****************************************************************************
3494
#define SYSCTL_PRDMA_R0 0x00000001
// uDMA Module Peripheral Ready
3495
3496
//*****************************************************************************
3497
//
3498
// The following are defines for the bit fields in the SYSCTL_PREPI register.
3499
//
3500
//*****************************************************************************
3501
#define SYSCTL_PREPI_R0 0x00000001
// EPI Module Peripheral Ready
3502
3503
//*****************************************************************************
3504
//
3505
// The following are defines for the bit fields in the SYSCTL_PRHIB register.
3506
//
3507
//*****************************************************************************
3508
#define SYSCTL_PRHIB_R0 0x00000001
// Hibernation Module Peripheral
3509
// Ready
3510
3511
//*****************************************************************************
3512
//
3513
// The following are defines for the bit fields in the SYSCTL_PRUART register.
3514
//
3515
//*****************************************************************************
3516
#define SYSCTL_PRUART_R7 0x00000080
// UART Module 7 Peripheral Ready
3517
#define SYSCTL_PRUART_R6 0x00000040
// UART Module 6 Peripheral Ready
3518
#define SYSCTL_PRUART_R5 0x00000020
// UART Module 5 Peripheral Ready
3519
#define SYSCTL_PRUART_R4 0x00000010
// UART Module 4 Peripheral Ready
3520
#define SYSCTL_PRUART_R3 0x00000008
// UART Module 3 Peripheral Ready
3521
#define SYSCTL_PRUART_R2 0x00000004
// UART Module 2 Peripheral Ready
3522
#define SYSCTL_PRUART_R1 0x00000002
// UART Module 1 Peripheral Ready
3523
#define SYSCTL_PRUART_R0 0x00000001
// UART Module 0 Peripheral Ready
3524
3525
//*****************************************************************************
3526
//
3527
// The following are defines for the bit fields in the SYSCTL_PRSSI register.
3528
//
3529
//*****************************************************************************
3530
#define SYSCTL_PRSSI_R3 0x00000008
// SSI Module 3 Peripheral Ready
3531
#define SYSCTL_PRSSI_R2 0x00000004
// SSI Module 2 Peripheral Ready
3532
#define SYSCTL_PRSSI_R1 0x00000002
// SSI Module 1 Peripheral Ready
3533
#define SYSCTL_PRSSI_R0 0x00000001
// SSI Module 0 Peripheral Ready
3534
3535
//*****************************************************************************
3536
//
3537
// The following are defines for the bit fields in the SYSCTL_PRI2C register.
3538
//
3539
//*****************************************************************************
3540
#define SYSCTL_PRI2C_R9 0x00000200
// I2C Module 9 Peripheral Ready
3541
#define SYSCTL_PRI2C_R8 0x00000100
// I2C Module 8 Peripheral Ready
3542
#define SYSCTL_PRI2C_R7 0x00000080
// I2C Module 7 Peripheral Ready
3543
#define SYSCTL_PRI2C_R6 0x00000040
// I2C Module 6 Peripheral Ready
3544
#define SYSCTL_PRI2C_R5 0x00000020
// I2C Module 5 Peripheral Ready
3545
#define SYSCTL_PRI2C_R4 0x00000010
// I2C Module 4 Peripheral Ready
3546
#define SYSCTL_PRI2C_R3 0x00000008
// I2C Module 3 Peripheral Ready
3547
#define SYSCTL_PRI2C_R2 0x00000004
// I2C Module 2 Peripheral Ready
3548
#define SYSCTL_PRI2C_R1 0x00000002
// I2C Module 1 Peripheral Ready
3549
#define SYSCTL_PRI2C_R0 0x00000001
// I2C Module 0 Peripheral Ready
3550
3551
//*****************************************************************************
3552
//
3553
// The following are defines for the bit fields in the SYSCTL_PRUSB register.
3554
//
3555
//*****************************************************************************
3556
#define SYSCTL_PRUSB_R0 0x00000001
// USB Module Peripheral Ready
3557
3558
//*****************************************************************************
3559
//
3560
// The following are defines for the bit fields in the SYSCTL_PREPHY register.
3561
//
3562
//*****************************************************************************
3563
#define SYSCTL_PREPHY_R0 0x00000001
// Ethernet PHY Module Peripheral
3564
// Ready
3565
3566
//*****************************************************************************
3567
//
3568
// The following are defines for the bit fields in the SYSCTL_PRCAN register.
3569
//
3570
//*****************************************************************************
3571
#define SYSCTL_PRCAN_R1 0x00000002
// CAN Module 1 Peripheral Ready
3572
#define SYSCTL_PRCAN_R0 0x00000001
// CAN Module 0 Peripheral Ready
3573
3574
//*****************************************************************************
3575
//
3576
// The following are defines for the bit fields in the SYSCTL_PRADC register.
3577
//
3578
//*****************************************************************************
3579
#define SYSCTL_PRADC_R1 0x00000002
// ADC Module 1 Peripheral Ready
3580
#define SYSCTL_PRADC_R0 0x00000001
// ADC Module 0 Peripheral Ready
3581
3582
//*****************************************************************************
3583
//
3584
// The following are defines for the bit fields in the SYSCTL_PRACMP register.
3585
//
3586
//*****************************************************************************
3587
#define SYSCTL_PRACMP_R0 0x00000001
// Analog Comparator Module 0
3588
// Peripheral Ready
3589
3590
//*****************************************************************************
3591
//
3592
// The following are defines for the bit fields in the SYSCTL_PRPWM register.
3593
//
3594
//*****************************************************************************
3595
#define SYSCTL_PRPWM_R1 0x00000002
// PWM Module 1 Peripheral Ready
3596
#define SYSCTL_PRPWM_R0 0x00000001
// PWM Module 0 Peripheral Ready
3597
3598
//*****************************************************************************
3599
//
3600
// The following are defines for the bit fields in the SYSCTL_PRQEI register.
3601
//
3602
//*****************************************************************************
3603
#define SYSCTL_PRQEI_R1 0x00000002
// QEI Module 1 Peripheral Ready
3604
#define SYSCTL_PRQEI_R0 0x00000001
// QEI Module 0 Peripheral Ready
3605
3606
//*****************************************************************************
3607
//
3608
// The following are defines for the bit fields in the SYSCTL_PREEPROM
3609
// register.
3610
//
3611
//*****************************************************************************
3612
#define SYSCTL_PREEPROM_R0 0x00000001
// EEPROM Module Peripheral Ready
3613
3614
//*****************************************************************************
3615
//
3616
// The following are defines for the bit fields in the SYSCTL_PRWTIMER
3617
// register.
3618
//
3619
//*****************************************************************************
3620
#define SYSCTL_PRWTIMER_R5 0x00000020
// 32/64-Bit Wide General-Purpose
3621
// Timer 5 Peripheral Ready
3622
#define SYSCTL_PRWTIMER_R4 0x00000010
// 32/64-Bit Wide General-Purpose
3623
// Timer 4 Peripheral Ready
3624
#define SYSCTL_PRWTIMER_R3 0x00000008
// 32/64-Bit Wide General-Purpose
3625
// Timer 3 Peripheral Ready
3626
#define SYSCTL_PRWTIMER_R2 0x00000004
// 32/64-Bit Wide General-Purpose
3627
// Timer 2 Peripheral Ready
3628
#define SYSCTL_PRWTIMER_R1 0x00000002
// 32/64-Bit Wide General-Purpose
3629
// Timer 1 Peripheral Ready
3630
#define SYSCTL_PRWTIMER_R0 0x00000001
// 32/64-Bit Wide General-Purpose
3631
// Timer 0 Peripheral Ready
3632
3633
//*****************************************************************************
3634
//
3635
// The following are defines for the bit fields in the SYSCTL_PRCCM register.
3636
//
3637
//*****************************************************************************
3638
#define SYSCTL_PRCCM_R0 0x00000001
// CRC and Cryptographic Modules
3639
// Peripheral Ready
3640
3641
//*****************************************************************************
3642
//
3643
// The following are defines for the bit fields in the SYSCTL_PRLCD register.
3644
//
3645
//*****************************************************************************
3646
#define SYSCTL_PRLCD_R0 0x00000001
// LCD Controller Module 0
3647
// Peripheral Ready
3648
3649
//*****************************************************************************
3650
//
3651
// The following are defines for the bit fields in the SYSCTL_PROWIRE register.
3652
//
3653
//*****************************************************************************
3654
#define SYSCTL_PROWIRE_R0 0x00000001
// 1-Wire Module 0 Peripheral Ready
3655
3656
//*****************************************************************************
3657
//
3658
// The following are defines for the bit fields in the SYSCTL_PREMAC register.
3659
//
3660
//*****************************************************************************
3661
#define SYSCTL_PREMAC_R0 0x00000001
// Ethernet MAC Module 0 Peripheral
3662
// Ready
3663
3664
//*****************************************************************************
3665
//
3666
// The following are defines for the bit fields in the SYSCTL_UNIQUEID0
3667
// register.
3668
//
3669
//*****************************************************************************
3670
#define SYSCTL_UNIQUEID0_ID_M 0xFFFFFFFF
// Unique ID
3671
#define SYSCTL_UNIQUEID0_ID_S 0
3672
3673
//*****************************************************************************
3674
//
3675
// The following are defines for the bit fields in the SYSCTL_UNIQUEID1
3676
// register.
3677
//
3678
//*****************************************************************************
3679
#define SYSCTL_UNIQUEID1_ID_M 0xFFFFFFFF
// Unique ID
3680
#define SYSCTL_UNIQUEID1_ID_S 0
3681
3682
//*****************************************************************************
3683
//
3684
// The following are defines for the bit fields in the SYSCTL_UNIQUEID2
3685
// register.
3686
//
3687
//*****************************************************************************
3688
#define SYSCTL_UNIQUEID2_ID_M 0xFFFFFFFF
// Unique ID
3689
#define SYSCTL_UNIQUEID2_ID_S 0
3690
3691
//*****************************************************************************
3692
//
3693
// The following are defines for the bit fields in the SYSCTL_UNIQUEID3
3694
// register.
3695
//
3696
//*****************************************************************************
3697
#define SYSCTL_UNIQUEID3_ID_M 0xFFFFFFFF
// Unique ID
3698
#define SYSCTL_UNIQUEID3_ID_S 0
3699
3700
//*****************************************************************************
3701
//
3702
// The following are defines for the bit fields in the SYSCTL_CCMCGREQ
3703
// register.
3704
//
3705
//*****************************************************************************
3706
#define SYSCTL_CCMCGREQ_DESCFG 0x00000004
// DES Clock Gating Request
3707
#define SYSCTL_CCMCGREQ_AESCFG 0x00000002
// AES Clock Gating Request
3708
#define SYSCTL_CCMCGREQ_SHACFG 0x00000001
// SHA/MD5 Clock Gating Request
3709
3710
//*****************************************************************************
3711
//
3712
// The following definitions are deprecated.
3713
//
3714
//*****************************************************************************
3715
#ifndef DEPRECATED
3716
3717
//*****************************************************************************
3718
//
3719
// The following are deprecated defines for the bit fields in the SYSCTL_DID0
3720
// register.
3721
//
3722
//*****************************************************************************
3723
#define SYSCTL_DID0_CLASS_BLIZZARD \
3724
0x00050000
// Tiva(TM) C Series TM4C123-class
3725
// microcontrollers
3726
#define SYSCTL_DID0_CLASS_SNOWFLAKE \
3727
0x000A0000
// Tiva(TM) C Series TM4C129-class
3728
// microcontrollers
3729
3730
//*****************************************************************************
3731
//
3732
// The following are deprecated defines for the bit fields in the SYSCTL_RESC
3733
// register.
3734
//
3735
//*****************************************************************************
3736
#define SYSCTL_RESC_HIB 0x00000040
// HIB Reset
3737
3738
//*****************************************************************************
3739
//
3740
// The following are deprecated defines for the bit fields in the SYSCTL_PWRTC
3741
// register.
3742
//
3743
//*****************************************************************************
3744
#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010
// VDDA Under BOR0 Status
3745
#define SYSCTL_PWRTC_VDD_UBOR0 0x00000001
// VDD Under BOR0 Status
3746
3747
#endif
3748
3749
#endif
// __HW_SYSCTL_H__