mikroSDK Reference Manual
ksz9897_driver.h
Go to the documentation of this file.
1
31#ifndef _KSZ9897_DRIVER_H
32#define _KSZ9897_DRIVER_H
33
34//Dependencies
35#include "core/nic.h"
36
37//Port identifiers
38#define KSZ9897_PORT1 1
39#define KSZ9897_PORT2 2
40#define KSZ9897_PORT3 3
41#define KSZ9897_PORT4 4
42#define KSZ9897_PORT5 5
43#define KSZ9897_PORT6 6
44#define KSZ9897_PORT7 7
45
46//Port masks
47#define KSZ9897_PORT_MASK 0x7F
48#define KSZ9897_PORT1_MASK 0x01
49#define KSZ9897_PORT2_MASK 0x02
50#define KSZ9897_PORT3_MASK 0x04
51#define KSZ9897_PORT4_MASK 0x08
52#define KSZ9897_PORT5_MASK 0x10
53#define KSZ9897_PORT6_MASK 0x20
54#define KSZ9897_PORT7_MASK 0x40
55
56//SPI command byte
57#define KSZ9897_SPI_CMD_WRITE 0x40000000
58#define KSZ9897_SPI_CMD_READ 0x60000000
59#define KSZ9897_SPI_CMD_ADDR 0x001FFFE0
60
61//Size of static and dynamic MAC tables
62#define KSZ9897_STATIC_MAC_TABLE_SIZE 16
63#define KSZ9897_DYNAMIC_MAC_TABLE_SIZE 4096
64
65//Tail tag rules (host to KSZ9897)
66#define KSZ9897_TAIL_TAG_NORMAL_ADDR_LOOKUP 0x0400
67#define KSZ9897_TAIL_TAG_PORT_BLOCKING_OVERRIDE 0x0200
68#define KSZ9897_TAIL_TAG_PRIORITY 0x0180
69#define KSZ9897_TAIL_TAG_DEST_PORT7 0x0040
70#define KSZ9897_TAIL_TAG_DEST_PORT6 0x0020
71#define KSZ9897_TAIL_TAG_DEST_PORT5 0x0010
72#define KSZ9897_TAIL_TAG_DEST_PORT4 0x0008
73#define KSZ9897_TAIL_TAG_DEST_PORT3 0x0004
74#define KSZ9897_TAIL_TAG_DEST_PORT2 0x0002
75#define KSZ9897_TAIL_TAG_DEST_PORT1 0x0001
76
77//Tail tag rules (KSZ9897 to host)
78#define KSZ9897_TAIL_TAG_PTP_MSG 0x80
79#define KSZ9897_TAIL_TAG_SRC_PORT 0x07
80
81//KSZ9897 PHY registers
82#define KSZ9897_BMCR 0x00
83#define KSZ9897_BMSR 0x01
84#define KSZ9897_PHYID1 0x02
85#define KSZ9897_PHYID2 0x03
86#define KSZ9897_ANAR 0x04
87#define KSZ9897_ANLPAR 0x05
88#define KSZ9897_ANER 0x06
89#define KSZ9897_ANNPR 0x07
90#define KSZ9897_ANLPNPR 0x08
91#define KSZ9897_GBCR 0x09
92#define KSZ9897_GBSR 0x0A
93#define KSZ9897_MMDACR 0x0D
94#define KSZ9897_MMDAADR 0x0E
95#define KSZ9897_GBESR 0x0F
96#define KSZ9897_RLB 0x11
97#define KSZ9897_LINKMD 0x12
98#define KSZ9897_DPMAPCSS 0x13
99#define KSZ9897_RXERCTR 0x15
100#define KSZ9897_ICSR 0x1B
101#define KSZ9897_AUTOMDI 0x1C
102#define KSZ9897_PHYCON 0x1F
103
104//KSZ9897 MMD registers
105#define KSZ9897_MMD_LED_MODE 0x02, 0x00
106#define KSZ9897_MMD_EEE_ADV 0x07, 0x3C
107
108//KSZ9897 Switch registers
109#define KSZ9897_CHIP_ID0 0x0000
110#define KSZ9897_CHIP_ID1 0x0001
111#define KSZ9897_CHIP_ID2 0x0002
112#define KSZ9897_CHIP_ID3 0x0003
113#define KSZ9897_PME_PIN_CTRL 0x0006
114#define KSZ9897_GLOBAL_INT_STAT 0x0010
115#define KSZ9897_GLOBAL_INT_MASK 0x0014
116#define KSZ9897_GLOBAL_PORT_INT_STAT 0x0018
117#define KSZ9897_GLOBAL_PORT_INT_MASK 0x001C
118#define KSZ9897_SERIAL_IO_CTRL 0x0100
119#define KSZ9897_OUT_CLK_CTRL 0x0103
120#define KSZ9897_IBA_CTRL 0x0104
121#define KSZ9897_IO_DRIVE_STRENGTH 0x010D
122#define KSZ9897_IBA_OP_STAT1 0x0110
123#define KSZ9897_LED_OVERRIDE 0x0120
124#define KSZ9897_LED_OUTPUT 0x0124
125#define KSZ9897_PWR_DOWN_CTRL0 0x0201
126#define KSZ9897_LED_STRAP_IN 0x0210
127#define KSZ9897_SWITCH_OP 0x0300
128#define KSZ9897_SWITCH_MAC_ADDR0 0x0302
129#define KSZ9897_SWITCH_MAC_ADDR1 0x0303
130#define KSZ9897_SWITCH_MAC_ADDR2 0x0304
131#define KSZ9897_SWITCH_MAC_ADDR3 0x0305
132#define KSZ9897_SWITCH_MAC_ADDR4 0x0306
133#define KSZ9897_SWITCH_MAC_ADDR5 0x0307
134#define KSZ9897_SWITCH_MTU 0x0308
135#define KSZ9897_SWITCH_ISP_TPID 0x030A
136#define KSZ9897_SWITCH_LUE_CTRL0 0x0310
137#define KSZ9897_SWITCH_LUE_CTRL1 0x0311
138#define KSZ9897_SWITCH_LUE_CTRL2 0x0312
139#define KSZ9897_SWITCH_LUE_CTRL3 0x0313
140#define KSZ9897_ALU_TABLE_INT 0x0314
141#define KSZ9897_ALU_TABLE_MASK 0x0315
142#define KSZ9897_ALU_TABLE_ENTRY_INDEX0 0x0316
143#define KSZ9897_ALU_TABLE_ENTRY_INDEX1 0x0318
144#define KSZ9897_ALU_TABLE_ENTRY_INDEX2 0x031A
145#define KSZ9897_UNKNOWN_UNICAST_CTRL 0x0320
146#define KSZ9897_UNKONWN_MULTICAST_CTRL 0x0324
147#define KSZ9897_UNKNOWN_VLAN_ID_CTRL 0x0328
148#define KSZ9897_SWITCH_MAC_CTRL0 0x0330
149#define KSZ9897_SWITCH_MAC_CTRL1 0x0331
150#define KSZ9897_SWITCH_MAC_CTRL2 0x0332
151#define KSZ9897_SWITCH_MAC_CTRL3 0x0333
152#define KSZ9897_SWITCH_MAC_CTRL4 0x0334
153#define KSZ9897_SWITCH_MAC_CTRL5 0x0335
154#define KSZ9897_SWITCH_MIB_CTRL 0x0336
155#define KSZ9897_802_1P_PRIO_MAPPING0 0x0338
156#define KSZ9897_802_1P_PRIO_MAPPING1 0x0339
157#define KSZ9897_802_1P_PRIO_MAPPING2 0x033A
158#define KSZ9897_802_1P_PRIO_MAPPING3 0x033B
159#define KSZ9897_IP_DIFFSERV_PRIO_EN 0x033E
160#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING0 0x0340
161#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING1 0x0341
162#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING2 0x0342
163#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING3 0x0343
164#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING4 0x0344
165#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING5 0x0345
166#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING6 0x0346
167#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING7 0x0347
168#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING8 0x0348
169#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING9 0x0349
170#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING10 0x034A
171#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING11 0x034B
172#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING12 0x034C
173#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING13 0x034D
174#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING14 0x034E
175#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING15 0x034F
176#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING16 0x0350
177#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING17 0x0351
178#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING18 0x0352
179#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING19 0x0353
180#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING20 0x0354
181#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING21 0x0355
182#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING22 0x0356
183#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING23 0x0357
184#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING24 0x0358
185#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING25 0x0359
186#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING26 0x035A
187#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING27 0x035B
188#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING28 0x035C
189#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING29 0x035D
190#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING30 0x035E
191#define KSZ9897_IP_DIFFSERV_PRIO_MAPPING31 0x035F
192#define KSZ9897_GLOBAL_PORT_MIRROR_SNOOP_CTRL 0x0370
193#define KSZ9897_WRED_DIFFSERV_COLOR_MAPPING 0x0378
194#define KSZ9897_QUEUE_MGMT_CTRL0 0x0390
195#define KSZ9897_VLAN_TABLE_ENTRY0 0x0400
196#define KSZ9897_VLAN_TABLE_ENTRY1 0x0404
197#define KSZ9897_VLAN_TABLE_ENTRY2 0x0408
198#define KSZ9897_VLAN_TABLE_INDEX 0x040C
199#define KSZ9897_VLAN_TABLE_ACCESS_CTRL 0x040E
200#define KSZ9897_ALU_TABLE_INDEX0 0x0410
201#define KSZ9897_ALU_TABLE_INDEX1 0x0414
202#define KSZ9897_ALU_TABLE_CTRL 0x0418
203#define KSZ9897_STATIC_RES_MCAST_TABLE_CTRL 0x041C
204#define KSZ9897_ALU_TABLE_ENTRY1 0x0420
205#define KSZ9897_STATIC_TABLE_ENTRY1 0x0420
206#define KSZ9897_ALU_TABLE_ENTRY2 0x0424
207#define KSZ9897_STATIC_TABLE_ENTRY2 0x0424
208#define KSZ9897_RES_MCAST_TABLE_ENTRY2 0x0424
209#define KSZ9897_ALU_TABLE_ENTRY3 0x0428
210#define KSZ9897_STATIC_TABLE_ENTRY3 0x0428
211#define KSZ9897_ALU_TABLE_ENTRY4 0x042C
212#define KSZ9897_STATIC_TABLE_ENTRY4 0x042C
213#define KSZ9897_PORT1_DEFAULT_TAG0 0x1000
214#define KSZ9897_PORT1_DEFAULT_TAG1 0x1001
215#define KSZ9897_PORT1_PME_WOL_EVENT 0x1013
216#define KSZ9897_PORT1_PME_WOL_EN 0x1017
217#define KSZ9897_PORT1_INT_STATUS 0x101B
218#define KSZ9897_PORT1_INT_MASK 0x101F
219#define KSZ9897_PORT1_OP_CTRL0 0x1020
220#define KSZ9897_PORT1_STATUS 0x1030
221#define KSZ9897_PORT1_MAC_CTRL0 0x1400
222#define KSZ9897_PORT1_MAC_CTRL1 0x1401
223#define KSZ9897_PORT1_IG_RATE_LIMIT_CTRL 0x1403
224#define KSZ9897_PORT1_PRIO0_IG_LIMIT_CTRL 0x1410
225#define KSZ9897_PORT1_PRIO1_IG_LIMIT_CTRL 0x1411
226#define KSZ9897_PORT1_PRIO2_IG_LIMIT_CTRL 0x1412
227#define KSZ9897_PORT1_PRIO3_IG_LIMIT_CTRL 0x1413
228#define KSZ9897_PORT1_PRIO4_IG_LIMIT_CTRL 0x1414
229#define KSZ9897_PORT1_PRIO5_IG_LIMIT_CTRL 0x1415
230#define KSZ9897_PORT1_PRIO6_IG_LIMIT_CTRL 0x1416
231#define KSZ9897_PORT1_PRIO7_IG_LIMIT_CTRL 0x1417
232#define KSZ9897_PORT1_QUEUE0_EG_LIMIT_CTRL 0x1420
233#define KSZ9897_PORT1_QUEUE1_EG_LIMIT_CTRL 0x1421
234#define KSZ9897_PORT1_QUEUE2_EG_LIMIT_CTRL 0x1422
235#define KSZ9897_PORT1_QUEUE3_EG_LIMIT_CTRL 0x1423
236#define KSZ9897_PORT1_MIB_CTRL_STAT 0x1500
237#define KSZ9897_PORT1_MIB_DATA 0x1504
238#define KSZ9897_PORT1_ACL_ACCESS0 0x1600
239#define KSZ9897_PORT1_ACL_ACCESS1 0x1601
240#define KSZ9897_PORT1_ACL_ACCESS2 0x1602
241#define KSZ9897_PORT1_ACL_ACCESS3 0x1603
242#define KSZ9897_PORT1_ACL_ACCESS4 0x1604
243#define KSZ9897_PORT1_ACL_ACCESS5 0x1605
244#define KSZ9897_PORT1_ACL_ACCESS6 0x1606
245#define KSZ9897_PORT1_ACL_ACCESS7 0x1607
246#define KSZ9897_PORT1_ACL_ACCESS8 0x1608
247#define KSZ9897_PORT1_ACL_ACCESS9 0x1609
248#define KSZ9897_PORT1_ACL_ACCESS10 0x160A
249#define KSZ9897_PORT1_ACL_ACCESS11 0x160B
250#define KSZ9897_PORT1_ACL_ACCESS12 0x160C
251#define KSZ9897_PORT1_ACL_ACCESS13 0x160D
252#define KSZ9897_PORT1_ACL_ACCESS14 0x160E
253#define KSZ9897_PORT1_ACL_ACCESS15 0x160F
254#define KSZ9897_PORT1_ACL_BYTE_EN_MSB 0x1610
255#define KSZ9897_PORT1_ACL_BYTE_EN_LSB 0x1611
256#define KSZ9897_PORT1_ACL_ACCESS_CTRL0 0x1612
257#define KSZ9897_PORT1_MIRRORING_CTRL 0x1800
258#define KSZ9897_PORT1_PRIO_CTRL 0x1801
259#define KSZ9897_PORT1_IG_MAC_CTRL 0x1802
260#define KSZ9897_PORT1_AUTH_CTRL 0x1803
261#define KSZ9897_PORT1_PTR 0x1804
262#define KSZ9897_PORT1_PRIO_TO_QUEUE_MAPPING 0x1808
263#define KSZ9897_PORT1_POLICE_CTRL 0x180C
264#define KSZ9897_PORT1_POLICE_QUEUE_RATE 0x1820
265#define KSZ9897_PORT1_POLICE_QUEUE_BURST_SIZE 0x1824
266#define KSZ9897_PORT1_WRED_PKT_MEM_CTRL0 0x1830
267#define KSZ9897_PORT1_WRED_PKT_MEM_CTRL1 0x1834
268#define KSZ9897_PORT1_WRED_QUEUE_CTRL0 0x1840
269#define KSZ9897_PORT1_WRED_QUEUE_CTRL1 0x1844
270#define KSZ9897_PORT1_WRED_QUEUE_PERF_MON_CTRL 0x1848
271#define KSZ9897_PORT1_TX_QUEUE_INDEX 0x1900
272#define KSZ9897_PORT1_TX_QUEUE_PVID 0x1904
273#define KSZ9897_PORT1_TX_QUEUE_CTRL0 0x1914
274#define KSZ9897_PORT1_TX_QUEUE_CTRL1 0x1915
275#define KSZ9897_PORT1_CTRL0 0x1A00
276#define KSZ9897_PORT1_CTRL1 0x1A04
277#define KSZ9897_PORT1_CTRL2 0x1B00
278#define KSZ9897_PORT1_MSTP_PTR 0x1B01
279#define KSZ9897_PORT1_MSTP_STATE 0x1B04
280#define KSZ9897_PORT2_DEFAULT_TAG0 0x2000
281#define KSZ9897_PORT2_DEFAULT_TAG1 0x2001
282#define KSZ9897_PORT2_PME_WOL_EVENT 0x2013
283#define KSZ9897_PORT2_PME_WOL_EN 0x2017
284#define KSZ9897_PORT2_INT_STATUS 0x201B
285#define KSZ9897_PORT2_INT_MASK 0x201F
286#define KSZ9897_PORT2_OP_CTRL0 0x2020
287#define KSZ9897_PORT2_STATUS 0x2030
288#define KSZ9897_PORT2_MAC_CTRL0 0x2400
289#define KSZ9897_PORT2_MAC_CTRL1 0x2401
290#define KSZ9897_PORT2_IG_RATE_LIMIT_CTRL 0x2403
291#define KSZ9897_PORT2_PRIO0_IG_LIMIT_CTRL 0x2410
292#define KSZ9897_PORT2_PRIO1_IG_LIMIT_CTRL 0x2411
293#define KSZ9897_PORT2_PRIO2_IG_LIMIT_CTRL 0x2412
294#define KSZ9897_PORT2_PRIO3_IG_LIMIT_CTRL 0x2413
295#define KSZ9897_PORT2_PRIO4_IG_LIMIT_CTRL 0x2414
296#define KSZ9897_PORT2_PRIO5_IG_LIMIT_CTRL 0x2415
297#define KSZ9897_PORT2_PRIO6_IG_LIMIT_CTRL 0x2416
298#define KSZ9897_PORT2_PRIO7_IG_LIMIT_CTRL 0x2417
299#define KSZ9897_PORT2_QUEUE0_EG_LIMIT_CTRL 0x2420
300#define KSZ9897_PORT2_QUEUE1_EG_LIMIT_CTRL 0x2421
301#define KSZ9897_PORT2_QUEUE2_EG_LIMIT_CTRL 0x2422
302#define KSZ9897_PORT2_QUEUE3_EG_LIMIT_CTRL 0x2423
303#define KSZ9897_PORT2_MIB_CTRL_STAT 0x2500
304#define KSZ9897_PORT2_MIB_DATA 0x2504
305#define KSZ9897_PORT2_ACL_ACCESS0 0x2600
306#define KSZ9897_PORT2_ACL_ACCESS1 0x2601
307#define KSZ9897_PORT2_ACL_ACCESS2 0x2602
308#define KSZ9897_PORT2_ACL_ACCESS3 0x2603
309#define KSZ9897_PORT2_ACL_ACCESS4 0x2604
310#define KSZ9897_PORT2_ACL_ACCESS5 0x2605
311#define KSZ9897_PORT2_ACL_ACCESS6 0x2606
312#define KSZ9897_PORT2_ACL_ACCESS7 0x2607
313#define KSZ9897_PORT2_ACL_ACCESS8 0x2608
314#define KSZ9897_PORT2_ACL_ACCESS9 0x2609
315#define KSZ9897_PORT2_ACL_ACCESS10 0x260A
316#define KSZ9897_PORT2_ACL_ACCESS11 0x260B
317#define KSZ9897_PORT2_ACL_ACCESS12 0x260C
318#define KSZ9897_PORT2_ACL_ACCESS13 0x260D
319#define KSZ9897_PORT2_ACL_ACCESS14 0x260E
320#define KSZ9897_PORT2_ACL_ACCESS15 0x260F
321#define KSZ9897_PORT2_ACL_BYTE_EN_MSB 0x2610
322#define KSZ9897_PORT2_ACL_BYTE_EN_LSB 0x2611
323#define KSZ9897_PORT2_ACL_ACCESS_CTRL0 0x2612
324#define KSZ9897_PORT2_MIRRORING_CTRL 0x2800
325#define KSZ9897_PORT2_PRIO_CTRL 0x2801
326#define KSZ9897_PORT2_IG_MAC_CTRL 0x2802
327#define KSZ9897_PORT2_AUTH_CTRL 0x2803
328#define KSZ9897_PORT2_PTR 0x2804
329#define KSZ9897_PORT2_PRIO_TO_QUEUE_MAPPING 0x2808
330#define KSZ9897_PORT2_POLICE_CTRL 0x280C
331#define KSZ9897_PORT2_POLICE_QUEUE_RATE 0x2820
332#define KSZ9897_PORT2_POLICE_QUEUE_BURST_SIZE 0x2824
333#define KSZ9897_PORT2_WRED_PKT_MEM_CTRL0 0x2830
334#define KSZ9897_PORT2_WRED_PKT_MEM_CTRL1 0x2834
335#define KSZ9897_PORT2_WRED_QUEUE_CTRL0 0x2840
336#define KSZ9897_PORT2_WRED_QUEUE_CTRL1 0x2844
337#define KSZ9897_PORT2_WRED_QUEUE_PERF_MON_CTRL 0x2848
338#define KSZ9897_PORT2_TX_QUEUE_INDEX 0x2900
339#define KSZ9897_PORT2_TX_QUEUE_PVID 0x2904
340#define KSZ9897_PORT2_TX_QUEUE_CTRL0 0x2914
341#define KSZ9897_PORT2_TX_QUEUE_CTRL1 0x2915
342#define KSZ9897_PORT2_CTRL0 0x2A00
343#define KSZ9897_PORT2_CTRL1 0x2A04
344#define KSZ9897_PORT2_CTRL2 0x2B00
345#define KSZ9897_PORT2_MSTP_PTR 0x2B01
346#define KSZ9897_PORT2_MSTP_STATE 0x2B04
347#define KSZ9897_PORT3_DEFAULT_TAG0 0x3000
348#define KSZ9897_PORT3_DEFAULT_TAG1 0x3001
349#define KSZ9897_PORT3_PME_WOL_EVENT 0x3013
350#define KSZ9897_PORT3_PME_WOL_EN 0x3017
351#define KSZ9897_PORT3_INT_STATUS 0x301B
352#define KSZ9897_PORT3_INT_MASK 0x301F
353#define KSZ9897_PORT3_OP_CTRL0 0x3020
354#define KSZ9897_PORT3_STATUS 0x3030
355#define KSZ9897_PORT3_MAC_CTRL0 0x3400
356#define KSZ9897_PORT3_MAC_CTRL1 0x3401
357#define KSZ9897_PORT3_IG_RATE_LIMIT_CTRL 0x3403
358#define KSZ9897_PORT3_PRIO0_IG_LIMIT_CTRL 0x3410
359#define KSZ9897_PORT3_PRIO1_IG_LIMIT_CTRL 0x3411
360#define KSZ9897_PORT3_PRIO2_IG_LIMIT_CTRL 0x3412
361#define KSZ9897_PORT3_PRIO3_IG_LIMIT_CTRL 0x3413
362#define KSZ9897_PORT3_PRIO4_IG_LIMIT_CTRL 0x3414
363#define KSZ9897_PORT3_PRIO5_IG_LIMIT_CTRL 0x3415
364#define KSZ9897_PORT3_PRIO6_IG_LIMIT_CTRL 0x3416
365#define KSZ9897_PORT3_PRIO7_IG_LIMIT_CTRL 0x3417
366#define KSZ9897_PORT3_QUEUE0_EG_LIMIT_CTRL 0x3420
367#define KSZ9897_PORT3_QUEUE1_EG_LIMIT_CTRL 0x3421
368#define KSZ9897_PORT3_QUEUE2_EG_LIMIT_CTRL 0x3422
369#define KSZ9897_PORT3_QUEUE3_EG_LIMIT_CTRL 0x3423
370#define KSZ9897_PORT3_MIB_CTRL_STAT 0x3500
371#define KSZ9897_PORT3_MIB_DATA 0x3504
372#define KSZ9897_PORT3_ACL_ACCESS0 0x3600
373#define KSZ9897_PORT3_ACL_ACCESS1 0x3601
374#define KSZ9897_PORT3_ACL_ACCESS2 0x3602
375#define KSZ9897_PORT3_ACL_ACCESS3 0x3603
376#define KSZ9897_PORT3_ACL_ACCESS4 0x3604
377#define KSZ9897_PORT3_ACL_ACCESS5 0x3605
378#define KSZ9897_PORT3_ACL_ACCESS6 0x3606
379#define KSZ9897_PORT3_ACL_ACCESS7 0x3607
380#define KSZ9897_PORT3_ACL_ACCESS8 0x3608
381#define KSZ9897_PORT3_ACL_ACCESS9 0x3609
382#define KSZ9897_PORT3_ACL_ACCESS10 0x360A
383#define KSZ9897_PORT3_ACL_ACCESS11 0x360B
384#define KSZ9897_PORT3_ACL_ACCESS12 0x360C
385#define KSZ9897_PORT3_ACL_ACCESS13 0x360D
386#define KSZ9897_PORT3_ACL_ACCESS14 0x360E
387#define KSZ9897_PORT3_ACL_ACCESS15 0x360F
388#define KSZ9897_PORT3_ACL_BYTE_EN_MSB 0x3610
389#define KSZ9897_PORT3_ACL_BYTE_EN_LSB 0x3611
390#define KSZ9897_PORT3_ACL_ACCESS_CTRL0 0x3612
391#define KSZ9897_PORT3_MIRRORING_CTRL 0x3800
392#define KSZ9897_PORT3_PRIO_CTRL 0x3801
393#define KSZ9897_PORT3_IG_MAC_CTRL 0x3802
394#define KSZ9897_PORT3_AUTH_CTRL 0x3803
395#define KSZ9897_PORT3_PTR 0x3804
396#define KSZ9897_PORT3_PRIO_TO_QUEUE_MAPPING 0x3808
397#define KSZ9897_PORT3_POLICE_CTRL 0x380C
398#define KSZ9897_PORT3_POLICE_QUEUE_RATE 0x3820
399#define KSZ9897_PORT3_POLICE_QUEUE_BURST_SIZE 0x3824
400#define KSZ9897_PORT3_WRED_PKT_MEM_CTRL0 0x3830
401#define KSZ9897_PORT3_WRED_PKT_MEM_CTRL1 0x3834
402#define KSZ9897_PORT3_WRED_QUEUE_CTRL0 0x3840
403#define KSZ9897_PORT3_WRED_QUEUE_CTRL1 0x3844
404#define KSZ9897_PORT3_WRED_QUEUE_PERF_MON_CTRL 0x3848
405#define KSZ9897_PORT3_TX_QUEUE_INDEX 0x3900
406#define KSZ9897_PORT3_TX_QUEUE_PVID 0x3904
407#define KSZ9897_PORT3_TX_QUEUE_CTRL0 0x3914
408#define KSZ9897_PORT3_TX_QUEUE_CTRL1 0x3915
409#define KSZ9897_PORT3_CTRL0 0x3A00
410#define KSZ9897_PORT3_CTRL1 0x3A04
411#define KSZ9897_PORT3_CTRL2 0x3B00
412#define KSZ9897_PORT3_MSTP_PTR 0x3B01
413#define KSZ9897_PORT3_MSTP_STATE 0x3B04
414#define KSZ9897_PORT4_DEFAULT_TAG0 0x4000
415#define KSZ9897_PORT4_DEFAULT_TAG1 0x4001
416#define KSZ9897_PORT4_PME_WOL_EVENT 0x4013
417#define KSZ9897_PORT4_PME_WOL_EN 0x4017
418#define KSZ9897_PORT4_INT_STATUS 0x401B
419#define KSZ9897_PORT4_INT_MASK 0x401F
420#define KSZ9897_PORT4_OP_CTRL0 0x4020
421#define KSZ9897_PORT4_STATUS 0x4030
422#define KSZ9897_PORT4_MAC_CTRL0 0x4400
423#define KSZ9897_PORT4_MAC_CTRL1 0x4401
424#define KSZ9897_PORT4_IG_RATE_LIMIT_CTRL 0x4403
425#define KSZ9897_PORT4_PRIO0_IG_LIMIT_CTRL 0x4410
426#define KSZ9897_PORT4_PRIO1_IG_LIMIT_CTRL 0x4411
427#define KSZ9897_PORT4_PRIO2_IG_LIMIT_CTRL 0x4412
428#define KSZ9897_PORT4_PRIO3_IG_LIMIT_CTRL 0x4413
429#define KSZ9897_PORT4_PRIO4_IG_LIMIT_CTRL 0x4414
430#define KSZ9897_PORT4_PRIO5_IG_LIMIT_CTRL 0x4415
431#define KSZ9897_PORT4_PRIO6_IG_LIMIT_CTRL 0x4416
432#define KSZ9897_PORT4_PRIO7_IG_LIMIT_CTRL 0x4417
433#define KSZ9897_PORT4_QUEUE0_EG_LIMIT_CTRL 0x4420
434#define KSZ9897_PORT4_QUEUE1_EG_LIMIT_CTRL 0x4421
435#define KSZ9897_PORT4_QUEUE2_EG_LIMIT_CTRL 0x4422
436#define KSZ9897_PORT4_QUEUE3_EG_LIMIT_CTRL 0x4423
437#define KSZ9897_PORT4_MIB_CTRL_STAT 0x4500
438#define KSZ9897_PORT4_MIB_DATA 0x4504
439#define KSZ9897_PORT4_ACL_ACCESS0 0x4600
440#define KSZ9897_PORT4_ACL_ACCESS1 0x4601
441#define KSZ9897_PORT4_ACL_ACCESS2 0x4602
442#define KSZ9897_PORT4_ACL_ACCESS3 0x4603
443#define KSZ9897_PORT4_ACL_ACCESS4 0x4604
444#define KSZ9897_PORT4_ACL_ACCESS5 0x4605
445#define KSZ9897_PORT4_ACL_ACCESS6 0x4606
446#define KSZ9897_PORT4_ACL_ACCESS7 0x4607
447#define KSZ9897_PORT4_ACL_ACCESS8 0x4608
448#define KSZ9897_PORT4_ACL_ACCESS9 0x4609
449#define KSZ9897_PORT4_ACL_ACCESS10 0x460A
450#define KSZ9897_PORT4_ACL_ACCESS11 0x460B
451#define KSZ9897_PORT4_ACL_ACCESS12 0x460C
452#define KSZ9897_PORT4_ACL_ACCESS13 0x460D
453#define KSZ9897_PORT4_ACL_ACCESS14 0x460E
454#define KSZ9897_PORT4_ACL_ACCESS15 0x460F
455#define KSZ9897_PORT4_ACL_BYTE_EN_MSB 0x4610
456#define KSZ9897_PORT4_ACL_BYTE_EN_LSB 0x4611
457#define KSZ9897_PORT4_ACL_ACCESS_CTRL0 0x4612
458#define KSZ9897_PORT4_MIRRORING_CTRL 0x4800
459#define KSZ9897_PORT4_PRIO_CTRL 0x4801
460#define KSZ9897_PORT4_IG_MAC_CTRL 0x4802
461#define KSZ9897_PORT4_AUTH_CTRL 0x4803
462#define KSZ9897_PORT4_PTR 0x4804
463#define KSZ9897_PORT4_PRIO_TO_QUEUE_MAPPING 0x4808
464#define KSZ9897_PORT4_POLICE_CTRL 0x480C
465#define KSZ9897_PORT4_POLICE_QUEUE_RATE 0x4820
466#define KSZ9897_PORT4_POLICE_QUEUE_BURST_SIZE 0x4824
467#define KSZ9897_PORT4_WRED_PKT_MEM_CTRL0 0x4830
468#define KSZ9897_PORT4_WRED_PKT_MEM_CTRL1 0x4834
469#define KSZ9897_PORT4_WRED_QUEUE_CTRL0 0x4840
470#define KSZ9897_PORT4_WRED_QUEUE_CTRL1 0x4844
471#define KSZ9897_PORT4_WRED_QUEUE_PERF_MON_CTRL 0x4848
472#define KSZ9897_PORT4_TX_QUEUE_INDEX 0x4900
473#define KSZ9897_PORT4_TX_QUEUE_PVID 0x4904
474#define KSZ9897_PORT4_TX_QUEUE_CTRL0 0x4914
475#define KSZ9897_PORT4_TX_QUEUE_CTRL1 0x4915
476#define KSZ9897_PORT4_CTRL0 0x4A00
477#define KSZ9897_PORT4_CTRL1 0x4A04
478#define KSZ9897_PORT4_CTRL2 0x4B00
479#define KSZ9897_PORT4_MSTP_PTR 0x4B01
480#define KSZ9897_PORT4_MSTP_STATE 0x4B04
481#define KSZ9897_PORT5_DEFAULT_TAG0 0x5000
482#define KSZ9897_PORT5_DEFAULT_TAG1 0x5001
483#define KSZ9897_PORT5_PME_WOL_EVENT 0x5013
484#define KSZ9897_PORT5_PME_WOL_EN 0x5017
485#define KSZ9897_PORT5_INT_STATUS 0x501B
486#define KSZ9897_PORT5_INT_MASK 0x501F
487#define KSZ9897_PORT5_OP_CTRL0 0x5020
488#define KSZ9897_PORT5_STATUS 0x5030
489#define KSZ9897_PORT5_MAC_CTRL0 0x5400
490#define KSZ9897_PORT5_MAC_CTRL1 0x5401
491#define KSZ9897_PORT5_IG_RATE_LIMIT_CTRL 0x5403
492#define KSZ9897_PORT5_PRIO0_IG_LIMIT_CTRL 0x5410
493#define KSZ9897_PORT5_PRIO1_IG_LIMIT_CTRL 0x5411
494#define KSZ9897_PORT5_PRIO2_IG_LIMIT_CTRL 0x5412
495#define KSZ9897_PORT5_PRIO3_IG_LIMIT_CTRL 0x5413
496#define KSZ9897_PORT5_PRIO4_IG_LIMIT_CTRL 0x5414
497#define KSZ9897_PORT5_PRIO5_IG_LIMIT_CTRL 0x5415
498#define KSZ9897_PORT5_PRIO6_IG_LIMIT_CTRL 0x5416
499#define KSZ9897_PORT5_PRIO7_IG_LIMIT_CTRL 0x5417
500#define KSZ9897_PORT5_QUEUE0_EG_LIMIT_CTRL 0x5420
501#define KSZ9897_PORT5_QUEUE1_EG_LIMIT_CTRL 0x5421
502#define KSZ9897_PORT5_QUEUE2_EG_LIMIT_CTRL 0x5422
503#define KSZ9897_PORT5_QUEUE3_EG_LIMIT_CTRL 0x5423
504#define KSZ9897_PORT5_MIB_CTRL_STAT 0x5500
505#define KSZ9897_PORT5_MIB_DATA 0x5504
506#define KSZ9897_PORT5_ACL_ACCESS0 0x5600
507#define KSZ9897_PORT5_ACL_ACCESS1 0x5601
508#define KSZ9897_PORT5_ACL_ACCESS2 0x5602
509#define KSZ9897_PORT5_ACL_ACCESS3 0x5603
510#define KSZ9897_PORT5_ACL_ACCESS4 0x5604
511#define KSZ9897_PORT5_ACL_ACCESS5 0x5605
512#define KSZ9897_PORT5_ACL_ACCESS6 0x5606
513#define KSZ9897_PORT5_ACL_ACCESS7 0x5607
514#define KSZ9897_PORT5_ACL_ACCESS8 0x5608
515#define KSZ9897_PORT5_ACL_ACCESS9 0x5609
516#define KSZ9897_PORT5_ACL_ACCESS10 0x560A
517#define KSZ9897_PORT5_ACL_ACCESS11 0x560B
518#define KSZ9897_PORT5_ACL_ACCESS12 0x560C
519#define KSZ9897_PORT5_ACL_ACCESS13 0x560D
520#define KSZ9897_PORT5_ACL_ACCESS14 0x560E
521#define KSZ9897_PORT5_ACL_ACCESS15 0x560F
522#define KSZ9897_PORT5_ACL_BYTE_EN_MSB 0x5610
523#define KSZ9897_PORT5_ACL_BYTE_EN_LSB 0x5611
524#define KSZ9897_PORT5_ACL_ACCESS_CTRL0 0x5612
525#define KSZ9897_PORT5_MIRRORING_CTRL 0x5800
526#define KSZ9897_PORT5_PRIO_CTRL 0x5801
527#define KSZ9897_PORT5_IG_MAC_CTRL 0x5802
528#define KSZ9897_PORT5_AUTH_CTRL 0x5803
529#define KSZ9897_PORT5_PTR 0x5804
530#define KSZ9897_PORT5_PRIO_TO_QUEUE_MAPPING 0x5808
531#define KSZ9897_PORT5_POLICE_CTRL 0x580C
532#define KSZ9897_PORT5_POLICE_QUEUE_RATE 0x5820
533#define KSZ9897_PORT5_POLICE_QUEUE_BURST_SIZE 0x5824
534#define KSZ9897_PORT5_WRED_PKT_MEM_CTRL0 0x5830
535#define KSZ9897_PORT5_WRED_PKT_MEM_CTRL1 0x5834
536#define KSZ9897_PORT5_WRED_QUEUE_CTRL0 0x5840
537#define KSZ9897_PORT5_WRED_QUEUE_CTRL1 0x5844
538#define KSZ9897_PORT5_WRED_QUEUE_PERF_MON_CTRL 0x5848
539#define KSZ9897_PORT5_TX_QUEUE_INDEX 0x5900
540#define KSZ9897_PORT5_TX_QUEUE_PVID 0x5904
541#define KSZ9897_PORT5_TX_QUEUE_CTRL0 0x5914
542#define KSZ9897_PORT5_TX_QUEUE_CTRL1 0x5915
543#define KSZ9897_PORT5_CTRL0 0x5A00
544#define KSZ9897_PORT5_CTRL1 0x5A04
545#define KSZ9897_PORT5_CTRL2 0x5B00
546#define KSZ9897_PORT5_MSTP_PTR 0x5B01
547#define KSZ9897_PORT5_MSTP_STATE 0x5B04
548#define KSZ9897_PORT6_DEFAULT_TAG0 0x6000
549#define KSZ9897_PORT6_DEFAULT_TAG1 0x6001
550#define KSZ9897_PORT6_PME_WOL_EVENT 0x6013
551#define KSZ9897_PORT6_PME_WOL_EN 0x6017
552#define KSZ9897_PORT6_INT_STATUS 0x601B
553#define KSZ9897_PORT6_INT_MASK 0x601F
554#define KSZ9897_PORT6_OP_CTRL0 0x6020
555#define KSZ9897_PORT6_STATUS 0x6030
556#define KSZ9897_PORT6_XMII_CTRL0 0x6300
557#define KSZ9897_PORT6_XMII_CTRL1 0x6301
558#define KSZ9897_PORT6_MAC_CTRL0 0x6400
559#define KSZ9897_PORT6_MAC_CTRL1 0x6401
560#define KSZ9897_PORT6_IG_RATE_LIMIT_CTRL 0x6403
561#define KSZ9897_PORT6_PRIO0_IG_LIMIT_CTRL 0x6410
562#define KSZ9897_PORT6_PRIO1_IG_LIMIT_CTRL 0x6411
563#define KSZ9897_PORT6_PRIO2_IG_LIMIT_CTRL 0x6412
564#define KSZ9897_PORT6_PRIO3_IG_LIMIT_CTRL 0x6413
565#define KSZ9897_PORT6_PRIO4_IG_LIMIT_CTRL 0x6414
566#define KSZ9897_PORT6_PRIO5_IG_LIMIT_CTRL 0x6415
567#define KSZ9897_PORT6_PRIO6_IG_LIMIT_CTRL 0x6416
568#define KSZ9897_PORT6_PRIO7_IG_LIMIT_CTRL 0x6417
569#define KSZ9897_PORT6_QUEUE0_EG_LIMIT_CTRL 0x6420
570#define KSZ9897_PORT6_QUEUE1_EG_LIMIT_CTRL 0x6421
571#define KSZ9897_PORT6_QUEUE2_EG_LIMIT_CTRL 0x6422
572#define KSZ9897_PORT6_QUEUE3_EG_LIMIT_CTRL 0x6423
573#define KSZ9897_PORT6_MIB_CTRL_STAT 0x6500
574#define KSZ9897_PORT6_MIB_DATA 0x6504
575#define KSZ9897_PORT6_ACL_ACCESS0 0x6600
576#define KSZ9897_PORT6_ACL_ACCESS1 0x6601
577#define KSZ9897_PORT6_ACL_ACCESS2 0x6602
578#define KSZ9897_PORT6_ACL_ACCESS3 0x6603
579#define KSZ9897_PORT6_ACL_ACCESS4 0x6604
580#define KSZ9897_PORT6_ACL_ACCESS5 0x6605
581#define KSZ9897_PORT6_ACL_ACCESS6 0x6606
582#define KSZ9897_PORT6_ACL_ACCESS7 0x6607
583#define KSZ9897_PORT6_ACL_ACCESS8 0x6608
584#define KSZ9897_PORT6_ACL_ACCESS9 0x6609
585#define KSZ9897_PORT6_ACL_ACCESS10 0x660A
586#define KSZ9897_PORT6_ACL_ACCESS11 0x660B
587#define KSZ9897_PORT6_ACL_ACCESS12 0x660C
588#define KSZ9897_PORT6_ACL_ACCESS13 0x660D
589#define KSZ9897_PORT6_ACL_ACCESS14 0x660E
590#define KSZ9897_PORT6_ACL_ACCESS15 0x660F
591#define KSZ9897_PORT6_ACL_BYTE_EN_MSB 0x6610
592#define KSZ9897_PORT6_ACL_BYTE_EN_LSB 0x6611
593#define KSZ9897_PORT6_ACL_ACCESS_CTRL0 0x6612
594#define KSZ9897_PORT6_MIRRORING_CTRL 0x6800
595#define KSZ9897_PORT6_PRIO_CTRL 0x6801
596#define KSZ9897_PORT6_IG_MAC_CTRL 0x6802
597#define KSZ9897_PORT6_AUTH_CTRL 0x6803
598#define KSZ9897_PORT6_PTR 0x6804
599#define KSZ9897_PORT6_PRIO_TO_QUEUE_MAPPING 0x6808
600#define KSZ9897_PORT6_POLICE_CTRL 0x680C
601#define KSZ9897_PORT6_POLICE_QUEUE_RATE 0x6820
602#define KSZ9897_PORT6_POLICE_QUEUE_BURST_SIZE 0x6824
603#define KSZ9897_PORT6_WRED_PKT_MEM_CTRL0 0x6830
604#define KSZ9897_PORT6_WRED_PKT_MEM_CTRL1 0x6834
605#define KSZ9897_PORT6_WRED_QUEUE_CTRL0 0x6840
606#define KSZ9897_PORT6_WRED_QUEUE_CTRL1 0x6844
607#define KSZ9897_PORT6_WRED_QUEUE_PERF_MON_CTRL 0x6848
608#define KSZ9897_PORT6_TX_QUEUE_INDEX 0x6900
609#define KSZ9897_PORT6_TX_QUEUE_PVID 0x6904
610#define KSZ9897_PORT6_TX_QUEUE_CTRL0 0x6914
611#define KSZ9897_PORT6_TX_QUEUE_CTRL1 0x6915
612#define KSZ9897_PORT6_CTRL0 0x6A00
613#define KSZ9897_PORT6_CTRL1 0x6A04
614#define KSZ9897_PORT6_CTRL2 0x6B00
615#define KSZ9897_PORT6_MSTP_PTR 0x6B01
616#define KSZ9897_PORT6_MSTP_STATE 0x6B04
617#define KSZ9897_PORT7_DEFAULT_TAG0 0x7000
618#define KSZ9897_PORT7_DEFAULT_TAG1 0x7001
619#define KSZ9897_PORT7_PME_WOL_EVENT 0x7013
620#define KSZ9897_PORT7_PME_WOL_EN 0x7017
621#define KSZ9897_PORT7_INT_STATUS 0x701B
622#define KSZ9897_PORT7_INT_MASK 0x701F
623#define KSZ9897_PORT7_OP_CTRL0 0x7020
624#define KSZ9897_PORT7_STATUS 0x7030
625#define KSZ9897_PORT7_SGMII_ADDR 0x7200
626#define KSZ9897_PORT7_SGMII_DATA 0x7206
627#define KSZ9897_PORT7_XMII_CTRL0 0x7300
628#define KSZ9897_PORT7_XMII_CTRL1 0x7301
629#define KSZ9897_PORT7_MAC_CTRL0 0x7400
630#define KSZ9897_PORT7_MAC_CTRL1 0x7401
631#define KSZ9897_PORT7_IG_RATE_LIMIT_CTRL 0x7403
632#define KSZ9897_PORT7_PRIO0_IG_LIMIT_CTRL 0x7410
633#define KSZ9897_PORT7_PRIO1_IG_LIMIT_CTRL 0x7411
634#define KSZ9897_PORT7_PRIO2_IG_LIMIT_CTRL 0x7412
635#define KSZ9897_PORT7_PRIO3_IG_LIMIT_CTRL 0x7413
636#define KSZ9897_PORT7_PRIO4_IG_LIMIT_CTRL 0x7414
637#define KSZ9897_PORT7_PRIO5_IG_LIMIT_CTRL 0x7415
638#define KSZ9897_PORT7_PRIO6_IG_LIMIT_CTRL 0x7416
639#define KSZ9897_PORT7_PRIO7_IG_LIMIT_CTRL 0x7417
640#define KSZ9897_PORT7_QUEUE0_EG_LIMIT_CTRL 0x7420
641#define KSZ9897_PORT7_QUEUE1_EG_LIMIT_CTRL 0x7421
642#define KSZ9897_PORT7_QUEUE2_EG_LIMIT_CTRL 0x7422
643#define KSZ9897_PORT7_QUEUE3_EG_LIMIT_CTRL 0x7423
644#define KSZ9897_PORT7_MIB_CTRL_STAT 0x7500
645#define KSZ9897_PORT7_MIB_DATA 0x7504
646#define KSZ9897_PORT7_ACL_ACCESS0 0x7600
647#define KSZ9897_PORT7_ACL_ACCESS1 0x7601
648#define KSZ9897_PORT7_ACL_ACCESS2 0x7602
649#define KSZ9897_PORT7_ACL_ACCESS3 0x7603
650#define KSZ9897_PORT7_ACL_ACCESS4 0x7604
651#define KSZ9897_PORT7_ACL_ACCESS5 0x7605
652#define KSZ9897_PORT7_ACL_ACCESS6 0x7606
653#define KSZ9897_PORT7_ACL_ACCESS7 0x7607
654#define KSZ9897_PORT7_ACL_ACCESS8 0x7608
655#define KSZ9897_PORT7_ACL_ACCESS9 0x7609
656#define KSZ9897_PORT7_ACL_ACCESS10 0x760A
657#define KSZ9897_PORT7_ACL_ACCESS11 0x760B
658#define KSZ9897_PORT7_ACL_ACCESS12 0x760C
659#define KSZ9897_PORT7_ACL_ACCESS13 0x760D
660#define KSZ9897_PORT7_ACL_ACCESS14 0x760E
661#define KSZ9897_PORT7_ACL_ACCESS15 0x760F
662#define KSZ9897_PORT7_ACL_BYTE_EN_MSB 0x7610
663#define KSZ9897_PORT7_ACL_BYTE_EN_LSB 0x7611
664#define KSZ9897_PORT7_ACL_ACCESS_CTRL0 0x7612
665#define KSZ9897_PORT7_MIRRORING_CTRL 0x7800
666#define KSZ9897_PORT7_PRIO_CTRL 0x7801
667#define KSZ9897_PORT7_IG_MAC_CTRL 0x7802
668#define KSZ9897_PORT7_AUTH_CTRL 0x7803
669#define KSZ9897_PORT7_PTR 0x7804
670#define KSZ9897_PORT7_PRIO_TO_QUEUE_MAPPING 0x7808
671#define KSZ9897_PORT7_POLICE_CTRL 0x780C
672#define KSZ9897_PORT7_POLICE_QUEUE_RATE 0x7820
673#define KSZ9897_PORT7_POLICE_QUEUE_BURST_SIZE 0x7824
674#define KSZ9897_PORT7_WRED_PKT_MEM_CTRL0 0x7830
675#define KSZ9897_PORT7_WRED_PKT_MEM_CTRL1 0x7834
676#define KSZ9897_PORT7_WRED_QUEUE_CTRL0 0x7840
677#define KSZ9897_PORT7_WRED_QUEUE_CTRL1 0x7844
678#define KSZ9897_PORT7_WRED_QUEUE_PERF_MON_CTRL 0x7848
679#define KSZ9897_PORT7_TX_QUEUE_INDEX 0x7900
680#define KSZ9897_PORT7_TX_QUEUE_PVID 0x7904
681#define KSZ9897_PORT7_TX_QUEUE_CTRL0 0x7914
682#define KSZ9897_PORT7_TX_QUEUE_CTRL1 0x7915
683#define KSZ9897_PORT7_CTRL0 0x7A00
684#define KSZ9897_PORT7_CTRL1 0x7A04
685#define KSZ9897_PORT7_CTRL2 0x7B00
686#define KSZ9897_PORT7_MSTP_PTR 0x7B01
687#define KSZ9897_PORT7_MSTP_STATE 0x7B04
688
689//KSZ9897 Switch register access macros
690#define KSZ9897_PORTn_DEFAULT_TAG0(port) (0x0000 + ((port) * 0x1000))
691#define KSZ9897_PORTn_DEFAULT_TAG1(port) (0x0001 + ((port) * 0x1000))
692#define KSZ9897_PORTn_PME_WOL_EVENT(port) (0x0013 + ((port) * 0x1000))
693#define KSZ9897_PORTn_PME_WOL_EN(port) (0x0017 + ((port) * 0x1000))
694#define KSZ9897_PORTn_INT_STATUS(port) (0x001B + ((port) * 0x1000))
695#define KSZ9897_PORTn_INT_MASK(port) (0x001F + ((port) * 0x1000))
696#define KSZ9897_PORTn_OP_CTRL0(port) (0x0020 + ((port) * 0x1000))
697#define KSZ9897_PORTn_STATUS(port) (0x0030 + ((port) * 0x1000))
698#define KSZ9897_PORTn_XMII_CTRL0(port) (0x0300 + ((port) * 0x1000))
699#define KSZ9897_PORTn_XMII_CTRL1(port) (0x0301 + ((port) * 0x1000))
700#define KSZ9897_PORTn_MAC_CTRL0(port) (0x0400 + ((port) * 0x1000))
701#define KSZ9897_PORTn_MAC_CTRL1(port) (0x0401 + ((port) * 0x1000))
702#define KSZ9897_PORTn_IG_RATE_LIMIT_CTRL(port) (0x0403 + ((port) * 0x1000))
703#define KSZ9897_PORTn_PRIO0_IG_LIMIT_CTRL(port) (0x0410 + ((port) * 0x1000))
704#define KSZ9897_PORTn_PRIO1_IG_LIMIT_CTRL(port) (0x0411 + ((port) * 0x1000))
705#define KSZ9897_PORTn_PRIO2_IG_LIMIT_CTRL(port) (0x0412 + ((port) * 0x1000))
706#define KSZ9897_PORTn_PRIO3_IG_LIMIT_CTRL(port) (0x0413 + ((port) * 0x1000))
707#define KSZ9897_PORTn_PRIO4_IG_LIMIT_CTRL(port) (0x0414 + ((port) * 0x1000))
708#define KSZ9897_PORTn_PRIO5_IG_LIMIT_CTRL(port) (0x0415 + ((port) * 0x1000))
709#define KSZ9897_PORTn_PRIO6_IG_LIMIT_CTRL(port) (0x0416 + ((port) * 0x1000))
710#define KSZ9897_PORTn_PRIO7_IG_LIMIT_CTRL(port) (0x0417 + ((port) * 0x1000))
711#define KSZ9897_PORTn_QUEUE0_EG_LIMIT_CTRL(port) (0x0420 + ((port) * 0x1000))
712#define KSZ9897_PORTn_QUEUE1_EG_LIMIT_CTRL(port) (0x0421 + ((port) * 0x1000))
713#define KSZ9897_PORTn_QUEUE2_EG_LIMIT_CTRL(port) (0x0422 + ((port) * 0x1000))
714#define KSZ9897_PORTn_QUEUE3_EG_LIMIT_CTRL(port) (0x0423 + ((port) * 0x1000))
715#define KSZ9897_PORTn_MIB_CTRL_STAT(port) (0x0500 + ((port) * 0x1000))
716#define KSZ9897_PORTn_MIB_DATA(port) (0x0504 + ((port) * 0x1000))
717#define KSZ9897_PORTn_ACL_ACCESS0(port) (0x0600 + ((port) * 0x1000))
718#define KSZ9897_PORTn_ACL_ACCESS1(port) (0x0601 + ((port) * 0x1000))
719#define KSZ9897_PORTn_ACL_ACCESS2(port) (0x0602 + ((port) * 0x1000))
720#define KSZ9897_PORTn_ACL_ACCESS3(port) (0x0603 + ((port) * 0x1000))
721#define KSZ9897_PORTn_ACL_ACCESS4(port) (0x0604 + ((port) * 0x1000))
722#define KSZ9897_PORTn_ACL_ACCESS5(port) (0x0605 + ((port) * 0x1000))
723#define KSZ9897_PORTn_ACL_ACCESS6(port) (0x0606 + ((port) * 0x1000))
724#define KSZ9897_PORTn_ACL_ACCESS7(port) (0x0607 + ((port) * 0x1000))
725#define KSZ9897_PORTn_ACL_ACCESS8(port) (0x0608 + ((port) * 0x1000))
726#define KSZ9897_PORTn_ACL_ACCESS9(port) (0x0609 + ((port) * 0x1000))
727#define KSZ9897_PORTn_ACL_ACCESS10(port) (0x060A + ((port) * 0x1000))
728#define KSZ9897_PORTn_ACL_ACCESS11(port) (0x060B + ((port) * 0x1000))
729#define KSZ9897_PORTn_ACL_ACCESS12(port) (0x060C + ((port) * 0x1000))
730#define KSZ9897_PORTn_ACL_ACCESS13(port) (0x060D + ((port) * 0x1000))
731#define KSZ9897_PORTn_ACL_ACCESS14(port) (0x060E + ((port) * 0x1000))
732#define KSZ9897_PORTn_ACL_ACCESS15(port) (0x060F + ((port) * 0x1000))
733#define KSZ9897_PORTn_ACL_BYTE_EN_MSB(port) (0x0610 + ((port) * 0x1000))
734#define KSZ9897_PORTn_ACL_BYTE_EN_LSB(port) (0x0611 + ((port) * 0x1000))
735#define KSZ9897_PORTn_ACL_ACCESS_CTRL0(port) (0x0612 + ((port) * 0x1000))
736#define KSZ9897_PORTn_MIRRORING_CTRL(port) (0x0800 + ((port) * 0x1000))
737#define KSZ9897_PORTn_PRIO_CTRL(port) (0x0801 + ((port) * 0x1000))
738#define KSZ9897_PORTn_IG_MAC_CTRL(port) (0x0802 + ((port) * 0x1000))
739#define KSZ9897_PORTn_AUTH_CTRL(port) (0x0803 + ((port) * 0x1000))
740#define KSZ9897_PORTn_PTR(port) (0x0804 + ((port) * 0x1000))
741#define KSZ9897_PORTn_PRIO_TO_QUEUE_MAPPING(port) (0x0808 + ((port) * 0x1000))
742#define KSZ9897_PORTn_POLICE_CTRL(port) (0x080C + ((port) * 0x1000))
743#define KSZ9897_PORTn_POLICE_QUEUE_RATE(port) (0x0820 + ((port) * 0x1000))
744#define KSZ9897_PORTn_POLICE_QUEUE_BURST_SIZE(port) (0x0824 + ((port) * 0x1000))
745#define KSZ9897_PORTn_WRED_PKT_MEM_CTRL0(port) (0x0830 + ((port) * 0x1000))
746#define KSZ9897_PORTn_WRED_PKT_MEM_CTRL1(port) (0x0834 + ((port) * 0x1000))
747#define KSZ9897_PORTn_WRED_QUEUE_CTRL0(port) (0x0840 + ((port) * 0x1000))
748#define KSZ9897_PORTn_WRED_QUEUE_CTRL1(port) (0x0844 + ((port) * 0x1000))
749#define KSZ9897_PORTn_WRED_QUEUE_PERF_MON_CTRL(port) (0x0848 + ((port) * 0x1000))
750#define KSZ9897_PORTn_TX_QUEUE_INDEX(port) (0x0900 + ((port) * 0x1000))
751#define KSZ9897_PORTn_TX_QUEUE_PVID(port) (0x0904 + ((port) * 0x1000))
752#define KSZ9897_PORTn_TX_QUEUE_CTRL0(port) (0x0914 + ((port) * 0x1000))
753#define KSZ9897_PORTn_TX_QUEUE_CTRL1(port) (0x0915 + ((port) * 0x1000))
754#define KSZ9897_PORTn_CTRL0(port) (0x0A00 + ((port) * 0x1000))
755#define KSZ9897_PORTn_CTRL1(port) (0x0A04 + ((port) * 0x1000))
756#define KSZ9897_PORTn_CTRL2(port) (0x0B00 + ((port) * 0x1000))
757#define KSZ9897_PORTn_MSTP_PTR(port) (0x0B01 + ((port) * 0x1000))
758#define KSZ9897_PORTn_MSTP_STATE(port) (0x0B04 + ((port) * 0x1000))
759#define KSZ9897_PORTn_ETH_PHY_REG(port, addr) (0x0100 + ((port) * 0x1000) + ((addr) * 2))
760
761//PHY Basic Control register
762#define KSZ9897_BMCR_RESET 0x8000
763#define KSZ9897_BMCR_LOOPBACK 0x4000
764#define KSZ9897_BMCR_SPEED_SEL_LSB 0x2000
765#define KSZ9897_BMCR_AN_EN 0x1000
766#define KSZ9897_BMCR_POWER_DOWN 0x0800
767#define KSZ9897_BMCR_ISOLATE 0x0400
768#define KSZ9897_BMCR_RESTART_AN 0x0200
769#define KSZ9897_BMCR_DUPLEX_MODE 0x0100
770#define KSZ9897_BMCR_COL_TEST 0x0080
771#define KSZ9897_BMCR_SPEED_SEL_MSB 0x0040
772
773//PHY Basic Status register
774#define KSZ9897_BMSR_100BT4 0x8000
775#define KSZ9897_BMSR_100BTX_FD 0x4000
776#define KSZ9897_BMSR_100BTX_HD 0x2000
777#define KSZ9897_BMSR_10BT_FD 0x1000
778#define KSZ9897_BMSR_10BT_HD 0x0800
779#define KSZ9897_BMSR_EXTENDED_STATUS 0x0100
780#define KSZ9897_BMSR_MF_PREAMBLE_SUPPR 0x0040
781#define KSZ9897_BMSR_AN_COMPLETE 0x0020
782#define KSZ9897_BMSR_REMOTE_FAULT 0x0010
783#define KSZ9897_BMSR_AN_CAPABLE 0x0008
784#define KSZ9897_BMSR_LINK_STATUS 0x0004
785#define KSZ9897_BMSR_JABBER_DETECT 0x0002
786#define KSZ9897_BMSR_EXTENDED_CAPABLE 0x0001
787
788//PHY ID High register
789#define KSZ9897_PHYID1_DEFAULT 0x0022
790
791//PHY ID Low register
792#define KSZ9897_PHYID2_DEFAULT 0x1631
793
794//PHY Auto-Negotiation Advertisement register
795#define KSZ9897_ANAR_NEXT_PAGE 0x8000
796#define KSZ9897_ANAR_REMOTE_FAULT 0x2000
797#define KSZ9897_ANAR_PAUSE 0x0C00
798#define KSZ9897_ANAR_100BT4 0x0200
799#define KSZ9897_ANAR_100BTX_FD 0x0100
800#define KSZ9897_ANAR_100BTX_HD 0x0080
801#define KSZ9897_ANAR_10BT_FD 0x0040
802#define KSZ9897_ANAR_10BT_HD 0x0020
803#define KSZ9897_ANAR_SELECTOR 0x001F
804#define KSZ9897_ANAR_SELECTOR_DEFAULT 0x0001
805
806//PHY Auto-Negotiation Link Partner Ability register
807#define KSZ9897_ANLPAR_NEXT_PAGE 0x8000
808#define KSZ9897_ANLPAR_ACK 0x4000
809#define KSZ9897_ANLPAR_REMOTE_FAULT 0x2000
810#define KSZ9897_ANLPAR_PAUSE 0x0C00
811#define KSZ9897_ANLPAR_100BT4 0x0200
812#define KSZ9897_ANLPAR_100BTX_FD 0x0100
813#define KSZ9897_ANLPAR_100BTX_HD 0x0080
814#define KSZ9897_ANLPAR_10BT_FD 0x0040
815#define KSZ9897_ANLPAR_10BT_HD 0x0020
816#define KSZ9897_ANLPAR_SELECTOR 0x001F
817#define KSZ9897_ANLPAR_SELECTOR_DEFAULT 0x0001
818
819//PHY Auto-Negotiation Expansion Status register
820#define KSZ9897_ANER_PAR_DETECT_FAULT 0x0010
821#define KSZ9897_ANER_LP_NEXT_PAGE_ABLE 0x0008
822#define KSZ9897_ANER_NEXT_PAGE_ABLE 0x0004
823#define KSZ9897_ANER_PAGE_RECEIVED 0x0002
824#define KSZ9897_ANER_LP_AN_ABLE 0x0001
825
826//PHY Auto-Negotiation Next Page register
827#define KSZ9897_ANNPR_NEXT_PAGE 0x8000
828#define KSZ9897_ANNPR_MSG_PAGE 0x2000
829#define KSZ9897_ANNPR_ACK2 0x1000
830#define KSZ9897_ANNPR_TOGGLE 0x0800
831#define KSZ9897_ANNPR_MESSAGE 0x07FF
832
833//PHY Auto-Negotiation Link Partner Next Page Ability register
834#define KSZ9897_ANLPNPR_NEXT_PAGE 0x8000
835#define KSZ9897_ANLPNPR_ACK 0x4000
836#define KSZ9897_ANLPNPR_MSG_PAGE 0x2000
837#define KSZ9897_ANLPNPR_ACK2 0x1000
838#define KSZ9897_ANLPNPR_TOGGLE 0x0800
839#define KSZ9897_ANLPNPR_MESSAGE 0x07FF
840
841//PHY 1000BASE-T Control register
842#define KSZ9897_GBCR_TEST_MODE 0xE000
843#define KSZ9897_GBCR_MS_MAN_CONF_EN 0x1000
844#define KSZ9897_GBCR_MS_MAN_CONF_VAL 0x0800
845#define KSZ9897_GBCR_PORT_TYPE 0x0400
846#define KSZ9897_GBCR_1000BT_FD 0x0200
847#define KSZ9897_GBCR_1000BT_HD 0x0100
848
849//PHY 1000BASE-T Status register
850#define KSZ9897_GBSR_MS_CONF_FAULT 0x8000
851#define KSZ9897_GBSR_MS_CONF_RES 0x4000
852#define KSZ9897_GBSR_LOCAL_RECEIVER_STATUS 0x2000
853#define KSZ9897_GBSR_REMOTE_RECEIVER_STATUS 0x1000
854#define KSZ9897_GBSR_LP_1000BT_FD 0x0800
855#define KSZ9897_GBSR_LP_1000BT_HD 0x0400
856#define KSZ9897_GBSR_IDLE_ERR_COUNT 0x00FF
857
858//PHY MMD Setup register
859#define KSZ9897_MMDACR_FUNC 0xC000
860#define KSZ9897_MMDACR_FUNC_ADDR 0x0000
861#define KSZ9897_MMDACR_FUNC_DATA_NO_POST_INC 0x4000
862#define KSZ9897_MMDACR_FUNC_DATA_POST_INC_RW 0x8000
863#define KSZ9897_MMDACR_FUNC_DATA_POST_INC_W 0xC000
864#define KSZ9897_MMDACR_DEVAD 0x001F
865
866//PHY Extended Status register
867#define KSZ9897_GBESR_1000BX_FD 0x8000
868#define KSZ9897_GBESR_1000BX_HD 0x4000
869#define KSZ9897_GBESR_1000BT_FD 0x2000
870#define KSZ9897_GBESR_1000BT_HD 0x1000
871
872//PHY Remote Loopback register
873#define KSZ9897_RLB_REMOTE_LOOPBACK 0x0100
874
875//PHY LinkMD register
876#define KSZ9897_LINKMD_TEST_EN 0x8000
877#define KSZ9897_LINKMD_PAIR 0x3000
878#define KSZ9897_LINKMD_PAIR_A 0x0000
879#define KSZ9897_LINKMD_PAIR_B 0x1000
880#define KSZ9897_LINKMD_PAIR_C 0x2000
881#define KSZ9897_LINKMD_PAIR_D 0x3000
882#define KSZ9897_LINKMD_STATUS 0x0300
883#define KSZ9897_LINKMD_STATUS_NORMAL 0x0000
884#define KSZ9897_LINKMD_STATUS_OPEN 0x0100
885#define KSZ9897_LINKMD_STATUS_SHORT 0x0200
886#define KSZ9897_LINKMD_RESULT 0x00FF
887
888//PHY Digital PMA/PCS Status register
889#define KSZ9897_DPMAPCSS_1000BT_LINK_STATUS 0x0002
890#define KSZ9897_DPMAPCSS_100BTX_LINK_STATUS 0x0001
891
892//Port Interrupt Control/Status register
893#define KSZ9897_ICSR_JABBER_IE 0x8000
894#define KSZ9897_ICSR_RECEIVE_ERROR_IE 0x4000
895#define KSZ9897_ICSR_PAGE_RECEIVED_IE 0x2000
896#define KSZ9897_ICSR_PAR_DETECT_FAULT_IE 0x1000
897#define KSZ9897_ICSR_LP_ACK_IE 0x0800
898#define KSZ9897_ICSR_LINK_DOWN_IE 0x0400
899#define KSZ9897_ICSR_REMOTE_FAULT_IE 0x0200
900#define KSZ9897_ICSR_LINK_UP_IE 0x0100
901#define KSZ9897_ICSR_JABBER_IF 0x0080
902#define KSZ9897_ICSR_RECEIVE_ERROR_IF 0x0040
903#define KSZ9897_ICSR_PAGE_RECEIVED_IF 0x0020
904#define KSZ9897_ICSR_PAR_DETECT_FAULT_IF 0x0010
905#define KSZ9897_ICSR_LP_ACK_IF 0x0008
906#define KSZ9897_ICSR_LINK_DOWN_IF 0x0004
907#define KSZ9897_ICSR_REMOTE_FAULT_IF 0x0002
908#define KSZ9897_ICSR_LINK_UP_IF 0x0001
909
910//PHY Auto MDI/MDI-X register
911#define KSZ9897_AUTOMDI_MDI_SET 0x0080
912#define KSZ9897_AUTOMDI_SWAP_OFF 0x0040
913
914//PHY Control register
915#define KSZ9897_PHYCON_JABBER_EN 0x0200
916#define KSZ9897_PHYCON_SPEED_1000BT 0x0040
917#define KSZ9897_PHYCON_SPEED_100BTX 0x0020
918#define KSZ9897_PHYCON_SPEED_10BT 0x0010
919#define KSZ9897_PHYCON_DUPLEX_STATUS 0x0008
920#define KSZ9897_PHYCON_1000BT_MS_STATUS 0x0004
921
922//MMD LED Mode register
923#define KSZ9897_MMD_LED_MODE_LED_MODE 0x0010
924#define KSZ9897_MMD_LED_MODE_LED_MODE_TRI_COLOR_DUAL 0x0000
925#define KSZ9897_MMD_LED_MODE_LED_MODE_SINGLE 0x0010
926#define KSZ9897_MMD_LED_MODE_RESERVED 0x000F
927#define KSZ9897_MMD_LED_MODE_RESERVED_DEFAULT 0x0001
928
929//MMD EEE Advertisement register
930#define KSZ9897_MMD_EEE_ADV_1000BT_EEE_EN 0x0004
931#define KSZ9897_MMD_EEE_ADV_100BT_EEE_EN 0x0002
932
933//Global Chip ID 0 register
934#define KSZ9897_CHIP_ID0_DEFAULT 0x00
935
936//Global Chip ID 1 register
937#define KSZ9897_CHIP_ID1_DEFAULT 0x98
938
939//Global Chip ID 2 register
940#define KSZ9897_CHIP_ID2_DEFAULT 0x97
941
942//Global Chip ID 3 register
943#define KSZ9897_CHIP_ID3_REVISION_ID 0xF0
944#define KSZ9897_CHIP_ID3_GLOBAL_SOFT_RESET 0x01
945
946//PME Pin Control register
947#define KSZ9897_PME_PIN_CTRL_PME_PIN_OUT_EN 0x02
948#define KSZ9897_PME_PIN_CTRL_PME_PIN_OUT_POL 0x01
949
950//Global Interrupt Status register
951#define KSZ9897_GLOBAL_INT_STAT_LUE 0x80000000
952
953//Global Interrupt Mask register
954#define KSZ9897_GLOBAL_INT_MASK_LUE 0x80000000
955
956//Global Port Interrupt Status register
957#define KSZ9897_GLOBAL_PORT_INT_STAT_PORT7 0x00000040
958#define KSZ9897_GLOBAL_PORT_INT_STAT_PORT6 0x00000020
959#define KSZ9897_GLOBAL_PORT_INT_STAT_PORT5 0x00000010
960#define KSZ9897_GLOBAL_PORT_INT_STAT_PORT4 0x00000008
961#define KSZ9897_GLOBAL_PORT_INT_STAT_PORT3 0x00000004
962#define KSZ9897_GLOBAL_PORT_INT_STAT_PORT2 0x00000002
963#define KSZ9897_GLOBAL_PORT_INT_STAT_PORT1 0x00000001
964
965//Global Port Interrupt Mask register
966#define KSZ9897_GLOBAL_PORT_INT_MASK_PORT7 0x00000040
967#define KSZ9897_GLOBAL_PORT_INT_MASK_PORT6 0x00000020
968#define KSZ9897_GLOBAL_PORT_INT_MASK_PORT5 0x00000010
969#define KSZ9897_GLOBAL_PORT_INT_MASK_PORT4 0x00000008
970#define KSZ9897_GLOBAL_PORT_INT_MASK_PORT3 0x00000004
971#define KSZ9897_GLOBAL_PORT_INT_MASK_PORT2 0x00000002
972#define KSZ9897_GLOBAL_PORT_INT_MASK_PORT1 0x00000001
973
974//Serial I/O Control register
975#define KSZ9897_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPR 0x04
976#define KSZ9897_SERIAL_IO_CTRL_AUTO_SPI_DATA_OUT_EDGE_SEL 0x02
977#define KSZ9897_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL 0x01
978#define KSZ9897_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL_FALLING 0x00
979#define KSZ9897_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL_RISING 0x01
980
981//Output Clock Control register
982#define KSZ9897_OUT_CLK_CTRL_CLKO_25_125_EN 0x02
983#define KSZ9897_OUT_CLK_CTRL_CLKO_25_125_FREQ 0x01
984#define KSZ9897_OUT_CLK_CTRL_CLKO_25_125_FREQ_25MHZ 0x00
985#define KSZ9897_OUT_CLK_CTRL_CLKO_25_125_FREQ_125MHZ 0x01
986
987//In-Band Management Control register
988#define KSZ9897_IBA_CTRL_IBA_EN 0x80000000
989#define KSZ9897_IBA_CTRL_DEST_MAC_ADDR_MATCH_EN 0x40000000
990#define KSZ9897_IBA_CTRL_IBA_RESET 0x20000000
991#define KSZ9897_IBA_CTRL_RESP_PRIO_QUEUE 0x00C00000
992#define KSZ9897_IBA_CTRL_RESP_PRIO_QUEUE_DEFAULT 0x00400000
993#define KSZ9897_IBA_CTRL_IBA_COMM 0x00070000
994#define KSZ9897_IBA_CTRL_IBA_COMM_PORT1 0x00000000
995#define KSZ9897_IBA_CTRL_IBA_COMM_PORT2 0x00010000
996#define KSZ9897_IBA_CTRL_IBA_COMM_PORT3 0x00020000
997#define KSZ9897_IBA_CTRL_IBA_COMM_PORT4 0x00030000
998#define KSZ9897_IBA_CTRL_IBA_COMM_PORT5 0x00040000
999#define KSZ9897_IBA_CTRL_IBA_COMM_PORT6 0x00050000
1000#define KSZ9897_IBA_CTRL_IBA_COMM_PORT7 0x00060000
1001#define KSZ9897_IBA_CTRL_TPID 0x0000FFFF
1002#define KSZ9897_IBA_CTRL_TPID_DEFAULT 0x000040FE
1003
1004//I/O Drive Strength register
1005#define KSZ9897_IO_DRIVE_STRENGTH_HIGH_SPEED_DRIVE_STRENGTH 0x70
1006#define KSZ9897_IO_DRIVE_STRENGTH_LOW_SPEED_DRIVE_STRENGTH 0x07
1007
1008//In-Band Management Operation Status 1 register
1009#define KSZ9897_IBA_OP_STAT1_GOOD_PKT_DETECT 0x80000000
1010#define KSZ9897_IBA_OP_STAT1_RESP_PKT_TX_DONE 0x40000000
1011#define KSZ9897_IBA_OP_STAT1_EXEC_DONE 0x20000000
1012#define KSZ9897_IBA_OP_STAT1_MAC_ADDR_MISMATCH_ERR 0x00004000
1013#define KSZ9897_IBA_OP_STAT1_ACCESS_FORMAT_ERR 0x00002000
1014#define KSZ9897_IBA_OP_STAT1_ACCESS_CODE_ERR 0x00001000
1015#define KSZ9897_IBA_OP_STAT1_ACCESS_CMD_ERR 0x00000800
1016#define KSZ9897_IBA_OP_STAT1_OVERSIZE_PKT_ERR 0x00000400
1017#define KSZ9897_IBA_OP_STAT1_ACCESS_CODE_ERR_LOC 0x0000007F
1018
1019//LED Override register
1020#define KSZ9897_LED_OVERRIDE_OVERRIDE 0x000003FF
1021#define KSZ9897_LED_OVERRIDE_OVERRIDE_LED1_0 0x00000001
1022#define KSZ9897_LED_OVERRIDE_OVERRIDE_LED1_1 0x00000002
1023#define KSZ9897_LED_OVERRIDE_OVERRIDE_LED2_0 0x00000004
1024#define KSZ9897_LED_OVERRIDE_OVERRIDE_LED2_1 0x00000008
1025#define KSZ9897_LED_OVERRIDE_OVERRIDE_LED3_0 0x00000010
1026#define KSZ9897_LED_OVERRIDE_OVERRIDE_LED3_1 0x00000020
1027#define KSZ9897_LED_OVERRIDE_OVERRIDE_LED4_0 0x00000040
1028#define KSZ9897_LED_OVERRIDE_OVERRIDE_LED4_1 0x00000080
1029#define KSZ9897_LED_OVERRIDE_OVERRIDE_LED5_0 0x00000100
1030#define KSZ9897_LED_OVERRIDE_OVERRIDE_LED5_1 0x00000200
1031
1032//LED Output register
1033#define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL 0x000003FF
1034#define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED1_0 0x00000001
1035#define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED1_1 0x00000002
1036#define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED2_0 0x00000004
1037#define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED2_1 0x00000008
1038#define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED3_0 0x00000010
1039#define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED3_1 0x00000020
1040#define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED4_0 0x00000040
1041#define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED4_1 0x00000080
1042#define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED5_0 0x00000100
1043#define KSZ9897_LED_OUTPUT_GPIO_OUT_CTRL_LED5_1 0x00000200
1044
1045//Power Down Control 0 register
1046#define KSZ9897_PWR_DOWN_CTRL0_PLL_PWR_DOWN 0x20
1047#define KSZ9897_PWR_DOWN_CTRL0_PWR_MGMT_MODE 0x18
1048#define KSZ9897_PWR_DOWN_CTRL0_PWR_MGMT_MODE_NORMAL 0x00
1049#define KSZ9897_PWR_DOWN_CTRL0_PWR_MGMT_MODE_EDPD 0x08
1050#define KSZ9897_PWR_DOWN_CTRL0_PWR_MGMT_MODE_SOFT_PWR_DOWN 0x10
1051
1052//LED Strap-In register
1053#define KSZ9897_LED_STRAP_IN_STRAP_IN 0x000003FF
1054#define KSZ9897_LED_STRAP_IN_STRAP_IN_LED1_0 0x00000001
1055#define KSZ9897_LED_STRAP_IN_STRAP_IN_LED1_1 0x00000002
1056#define KSZ9897_LED_STRAP_IN_STRAP_IN_LED2_0 0x00000004
1057#define KSZ9897_LED_STRAP_IN_STRAP_IN_LED2_1 0x00000008
1058#define KSZ9897_LED_STRAP_IN_STRAP_IN_LED3_0 0x00000010
1059#define KSZ9897_LED_STRAP_IN_STRAP_IN_LED3_1 0x00000020
1060#define KSZ9897_LED_STRAP_IN_STRAP_IN_LED4_0 0x00000040
1061#define KSZ9897_LED_STRAP_IN_STRAP_IN_LED4_1 0x00000080
1062#define KSZ9897_LED_STRAP_IN_STRAP_IN_LED5_0 0x00000100
1063#define KSZ9897_LED_STRAP_IN_STRAP_IN_LED5_1 0x00000200
1064
1065//Switch Operation register
1066#define KSZ9897_SWITCH_OP_DOUBLE_TAG_EN 0x80
1067#define KSZ9897_SWITCH_OP_SOFT_HARD_RESET 0x02
1068#define KSZ9897_SWITCH_OP_START_SWITCH 0x01
1069
1070//Switch Maximum Transmit Unit register
1071#define KSZ9897_SWITCH_MTU_MTU 0x3FFF
1072#define KSZ9897_SWITCH_MTU_MTU_DEFAULT 0x07D0
1073
1074//Switch Lookup Engine Control 0 register
1075#define KSZ9897_SWITCH_LUE_CTRL0_VLAN_EN 0x80
1076#define KSZ9897_SWITCH_LUE_CTRL0_DROP_INVALID_VID 0x40
1077#define KSZ9897_SWITCH_LUE_CTRL0_AGE_COUNT 0x38
1078#define KSZ9897_SWITCH_LUE_CTRL0_AGE_COUNT_DEFAULT 0x20
1079#define KSZ9897_SWITCH_LUE_CTRL0_RESERVED_MCAST_LOOKUP_EN 0x04
1080#define KSZ9897_SWITCH_LUE_CTRL0_HASH_OPTION 0x03
1081#define KSZ9897_SWITCH_LUE_CTRL0_HASH_OPTION_NONE 0x00
1082#define KSZ9897_SWITCH_LUE_CTRL0_HASH_OPTION_CRC 0x01
1083#define KSZ9897_SWITCH_LUE_CTRL0_HASH_OPTION_XOR 0x02
1084
1085//Switch Lookup Engine Control 1 register
1086#define KSZ9897_SWITCH_LUE_CTRL1_UNICAST_LEARNING_DIS 0x80
1087#define KSZ9897_SWITCH_LUE_CTRL1_SELF_ADDR_FILT 0x40
1088#define KSZ9897_SWITCH_LUE_CTRL1_FLUSH_ALU_TABLE 0x20
1089#define KSZ9897_SWITCH_LUE_CTRL1_FLUSH_MSTP_ENTRIES 0x10
1090#define KSZ9897_SWITCH_LUE_CTRL1_MCAST_SRC_ADDR_FILT 0x08
1091#define KSZ9897_SWITCH_LUE_CTRL1_AGING_EN 0x04
1092#define KSZ9897_SWITCH_LUE_CTRL1_FAST_AGING 0x02
1093#define KSZ9897_SWITCH_LUE_CTRL1_LINK_DOWN_FLUSH 0x01
1094
1095//Switch Lookup Engine Control 2 register
1096#define KSZ9897_SWITCH_LUE_CTRL2_DOUBLE_TAG_MCAST_TRAP 0x40
1097#define KSZ9897_SWITCH_LUE_CTRL2_DYNAMIC_ENTRY_EG_VLAN_FILT 0x20
1098#define KSZ9897_SWITCH_LUE_CTRL2_STATIC_ENTRY_EG_VLAN_FILT 0x10
1099#define KSZ9897_SWITCH_LUE_CTRL2_FLUSH_OPTION 0x0C
1100#define KSZ9897_SWITCH_LUE_CTRL2_FLUSH_OPTION_NONE 0x00
1101#define KSZ9897_SWITCH_LUE_CTRL2_FLUSH_OPTION_DYNAMIC 0x04
1102#define KSZ9897_SWITCH_LUE_CTRL2_FLUSH_OPTION_STATIC 0x08
1103#define KSZ9897_SWITCH_LUE_CTRL2_FLUSH_OPTION_BOTH 0x0C
1104#define KSZ9897_SWITCH_LUE_CTRL2_MAC_ADDR_PRIORITY 0x03
1105
1106//Switch Lookup Engine Control 3 register
1107#define KSZ9897_SWITCH_LUE_CTRL3_AGE_PERIOD 0xFF
1108#define KSZ9897_SWITCH_LUE_CTRL3_AGE_PERIOD_DEFAULT 0x4B
1109
1110//Address Lookup Table Interrupt register
1111#define KSZ9897_ALU_TABLE_INT_LEARN_FAIL 0x04
1112#define KSZ9897_ALU_TABLE_INT_ALMOST_FULL 0x02
1113#define KSZ9897_ALU_TABLE_INT_WRITE_FAIL 0x01
1114
1115//Address Lookup Table Mask register
1116#define KSZ9897_ALU_TABLE_MASK_LEARN_FAIL 0x04
1117#define KSZ9897_ALU_TABLE_MASK_ALMOST_FULL 0x02
1118#define KSZ9897_ALU_TABLE_MASK_WRITE_FAIL 0x01
1119
1120//Address Lookup Table Entry Index 0 register
1121#define KSZ9897_ALU_TABLE_ENTRY_INDEX0_ALMOST_FULL_ENTRY_INDEX 0x0FFF
1122#define KSZ9897_ALU_TABLE_ENTRY_INDEX0_FAIL_WRITE_INDEX 0x03FF
1123
1124//Address Lookup Table Entry Index 1 register
1125#define KSZ9897_ALU_TABLE_ENTRY_INDEX1_FAIL_LEARN_INDEX 0x03FF
1126
1127//Address Lookup Table Entry Index 2 register
1128#define KSZ9897_ALU_TABLE_ENTRY_INDEX2_CPU_ACCESS_INDEX 0x03FF
1129
1130//Unknown Unicast Control register
1131#define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD 0x80000000
1132#define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP 0x0000007F
1133#define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT1 0x00000001
1134#define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT2 0x00000002
1135#define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT3 0x00000004
1136#define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT4 0x00000008
1137#define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT5 0x00000010
1138#define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT6 0x00000020
1139#define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT7 0x00000040
1140#define KSZ9897_UNKNOWN_UNICAST_CTRL_FWD_MAP_ALL 0x0000007F
1141
1142//Unknown Multicast Control register
1143#define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD 0x80000000
1144#define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP 0x0000007F
1145#define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT1 0x00000001
1146#define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT2 0x00000002
1147#define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT3 0x00000004
1148#define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT4 0x00000008
1149#define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT5 0x00000010
1150#define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT6 0x00000020
1151#define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT7 0x00000040
1152#define KSZ9897_UNKONWN_MULTICAST_CTRL_FWD_MAP_ALL 0x0000007F
1153
1154//Unknown VLAN ID Control register
1155#define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD 0x80000000
1156#define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP 0x0000007F
1157#define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT1 0x00000001
1158#define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT2 0x00000002
1159#define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT3 0x00000004
1160#define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT4 0x00000008
1161#define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT5 0x00000010
1162#define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT6 0x00000020
1163#define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT7 0x00000040
1164#define KSZ9897_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_ALL 0x0000007F
1165
1166//Switch MAC Control 0 register
1167#define KSZ9897_SWITCH_MAC_CTRL0_ALT_BACK_OFF_MODE 0x80
1168#define KSZ9897_SWITCH_MAC_CTRL0_FRAME_LEN_CHECK_EN 0x08
1169#define KSZ9897_SWITCH_MAC_CTRL0_FLOW_CTRL_PKT_DROP_MODE 0x02
1170#define KSZ9897_SWITCH_MAC_CTRL0_AGGRESSIVE_BACK_OFF_EN 0x01
1171
1172//Switch MAC Control 1 register
1173#define KSZ9897_SWITCH_MAC_CTRL1_MCAST_STORM_PROTECT_DIS 0x40
1174#define KSZ9897_SWITCH_MAC_CTRL1_BACK_PRESSURE_MODE 0x20
1175#define KSZ9897_SWITCH_MAC_CTRL1_FLOW_CTRL_FAIR_MODE 0x10
1176#define KSZ9897_SWITCH_MAC_CTRL1_NO_EXCESSIVE_COL_DROP 0x08
1177#define KSZ9897_SWITCH_MAC_CTRL1_JUMBO_PKT_SUPPORT 0x04
1178#define KSZ9897_SWITCH_MAC_CTRL1_MAX_PKT_SIZE_CHECK_DIS 0x02
1179#define KSZ9897_SWITCH_MAC_CTRL1_PASS_SHORT_PKT 0x01
1180
1181//Switch MAC Control 2 register
1182#define KSZ9897_SWITCH_MAC_CTRL2_NULL_VID_REPLACEMENT 0x08
1183#define KSZ9897_SWITCH_MAC_CTRL2_BCAST_STORM_PROTECT_RATE_MSB 0x07
1184
1185//Switch MAC Control 3 register
1186#define KSZ9897_SWITCH_MAC_CTRL3_BCAST_STORM_PROTECT_RATE_LSB 0xFF
1187
1188//Switch MAC Control 4 register
1189#define KSZ9897_SWITCH_MAC_CTRL4_PASS_FLOW_CTRL_PKT 0x01
1190
1191//Switch MAC Control 5 register
1192#define KSZ9897_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD 0x30
1193#define KSZ9897_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_16MS 0x00
1194#define KSZ9897_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_64MS 0x10
1195#define KSZ9897_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_256MS 0x20
1196#define KSZ9897_SWITCH_MAC_CTRL5_QUEUE_BASED_EG_RATE_LIMITE_EN 0x08
1197
1198//Switch MIB Control register
1199#define KSZ9897_SWITCH_MIB_CTRL_FLUSH 0x80
1200#define KSZ9897_SWITCH_MIB_CTRL_FREEZE 0x40
1201
1202//Global Port Mirroring and Snooping Control register
1203#define KSZ9897_GLOBAL_PORT_MIRROR_SNOOP_CTRL_IGMP_SNOOP_EN 0x40
1204#define KSZ9897_GLOBAL_PORT_MIRROR_SNOOP_CTRL_MLD_SNOOP_OPT 0x08
1205#define KSZ9897_GLOBAL_PORT_MIRROR_SNOOP_CTRL_MLD_SNOOP_EN 0x04
1206#define KSZ9897_GLOBAL_PORT_MIRROR_SNOOP_CTRL_SNIFF_MODE_SEL 0x01
1207
1208//WRED DiffServ Color Mapping register
1209#define KSZ9897_WRED_DIFFSERV_COLOR_MAPPING_RED 0x30
1210#define KSZ9897_WRED_DIFFSERV_COLOR_MAPPING_YELLOW 0x0C
1211#define KSZ9897_WRED_DIFFSERV_COLOR_MAPPING_GREEN 0x03
1212
1213//Queue Management Control 0 register
1214#define KSZ9897_QUEUE_MGMT_CTRL0_PRIORITY_2Q 0x000000C0
1215#define KSZ9897_QUEUE_MGMT_CTRL0_UNICAST_PORT_VLAN_DISCARD 0x00000002
1216
1217//VLAN Table Entry 0 register
1218#define KSZ9897_VLAN_TABLE_ENTRY0_VALID 0x80000000
1219#define KSZ9897_VLAN_TABLE_ENTRY0_FORWARD_OPTION 0x08000000
1220#define KSZ9897_VLAN_TABLE_ENTRY0_PRIORITY 0x07000000
1221#define KSZ9897_VLAN_TABLE_ENTRY0_MSTP_INDEX 0x00007000
1222#define KSZ9897_VLAN_TABLE_ENTRY0_FID 0x0000007F
1223
1224//VLAN Table Entry 1 register
1225#define KSZ9897_VLAN_TABLE_ENTRY1_PORT_UNTAG 0x0000007F
1226#define KSZ9897_VLAN_TABLE_ENTRY1_PORT7_UNTAG 0x00000040
1227#define KSZ9897_VLAN_TABLE_ENTRY1_PORT6_UNTAG 0x00000020
1228#define KSZ9897_VLAN_TABLE_ENTRY1_PORT5_UNTAG 0x00000010
1229#define KSZ9897_VLAN_TABLE_ENTRY1_PORT4_UNTAG 0x00000008
1230#define KSZ9897_VLAN_TABLE_ENTRY1_PORT3_UNTAG 0x00000004
1231#define KSZ9897_VLAN_TABLE_ENTRY1_PORT2_UNTAG 0x00000002
1232#define KSZ9897_VLAN_TABLE_ENTRY1_PORT1_UNTAG 0x00000001
1233
1234//VLAN Table Entry 2 register
1235#define KSZ9897_VLAN_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1236#define KSZ9897_VLAN_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1237#define KSZ9897_VLAN_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1238#define KSZ9897_VLAN_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1239#define KSZ9897_VLAN_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1240#define KSZ9897_VLAN_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1241#define KSZ9897_VLAN_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1242#define KSZ9897_VLAN_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1243
1244//VLAN Table Index register
1245#define KSZ9897_VLAN_TABLE_INDEX_VLAN_INDEX 0x0FFF
1246
1247//VLAN Table Access Control register
1248#define KSZ9897_VLAN_TABLE_ACCESS_CTRL_START_FINISH 0x80
1249#define KSZ9897_VLAN_TABLE_ACCESS_CTRL_ACTION 0x03
1250#define KSZ9897_VLAN_TABLE_ACCESS_CTRL_ACTION_NOP 0x00
1251#define KSZ9897_VLAN_TABLE_ACCESS_CTRL_ACTION_WRITE 0x01
1252#define KSZ9897_VLAN_TABLE_ACCESS_CTRL_ACTION_READ 0x02
1253#define KSZ9897_VLAN_TABLE_ACCESS_CTRL_ACTION_CLEAR 0x03
1254
1255//ALU Table Index 0 register
1256#define KSZ9897_ALU_TABLE_INDEX0_FID_INDEX 0x007F0000
1257#define KSZ9897_ALU_TABLE_INDEX0_MAC_INDEX_MSB 0x0000FFFF
1258
1259//ALU Table Index 1 register
1260#define KSZ9897_ALU_TABLE_INDEX1_MAC_INDEX_LSB 0xFFFFFFFF
1261
1262//ALU Table Access Control register
1263#define KSZ9897_ALU_TABLE_CTRL_VALID_COUNT 0x3FFF0000
1264#define KSZ9897_ALU_TABLE_CTRL_START_FINISH 0x00000080
1265#define KSZ9897_ALU_TABLE_CTRL_VALID 0x00000040
1266#define KSZ9897_ALU_TABLE_CTRL_VALID_ENTRY_OR_SEARCH_END 0x00000020
1267#define KSZ9897_ALU_TABLE_CTRL_DIRECT 0x00000004
1268#define KSZ9897_ALU_TABLE_CTRL_ACTION 0x00000003
1269#define KSZ9897_ALU_TABLE_CTRL_ACTION_NOP 0x00000000
1270#define KSZ9897_ALU_TABLE_CTRL_ACTION_WRITE 0x00000001
1271#define KSZ9897_ALU_TABLE_CTRL_ACTION_READ 0x00000002
1272#define KSZ9897_ALU_TABLE_CTRL_ACTION_SEARCH 0x00000003
1273
1274//Static Address and Reserved Multicast Table Control register
1275#define KSZ9897_STATIC_RES_MCAST_TABLE_CTRL_TABLE_INDEX 0x003F0000
1276#define KSZ9897_STATIC_RES_MCAST_TABLE_CTRL_START_FINISH 0x00000080
1277#define KSZ9897_STATIC_RES_MCAST_TABLE_CTRL_TABLE_SELECT 0x00000002
1278#define KSZ9897_STATIC_RES_MCAST_TABLE_CTRL_ACTION 0x00000001
1279#define KSZ9897_STATIC_RES_MCAST_TABLE_CTRL_ACTION_READ 0x00000000
1280#define KSZ9897_STATIC_RES_MCAST_TABLE_CTRL_ACTION_WRITE 0x00000001
1281
1282//ALU Table Entry 1 register
1283#define KSZ9897_ALU_TABLE_ENTRY1_STATIC 0x80000000
1284#define KSZ9897_ALU_TABLE_ENTRY1_SRC_FILTER 0x40000000
1285#define KSZ9897_ALU_TABLE_ENTRY1_DES_FILTER 0x20000000
1286#define KSZ9897_ALU_TABLE_ENTRY1_PRIORITY 0x1C000000
1287#define KSZ9897_ALU_TABLE_ENTRY1_AGE_COUNT 0x1C000000
1288#define KSZ9897_ALU_TABLE_ENTRY1_MSTP 0x00000007
1289
1290//ALU Table Entry 2 register
1291#define KSZ9897_ALU_TABLE_ENTRY2_OVERRIDE 0x80000000
1292#define KSZ9897_ALU_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1293#define KSZ9897_ALU_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1294#define KSZ9897_ALU_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1295#define KSZ9897_ALU_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1296#define KSZ9897_ALU_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1297#define KSZ9897_ALU_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1298#define KSZ9897_ALU_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1299#define KSZ9897_ALU_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1300
1301//ALU Table Entry 3 register
1302#define KSZ9897_ALU_TABLE_ENTRY3_FID 0x007F0000
1303#define KSZ9897_ALU_TABLE_ENTRY3_MAC_ADDR_MSB 0x0000FFFF
1304
1305//ALU Table Entry 4 register
1306#define KSZ9897_ALU_TABLE_ENTRY4_MAC_ADDR_LSB 0xFFFFFFFF
1307
1308//Static Address Table Entry 1 register
1309#define KSZ9897_STATIC_TABLE_ENTRY1_VALID 0x80000000
1310#define KSZ9897_STATIC_TABLE_ENTRY1_SRC_FILTER 0x40000000
1311#define KSZ9897_STATIC_TABLE_ENTRY1_DES_FILTER 0x20000000
1312#define KSZ9897_STATIC_TABLE_ENTRY1_PRIORITY 0x1C000000
1313#define KSZ9897_STATIC_TABLE_ENTRY1_MSTP 0x00000007
1314
1315//Static Address Table Entry 2 register
1316#define KSZ9897_STATIC_TABLE_ENTRY2_OVERRIDE 0x80000000
1317#define KSZ9897_STATIC_TABLE_ENTRY2_USE_FID 0x40000000
1318#define KSZ9897_STATIC_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1319#define KSZ9897_STATIC_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1320#define KSZ9897_STATIC_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1321#define KSZ9897_STATIC_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1322#define KSZ9897_STATIC_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1323#define KSZ9897_STATIC_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1324#define KSZ9897_STATIC_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1325#define KSZ9897_STATIC_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1326
1327//Static Address Table Entry 3 register
1328#define KSZ9897_STATIC_TABLE_ENTRY3_FID 0x007F0000
1329#define KSZ9897_STATIC_TABLE_ENTRY3_MAC_ADDR_MSB 0x0000FFFF
1330
1331//Static Address Table Entry 4 register
1332#define KSZ9897_STATIC_TABLE_ENTRY4_MAC_ADDR_LSB 0xFFFFFFFF
1333
1334//Reserved Multicast Table Entry 2 register
1335#define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT_FORWARD 0x0000007F
1336#define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT7_FORWARD 0x00000040
1337#define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT6_FORWARD 0x00000020
1338#define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT5_FORWARD 0x00000010
1339#define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT4_FORWARD 0x00000008
1340#define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1341#define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1342#define KSZ9897_RES_MCAST_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1343
1344//Port N Default Tag 0 register
1345#define KSZ9897_PORTn_DEFAULT_TAG0_PCP 0xE0
1346#define KSZ9897_PORTn_DEFAULT_TAG0_DEI 0x10
1347#define KSZ9897_PORTn_DEFAULT_TAG0_VID_MSB 0x0F
1348
1349//Port N Default Tag 1 register
1350#define KSZ9897_PORTn_DEFAULT_TAG1_VID_LSB 0xFF
1351
1352//Port N Interrupt Status register
1353#define KSZ9897_PORTn_INT_STATUS_SGMII_AN_DONE 0x08
1354#define KSZ9897_PORTn_INT_STATUS_PHY 0x02
1355#define KSZ9897_PORTn_INT_STATUS_ACL 0x01
1356
1357//Port N Interrupt Mask register
1358#define KSZ9897_PORTn_INT_MASK_SGMII_AN_DONE 0x08
1359#define KSZ9897_PORTn_INT_MASK_PHY 0x02
1360#define KSZ9897_PORTn_INT_MASK_ACL 0x01
1361
1362//Port N Operation Control 0 register
1363#define KSZ9897_PORTn_OP_CTRL0_LOCAL_LOOPBACK 0x80
1364#define KSZ9897_PORTn_OP_CTRL0_REMOTE_LOOPBACK 0x40
1365#define KSZ9897_PORTn_OP_CTRL0_TAIL_TAG_EN 0x04
1366#define KSZ9897_PORTn_OP_CTRL0_TX_QUEUE_SPLIT_EN 0x03
1367
1368//Port N Status register
1369#define KSZ9897_PORTn_STATUS_SPEED 0x18
1370#define KSZ9897_PORTn_STATUS_SPEED_10MBPS 0x00
1371#define KSZ9897_PORTn_STATUS_SPEED_100MBPS 0x08
1372#define KSZ9897_PORTn_STATUS_SPEED_1000MBPS 0x10
1373#define KSZ9897_PORTn_STATUS_DUPLEX 0x04
1374#define KSZ9897_PORTn_STATUS_TX_FLOW_CTRL_EN 0x02
1375#define KSZ9897_PORTn_STATUS_RX_FLOW_CTRL_EN 0x01
1376
1377//XMII Port N Control 0 register
1378#define KSZ9897_PORTn_XMII_CTRL0_DUPLEX 0x40
1379#define KSZ9897_PORTn_XMII_CTRL0_TX_FLOW_CTRL_EN 0x20
1380#define KSZ9897_PORTn_XMII_CTRL0_SPEED_10_100 0x10
1381#define KSZ9897_PORTn_XMII_CTRL0_RX_FLOW_CTRL_EN 0x08
1382
1383//XMII Port N Control 1 register
1384#define KSZ9897_PORTn_XMII_CTRL1_SPEED_1000 0x40
1385#define KSZ9897_PORTn_XMII_CTRL1_RGMII_ID_IG 0x10
1386#define KSZ9897_PORTn_XMII_CTRL1_RGMII_ID_EG 0x08
1387#define KSZ9897_PORTn_XMII_CTRL1_MII_RMII_MODE 0x04
1388#define KSZ9897_PORTn_XMII_CTRL1_IF_TYPE 0x03
1389#define KSZ9897_PORTn_XMII_CTRL1_IF_TYPE_RGMII 0x00
1390#define KSZ9897_PORTn_XMII_CTRL1_IF_TYPE_RMII 0x01
1391#define KSZ9897_PORTn_XMII_CTRL1_IF_TYPE_MII 0x03
1392
1393//Port N MAC Control 0 register
1394#define KSZ9897_PORTn_MAC_CTRL0_BCAST_STORM_PROTECT_EN 0x02
1395
1396//Port N MAC Control 1 register
1397#define KSZ9897_PORTn_MAC_CTRL1_BACK_PRESSURE_EN 0x08
1398#define KSZ9897_PORTn_MAC_CTRL1_PASS_ALL_FRAMES 0x01
1399
1400//Port N MIB Control and Status register
1401#define KSZ9897_PORTn_MIB_CTRL_STAT_MIB_COUNTER_OVERFLOW 0x80000000
1402#define KSZ9897_PORTn_MIB_CTRL_STAT_MIB_READ 0x02000000
1403#define KSZ9897_PORTn_MIB_CTRL_STAT_MIB_FLUSH_FREEZE 0x01000000
1404#define KSZ9897_PORTn_MIB_CTRL_STAT_MIB_INDEX 0x00FF0000
1405#define KSZ9897_PORTn_MIB_CTRL_STAT_MIB_COUNTER_VALUE_35_32 0x0000000F
1406
1407//Port N MIB Data register
1408#define KSZ9897_PORTn_MIB_DATA_MIB_COUNTER_VALUE_31_0 0xFFFFFFFF
1409
1410//Port N ACL Access Control 0 register
1411#define KSZ9897_PORTn_ACL_ACCESS_CTRL0_WRITE_STATUS 0x40
1412#define KSZ9897_PORTn_ACL_ACCESS_CTRL0_READ_STATUS 0x20
1413#define KSZ9897_PORTn_ACL_ACCESS_CTRL0_READ 0x00
1414#define KSZ9897_PORTn_ACL_ACCESS_CTRL0_WRITE 0x10
1415#define KSZ9897_PORTn_ACL_ACCESS_CTRL0_ACL_INDEX 0x0F
1416
1417//Port N Port Mirroring Control register
1418#define KSZ9897_PORTn_MIRRORING_CTRL_RECEIVE_SNIFF 0x40
1419#define KSZ9897_PORTn_MIRRORING_CTRL_TRANSMIT_SNIFF 0x20
1420#define KSZ9897_PORTn_MIRRORING_CTRL_SNIFFER_PORT 0x02
1421
1422//Port N Authentication Control register
1423#define KSZ9897_PORTn_AUTH_CTRL_ACL_EN 0x04
1424#define KSZ9897_PORTn_AUTH_CTRL_AUTH_MODE 0x03
1425#define KSZ9897_PORTn_AUTH_CTRL_AUTH_MODE_PASS 0x00
1426#define KSZ9897_PORTn_AUTH_CTRL_AUTH_MODE_BLOCK 0x01
1427#define KSZ9897_PORTn_AUTH_CTRL_AUTH_MODE_TRAP 0x02
1428
1429//Port N Pointer register
1430#define KSZ9897_PORTn_PTR_PORT_INDEX 0x00070000
1431#define KSZ9897_PORTn_PTR_QUEUE_PTR 0x00000003
1432
1433//Port N Control 1 register
1434#define KSZ9897_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x0000007F
1435#define KSZ9897_PORTn_CTRL1_PORT7_VLAN_MEMBERSHIP 0x00000040
1436#define KSZ9897_PORTn_CTRL1_PORT6_VLAN_MEMBERSHIP 0x00000020
1437#define KSZ9897_PORTn_CTRL1_PORT5_VLAN_MEMBERSHIP 0x00000010
1438#define KSZ9897_PORTn_CTRL1_PORT4_VLAN_MEMBERSHIP 0x00000008
1439#define KSZ9897_PORTn_CTRL1_PORT3_VLAN_MEMBERSHIP 0x00000004
1440#define KSZ9897_PORTn_CTRL1_PORT2_VLAN_MEMBERSHIP 0x00000002
1441#define KSZ9897_PORTn_CTRL1_PORT1_VLAN_MEMBERSHIP 0x00000001
1442
1443//Port N Control 2 register
1444#define KSZ9897_PORTn_CTRL2_NULL_VID_LOOKUP_EN 0x80
1445#define KSZ9897_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
1446#define KSZ9897_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
1447#define KSZ9897_PORTn_CTRL2_802_1X_EN 0x10
1448#define KSZ9897_PORTn_CTRL2_SELF_ADDR_FILT 0x08
1449
1450//Port N MSTP Pointer register
1451#define KSZ9897_PORTn_MSTP_PTR_MSTP_PTR 0x07
1452
1453//Port N MSTP State register
1454#define KSZ9897_PORTn_MSTP_STATE_TRANSMIT_EN 0x04
1455#define KSZ9897_PORTn_MSTP_STATE_RECEIVE_EN 0x02
1456#define KSZ9897_PORTn_MSTP_STATE_LEARNING_DIS 0x01
1457
1458//C++ guard
1459#ifdef __cplusplus
1460extern "C" {
1461#endif
1462
1463//KSZ9897 Ethernet switch driver
1464extern const SwitchDriver ksz9897SwitchDriver;
1465
1466//KSZ9897 related functions
1467error_t ksz9897Init(NetInterface *interface);
1468void ksz9897InitHook(NetInterface *interface);
1469
1470void ksz9897Tick(NetInterface *interface);
1471
1472void ksz9897EnableIrq(NetInterface *interface);
1473void ksz9897DisableIrq(NetInterface *interface);
1474
1475void ksz9897EventHandler(NetInterface *interface);
1476
1477error_t ksz9897TagFrame(NetInterface *interface, NetBuffer *buffer,
1478 size_t *offset, NetTxAncillary *ancillary);
1479
1480error_t ksz9897UntagFrame(NetInterface *interface, uint8_t **frame,
1481 size_t *length, NetRxAncillary *ancillary);
1482
1483bool_t ksz9897GetLinkState(NetInterface *interface, uint8_t port);
1484uint32_t ksz9897GetLinkSpeed(NetInterface *interface, uint8_t port);
1485NicDuplexMode ksz9897GetDuplexMode(NetInterface *interface, uint8_t port);
1486
1487void ksz9897SetPortState(NetInterface *interface, uint8_t port,
1488 SwitchPortState state);
1489
1490SwitchPortState ksz9897GetPortState(NetInterface *interface, uint8_t port);
1491
1492void ksz9897SetAgingTime(NetInterface *interface, uint32_t agingTime);
1493
1494void ksz9897EnableIgmpSnooping(NetInterface *interface, bool_t enable);
1495void ksz9897EnableMldSnooping(NetInterface *interface, bool_t enable);
1496void ksz9897EnableRsvdMcastTable(NetInterface *interface, bool_t enable);
1497
1498error_t ksz9897AddStaticFdbEntry(NetInterface *interface,
1499 const SwitchFdbEntry *entry);
1500
1501error_t ksz9897DeleteStaticFdbEntry(NetInterface *interface,
1502 const SwitchFdbEntry *entry);
1503
1504error_t ksz9897GetStaticFdbEntry(NetInterface *interface, uint_t index,
1505 SwitchFdbEntry *entry);
1506
1507void ksz9897FlushStaticFdbTable(NetInterface *interface);
1508
1509error_t ksz9897GetDynamicFdbEntry(NetInterface *interface, uint_t index,
1510 SwitchFdbEntry *entry);
1511
1512void ksz9897FlushDynamicFdbTable(NetInterface *interface, uint8_t port);
1513
1514void ksz9897SetUnknownMcastFwdPorts(NetInterface *interface,
1515 bool_t enable, uint32_t forwardPorts);
1516
1517void ksz9897WritePhyReg(NetInterface *interface, uint8_t port,
1518 uint8_t address, uint16_t data);
1519
1520uint16_t ksz9897ReadPhyReg(NetInterface *interface, uint8_t port,
1521 uint8_t address);
1522
1523void ksz9897DumpPhyReg(NetInterface *interface, uint8_t port);
1524
1525void ksz9897WriteMmdReg(NetInterface *interface, uint8_t port,
1526 uint8_t devAddr, uint16_t regAddr, uint16_t data);
1527
1528uint16_t ksz9897ReadMmdReg(NetInterface *interface, uint8_t port,
1529 uint8_t devAddr, uint16_t regAddr);
1530
1531void ksz9897WriteSwitchReg8(NetInterface *interface, uint16_t address,
1532 uint8_t data);
1533
1534uint8_t ksz9897ReadSwitchReg8(NetInterface *interface, uint16_t address);
1535
1536void ksz9897WriteSwitchReg16(NetInterface *interface, uint16_t address,
1537 uint16_t data);
1538
1539uint16_t ksz9897ReadSwitchReg16(NetInterface *interface, uint16_t address);
1540
1541void ksz9897WriteSwitchReg32(NetInterface *interface, uint16_t address,
1542 uint32_t data);
1543
1544uint32_t ksz9897ReadSwitchReg32(NetInterface *interface, uint16_t address);
1545
1546//C++ guard
1547#ifdef __cplusplus
1548}
1549#endif
1550
1551#endif
error_t
Error codes.
Definition error.h:43
Network interface controller abstraction layer.
NicDuplexMode
Duplex mode.
Definition nic.h:122
SwitchPortState
Switch port state.
Definition nic.h:134
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
Ethernet switch driver.
Definition nic.h:322
Forwarding database entry.
Definition nic.h:149