31#ifndef _MPC5748_ETH1_DRIVER_H
32#define _MPC5748_ETH1_DRIVER_H
35#ifndef MPC5748_ETH1_TX_BUFFER_COUNT
36 #define MPC5748_ETH1_TX_BUFFER_COUNT 3
37#elif (MPC5748_ETH1_TX_BUFFER_COUNT < 1)
38 #error MPC5748_ETH1_TX_BUFFER_COUNT parameter is not valid
42#ifndef MPC5748_ETH1_TX_BUFFER_SIZE
43 #define MPC5748_ETH1_TX_BUFFER_SIZE 1536
44#elif (MPC5748_ETH1_TX_BUFFER_SIZE != 1536)
45 #error MPC5748_ETH1_TX_BUFFER_SIZE parameter is not valid
49#ifndef MPC5748_ETH1_RX_BUFFER_COUNT
50 #define MPC5748_ETH1_RX_BUFFER_COUNT 6
51#elif (MPC5748_ETH1_RX_BUFFER_COUNT < 1)
52 #error MPC5748_ETH1_RX_BUFFER_COUNT parameter is not valid
56#ifndef MPC5748_ETH1_RX_BUFFER_SIZE
57 #define MPC5748_ETH1_RX_BUFFER_SIZE 1536
58#elif (MPC5748_ETH1_RX_BUFFER_SIZE != 1536)
59 #error MPC5748_ETH1_RX_BUFFER_SIZE parameter is not valid
63#ifndef MPC5748_ETH1_IRQ_PRIORITY
64 #define MPC5748_ETH1_IRQ_PRIORITY 10
65#elif (MPC5748_ETH1_IRQ_PRIORITY < 0)
66 #error MPC5748_ETH1_IRQ_PRIORITY parameter is not valid
70#define ENET_TBD0_R 0x80000000
71#define ENET_TBD0_TO1 0x40000000
72#define ENET_TBD0_W 0x20000000
73#define ENET_TBD0_TO2 0x10000000
74#define ENET_TBD0_L 0x08000000
75#define ENET_TBD0_TC 0x04000000
76#define ENET_TBD0_DATA_LENGTH 0x0000FFFF
77#define ENET_TBD1_DATA_POINTER 0xFFFFFFFF
78#define ENET_TBD2_INT 0x40000000
79#define ENET_TBD2_TS 0x20000000
80#define ENET_TBD2_PINS 0x10000000
81#define ENET_TBD2_IINS 0x08000000
82#define ENET_TBD2_TXE 0x00008000
83#define ENET_TBD2_UE 0x00002000
84#define ENET_TBD2_EE 0x00001000
85#define ENET_TBD2_FE 0x00000800
86#define ENET_TBD2_LCE 0x00000400
87#define ENET_TBD2_OE 0x00000200
88#define ENET_TBD2_TSE 0x00000100
89#define ENET_TBD4_BDU 0x80000000
90#define ENET_TBD5_TIMESTAMP 0xFFFFFFFF
93#define ENET_RBD0_E 0x80000000
94#define ENET_RBD0_RO1 0x40000000
95#define ENET_RBD0_W 0x20000000
96#define ENET_RBD0_RO2 0x10000000
97#define ENET_RBD0_L 0x08000000
98#define ENET_RBD0_M 0x01000000
99#define ENET_RBD0_BC 0x00800000
100#define ENET_RBD0_MC 0x00400000
101#define ENET_RBD0_LG 0x00200000
102#define ENET_RBD0_NO 0x00100000
103#define ENET_RBD0_CR 0x00040000
104#define ENET_RBD0_OV 0x00020000
105#define ENET_RBD0_TR 0x00010000
106#define ENET_RBD0_DATA_LENGTH 0x0000FFFF
107#define ENET_RBD1_DATA_POINTER 0xFFFFFFFF
108#define ENET_RBD2_ME 0x80000000
109#define ENET_RBD2_PE 0x04000000
110#define ENET_RBD2_CE 0x02000000
111#define ENET_RBD2_UC 0x01000000
112#define ENET_RBD2_INT 0x00800000
113#define ENET_RBD2_VPCP 0x0000E000
114#define ENET_RBD2_ICE 0x00000020
115#define ENET_RBD2_PCR 0x00000010
116#define ENET_RBD2_VLAN 0x00000004
117#define ENET_RBD2_IPV6 0x00000002
118#define ENET_RBD2_FRAG 0x00000001
119#define ENET_RBD3_HEADER_LENGTH 0xF8000000
120#define ENET_RBD3_PROTOCOL_TYPE 0x00FF0000
121#define ENET_RBD3_PAYLOAD_CHECKSUM 0x0000FFFF
122#define ENET_RBD4_BDU 0x80000000
123#define ENET_RBD5_TIMESTAMP 0xFFFFFFFF
134error_t mpc5748Eth1Init(NetInterface *interface);
135void mpc5748Eth1InitGpio(NetInterface *interface);
136void mpc5748Eth1InitBufferDesc(NetInterface *interface);
138void mpc5748Eth1Tick(NetInterface *interface);
140void mpc5748Eth1EnableIrq(NetInterface *interface);
141void mpc5748Eth1DisableIrq(NetInterface *interface);
142void mpc5748Eth1EventHandler(NetInterface *interface);
144error_t mpc5748Eth1SendPacket(NetInterface *interface,
145 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
147error_t mpc5748Eth1ReceivePacket(NetInterface *interface);
149error_t mpc5748Eth1UpdateMacAddrFilter(NetInterface *interface);
150error_t mpc5748Eth1UpdateMacConfig(NetInterface *interface);
152void mpc5748Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr,
153 uint8_t regAddr, uint16_t data);
155uint16_t mpc5748Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
158uint32_t mpc5748Eth1CalcCrc(
const void *data,
size_t length);
error_t
Error codes.
Definition error.h:43
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283