31#ifndef _MPFSXXX_ETH1_DRIVER_H
32#define _MPFSXXX_ETH1_DRIVER_H
35#ifndef MPFSXXX_ETH1_TX_BUFFER_COUNT
36 #define MPFSXXX_ETH1_TX_BUFFER_COUNT 16
37#elif (MPFSXXX_ETH1_TX_BUFFER_COUNT < 1)
38 #error MPFSXXX_ETH1_TX_BUFFER_COUNT parameter is not valid
42#ifndef MPFSXXX_ETH1_TX_BUFFER_SIZE
43 #define MPFSXXX_ETH1_TX_BUFFER_SIZE 1536
44#elif (MPFSXXX_ETH1_TX_BUFFER_SIZE != 1536)
45 #error MPFSXXX_ETH1_TX_BUFFER_SIZE parameter is not valid
49#ifndef MPFSXXX_ETH1_RX_BUFFER_COUNT
50 #define MPFSXXX_ETH1_RX_BUFFER_COUNT 16
51#elif (MPFSXXX_ETH1_RX_BUFFER_COUNT < 12)
52 #error MPFSXXX_ETH1_RX_BUFFER_COUNT parameter is not valid
56#ifndef MPFSXXX_ETH1_RX_BUFFER_SIZE
57 #define MPFSXXX_ETH1_RX_BUFFER_SIZE 1536
58#elif (MPFSXXX_ETH1_RX_BUFFER_SIZE != 1536)
59 #error MPFSXXX_ETH1_RX_BUFFER_SIZE parameter is not valid
63#ifndef MPFSXXX_ETH1_DUMMY_BUFFER_COUNT
64 #define MPFSXXX_ETH1_DUMMY_BUFFER_COUNT 2
65#elif (MPFSXXX_ETH1_DUMMY_BUFFER_COUNT < 1)
66 #error MPFSXXX_ETH1_DUMMY_BUFFER_COUNT parameter is not valid
70#ifndef MPFSXXX_ETH1_DUMMY_BUFFER_SIZE
71 #define MPFSXXX_ETH1_DUMMY_BUFFER_SIZE 128
72#elif (MPFSXXX_ETH1_DUMMY_BUFFER_SIZE != 128)
73 #error MPFSXXX_ETH1_DUMMY_BUFFER_SIZE parameter is not valid
77#ifndef MPFSXXX_ETH1_IRQ_PRIORITY
78 #define MPFSXXX_ETH1_IRQ_PRIORITY 7
79#elif (MPFSXXX_ETH1_IRQ_PRIORITY < 0)
80 #error MPFSXXX_ETH1_IRQ_PRIORITY parameter is not valid
84#ifndef MPFSXXX_ETH1_RAM_SECTION
85 #define MPFSXXX_ETH1_RAM_SECTION ".ram_no_cache"
89#define MAC0 ((MAC_TypeDef *) 0x20110000)
92#define MAC_TX_USED 0x80000000
93#define MAC_TX_WRAP 0x40000000
94#define MAC_TX_RLE_ERROR 0x20000000
95#define MAC_TX_UNDERRUN_ERROR 0x10000000
96#define MAC_TX_AHB_ERROR 0x08000000
97#define MAC_TX_LATE_COL_ERROR 0x04000000
98#define MAC_TX_CHECKSUM_ERROR 0x00700000
99#define MAC_TX_NO_CRC 0x00010000
100#define MAC_TX_LAST 0x00008000
101#define MAC_TX_LENGTH 0x00003FFF
104#define MAC_RX_ADDRESS 0xFFFFFFFC
105#define MAC_RX_WRAP 0x00000002
106#define MAC_RX_OWNERSHIP 0x00000001
107#define MAC_RX_BROADCAST 0x80000000
108#define MAC_RX_MULTICAST_HASH 0x40000000
109#define MAC_RX_UNICAST_HASH 0x20000000
110#define MAC_RX_SAR 0x08000000
111#define MAC_RX_SAR_MASK 0x06000000
112#define MAC_RX_TYPE_ID 0x01000000
113#define MAC_RX_SNAP 0x01000000
114#define MAC_RX_TYPE_ID_MASK 0x00C00000
115#define MAC_RX_CHECKSUM_VALID 0x00C00000
116#define MAC_RX_VLAN_TAG 0x00200000
117#define MAC_RX_PRIORITY_TAG 0x00100000
118#define MAC_RX_VLAN_PRIORITY 0x000E0000
119#define MAC_RX_CFI 0x00010000
120#define MAC_RX_EOF 0x00008000
121#define MAC_RX_SOF 0x00004000
122#define MAC_RX_LENGTH_MSB 0x00002000
123#define MAC_RX_BAD_FCS 0x00002000
124#define MAC_RX_LENGTH 0x00001FFF
142 uint32_t nanoSeconds;
157 uint32_t nanoSeconds;
166error_t mpfsxxxEth1Init(NetInterface *interface);
167void mpfsxxxEth1InitGpio(NetInterface *interface);
168void mpfsxxxEth1InitBufferDesc(NetInterface *interface);
170void mpfsxxxEth1Tick(NetInterface *interface);
172void mpfsxxxEth1EnableIrq(NetInterface *interface);
173void mpfsxxxEth1DisableIrq(NetInterface *interface);
174void mpfsxxxEth1EventHandler(NetInterface *interface);
176error_t mpfsxxxEth1SendPacket(NetInterface *interface,
177 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
179error_t mpfsxxxEth1ReceivePacket(NetInterface *interface);
181error_t mpfsxxxEth1UpdateMacAddrFilter(NetInterface *interface);
182error_t mpfsxxxEth1UpdateMacConfig(NetInterface *interface);
184void mpfsxxxEth1WritePhyReg(uint8_t opcode, uint8_t phyAddr,
185 uint8_t regAddr, uint16_t data);
187uint16_t mpfsxxxEth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
error_t
Error codes.
Definition error.h:43
Receive buffer descriptor.
Definition mpfsxxx_eth1_driver.h:152
Transmit buffer descriptor.
Definition mpfsxxx_eth1_driver.h:137
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283