31#ifndef _MSP432E4_ETH_DRIVER_H
32#define _MSP432E4_ETH_DRIVER_H
38#ifndef MSP432E4_ETH_TX_BUFFER_COUNT
39 #define MSP432E4_ETH_TX_BUFFER_COUNT 3
40#elif (MSP432E4_ETH_TX_BUFFER_COUNT < 1)
41 #error MSP432E4_ETH_TX_BUFFER_COUNT parameter is not valid
45#ifndef MSP432E4_ETH_TX_BUFFER_SIZE
46 #define MSP432E4_ETH_TX_BUFFER_SIZE 1536
47#elif (MSP432E4_ETH_TX_BUFFER_SIZE != 1536)
48 #error MSP432E4_ETH_TX_BUFFER_SIZE parameter is not valid
52#ifndef MSP432E4_ETH_RX_BUFFER_COUNT
53 #define MSP432E4_ETH_RX_BUFFER_COUNT 6
54#elif (MSP432E4_ETH_RX_BUFFER_COUNT < 1)
55 #error MSP432E4_ETH_RX_BUFFER_COUNT parameter is not valid
59#ifndef MSP432E4_ETH_RX_BUFFER_SIZE
60 #define MSP432E4_ETH_RX_BUFFER_SIZE 1536
61#elif (MSP432E4_ETH_RX_BUFFER_SIZE != 1536)
62 #error MSP432E4_ETH_RX_BUFFER_SIZE parameter is not valid
66#ifndef MSP432E4_ETH_IRQ_PRIORITY_GROUPING
67 #define MSP432E4_ETH_IRQ_PRIORITY_GROUPING 3
68#elif (MSP432E4_ETH_IRQ_PRIORITY_GROUPING < 0)
69 #error MSP432E4_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
73#ifndef MSP432E4_ETH_IRQ_PRIORITY
74 #define MSP432E4_ETH_IRQ_PRIORITY 192
75#elif (MSP432E4_ETH_IRQ_PRIORITY < 0)
76 #error MSP432E4_ETH_IRQ_PRIORITY parameter is not valid
80#define EMAC_DMABUSMOD_RPBL_1 (1 << EMAC_DMABUSMOD_RPBL_S)
81#define EMAC_DMABUSMOD_RPBL_2 (2 << EMAC_DMABUSMOD_RPBL_S)
82#define EMAC_DMABUSMOD_RPBL_4 (4 << EMAC_DMABUSMOD_RPBL_S)
83#define EMAC_DMABUSMOD_RPBL_8 (8 << EMAC_DMABUSMOD_RPBL_S)
84#define EMAC_DMABUSMOD_RPBL_16 (16 << EMAC_DMABUSMOD_RPBL_S)
85#define EMAC_DMABUSMOD_RPBL_32 (32 << EMAC_DMABUSMOD_RPBL_S)
87#define EMAC_DMABUSMOD_PR_1_1 (0 << EMAC_DMABUSMOD_PR_S)
88#define EMAC_DMABUSMOD_PR_2_1 (1 << EMAC_DMABUSMOD_PR_S)
89#define EMAC_DMABUSMOD_PR_3_1 (2 << EMAC_DMABUSMOD_PR_S)
90#define EMAC_DMABUSMOD_PR_4_1 (3 << EMAC_DMABUSMOD_PR_S)
92#define EMAC_DMABUSMOD_PBL_1 (1 << EMAC_DMABUSMOD_PBL_S)
93#define EMAC_DMABUSMOD_PBL_2 (2 << EMAC_DMABUSMOD_PBL_S)
94#define EMAC_DMABUSMOD_PBL_4 (4 << EMAC_DMABUSMOD_PBL_S)
95#define EMAC_DMABUSMOD_PBL_8 (8 << EMAC_DMABUSMOD_PBL_S)
96#define EMAC_DMABUSMOD_PBL_16 (16 << EMAC_DMABUSMOD_PBL_S)
97#define EMAC_DMABUSMOD_PBL_32 (32 << EMAC_DMABUSMOD_PBL_S)
100#define EMAC_TDES0_OWN 0x80000000
101#define EMAC_TDES0_IC 0x40000000
102#define EMAC_TDES0_LS 0x20000000
103#define EMAC_TDES0_FS 0x10000000
104#define EMAC_TDES0_DC 0x08000000
105#define EMAC_TDES0_DP 0x04000000
106#define EMAC_TDES0_TTSE 0x02000000
107#define EMAC_TDES0_CRCR 0x01000000
108#define EMAC_TDES0_CIC 0x00C00000
109#define EMAC_TDES0_TER 0x00200000
110#define EMAC_TDES0_TCH 0x00100000
111#define EMAC_TDES0_VLIC 0x000C0000
112#define EMAC_TDES0_TTSS 0x00020000
113#define EMAC_TDES0_IHE 0x00010000
114#define EMAC_TDES0_ES 0x00008000
115#define EMAC_TDES0_JT 0x00004000
116#define EMAC_TDES0_FF 0x00002000
117#define EMAC_TDES0_IPE 0x00001000
118#define EMAC_TDES0_LCA 0x00000800
119#define EMAC_TDES0_NC 0x00000400
120#define EMAC_TDES0_LCO 0x00000200
121#define EMAC_TDES0_EC 0x00000100
122#define EMAC_TDES0_VF 0x00000080
123#define EMAC_TDES0_CC 0x00000078
124#define EMAC_TDES0_ED 0x00000004
125#define EMAC_TDES0_UF 0x00000002
126#define EMAC_TDES0_DB 0x00000001
127#define EMAC_TDES1_SAIC 0xE0000000
128#define EMAC_TDES1_TBS2 0x1FFF0000
129#define EMAC_TDES1_TBS1 0x00001FFF
130#define EMAC_TDES2_TBAP1 0xFFFFFFFF
131#define EMAC_TDES3_TBAP2 0xFFFFFFFF
132#define EMAC_TDES6_TTSL 0xFFFFFFFF
133#define EMAC_TDES7_TTSH 0xFFFFFFFF
136#define EMAC_RDES0_OWN 0x80000000
137#define EMAC_RDES0_AFM 0x40000000
138#define EMAC_RDES0_FL 0x3FFF0000
139#define EMAC_RDES0_ES 0x00008000
140#define EMAC_RDES0_DE 0x00004000
141#define EMAC_RDES0_SAF 0x00002000
142#define EMAC_RDES0_LE 0x00001000
143#define EMAC_RDES0_OE 0x00000800
144#define EMAC_RDES0_VLAN 0x00000400
145#define EMAC_RDES0_FS 0x00000200
146#define EMAC_RDES0_LS 0x00000100
147#define EMAC_RDES0_TSA_GF 0x00000080
148#define EMAC_RDES0_LCO 0x00000040
149#define EMAC_RDES0_FT 0x00000020
150#define EMAC_RDES0_RWT 0x00000010
151#define EMAC_RDES0_RE 0x00000008
152#define EMAC_RDES0_DBE 0x00000004
153#define EMAC_RDES0_CE 0x00000002
154#define EMAC_RDES0_ESA 0x00000001
155#define EMAC_RDES1_DIC 0x80000000
156#define EMAC_RDES1_RBS2 0x1FFF0000
157#define EMAC_RDES1_RER 0x00008000
158#define EMAC_RDES1_RCH 0x00004000
159#define EMAC_RDES1_RBS1 0x00001FFF
160#define EMAC_RDES2_RBAP1 0xFFFFFFFF
161#define EMAC_RDES3_RBAP2 0xFFFFFFFF
162#define EMAC_RDES4_TSD 0x00004000
163#define EMAC_RDES4_PV 0x00002000
164#define EMAC_RDES4_PFT 0x00001000
165#define EMAC_RDES4_PMT 0x00000F00
166#define EMAC_RDES4_IPV6PR 0x00000080
167#define EMAC_RDES4_IPV4PR 0x00000040
168#define EMAC_RDES4_IPCB 0x00000020
169#define EMAC_RDES4_IPPE 0x00000010
170#define EMAC_RDES4_IPHE 0x00000008
171#define EMAC_RDES4_IPPT 0x00000007
172#define EMAC_RDES6_RTSL 0xFFFFFFFF
173#define EMAC_RDES7_RTSH 0xFFFFFFFF
175#ifndef ti_sysbios_BIOS___VERS
176 #define msp432e4EthIrqHandler EMAC0_IRQHandler
223error_t msp432e4EthInit(NetInterface *interface);
224void msp432e4EthInitGpio(NetInterface *interface);
225void msp432e4EthInitDmaDesc(NetInterface *interface);
227void msp432e4EthTick(NetInterface *interface);
229void msp432e4EthEnableIrq(NetInterface *interface);
230void msp432e4EthDisableIrq(NetInterface *interface);
231void msp432e4EthIrqHandler(
void);
232void msp432e4EthEventHandler(NetInterface *interface);
234error_t msp432e4EthSendPacket(NetInterface *interface,
235 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
237error_t msp432e4EthReceivePacket(NetInterface *interface);
239error_t msp432e4EthUpdateMacAddrFilter(NetInterface *interface);
240error_t msp432e4EthUpdateMacConfig(NetInterface *interface);
242void msp432e4EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
243 uint8_t regAddr, uint16_t data);
245uint16_t msp432e4EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
248void msp432e4EthDumpPhyReg(
void);
250uint32_t msp432e4EthCalcCrc(
const void *data,
size_t length);
error_t
Error codes.
Definition error.h:43
Network interface controller abstraction layer.
Enhanced RX DMA descriptor.
Definition msp432e4_eth_driver.h:207
Enhanced TX DMA descriptor.
Definition msp432e4_eth_driver.h:190
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283