31#ifndef _NUC472_ETH_DRIVER_H
32#define _NUC472_ETH_DRIVER_H
38#ifndef NUC472_ETH_TX_BUFFER_COUNT
39 #define NUC472_ETH_TX_BUFFER_COUNT 2
40#elif (NUC472_ETH_TX_BUFFER_COUNT < 1)
41 #error NUC472_ETH_TX_BUFFER_COUNT parameter is not valid
45#ifndef NUC472_ETH_TX_BUFFER_SIZE
46 #define NUC472_ETH_TX_BUFFER_SIZE 1536
47#elif (NUC472_ETH_TX_BUFFER_SIZE != 1536)
48 #error NUC472_ETH_TX_BUFFER_SIZE parameter is not valid
52#ifndef NUC472_ETH_RX_BUFFER_COUNT
53 #define NUC472_ETH_RX_BUFFER_COUNT 4
54#elif (NUC472_ETH_RX_BUFFER_COUNT < 1)
55 #error NUC472_ETH_RX_BUFFER_COUNT parameter is not valid
59#ifndef NUC472_ETH_RX_BUFFER_SIZE
60 #define NUC472_ETH_RX_BUFFER_SIZE 1536
61#elif (NUC472_ETH_RX_BUFFER_SIZE != 1536)
62 #error NUC472_ETH_RX_BUFFER_SIZE parameter is not valid
66#ifndef NUC472_ETH_IRQ_PRIORITY_GROUPING
67 #define NUC472_ETH_IRQ_PRIORITY_GROUPING 3
68#elif (NUC472_ETH_IRQ_PRIORITY_GROUPING < 0)
69 #error NUC472_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
73#ifndef NUC472_ETH_IRQ_GROUP_PRIORITY
74 #define NUC472_ETH_IRQ_GROUP_PRIORITY 12
75#elif (NUC472_ETH_IRQ_GROUP_PRIORITY < 0)
76 #error NUC472_ETH_IRQ_GROUP_PRIORITY parameter is not valid
80#ifndef NUC472_ETH_IRQ_SUB_PRIORITY
81 #define NUC472_ETH_IRQ_SUB_PRIORITY 0
82#elif (NUC472_ETH_IRQ_SUB_PRIORITY < 0)
83 #error NUC472_ETH_IRQ_SUB_PRIORITY parameter is not valid
87#define EMAC_TXDES0_OWNER 0x80000000
88#define EMAC_TXDES0_TTSEN 0x00000008
89#define EMAC_TXDES0_INTEN 0x00000004
90#define EMAC_TXDES0_CRCAPP 0x00000002
91#define EMAC_TXDES0_PADEN 0x00000001
92#define EMAC_TXDES1_TXBSA 0xFFFFFFFF
93#define EMAC_TXDES2_COLCNT 0xF0000000
94#define EMAC_TXDES2_TTSAS 0x08000000
95#define EMAC_TXDES2_SQE 0x04000000
96#define EMAC_TXDES2_TXPAUSED 0x02000000
97#define EMAC_TXDES2_TXHALT 0x01000000
98#define EMAC_TXDES2_LCIF 0x00800000
99#define EMAC_TXDES2_TXABTIF 0x00400000
100#define EMAC_TXDES2_NCSIF 0x00200000
101#define EMAC_TXDES2_EXDEFIF 0x00100000
102#define EMAC_TXDES2_TXCPIF 0x00080000
103#define EMAC_TXDES2_DEF 0x00020000
104#define EMAC_TXDES2_TXIF 0x00010000
105#define EMAC_TXDES2_TBC 0x0000FFFF
106#define EMAC_TXDES2_NTXDSA 0xFFFFFFFF
109#define EMAC_RXDES0_OWNER 0x80000000
110#define EMAC_RXDES0_RTSAS 0x00800000
111#define EMAC_RXDES0_RPIF 0x00400000
112#define EMAC_RXDES0_ALIEIF 0x00200000
113#define EMAC_RXDES0_RXGDIF 0x00100000
114#define EMAC_RXDES0_LPIF 0x00080000
115#define EMAC_RXDES0_CRCEIF 0x00020000
116#define EMAC_RXDES0_RXIF 0x00010000
117#define EMAC_RXDES0_RBC 0x0000FFFF
118#define EMAC_RXDES1_RXBSA 0xFFFFFFFF
119#define EMAC_RXDES3_NRXDSA 0xFFFFFFFF
157error_t nuc472EthInit(NetInterface *interface);
158void nuc472EthInitGpio(NetInterface *interface);
159void nuc472EthInitDmaDesc(NetInterface *interface);
161void nuc472EthTick(NetInterface *interface);
163void nuc472EthEnableIrq(NetInterface *interface);
164void nuc472EthDisableIrq(NetInterface *interface);
165void nuc472EthEventHandler(NetInterface *interface);
167error_t nuc472EthSendPacket(NetInterface *interface,
168 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
170error_t nuc472EthReceivePacket(NetInterface *interface);
172error_t nuc472EthUpdateMacAddrFilter(NetInterface *interface);
173error_t nuc472EthUpdateMacConfig(NetInterface *interface);
175void nuc472EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
176 uint8_t regAddr, uint16_t data);
178uint16_t nuc472EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
error_t
Error codes.
Definition error.h:43
Network interface controller abstraction layer.
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283
RX DMA descriptor.
Definition m487_eth_driver.h:145
TX DMA descriptor.
Definition m487_eth_driver.h:132