mikroSDK Reference Manual
ohci.h
1/*
2 * The MIT License (MIT)
3 *
4 * Copyright (c) 2019 Ha Thach (tinyusb.org)
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 *
24 * This file is part of the TinyUSB stack.
25 */
26
27#ifndef _TUSB_OHCI_H_
28#define _TUSB_OHCI_H_
29
30#ifdef __cplusplus
31 extern "C" {
32#endif
33
34//--------------------------------------------------------------------+
35// OHCI CONFIGURATION & CONSTANTS
36//--------------------------------------------------------------------+
37#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enabled
38#define OHCI_PERIODIC_LIST (defined HOST_HCD_XFER_INTERRUPT || defined HOST_HCD_XFER_ISOCHRONOUS)
39
40// TODO merge OHCI with EHCI
41enum {
42 OHCI_MAX_ITD = 4
43};
44
45#define ED_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX)
46#define GTD_MAX ED_MAX
47
48//--------------------------------------------------------------------+
49// OHCI Data Structure
50//--------------------------------------------------------------------+
51typedef struct {
52 uint32_t interrupt_table[32];
53 volatile uint16_t frame_number;
54 volatile uint16_t frame_pad;
55 volatile uint32_t done_head;
56 uint8_t reserved[116+4]; // TODO try to make use of this area if possible, extra 4 byte to make the whole struct size = 256
57}ohci_hcca_t; // TU_ATTR_ALIGNED(256)
58
59TU_VERIFY_STATIC( sizeof(ohci_hcca_t) == 256, "size is not correct" );
60
61// common link item for gtd and itd for list travel
62// use as pointer only
63typedef struct TU_ATTR_ALIGNED(16) {
64 uint32_t reserved[2];
65 volatile uint32_t next;
66 uint32_t reserved2;
67}ohci_td_item_t;
68
69typedef struct TU_ATTR_ALIGNED(16)
70{
71 // Word 0
72 uint32_t used : 1;
73 uint32_t index : 4; // endpoint index the td belongs to, or device address in case of control xfer
74 uint32_t expected_bytes : 13; // TODO available for hcd
75
76 uint32_t buffer_rounding : 1;
77 uint32_t pid : 2;
78 uint32_t delay_interrupt : 3;
79 volatile uint32_t data_toggle : 2;
80 volatile uint32_t error_count : 2;
81 volatile uint32_t condition_code : 4;
82
83 // Word 1
84 volatile uint8_t* current_buffer_pointer;
85
86 // Word 2 : next TD
87 volatile uint32_t next;
88
89 // Word 3
90 uint8_t* buffer_end;
91} ohci_gtd_t;
92
93TU_VERIFY_STATIC( sizeof(ohci_gtd_t) == 16, "size is not correct" );
94
95typedef struct TU_ATTR_ALIGNED(16)
96{
97 // Word 0
98 uint32_t dev_addr : 7;
99 uint32_t ep_number : 4;
100 uint32_t pid : 2;
101 uint32_t speed : 1;
102 uint32_t skip : 1;
103 uint32_t is_iso : 1;
104 uint32_t max_packet_size : 11;
105 // HCD: make use of 5 reserved bits
106 uint32_t used : 1;
107 uint32_t is_interrupt_xfer : 1;
108 uint32_t is_stalled : 1;
109 uint32_t : 2;
110
111 // Word 1
112 uint32_t td_tail;
113
114 // Word 2
115 volatile union {
116 uint32_t address;
117 struct {
118 uint32_t halted : 1;
119 uint32_t toggle : 1;
120 uint32_t : 30;
121 };
122 }td_head;
123
124 // Word 3: next ED
125 uint32_t next;
126} ohci_ed_t;
127
128TU_VERIFY_STATIC( sizeof(ohci_ed_t) == 16, "size is not correct" );
129
130typedef struct TU_ATTR_ALIGNED(32)
131{
132 /*---------- Word 1 ----------*/
133 uint32_t starting_frame : 16;
134 uint32_t : 5; // can be used
135 uint32_t delay_interrupt : 3;
136 uint32_t frame_count : 3;
137 uint32_t : 1; // can be used
138 volatile uint32_t condition_code : 4;
139
140 /*---------- Word 2 ----------*/
141 uint32_t buffer_page0; // 12 lsb bits can be used
142
143 /*---------- Word 3 ----------*/
144 volatile uint32_t next;
145
146 /*---------- Word 4 ----------*/
147 uint32_t buffer_end;
148
149 /*---------- Word 5-8 ----------*/
150 volatile uint16_t offset_packetstatus[8];
151} ochi_itd_t;
152
153TU_VERIFY_STATIC( sizeof(ochi_itd_t) == 32, "size is not correct" );
154
155// structure with member alignment required from large to small
156typedef struct TU_ATTR_ALIGNED(256)
157{
158 ohci_hcca_t hcca;
159
160 ohci_ed_t bulk_head_ed; // static bulk head (dummy)
161 ohci_ed_t period_head_ed; // static periodic list head (dummy)
162
163 // control endpoints has reserved resources
164 struct {
165 ohci_ed_t ed;
166 ohci_gtd_t gtd;
167 }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
168
169 // ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
170 ohci_ed_t ed_pool[ED_MAX];
171 ohci_gtd_t gtd_pool[GTD_MAX];
172
173 volatile uint16_t frame_number_hi;
174
175} ohci_data_t;
176
177//--------------------------------------------------------------------+
178// OHCI Operational Register
179//--------------------------------------------------------------------+
180
181
182//--------------------------------------------------------------------+
183// OHCI Data Organization
184//--------------------------------------------------------------------+
185typedef volatile struct
186{
187 uint32_t revision;
188
189 union {
190 uint32_t control;
191 struct {
192 uint32_t control_bulk_service_ratio : 2;
193 uint32_t periodic_list_enable : 1;
194 uint32_t isochronous_enable : 1;
195 uint32_t control_list_enable : 1;
196 uint32_t bulk_list_enable : 1;
197 uint32_t hc_functional_state : 2;
198 uint32_t interrupt_routing : 1;
199 uint32_t remote_wakeup_connected : 1;
200 uint32_t remote_wakeup_enale : 1;
201 uint32_t TU_RESERVED : 21;
202 }control_bit;
203 };
204
205 union {
206 uint32_t command_status;
207 struct {
208 uint32_t controller_reset : 1;
209 uint32_t control_list_filled : 1;
210 uint32_t bulk_list_filled : 1;
211 uint32_t ownership_change_request : 1;
212 uint32_t : 12;
213 uint32_t scheduling_overrun_count : 2;
214 }command_status_bit;
215 };
216
217 uint32_t interrupt_status;
218 uint32_t interrupt_enable;
219 uint32_t interrupt_disable;
220
221 uint32_t hcca;
222 uint32_t period_current_ed;
223 uint32_t control_head_ed;
224 uint32_t control_current_ed;
225 uint32_t bulk_head_ed;
226 uint32_t bulk_current_ed;
227 uint32_t done_head;
228
229 uint32_t frame_interval;
230 uint32_t frame_remaining;
231 uint32_t frame_number;
232 uint32_t periodic_start;
233 uint32_t lowspeed_threshold;
234
235 union {
236 uint32_t rh_descriptorA;
237 struct {
238 uint32_t number_downstream_ports : 8;
239 uint32_t power_switching_mode : 1;
240 uint32_t no_power_switching : 1;
241 uint32_t device_type : 1;
242 uint32_t overcurrent_protection_mode : 1;
243 uint32_t no_over_current_protection : 1;
244 uint32_t reserved : 11;
245 uint32_t power_on_to_good_time : 8;
246 } rh_descriptorA_bit;
247 };
248
249 union {
250 uint32_t rh_descriptorB;
251 struct {
252 uint32_t device_removable : 16;
253 uint32_t port_power_control_mask : 16;
254 } rh_descriptorB_bit;
255 };
256
257 union {
258 uint32_t rh_status;
259 struct {
260 uint32_t local_power_status : 1; // read Local Power Status; write: Clear Global Power
261 uint32_t over_current_indicator : 1;
262 uint32_t : 13;
263 uint32_t device_remote_wakeup_enable : 1;
264 uint32_t local_power_status_change : 1;
265 uint32_t over_current_indicator_change : 1;
266 uint32_t : 13;
267 uint32_t clear_remote_wakeup_enable : 1;
268 }rh_status_bit;
269 };
270
271 union {
272 uint32_t rhport_status[TUP_OHCI_RHPORTS];
273 struct {
274 uint32_t current_connect_status : 1;
275 uint32_t port_enable_status : 1;
276 uint32_t port_suspend_status : 1;
277 uint32_t port_over_current_indicator : 1;
278 uint32_t port_reset_status : 1;
279 uint32_t : 3;
280 uint32_t port_power_status : 1;
281 uint32_t low_speed_device_attached : 1;
282 uint32_t : 6;
283 uint32_t connect_status_change : 1;
284 uint32_t port_enable_status_change : 1;
285 uint32_t port_suspend_status_change : 1;
286 uint32_t port_over_current_indicator_change : 1;
287 uint32_t port_reset_status_change : 1;
288 uint32_t TU_RESERVED : 11;
289 }rhport_status_bit[TUP_OHCI_RHPORTS];
290 };
291}ohci_registers_t;
292
293TU_VERIFY_STATIC( sizeof(ohci_registers_t) == (0x54 + (4 * TUP_OHCI_RHPORTS)), "size is not correct");
294
295#ifdef __cplusplus
296 }
297#endif
298
299#endif /* _TUSB_OHCI_H_ */
ohci_hcca_t
Definition ohci.h:51
ohci_registers_t
Definition ohci.h:186