31#ifndef _PIC32MX_ETH_DRIVER_H
32#define _PIC32MX_ETH_DRIVER_H
38#ifndef PIC32MX_ETH_TX_BUFFER_COUNT
39 #define PIC32MX_ETH_TX_BUFFER_COUNT 2
40#elif (PIC32MX_ETH_TX_BUFFER_COUNT < 1)
41 #error PIC32MX_ETH_TX_BUFFER_COUNT parameter is not valid
45#ifndef PIC32MX_ETH_TX_BUFFER_SIZE
46 #define PIC32MX_ETH_TX_BUFFER_SIZE 1536
47#elif (PIC32MX_ETH_TX_BUFFER_SIZE != 1536)
48 #error PIC32MX_ETH_TX_BUFFER_SIZE parameter is not valid
52#ifndef PIC32MX_ETH_RX_BUFFER_COUNT
53 #define PIC32MX_ETH_RX_BUFFER_COUNT 4
54#elif (PIC32MX_ETH_RX_BUFFER_COUNT < 1)
55 #error PIC32MX_ETH_RX_BUFFER_COUNT parameter is not valid
59#ifndef PIC32MX_ETH_RX_BUFFER_SIZE
60 #define PIC32MX_ETH_RX_BUFFER_SIZE 1536
61#elif (PIC32MX_ETH_RX_BUFFER_SIZE != 1536)
62 #error PIC32MX_ETH_RX_BUFFER_SIZE parameter is not valid
66#ifndef PIC32MX_ETH_IRQ_PRIORITY
67 #define PIC32MX_ETH_IRQ_PRIORITY 2
68#elif (PIC32MX_ETH_IRQ_PRIORITY < 0)
69 #error PIC32MX_ETH_IRQ_PRIORITY parameter is not valid
73#ifndef PIC32MX_ETH_IRQ_SUB_PRIORITY
74 #define PIC32MX_ETH_IRQ_SUB_PRIORITY 0
75#elif (PIC32MX_ETH_IRQ_SUB_PRIORITY < 0)
76 #error PIC32MX_ETH_IRQ_SUB_PRIORITY parameter is not valid
80#define _EMAC1MCFG_CLKSEL_DIV4 (0 << _EMAC1MCFG_CLKSEL_POSITION)
81#define _EMAC1MCFG_CLKSEL_DIV6 (2 << _EMAC1MCFG_CLKSEL_POSITION)
82#define _EMAC1MCFG_CLKSEL_DIV8 (3 << _EMAC1MCFG_CLKSEL_POSITION)
83#define _EMAC1MCFG_CLKSEL_DIV10 (4 << _EMAC1MCFG_CLKSEL_POSITION)
84#define _EMAC1MCFG_CLKSEL_DIV14 (5 << _EMAC1MCFG_CLKSEL_POSITION)
85#define _EMAC1MCFG_CLKSEL_DIV20 (6 << _EMAC1MCFG_CLKSEL_POSITION)
86#define _EMAC1MCFG_CLKSEL_DIV28 (7 << _EMAC1MCFG_CLKSEL_POSITION)
87#define _EMAC1MCFG_CLKSEL_DIV40 (8 << _EMAC1MCFG_CLKSEL_POSITION)
90#define ETH_TX_CTRL_SOP 0x80000000
91#define ETH_TX_CTRL_EOP 0x40000000
92#define ETH_TX_CTRL_BYTE_COUNT 0x07FF0000
93#define ETH_TX_CTRL_NPV 0x00000100
94#define ETH_TX_CTRL_EOWN 0x00000080
95#define ETH_TX_STATUS1_VLAN 0x00080000
96#define ETH_TX_STATUS1_BACKPRESSURE 0x00040000
97#define ETH_TX_STATUS1_PAUSE 0x00020000
98#define ETH_TX_STATUS1_CONTROL 0x00010000
99#define ETH_TX_STATUS1_TOTAL_BYTES 0x0000FFFF
100#define ETH_TX_STATUS2_UNDERRUN 0x80000000
101#define ETH_TX_STATUS2_GIANT 0x40000000
102#define ETH_TX_STATUS2_LATE_COL 0x20000000
103#define ETH_TX_STATUS2_MAX_COL 0x10000000
104#define ETH_TX_STATUS2_EXCESSIVE_DEFER 0x08000000
105#define ETH_TX_STATUS2_PACKET_DEFER 0x04000000
106#define ETH_TX_STATUS2_BROADCAST 0x02000000
107#define ETH_TX_STATUS2_MULTICAST 0x01000000
108#define ETH_TX_STATUS2_DONE 0x00800000
109#define ETH_TX_STATUS2_LEN_OUT_OF_RANGE 0x00400000
110#define ETH_TX_STATUS2_LEN_CHECK_ERROR 0x00200000
111#define ETH_TX_STATUS2_CRC_ERROR 0x00100000
112#define ETH_TX_STATUS2_COL_COUNT 0x000F0000
113#define ETH_TX_STATUS2_BYTE_COUNT 0x0000FFFF
116#define ETH_RX_CTRL_SOP 0x80000000
117#define ETH_RX_CTRL_EOP 0x40000000
118#define ETH_RX_CTRL_BYTE_COUNT 0x07FF0000
119#define ETH_RX_CTRL_NPV 0x00000100
120#define ETH_RX_CTRL_EOWN 0x00000080
121#define ETH_RX_STATUS1_MULTICAST_MATCH 0x80000000
122#define ETH_RX_STATUS1_BROADCAST_MATCH 0x40000000
123#define ETH_RX_STATUS1_UNICAST_MATCH 0x20000000
124#define ETH_RX_STATUS1_PATTERN_MATCH 0x10000000
125#define ETH_RX_STATUS1_MAGIC_PACKET_MATCH 0x08000000
126#define ETH_RX_STATUS1_HASH_TABLE_MATCH 0x04000000
127#define ETH_RX_STATUS1_NOT_MATCH 0x02000000
128#define ETH_RX_STATUS1_RUNT_PACKET 0x01000000
129#define ETH_RX_STATUS1_PACKET_CHECKSUM 0x0000FFFF
130#define ETH_RX_STATUS2_VLAN 0x40000000
131#define ETH_RX_STATUS2_UNKNOWN_OP_CODE 0x20000000
132#define ETH_RX_STATUS2_PAUSE 0x10000000
133#define ETH_RX_STATUS2_CONTROL 0x08000000
134#define ETH_RX_STATUS2_DRIBBLE_NIBBLE 0x04000000
135#define ETH_RX_STATUS2_BROADCAST 0x02000000
136#define ETH_RX_STATUS2_MULTICAST 0x01000000
137#define ETH_RX_STATUS2_OK 0x00800000
138#define ETH_RX_STATUS2_LEN_OUT_OF_RANGE 0x00400000
139#define ETH_RX_STATUS2_LEN_CHECK_ERROR 0x00200000
140#define ETH_RX_STATUS2_CRC_ERROR 0x00100000
141#define ETH_RX_STATUS2_CODE_VIOLATION 0x00080000
142#define ETH_RX_STATUS2_CARRIER_EVENT 0x00040000
143#define ETH_RX_STATUS2_RXDV_EVENT 0x00020000
144#define ETH_RX_STATUS2_LONG_EVENT 0x00010000
145#define ETH_RX_STATUS2_BYTE_COUNT 0x0000FFFF
185error_t pic32mxEthInit(NetInterface *interface);
186void pic32mxEthInitGpio(NetInterface *interface);
187void pic32mxEthInitBufferDesc(NetInterface *interface);
189void pic32mxEthTick(NetInterface *interface);
191void pic32mxEthEnableIrq(NetInterface *interface);
192void pic32mxEthDisableIrq(NetInterface *interface);
193void pic32mxEthIrqHandler(
void);
194void pic32mxEthEventHandler(NetInterface *interface);
196error_t pic32mxEthSendPacket(NetInterface *interface,
197 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
199error_t pic32mxEthReceivePacket(NetInterface *interface);
201error_t pic32mxEthUpdateMacAddrFilter(NetInterface *interface);
202error_t pic32mxEthUpdateMacConfig(NetInterface *interface);
204void pic32mxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
205 uint8_t regAddr, uint16_t data);
207uint16_t pic32mxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
210uint32_t pic32mxEthCalcCrc(
const void *data,
size_t length);
error_t
Error codes.
Definition error.h:43
Network interface controller abstraction layer.
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283
RX buffer descriptor.
Definition pic32mx_eth_driver.h:172
TX buffer descriptor.
Definition pic32mx_eth_driver.h:158