mikroSDK Reference Manual
pic32mz_eth_driver.h
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1
31#ifndef _PIC32MZ_ETH_DRIVER_H
32#define _PIC32MZ_ETH_DRIVER_H
33
34//Dependencies
35#include "core/nic.h"
36
37//Number of TX buffers
38#ifndef PIC32MZ_ETH_TX_BUFFER_COUNT
39 #define PIC32MZ_ETH_TX_BUFFER_COUNT 3
40#elif (PIC32MZ_ETH_TX_BUFFER_COUNT < 1)
41 #error PIC32MZ_ETH_TX_BUFFER_COUNT parameter is not valid
42#endif
43
44//TX buffer size
45#ifndef PIC32MZ_ETH_TX_BUFFER_SIZE
46 #define PIC32MZ_ETH_TX_BUFFER_SIZE 1536
47#elif (PIC32MZ_ETH_TX_BUFFER_SIZE != 1536)
48 #error PIC32MZ_ETH_TX_BUFFER_SIZE parameter is not valid
49#endif
50
51//Number of RX buffers
52#ifndef PIC32MZ_ETH_RX_BUFFER_COUNT
53 #define PIC32MZ_ETH_RX_BUFFER_COUNT 6
54#elif (PIC32MZ_ETH_RX_BUFFER_COUNT < 1)
55 #error PIC32MZ_ETH_RX_BUFFER_COUNT parameter is not valid
56#endif
57
58//RX buffer size
59#ifndef PIC32MZ_ETH_RX_BUFFER_SIZE
60 #define PIC32MZ_ETH_RX_BUFFER_SIZE 1536
61#elif (PIC32MZ_ETH_RX_BUFFER_SIZE != 1536)
62 #error PIC32MZ_ETH_RX_BUFFER_SIZE parameter is not valid
63#endif
64
65//Ethernet interrupt priority
66#ifndef PIC32MZ_ETH_IRQ_PRIORITY
67 #define PIC32MZ_ETH_IRQ_PRIORITY 2
68#elif (PIC32MZ_ETH_IRQ_PRIORITY < 0)
69 #error PIC32MZ_ETH_IRQ_PRIORITY parameter is not valid
70#endif
71
72//Ethernet interrupt subpriority
73#ifndef PIC32MZ_ETH_IRQ_SUB_PRIORITY
74 #define PIC32MZ_ETH_IRQ_SUB_PRIORITY 0
75#elif (PIC32MZ_ETH_IRQ_SUB_PRIORITY < 0)
76 #error PIC32MZ_ETH_IRQ_SUB_PRIORITY parameter is not valid
77#endif
78
79//EMAC1MCFG register
80#define _EMAC1MCFG_CLKSEL_DIV4 (0 << _EMAC1MCFG_CLKSEL_POSITION)
81#define _EMAC1MCFG_CLKSEL_DIV6 (2 << _EMAC1MCFG_CLKSEL_POSITION)
82#define _EMAC1MCFG_CLKSEL_DIV8 (3 << _EMAC1MCFG_CLKSEL_POSITION)
83#define _EMAC1MCFG_CLKSEL_DIV10 (4 << _EMAC1MCFG_CLKSEL_POSITION)
84#define _EMAC1MCFG_CLKSEL_DIV14 (5 << _EMAC1MCFG_CLKSEL_POSITION)
85#define _EMAC1MCFG_CLKSEL_DIV20 (6 << _EMAC1MCFG_CLKSEL_POSITION)
86#define _EMAC1MCFG_CLKSEL_DIV28 (7 << _EMAC1MCFG_CLKSEL_POSITION)
87#define _EMAC1MCFG_CLKSEL_DIV40 (8 << _EMAC1MCFG_CLKSEL_POSITION)
88#define _EMAC1MCFG_CLKSEL_DIV48 (9 << _EMAC1MCFG_CLKSEL_POSITION)
89#define _EMAC1MCFG_CLKSEL_DIV50 (10 << _EMAC1MCFG_CLKSEL_POSITION)
90
91//Transmit buffer descriptor flags
92#define ETH_TX_CTRL_SOP 0x80000000
93#define ETH_TX_CTRL_EOP 0x40000000
94#define ETH_TX_CTRL_BYTE_COUNT 0x07FF0000
95#define ETH_TX_CTRL_NPV 0x00000100
96#define ETH_TX_CTRL_EOWN 0x00000080
97#define ETH_TX_STATUS1_VLAN 0x00080000
98#define ETH_TX_STATUS1_BACKPRESSURE 0x00040000
99#define ETH_TX_STATUS1_PAUSE 0x00020000
100#define ETH_TX_STATUS1_CONTROL 0x00010000
101#define ETH_TX_STATUS1_TOTAL_BYTES 0x0000FFFF
102#define ETH_TX_STATUS2_UNDERRUN 0x80000000
103#define ETH_TX_STATUS2_GIANT 0x40000000
104#define ETH_TX_STATUS2_LATE_COL 0x20000000
105#define ETH_TX_STATUS2_MAX_COL 0x10000000
106#define ETH_TX_STATUS2_EXCESSIVE_DEFER 0x08000000
107#define ETH_TX_STATUS2_PACKET_DEFER 0x04000000
108#define ETH_TX_STATUS2_BROADCAST 0x02000000
109#define ETH_TX_STATUS2_MULTICAST 0x01000000
110#define ETH_TX_STATUS2_DONE 0x00800000
111#define ETH_TX_STATUS2_LEN_OUT_OF_RANGE 0x00400000
112#define ETH_TX_STATUS2_LEN_CHECK_ERROR 0x00200000
113#define ETH_TX_STATUS2_CRC_ERROR 0x00100000
114#define ETH_TX_STATUS2_COL_COUNT 0x000F0000
115#define ETH_TX_STATUS2_BYTE_COUNT 0x0000FFFF
116
117//Receive buffer descriptor flags
118#define ETH_RX_CTRL_SOP 0x80000000
119#define ETH_RX_CTRL_EOP 0x40000000
120#define ETH_RX_CTRL_BYTE_COUNT 0x07FF0000
121#define ETH_RX_CTRL_NPV 0x00000100
122#define ETH_RX_CTRL_EOWN 0x00000080
123#define ETH_RX_STATUS1_MULTICAST_MATCH 0x80000000
124#define ETH_RX_STATUS1_BROADCAST_MATCH 0x40000000
125#define ETH_RX_STATUS1_UNICAST_MATCH 0x20000000
126#define ETH_RX_STATUS1_PATTERN_MATCH 0x10000000
127#define ETH_RX_STATUS1_MAGIC_PACKET_MATCH 0x08000000
128#define ETH_RX_STATUS1_HASH_TABLE_MATCH 0x04000000
129#define ETH_RX_STATUS1_NOT_MATCH 0x02000000
130#define ETH_RX_STATUS1_RUNT_PACKET 0x01000000
131#define ETH_RX_STATUS1_PACKET_CHECKSUM 0x0000FFFF
132#define ETH_RX_STATUS2_VLAN 0x40000000
133#define ETH_RX_STATUS2_UNKNOWN_OP_CODE 0x20000000
134#define ETH_RX_STATUS2_PAUSE 0x10000000
135#define ETH_RX_STATUS2_CONTROL 0x08000000
136#define ETH_RX_STATUS2_DRIBBLE_NIBBLE 0x04000000
137#define ETH_RX_STATUS2_BROADCAST 0x02000000
138#define ETH_RX_STATUS2_MULTICAST 0x01000000
139#define ETH_RX_STATUS2_OK 0x00800000
140#define ETH_RX_STATUS2_LEN_OUT_OF_RANGE 0x00400000
141#define ETH_RX_STATUS2_LEN_CHECK_ERROR 0x00200000
142#define ETH_RX_STATUS2_CRC_ERROR 0x00100000
143#define ETH_RX_STATUS2_CODE_VIOLATION 0x00080000
144#define ETH_RX_STATUS2_CARRIER_EVENT 0x00040000
145#define ETH_RX_STATUS2_RXDV_EVENT 0x00020000
146#define ETH_RX_STATUS2_LONG_EVENT 0x00010000
147#define ETH_RX_STATUS2_BYTE_COUNT 0x0000FFFF
148
149//C++ guard
150#ifdef __cplusplus
151extern "C" {
152#endif
153
154
159typedef struct
160{
161 uint32_t control;
162 uint32_t address;
163 uint32_t status1;
164 uint32_t status2;
165 uint32_t next;
167
168
173typedef struct
174{
175 uint32_t control;
176 uint32_t address;
177 uint32_t status1;
178 uint32_t status2;
179 uint32_t next;
181
182
183//PIC32MZ Ethernet MAC driver
184extern const NicDriver pic32mzEthDriver;
185
186//PIC32MZ Ethernet MAC related functions
187error_t pic32mzEthInit(NetInterface *interface);
188void pic32mzEthInitGpio(NetInterface *interface);
189void pic32mzEthInitBufferDesc(NetInterface *interface);
190
191void pic32mzEthTick(NetInterface *interface);
192
193void pic32mzEthEnableIrq(NetInterface *interface);
194void pic32mzEthDisableIrq(NetInterface *interface);
195void pic32mzEthIrqHandler(void);
196void pic32mzEthEventHandler(NetInterface *interface);
197
198error_t pic32mzEthSendPacket(NetInterface *interface,
199 const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
200
201error_t pic32mzEthReceivePacket(NetInterface *interface);
202
203error_t pic32mzEthUpdateMacAddrFilter(NetInterface *interface);
204error_t pic32mzEthUpdateMacConfig(NetInterface *interface);
205
206void pic32mzEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
207 uint8_t regAddr, uint16_t data);
208
209uint16_t pic32mzEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
210 uint8_t regAddr);
211
212uint32_t pic32mzEthCalcCrc(const void *data, size_t length);
213
214//C++ guard
215#ifdef __cplusplus
216}
217#endif
218
219#endif
error_t
Error codes.
Definition error.h:43
Network interface controller abstraction layer.
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283
RX buffer descriptor.
Definition pic32mz_eth_driver.h:174
TX buffer descriptor.
Definition pic32mz_eth_driver.h:160