31#ifndef _RA6_ETH_DRIVER_H
32#define _RA6_ETH_DRIVER_H
38#ifndef RA6_ETH_TX_BUFFER_COUNT
39 #define RA6_ETH_TX_BUFFER_COUNT 3
40#elif (RA6_ETH_TX_BUFFER_COUNT < 1)
41 #error RA6_ETH_TX_BUFFER_COUNT parameter is not valid
45#ifndef RA6_ETH_TX_BUFFER_SIZE
46 #define RA6_ETH_TX_BUFFER_SIZE 1536
47#elif (RA6_ETH_TX_BUFFER_SIZE != 1536)
48 #error RA6_ETH_TX_BUFFER_SIZE parameter is not valid
52#ifndef RA6_ETH_RX_BUFFER_COUNT
53 #define RA6_ETH_RX_BUFFER_COUNT 6
54#elif (RA6_ETH_RX_BUFFER_COUNT < 1)
55 #error RA6_ETH_RX_BUFFER_COUNT parameter is not valid
59#ifndef RA6_ETH_RX_BUFFER_SIZE
60 #define RA6_ETH_RX_BUFFER_SIZE 1536
61#elif (RA6_ETH_RX_BUFFER_SIZE != 1536)
62 #error RA6_ETH_RX_BUFFER_SIZE parameter is not valid
66#ifndef RA6_ETH_IRQ_PRIORITY_GROUPING
67 #define RA6_ETH_IRQ_PRIORITY_GROUPING 3
68#elif (RA6_ETH_IRQ_PRIORITY_GROUPING < 0)
69 #error RA6_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
73#ifndef RA6_ETH_IRQ_GROUP_PRIORITY
74 #define RA6_ETH_IRQ_GROUP_PRIORITY 12
75#elif (RA6_ETH_IRQ_GROUP_PRIORITY < 0)
76 #error RA6_ETH_IRQ_GROUP_PRIORITY parameter is not valid
80#ifndef RA6_ETH_IRQ_SUB_PRIORITY
81 #define RA6_ETH_IRQ_SUB_PRIORITY 0
82#elif (RA6_ETH_IRQ_SUB_PRIORITY < 0)
83 #error RA6_ETH_IRQ_SUB_PRIORITY parameter is not valid
87#ifndef RA6_ETH_RAM_SECTION
88 #define RA6_ETH_RAM_SECTION ".ns_buffer"
93 #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
97#define EDMAC_TD0_TACT 0x80000000
98#define EDMAC_TD0_TDLE 0x40000000
99#define EDMAC_TD0_TFP_SOF 0x20000000
100#define EDMAC_TD0_TFP_EOF 0x10000000
101#define EDMAC_TD0_TFE 0x08000000
102#define EDMAC_TD0_TWBI 0x04000000
103#define EDMAC_TD0_TFS_MASK 0x0000010F
104#define EDMAC_TD0_TFS_TABT 0x00000100
105#define EDMAC_TD0_TFS_CND 0x00000008
106#define EDMAC_TD0_TFS_DLC 0x00000004
107#define EDMAC_TD0_TFS_CD 0x00000002
108#define EDMAC_TD0_TFS_TRO 0x00000001
109#define EDMAC_TD1_TBL 0xFFFF0000
110#define EDMAC_TD2_TBA 0xFFFFFFFF
113#define EDMAC_RD0_RACT 0x80000000
114#define EDMAC_RD0_RDLE 0x40000000
115#define EDMAC_RD0_RFP_SOF 0x20000000
116#define EDMAC_RD0_RFP_EOF 0x10000000
117#define EDMAC_RD0_RFE 0x08000000
118#define EDMAC_RD0_RFS_MASK 0x0000039F
119#define EDMAC_RD0_RFS_RFOF 0x00000200
120#define EDMAC_RD0_RFS_RABT 0x00000100
121#define EDMAC_RD0_RFS_RMAF 0x00000080
122#define EDMAC_RD0_RFS_RRF 0x00000010
123#define EDMAC_RD0_RFS_RTLF 0x00000008
124#define EDMAC_RD0_RFS_RTSF 0x00000004
125#define EDMAC_RD0_RFS_PRE 0x00000002
126#define EDMAC_RD0_RFS_CERF 0x00000001
127#define EDMAC_RD1_RBL 0xFFFF0000
128#define EDMAC_RD1_RFL 0x0000FFFF
129#define EDMAC_RD2_RBA 0xFFFFFFFF
167error_t ra6EthInit(NetInterface *interface);
168void ra6EthInitGpio(NetInterface *interface);
169void ra6EthInitDmaDesc(NetInterface *interface);
171void ra6EthTick(NetInterface *interface);
173void ra6EthEnableIrq(NetInterface *interface);
174void ra6EthDisableIrq(NetInterface *interface);
175void ra6EthEventHandler(NetInterface *interface);
177error_t ra6EthSendPacket(NetInterface *interface,
178 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
180error_t ra6EthReceivePacket(NetInterface *interface);
182error_t ra6EthUpdateMacAddrFilter(NetInterface *interface);
183error_t ra6EthUpdateMacConfig(NetInterface *interface);
185void ra6EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
186 uint8_t regAddr, uint16_t data);
188uint16_t ra6EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
191void ra6EthWriteSmi(uint32_t data, uint_t length);
192uint32_t ra6EthReadSmi(uint_t length);
error_t
Error codes.
Definition error.h:43
Network interface controller abstraction layer.
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283
Receive DMA descriptor.
Definition ra6_eth_driver.h:155
Transmit DMA descriptor.
Definition ra6_eth_driver.h:142