mikroSDK Reference Manual
rx62n_eth_driver.h
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1
31#ifndef _RX62N_ETH_DRIVER_H
32#define _RX62N_ETH_DRIVER_H
33
34//Dependencies
35#include "core/nic.h"
36
37//Number of TX buffers
38#ifndef RX62N_ETH_TX_BUFFER_COUNT
39 #define RX62N_ETH_TX_BUFFER_COUNT 3
40#elif (RX62N_ETH_TX_BUFFER_COUNT < 1)
41 #error RX62N_ETH_TX_BUFFER_COUNT parameter is not valid
42#endif
43
44//TX buffer size
45#ifndef RX62N_ETH_TX_BUFFER_SIZE
46 #define RX62N_ETH_TX_BUFFER_SIZE 1536
47#elif (RX62N_ETH_TX_BUFFER_SIZE != 1536)
48 #error RX62N_ETH_TX_BUFFER_SIZE parameter is not valid
49#endif
50
51//Number of RX buffers
52#ifndef RX62N_ETH_RX_BUFFER_COUNT
53 #define RX62N_ETH_RX_BUFFER_COUNT 6
54#elif (RX62N_ETH_RX_BUFFER_COUNT < 1)
55 #error RX62N_ETH_RX_BUFFER_COUNT parameter is not valid
56#endif
57
58//RX buffer size
59#ifndef RX62N_ETH_RX_BUFFER_SIZE
60 #define RX62N_ETH_RX_BUFFER_SIZE 1536
61#elif (RX62N_ETH_RX_BUFFER_SIZE != 1536)
62 #error RX62N_ETH_RX_BUFFER_SIZE parameter is not valid
63#endif
64
65//Ethernet interrupt priority
66#ifndef RX62N_ETH_IRQ_PRIORITY
67 #define RX62N_ETH_IRQ_PRIORITY 2
68#elif (RX62N_ETH_IRQ_PRIORITY < 0)
69 #error RX62N_ETH_IRQ_PRIORITY parameter is not valid
70#endif
71
72//EESR register
73#define EDMAC_EESR_TWB 0x40000000
74#define EDMAC_EESR_TABT 0x04000000
75#define EDMAC_EESR_RABT 0x02000000
76#define EDMAC_EESR_RFCOF 0x01000000
77#define EDMAC_EESR_ADE 0x00800000
78#define EDMAC_EESR_ECI 0x00400000
79#define EDMAC_EESR_TC 0x00200000
80#define EDMAC_EESR_TDE 0x00100000
81#define EDMAC_EESR_TFUF 0x00080000
82#define EDMAC_EESR_FR 0x00040000
83#define EDMAC_EESR_RDE 0x00020000
84#define EDMAC_EESR_RFOF 0x00010000
85#define EDMAC_EESR_CND 0x00000800
86#define EDMAC_EESR_DLC 0x00000400
87#define EDMAC_EESR_CD 0x00000200
88#define EDMAC_EESR_TRO 0x00000100
89#define EDMAC_EESR_RMAF 0x00000080
90#define EDMAC_EESR_RRF 0x00000010
91#define EDMAC_EESR_RTLF 0x00000008
92#define EDMAC_EESR_RTSF 0x00000004
93#define EDMAC_EESR_PRE 0x00000002
94#define EDMAC_EESR_CERF 0x00000001
95
96//Transmit DMA descriptor flags
97#define EDMAC_TD0_TACT 0x80000000
98#define EDMAC_TD0_TDLE 0x40000000
99#define EDMAC_TD0_TFP_SOF 0x20000000
100#define EDMAC_TD0_TFP_EOF 0x10000000
101#define EDMAC_TD0_TFE 0x08000000
102#define EDMAC_TD0_TWBI 0x04000000
103#define EDMAC_TD0_TFS_MASK 0x0000010F
104#define EDMAC_TD0_TFS_TABT 0x00000100
105#define EDMAC_TD0_TFS_CND 0x00000008
106#define EDMAC_TD0_TFS_DLC 0x00000004
107#define EDMAC_TD0_TFS_CD 0x00000002
108#define EDMAC_TD0_TFS_TRO 0x00000001
109#define EDMAC_TD1_TBL 0xFFFF0000
110#define EDMAC_TD2_TBA 0xFFFFFFFF
111
112//Receive DMA descriptor flags
113#define EDMAC_RD0_RACT 0x80000000
114#define EDMAC_RD0_RDLE 0x40000000
115#define EDMAC_RD0_RFP_SOF 0x20000000
116#define EDMAC_RD0_RFP_EOF 0x10000000
117#define EDMAC_RD0_RFE 0x08000000
118#define EDMAC_RD0_RFS_MASK 0x0000039F
119#define EDMAC_RD0_RFS_RFOF 0x00000200
120#define EDMAC_RD0_RFS_RABT 0x00000100
121#define EDMAC_RD0_RFS_RMAF 0x00000080
122#define EDMAC_RD0_RFS_RRF 0x00000010
123#define EDMAC_RD0_RFS_RTLF 0x00000008
124#define EDMAC_RD0_RFS_RTSF 0x00000004
125#define EDMAC_RD0_RFS_PRE 0x00000002
126#define EDMAC_RD0_RFS_CERF 0x00000001
127#define EDMAC_RD1_RBL 0xFFFF0000
128#define EDMAC_RD1_RFL 0x0000FFFF
129#define EDMAC_RD2_RBA 0xFFFFFFFF
130
131//C++ guard
132#ifdef __cplusplus
133extern "C" {
134#endif
135
136
141typedef struct
142{
143 uint32_t td0;
144 uint32_t td1;
145 uint32_t td2;
146 uint32_t padding;
148
149
154typedef struct
155{
156 uint32_t rd0;
157 uint32_t rd1;
158 uint32_t rd2;
159 uint32_t padding;
161
162
163//RX62N Ethernet MAC driver
164extern const NicDriver rx62nEthDriver;
165
166//RX62N Ethernet MAC related functions
167error_t rx62nEthInit(NetInterface *interface);
168void rx62nEthInitGpio(NetInterface *interface);
169void rx62nEthInitDmaDesc(NetInterface *interface);
170
171void rx62nEthTick(NetInterface *interface);
172
173void rx62nEthEnableIrq(NetInterface *interface);
174void rx62nEthDisableIrq(NetInterface *interface);
175void rx62nEthEventHandler(NetInterface *interface);
176
177error_t rx62nEthSendPacket(NetInterface *interface,
178 const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
179
180error_t rx62nEthReceivePacket(NetInterface *interface);
181
182error_t rx62nEthUpdateMacAddrFilter(NetInterface *interface);
183error_t rx62nEthUpdateMacConfig(NetInterface *interface);
184
185void rx62nEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
186 uint8_t regAddr, uint16_t data);
187
188uint16_t rx62nEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
189 uint8_t regAddr);
190
191void rx62nEthWriteSmi(uint32_t data, uint_t length);
192uint32_t rx62nEthReadSmi(uint_t length);
193
194//C++ guard
195#ifdef __cplusplus
196}
197#endif
198
199#endif
error_t
Error codes.
Definition error.h:43
Network interface controller abstraction layer.
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283
Receive DMA descriptor.
Definition rx62n_eth_driver.h:155
Transmit DMA descriptor.
Definition rx62n_eth_driver.h:142