31#ifndef _SAM4E_ETH_DRIVER_H
32#define _SAM4E_ETH_DRIVER_H
35#ifndef SAM4E_ETH_TX_BUFFER_COUNT
36 #define SAM4E_ETH_TX_BUFFER_COUNT 2
37#elif (SAM4E_ETH_TX_BUFFER_COUNT < 1)
38 #error SAM4E_ETH_TX_BUFFER_COUNT parameter is not valid
42#ifndef SAM4E_ETH_TX_BUFFER_SIZE
43 #define SAM4E_ETH_TX_BUFFER_SIZE 1536
44#elif (SAM4E_ETH_TX_BUFFER_SIZE != 1536)
45 #error SAM4E_ETH_TX_BUFFER_SIZE parameter is not valid
49#ifndef SAM4E_ETH_RX_BUFFER_COUNT
50 #define SAM4E_ETH_RX_BUFFER_COUNT 48
51#elif (SAM4E_ETH_RX_BUFFER_COUNT < 12)
52 #error SAM4E_ETH_RX_BUFFER_COUNT parameter is not valid
56#ifndef SAM4E_ETH_RX_BUFFER_SIZE
57 #define SAM4E_ETH_RX_BUFFER_SIZE 128
58#elif (SAM4E_ETH_RX_BUFFER_SIZE != 128)
59 #error SAM4E_ETH_RX_BUFFER_SIZE parameter is not valid
63#ifndef SAM4E_ETH_IRQ_PRIORITY_GROUPING
64 #define SAM4E_ETH_IRQ_PRIORITY_GROUPING 3
65#elif (SAM4E_ETH_IRQ_PRIORITY_GROUPING < 0)
66 #error SAM4E_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70#ifndef SAM4E_ETH_IRQ_GROUP_PRIORITY
71 #define SAM4E_ETH_IRQ_GROUP_PRIORITY 12
72#elif (SAM4E_ETH_IRQ_GROUP_PRIORITY < 0)
73 #error SAM4E_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77#ifndef SAM4E_ETH_IRQ_SUB_PRIORITY
78 #define SAM4E_ETH_IRQ_SUB_PRIORITY 0
79#elif (SAM4E_ETH_IRQ_SUB_PRIORITY < 0)
80 #error SAM4E_ETH_IRQ_SUB_PRIORITY parameter is not valid
85 #define PIO_PD6A_GRX1 PIO_PD6A_GRX0
89#define GMAC_MII_MASK (PIO_PD16A_GTX3 | \
90 PIO_PD15A_GTX2 | PIO_PD14A_GRXCK | PIO_PD13A_GCOL | PIO_PD12A_GRX3 | \
91 PIO_PD11A_GRX2 | PIO_PD10A_GCRS | PIO_PD9A_GMDIO | PIO_PD8A_GMDC | \
92 PIO_PD7A_GRXER | PIO_PD6A_GRX1 | PIO_PD5A_GRX0 | PIO_PD4A_GRXDV | \
93 PIO_PD3A_GTX1 | PIO_PD2A_GTX0 | PIO_PD1A_GTXEN | PIO_PD0A_GTXCK)
96#define GMAC_TX_USED 0x80000000
97#define GMAC_TX_WRAP 0x40000000
98#define GMAC_TX_RLE_ERROR 0x20000000
99#define GMAC_TX_UNDERRUN_ERROR 0x10000000
100#define GMAC_TX_AHB_ERROR 0x08000000
101#define GMAC_TX_LATE_COL_ERROR 0x04000000
102#define GMAC_TX_CHECKSUM_ERROR 0x00700000
103#define GMAC_TX_NO_CRC 0x00010000
104#define GMAC_TX_LAST 0x00008000
105#define GMAC_TX_LENGTH 0x00003FFF
108#define GMAC_RX_ADDRESS 0xFFFFFFFC
109#define GMAC_RX_WRAP 0x00000002
110#define GMAC_RX_OWNERSHIP 0x00000001
111#define GMAC_RX_BROADCAST 0x80000000
112#define GMAC_RX_MULTICAST_HASH 0x40000000
113#define GMAC_RX_UNICAST_HASH 0x20000000
114#define GMAC_RX_SAR 0x08000000
115#define GMAC_RX_SAR_MASK 0x06000000
116#define GMAC_RX_TYPE_ID 0x01000000
117#define GMAC_RX_SNAP 0x01000000
118#define GMAC_RX_TYPE_ID_MASK 0x00C00000
119#define GMAC_RX_CHECKSUM_VALID 0x00C00000
120#define GMAC_RX_VLAN_TAG 0x00200000
121#define GMAC_RX_PRIORITY_TAG 0x00100000
122#define GMAC_RX_VLAN_PRIORITY 0x000E0000
123#define GMAC_RX_CFI 0x00010000
124#define GMAC_RX_EOF 0x00008000
125#define GMAC_RX_SOF 0x00004000
126#define GMAC_RX_LENGTH_MSB 0x00002000
127#define GMAC_RX_BAD_FCS 0x00002000
128#define GMAC_RX_LENGTH 0x00001FFF
162error_t sam4eEthInit(NetInterface *interface);
163void sam4eEthInitGpio(NetInterface *interface);
164void sam4eEthInitBufferDesc(NetInterface *interface);
166void sam4eEthTick(NetInterface *interface);
168void sam4eEthEnableIrq(NetInterface *interface);
169void sam4eEthDisableIrq(NetInterface *interface);
170void sam4eEthEventHandler(NetInterface *interface);
172error_t sam4eEthSendPacket(NetInterface *interface,
173 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
175error_t sam4eEthReceivePacket(NetInterface *interface);
177error_t sam4eEthUpdateMacAddrFilter(NetInterface *interface);
178error_t sam4eEthUpdateMacConfig(NetInterface *interface);
180void sam4eEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
181 uint8_t regAddr, uint16_t data);
183uint16_t sam4eEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
error_t
Error codes.
Definition error.h:43
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283
Receive buffer descriptor.
Definition sam4e_eth_driver.h:152
Transmit buffer descriptor.
Definition sam4e_eth_driver.h:141