31#ifndef _SAM9X60_ETH1_DRIVER_H
32#define _SAM9X60_ETH1_DRIVER_H
35#ifndef SAM9X60_ETH1_TX_BUFFER_COUNT
36 #define SAM9X60_ETH1_TX_BUFFER_COUNT 8
37#elif (SAM9X60_ETH1_TX_BUFFER_COUNT < 1)
38 #error SAM9X60_ETH1_TX_BUFFER_COUNT parameter is not valid
42#ifndef SAM9X60_ETH1_TX_BUFFER_SIZE
43 #define SAM9X60_ETH1_TX_BUFFER_SIZE 1536
44#elif (SAM9X60_ETH1_TX_BUFFER_SIZE != 1536)
45 #error SAM9X60_ETH1_TX_BUFFER_SIZE parameter is not valid
49#ifndef SAM9X60_ETH1_RX_BUFFER_COUNT
50 #define SAM9X60_ETH1_RX_BUFFER_COUNT 96
51#elif (SAM9X60_ETH1_RX_BUFFER_COUNT < 12)
52 #error SAM9X60_ETH1_RX_BUFFER_COUNT parameter is not valid
56#ifndef SAM9X60_ETH1_RX_BUFFER_SIZE
57 #define SAM9X60_ETH1_RX_BUFFER_SIZE 128
58#elif (SAM9X60_ETH1_RX_BUFFER_SIZE != 128)
59 #error SAM9X60_ETH1_RX_BUFFER_SIZE parameter is not valid
63#ifndef SAM9X60_ETH1_IRQ_PRIORITY
64 #define SAM9X60_ETH1_IRQ_PRIORITY 0
65#elif (SAM9X60_ETH1_IRQ_PRIORITY < 0)
66 #error SAM9X60_ETH1_IRQ_PRIORITY parameter is not valid
70#ifndef SAM9X60_ETH1_RAM_SECTION
71 #define SAM9X60_ETH1_RAM_SECTION ".region_nocache"
75#define EMAC0_RMII_MASK (PIO_PB10A_E0_TX1 | PIO_PB9A_E0_TX0 | \
76 PIO_PB7A_E0_TXEN | PIO_PB6A_E0_MDC | PIO_PB5A_E0_MDIO | PIO_PB4A_E0_TXCK | \
77 PIO_PB3A_E0_RXDV | PIO_PB2A_E0_RXER | PIO_PB1A_E0_RX1 | PIO_PB0A_E0_RX0)
80#define EMAC_TX_USED 0x80000000
81#define EMAC_TX_WRAP 0x40000000
82#define EMAC_TX_ERROR 0x20000000
83#define EMAC_TX_UNDERRUN 0x10000000
84#define EMAC_TX_EXHAUSTED 0x08000000
85#define EMAC_TX_NO_CRC 0x00010000
86#define EMAC_TX_LAST 0x00008000
87#define EMAC_TX_LENGTH 0x000007FF
90#define EMAC_RX_ADDRESS 0xFFFFFFFC
91#define EMAC_RX_WRAP 0x00000002
92#define EMAC_RX_OWNERSHIP 0x00000001
93#define EMAC_RX_BROADCAST 0x80000000
94#define EMAC_RX_MULTICAST_HASH 0x40000000
95#define EMAC_RX_UNICAST_HASH 0x20000000
96#define EMAC_RX_EXT_ADDR 0x10000000
97#define EMAC_RX_SAR1 0x04000000
98#define EMAC_RX_SAR2 0x02000000
99#define EMAC_RX_SAR3 0x01000000
100#define EMAC_RX_SAR4 0x00800000
101#define EMAC_RX_TYPE_ID 0x00400000
102#define EMAC_RX_VLAN_TAG 0x00200000
103#define EMAC_RX_PRIORITY_TAG 0x00100000
104#define EMAC_RX_VLAN_PRIORITY 0x000E0000
105#define EMAC_RX_CFI 0x00010000
106#define EMAC_RX_EOF 0x00008000
107#define EMAC_RX_SOF 0x00004000
108#define EMAC_RX_OFFSET 0x00003000
109#define EMAC_RX_LENGTH 0x00000FFF
143error_t sam9x60Eth1Init(NetInterface *interface);
144void sam9x60Eth1InitGpio(NetInterface *interface);
145void sam9x60Eth1InitBufferDesc(NetInterface *interface);
147void sam9x60Eth1Tick(NetInterface *interface);
149void sam9x60Eth1EnableIrq(NetInterface *interface);
150void sam9x60Eth1DisableIrq(NetInterface *interface);
151void sam9x60Eth1IrqHandler(
void);
152void sam9x60Eth1EventHandler(NetInterface *interface);
154error_t sam9x60Eth1SendPacket(NetInterface *interface,
155 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
157error_t sam9x60Eth1ReceivePacket(NetInterface *interface);
159error_t sam9x60Eth1UpdateMacAddrFilter(NetInterface *interface);
160error_t sam9x60Eth1UpdateMacConfig(NetInterface *interface);
162void sam9x60Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr,
163 uint8_t regAddr, uint16_t data);
165uint16_t sam9x60Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
169void emacIrqWrapper(
void);
error_t
Error codes.
Definition error.h:43
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283
Receive buffer descriptor.
Definition sam9x60_eth1_driver.h:133
Transmit buffer descriptor.
Definition sam9x60_eth1_driver.h:122