31#ifndef _SAMA5D2_ETH_DRIVER_H
32#define _SAMA5D2_ETH_DRIVER_H
35#ifndef SAMA5D2_ETH_TX_BUFFER_COUNT
36 #define SAMA5D2_ETH_TX_BUFFER_COUNT 4
37#elif (SAMA5D2_ETH_TX_BUFFER_COUNT < 1)
38 #error SAMA5D2_ETH_TX_BUFFER_COUNT parameter is not valid
42#ifndef SAMA5D2_ETH_TX_BUFFER_SIZE
43 #define SAMA5D2_ETH_TX_BUFFER_SIZE 1536
44#elif (SAMA5D2_ETH_TX_BUFFER_SIZE != 1536)
45 #error SAMA5D2_ETH_TX_BUFFER_SIZE parameter is not valid
49#ifndef SAMA5D2_ETH_RX_BUFFER_COUNT
50 #define SAMA5D2_ETH_RX_BUFFER_COUNT 96
51#elif (SAMA5D2_ETH_RX_BUFFER_COUNT < 12)
52 #error SAMA5D2_ETH_RX_BUFFER_COUNT parameter is not valid
56#ifndef SAMA5D2_ETH_RX_BUFFER_SIZE
57 #define SAMA5D2_ETH_RX_BUFFER_SIZE 128
58#elif (SAMA5D2_ETH_RX_BUFFER_SIZE != 128)
59 #error SAMA5D2_ETH_RX_BUFFER_SIZE parameter is not valid
63#ifndef SAMA5D2_ETH_DUMMY_BUFFER_COUNT
64 #define SAMA5D2_ETH_DUMMY_BUFFER_COUNT 2
65#elif (SAMA5D2_ETH_DUMMY_BUFFER_COUNT < 1)
66 #error SAMA5D2_ETH_DUMMY_BUFFER_COUNT parameter is not valid
70#ifndef SAMA5D2_ETH_DUMMY_BUFFER_SIZE
71 #define SAMA5D2_ETH_DUMMY_BUFFER_SIZE 128
72#elif (SAMA5D2_ETH_DUMMY_BUFFER_SIZE != 128)
73 #error SAMA5D2_ETH_DUMMY_BUFFER_SIZE parameter is not valid
77#ifndef SAMA5D2_ETH_IRQ_PRIORITY
78 #define SAMA5D2_ETH_IRQ_PRIORITY 0
79#elif (SAMA5D2_ETH_IRQ_PRIORITY < 0)
80 #error SAMA5D2_ETH_IRQ_PRIORITY parameter is not valid
84#ifndef SAMA5D2_ETH_RAM_SECTION
85 #define SAMA5D2_ETH_RAM_SECTION ".region_ddr_nocache"
89#define GMAC_TX_USED 0x80000000
90#define GMAC_TX_WRAP 0x40000000
91#define GMAC_TX_RLE_ERROR 0x20000000
92#define GMAC_TX_UNDERRUN_ERROR 0x10000000
93#define GMAC_TX_AHB_ERROR 0x08000000
94#define GMAC_TX_LATE_COL_ERROR 0x04000000
95#define GMAC_TX_CHECKSUM_ERROR 0x00700000
96#define GMAC_TX_NO_CRC 0x00010000
97#define GMAC_TX_LAST 0x00008000
98#define GMAC_TX_LENGTH 0x00003FFF
101#define GMAC_RX_ADDRESS 0xFFFFFFFC
102#define GMAC_RX_WRAP 0x00000002
103#define GMAC_RX_OWNERSHIP 0x00000001
104#define GMAC_RX_BROADCAST 0x80000000
105#define GMAC_RX_MULTICAST_HASH 0x40000000
106#define GMAC_RX_UNICAST_HASH 0x20000000
107#define GMAC_RX_SAR 0x08000000
108#define GMAC_RX_SAR_MASK 0x06000000
109#define GMAC_RX_TYPE_ID 0x01000000
110#define GMAC_RX_SNAP 0x01000000
111#define GMAC_RX_TYPE_ID_MASK 0x00C00000
112#define GMAC_RX_CHECKSUM_VALID 0x00C00000
113#define GMAC_RX_VLAN_TAG 0x00200000
114#define GMAC_RX_PRIORITY_TAG 0x00100000
115#define GMAC_RX_VLAN_PRIORITY 0x000E0000
116#define GMAC_RX_CFI 0x00010000
117#define GMAC_RX_EOF 0x00008000
118#define GMAC_RX_SOF 0x00004000
119#define GMAC_RX_LENGTH_MSB 0x00002000
120#define GMAC_RX_BAD_FCS 0x00002000
121#define GMAC_RX_LENGTH 0x00001FFF
155error_t sama5d2EthInit(NetInterface *interface);
156void sama5d2EthInitGpio(NetInterface *interface);
157void sama5d2EthInitBufferDesc(NetInterface *interface);
159void sama5d2EthTick(NetInterface *interface);
161void sama5d2EthEnableIrq(NetInterface *interface);
162void sama5d2EthDisableIrq(NetInterface *interface);
163void sama5d2EthIrqHandler(
void);
164void sama5d2EthEventHandler(NetInterface *interface);
166error_t sama5d2EthSendPacket(NetInterface *interface,
167 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
169error_t sama5d2EthReceivePacket(NetInterface *interface);
171error_t sama5d2EthUpdateMacAddrFilter(NetInterface *interface);
172error_t sama5d2EthUpdateMacConfig(NetInterface *interface);
174void sama5d2EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
175 uint8_t regAddr, uint16_t data);
177uint16_t sama5d2EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
error_t
Error codes.
Definition error.h:43
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283
Receive buffer descriptor.
Definition sama5d2_eth_driver.h:145
Transmit buffer descriptor.
Definition sama5d2_eth_driver.h:134