31#ifndef _SAMV71_ETH_DRIVER_H
32#define _SAMV71_ETH_DRIVER_H
35#ifndef SAMV71_ETH_TX_BUFFER_COUNT
36 #define SAMV71_ETH_TX_BUFFER_COUNT 4
37#elif (SAMV71_ETH_TX_BUFFER_COUNT < 1)
38 #error SAMV71_ETH_TX_BUFFER_COUNT parameter is not valid
42#ifndef SAMV71_ETH_TX_BUFFER_SIZE
43 #define SAMV71_ETH_TX_BUFFER_SIZE 1536
44#elif (SAMV71_ETH_TX_BUFFER_SIZE != 1536)
45 #error SAMV71_ETH_TX_BUFFER_SIZE parameter is not valid
49#ifndef SAMV71_ETH_RX_BUFFER_COUNT
50 #define SAMV71_ETH_RX_BUFFER_COUNT 96
51#elif (SAMV71_ETH_RX_BUFFER_COUNT < 12)
52 #error SAMV71_ETH_RX_BUFFER_COUNT parameter is not valid
56#ifndef SAMV71_ETH_RX_BUFFER_SIZE
57 #define SAMV71_ETH_RX_BUFFER_SIZE 128
58#elif (SAMV71_ETH_RX_BUFFER_SIZE != 128)
59 #error SAMV71_ETH_RX_BUFFER_SIZE parameter is not valid
63#ifndef SAMV71_ETH_DUMMY_BUFFER_COUNT
64 #define SAMV71_ETH_DUMMY_BUFFER_COUNT 2
65#elif (SAMV71_ETH_DUMMY_BUFFER_COUNT < 1)
66 #error SAMV71_ETH_DUMMY_BUFFER_COUNT parameter is not valid
70#ifndef SAMV71_ETH_DUMMY_BUFFER_SIZE
71 #define SAMV71_ETH_DUMMY_BUFFER_SIZE 128
72#elif (SAMV71_ETH_DUMMY_BUFFER_SIZE != 128)
73 #error SAMV71_ETH_DUMMY_BUFFER_SIZE parameter is not valid
77#ifndef SAMV71_ETH_IRQ_PRIORITY_GROUPING
78 #define SAMV71_ETH_IRQ_PRIORITY_GROUPING 4
79#elif (SAMV71_ETH_IRQ_PRIORITY_GROUPING < 0)
80 #error SAMV71_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
84#ifndef SAMV71_ETH_IRQ_GROUP_PRIORITY
85 #define SAMV71_ETH_IRQ_GROUP_PRIORITY 6
86#elif (SAMV71_ETH_IRQ_GROUP_PRIORITY < 0)
87 #error SAMV71_ETH_IRQ_GROUP_PRIORITY parameter is not valid
91#ifndef SAMV71_ETH_IRQ_SUB_PRIORITY
92 #define SAMV71_ETH_IRQ_SUB_PRIORITY 0
93#elif (SAMV71_ETH_IRQ_SUB_PRIORITY < 0)
94 #error SAMV71_ETH_IRQ_SUB_PRIORITY parameter is not valid
98#ifndef SAMV71_ETH_RAM_SECTION
99 #define SAMV71_ETH_RAM_SECTION ".ram_no_cache"
103#define GMAC_RMII_MASK (PIO_PD9A_GMAC_GMDIO | PIO_PD8A_GMAC_GMDC | \
104 PIO_PD7A_GMAC_GRXER | PIO_PD6A_GMAC_GRX1 | PIO_PD5A_GMAC_GRX0 | \
105 PIO_PD4A_GMAC_GRXDV | PIO_PD3A_GMAC_GTX1 | PIO_PD2A_GMAC_GTX0 | \
106 PIO_PD1A_GMAC_GTXEN | PIO_PD0A_GMAC_GTXCK)
109#define GMAC_TX_USED 0x80000000
110#define GMAC_TX_WRAP 0x40000000
111#define GMAC_TX_RLE_ERROR 0x20000000
112#define GMAC_TX_UNDERRUN_ERROR 0x10000000
113#define GMAC_TX_AHB_ERROR 0x08000000
114#define GMAC_TX_LATE_COL_ERROR 0x04000000
115#define GMAC_TX_CHECKSUM_ERROR 0x00700000
116#define GMAC_TX_NO_CRC 0x00010000
117#define GMAC_TX_LAST 0x00008000
118#define GMAC_TX_LENGTH 0x00003FFF
121#define GMAC_RX_ADDRESS 0xFFFFFFFC
122#define GMAC_RX_WRAP 0x00000002
123#define GMAC_RX_OWNERSHIP 0x00000001
124#define GMAC_RX_BROADCAST 0x80000000
125#define GMAC_RX_MULTICAST_HASH 0x40000000
126#define GMAC_RX_UNICAST_HASH 0x20000000
127#define GMAC_RX_SAR 0x08000000
128#define GMAC_RX_SAR_MASK 0x06000000
129#define GMAC_RX_TYPE_ID 0x01000000
130#define GMAC_RX_SNAP 0x01000000
131#define GMAC_RX_TYPE_ID_MASK 0x00C00000
132#define GMAC_RX_CHECKSUM_VALID 0x00C00000
133#define GMAC_RX_VLAN_TAG 0x00200000
134#define GMAC_RX_PRIORITY_TAG 0x00100000
135#define GMAC_RX_VLAN_PRIORITY 0x000E0000
136#define GMAC_RX_CFI 0x00010000
137#define GMAC_RX_EOF 0x00008000
138#define GMAC_RX_SOF 0x00004000
139#define GMAC_RX_LENGTH_MSB 0x00002000
140#define GMAC_RX_BAD_FCS 0x00002000
141#define GMAC_RX_LENGTH 0x00001FFF
175error_t samv71EthInit(NetInterface *interface);
176void samv71EthInitGpio(NetInterface *interface);
177void samv71EthInitBufferDesc(NetInterface *interface);
179void samv71EthTick(NetInterface *interface);
181void samv71EthEnableIrq(NetInterface *interface);
182void samv71EthDisableIrq(NetInterface *interface);
183void samv71EthEventHandler(NetInterface *interface);
185error_t samv71EthSendPacket(NetInterface *interface,
186 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
188error_t samv71EthReceivePacket(NetInterface *interface);
190error_t samv71EthUpdateMacAddrFilter(NetInterface *interface);
191error_t samv71EthUpdateMacConfig(NetInterface *interface);
193void samv71EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
194 uint8_t regAddr, uint16_t data);
196uint16_t samv71EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
error_t
Error codes.
Definition error.h:43
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283
Receive buffer descriptor.
Definition samv71_eth_driver.h:165
Transmit buffer descriptor.
Definition samv71_eth_driver.h:154