31#ifndef _STM32F7XX_ETH_DRIVER_H
32#define _STM32F7XX_ETH_DRIVER_H
38#ifndef STM32F7XX_ETH_TX_BUFFER_COUNT
39 #define STM32F7XX_ETH_TX_BUFFER_COUNT 3
40#elif (STM32F7XX_ETH_TX_BUFFER_COUNT < 1)
41 #error STM32F7XX_ETH_TX_BUFFER_COUNT parameter is not valid
45#ifndef STM32F7XX_ETH_TX_BUFFER_SIZE
46 #define STM32F7XX_ETH_TX_BUFFER_SIZE 1536
47#elif (STM32F7XX_ETH_TX_BUFFER_SIZE != 1536)
48 #error STM32F7XX_ETH_TX_BUFFER_SIZE parameter is not valid
52#ifndef STM32F7XX_ETH_RX_BUFFER_COUNT
53 #define STM32F7XX_ETH_RX_BUFFER_COUNT 6
54#elif (STM32F7XX_ETH_RX_BUFFER_COUNT < 1)
55 #error STM32F7XX_ETH_RX_BUFFER_COUNT parameter is not valid
59#ifndef STM32F7XX_ETH_RX_BUFFER_SIZE
60 #define STM32F7XX_ETH_RX_BUFFER_SIZE 1536
61#elif (STM32F7XX_ETH_RX_BUFFER_SIZE != 1536)
62 #error STM32F7XX_ETH_RX_BUFFER_SIZE parameter is not valid
66#ifndef STM32F7XX_ETH_IRQ_PRIORITY_GROUPING
67 #define STM32F7XX_ETH_IRQ_PRIORITY_GROUPING 3
68#elif (STM32F7XX_ETH_IRQ_PRIORITY_GROUPING < 0)
69 #error STM32F7XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
73#ifndef STM32F7XX_ETH_IRQ_GROUP_PRIORITY
74 #define STM32F7XX_ETH_IRQ_GROUP_PRIORITY 12
75#elif (STM32F7XX_ETH_IRQ_GROUP_PRIORITY < 0)
76 #error STM32F7XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
80#ifndef STM32F7XX_ETH_IRQ_SUB_PRIORITY
81 #define STM32F7XX_ETH_IRQ_SUB_PRIORITY 0
82#elif (STM32F7XX_ETH_IRQ_SUB_PRIORITY < 0)
83 #error STM32F7XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
87#ifndef STM32F7XX_ETH_RAM_SECTION
88 #define STM32F7XX_ETH_RAM_SECTION ".ram_no_cache"
92#define ETH_MACCR_RESERVED15 0x00008000
95#define ETH_TDES0_OWN 0x80000000
96#define ETH_TDES0_IC 0x40000000
97#define ETH_TDES0_LS 0x20000000
98#define ETH_TDES0_FS 0x10000000
99#define ETH_TDES0_DC 0x08000000
100#define ETH_TDES0_DP 0x04000000
101#define ETH_TDES0_TTSE 0x02000000
102#define ETH_TDES0_CIC 0x00C00000
103#define ETH_TDES0_TER 0x00200000
104#define ETH_TDES0_TCH 0x00100000
105#define ETH_TDES0_TTSS 0x00020000
106#define ETH_TDES0_IHE 0x00010000
107#define ETH_TDES0_ES 0x00008000
108#define ETH_TDES0_JT 0x00004000
109#define ETH_TDES0_FF 0x00002000
110#define ETH_TDES0_IPE 0x00001000
111#define ETH_TDES0_LCA 0x00000800
112#define ETH_TDES0_NC 0x00000400
113#define ETH_TDES0_LCO 0x00000200
114#define ETH_TDES0_EC 0x00000100
115#define ETH_TDES0_VF 0x00000080
116#define ETH_TDES0_CC 0x00000078
117#define ETH_TDES0_ED 0x00000004
118#define ETH_TDES0_UF 0x00000002
119#define ETH_TDES0_DB 0x00000001
120#define ETH_TDES1_TBS2 0x1FFF0000
121#define ETH_TDES1_TBS1 0x00001FFF
122#define ETH_TDES2_TBAP1 0xFFFFFFFF
123#define ETH_TDES3_TBAP2 0xFFFFFFFF
124#define ETH_TDES6_TTSL 0xFFFFFFFF
125#define ETH_TDES7_TTSH 0xFFFFFFFF
128#define ETH_RDES0_OWN 0x80000000
129#define ETH_RDES0_AFM 0x40000000
130#define ETH_RDES0_FL 0x3FFF0000
131#define ETH_RDES0_ES 0x00008000
132#define ETH_RDES0_DE 0x00004000
133#define ETH_RDES0_SAF 0x00002000
134#define ETH_RDES0_LE 0x00001000
135#define ETH_RDES0_OE 0x00000800
136#define ETH_RDES0_VLAN 0x00000400
137#define ETH_RDES0_FS 0x00000200
138#define ETH_RDES0_LS 0x00000100
139#define ETH_RDES0_IPHCE_TSV 0x00000080
140#define ETH_RDES0_LCO 0x00000040
141#define ETH_RDES0_FT 0x00000020
142#define ETH_RDES0_RWT 0x00000010
143#define ETH_RDES0_RE 0x00000008
144#define ETH_RDES0_DBE 0x00000004
145#define ETH_RDES0_CE 0x00000002
146#define ETH_RDES0_PCE_ESA 0x00000001
147#define ETH_RDES1_DIC 0x80000000
148#define ETH_RDES1_RBS2 0x1FFF0000
149#define ETH_RDES1_RER 0x00008000
150#define ETH_RDES1_RCH 0x00004000
151#define ETH_RDES1_RBS1 0x00001FFF
152#define ETH_RDES2_RBAP1 0xFFFFFFFF
153#define ETH_RDES3_RBAP2 0xFFFFFFFF
154#define ETH_RDES4_PV 0x00002000
155#define ETH_RDES4_PFT 0x00001000
156#define ETH_RDES4_PMT 0x00000F00
157#define ETH_RDES4_IPV6PR 0x00000080
158#define ETH_RDES4_IPV4PR 0x00000040
159#define ETH_RDES4_IPCB 0x00000020
160#define ETH_RDES4_IPPE 0x00000010
161#define ETH_RDES4_IPHE 0x00000008
162#define ETH_RDES4_IPPT 0x00000007
163#define ETH_RDES6_RTSL 0xFFFFFFFF
164#define ETH_RDES7_RTSH 0xFFFFFFFF
207extern const NicDriver stm32f7xxEthDriver;
210error_t stm32f7xxEthInit(NetInterface *interface);
212void stm32f7xxEthInitDmaDesc(NetInterface *interface);
214void stm32f7xxEthTick(NetInterface *interface);
216void stm32f7xxEthEnableIrq(NetInterface *interface);
217void stm32f7xxEthDisableIrq(NetInterface *interface);
218void stm32f7xxEthEventHandler(NetInterface *interface);
220error_t stm32f7xxEthSendPacket(NetInterface *interface,
221 const NetBuffer *buffer,
size_t offset, NetTxAncillary *ancillary);
223error_t stm32f7xxEthReceivePacket(NetInterface *interface);
225error_t stm32f7xxEthUpdateMacAddrFilter(NetInterface *interface);
226error_t stm32f7xxEthUpdateMacConfig(NetInterface *interface);
228void stm32f7xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
229 uint8_t regAddr, uint16_t data);
231uint16_t stm32f7xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
234uint32_t stm32f7xxEthCalcCrc(
const void *data,
size_t length);
error_t
Error codes.
Definition error.h:43
void stm32f7xxEthInitGpio(NetInterface *interface)
Externally linked API for ETH configuration.
Definition hw_eth.h:101
Network interface controller abstraction layer.
Structure describing a buffer that spans multiple chunks.
Definition net_mem.h:89
NIC driver.
Definition nic.h:283
Enhanced RX DMA descriptor.
Definition stm32f7xx_eth_driver.h:194
Enhanced TX DMA descriptor.
Definition stm32f7xx_eth_driver.h:177