mikroSDK Reference Manual
usbhs_registers.h
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23/*******************************************************************************
24 USBHS Peripheral Library Register Definitions
25
26 File Name:
27 usbhs_registers.h
28
29 Summary:
30 USBHS PLIB Register Definitions
31
32 Description:
33 This file contains the constants and definitions which are required by the
34 the USBHS library.
35*******************************************************************************/
36
37#ifndef __USBHS_REGISTERS_H__
38#define __USBHS_REGISTERS_H__
39
40#include <p32xxxx.h>
41#include <stdint.h>
42
43/*****************************************
44 * Module Register Offsets.
45 *****************************************/
46
47#define USBHS_REG_FADDR 0x000
48#define USBHS_REG_POWER 0x001
49#define USBHS_REG_INTRTX 0x002
50#define USBHS_REG_INTRRX 0x004
51#define USBHS_REG_INTRTXE 0x006
52#define USBHS_REG_INTRRXE 0x008
53#define USBHS_REG_INTRUSB 0x00A
54#define USBHS_REG_INTRUSBE 0x00B
55#define USBHS_REG_FRAME 0x00C
56#define USBHS_REG_INDEX 0x00E
57#define USBHS_REG_TESTMODE 0x00F
58
59/*******************************************************
60 * Endpoint Control Status Registers (CSR). These values
61 * should be added to either the 0x10 to access the
62 * register through Indexed CSR. To access the actual
63 * CSR, see ahead in this header file.
64 ******************************************************/
65
66#define USBHS_REG_EP_TXMAXP 0x000
67#define USBHS_REG_EP_CSR0L 0x002
68#define USBHS_REG_EP_CSR0H 0x003
69#define USBHS_REG_EP_TXCSRL 0x002
70#define USBHS_REG_EP_TXCSRH 0x003
71#define USBHS_REG_EP_RXMAXP 0x004
72#define USBHS_REG_EP_RXCSRL 0x006
73#define USBHS_REG_EP_RXCSRH 0x007
74#define USBHS_REG_EP_COUNT0 0x008
75#define USBHS_REG_EP_RXCOUNT 0x008
76#define USBHS_REG_EP_TYPE0 0x01A
77#define USBHS_REG_EP_TXTYPE 0x01A
78#define USBHS_REG_EP_NAKLIMIT0 0x01B
79#define USBHS_REG_EP_TXINTERVAL 0x01B
80#define USBHS_REG_EP_RXTYPE 0x01C
81#define USBHS_REG_EP_RXINTERVAL 0x01D
82#define USBHS_REG_EP_CONFIGDATA 0x01F
83#define USBHS_REG_EP_FIFOSIZE 0x01F
84
85#define USBHS_HOST_EP0_SETUPKT_SET 0x8
86#define USBHS_HOST_EP0_TXPKTRDY_SET 0x2
87#define USBHS_SOFT_RST_NRST_SET 0x1
88#define USBHS_SOFT_RST_NRSTX_SET 0x2
89#define USBHS_EP0_DEVICE_SERVICED_RXPKTRDY 0x40
90#define USBHS_EP0_DEVICE_DATAEND 0x08
91#define USBHS_EP0_DEVICE_TXPKTRDY 0x02
92#define USBHS_EP0_HOST_STATUS_STAGE_START 0x40
93#define USBHS_EP0_HOST_REQPKT 0x20
94#define USBHS_EP0_HOST_TXPKTRDY 0x02
95#define USBHS_EP0_HOST_RXPKTRDY 0x01
96#define USBHS_EP_DEVICE_TX_SENT_STALL 0x20
97#define USBHS_EP_DEVICE_TX_SEND_STALL 0x10
98#define USBHS_EP_DEVICE_RX_SENT_STALL 0x40
99#define USBHS_EP_DEVICE_RX_SEND_STALL 0x20
100
101/* FADDR - Device Function Address */
102typedef union
103{
104 struct __attribute__((packed))
105 {
106 unsigned FUNC:7;
107 unsigned :1;
108 };
109
110 uint8_t w;
111
112} __USBHS_FADDR_t;
113
114/* POWER - Control Resume and Suspend signalling */
115typedef union
116{
117 struct __attribute__((packed))
118 {
119 unsigned SUSPEN:1;
120 unsigned SUSPMODE:1;
121 unsigned RESUME:1;
122 unsigned RESET:1;
123 unsigned HSMODE:1;
124 unsigned HSEN:1;
125 unsigned SOFTCONN:1;
126 unsigned ISOUPD:1;
127 };
128 struct
129 {
130 uint8_t w;
131 };
132
133} __USBHS_POWER_t;
134
135/* INTRTXE - Transmit endpoint interrupt enable */
136typedef union
137{
138 struct __attribute__((packed))
139 {
140 unsigned EP0IE:1;
141 unsigned EP1TXIE:1;
142 unsigned EP2TXIE:1;
143 unsigned EP3TXIE:1;
144 unsigned EP4TXIE:1;
145 unsigned EP5TXIE:1;
146 unsigned EP6TXIE:1;
147 unsigned EP7TXIE:1;
148 unsigned :8;
149 };
150 struct
151 {
152 uint16_t w;
153 };
154
155} __USBHS_INTRTXE_t;
156
157/* INTRRXE - Receive endpoint interrupt enable */
158typedef union
159{
160 struct __attribute__((packed))
161 {
162 unsigned :1;
163 unsigned EP1RXIE:1;
164 unsigned EP2RXIE:1;
165 unsigned EP3RXIE:1;
166 unsigned EP4RXIE:1;
167 unsigned EP5RXIE:1;
168 unsigned EP6RXIE:1;
169 unsigned EP7RXIE:1;
170 unsigned :8;
171 };
172 struct
173 {
174 uint16_t w;
175 };
176
177} __USBHS_INTRRXE_t;
178
179/* INTRUSBE - General USB Interrupt enable */
180typedef union
181{
182 struct __attribute__((packed))
183 {
184 unsigned SUSPIE:1;
185 unsigned RESUMEIE:1;
186 unsigned RESETIE:1;
187 unsigned SOFIE:1;
188 unsigned CONNIE:1;
189 unsigned DISCONIE:1;
190 unsigned SESSRQIE:1;
191 unsigned VBUSERRIE:1;
192 };
193 struct
194 {
195 uint8_t w;
196 };
197
198} __USBHS_INTRUSBE_t;
199
200/* FRAME - Frame number */
201typedef union
202{
203 struct __attribute__((packed))
204 {
205 unsigned RFRMNUM:11;
206 unsigned :5;
207 };
208 struct
209 {
210 uint16_t w;
211 };
212
213} __USBHS_FRAME_t;
214
215/* INDEX - Endpoint index */
216typedef union
217{
218 struct __attribute__((packed))
219 {
220 unsigned ENDPOINT:4;
221 unsigned :4;
222 };
223 struct
224 {
225 uint8_t w;
226 };
227
228} __USBHS_INDEX_t;
229
230/* TESTMODE - Test mode register */
231typedef union
232{
233 struct __attribute__((packed))
234 {
235 unsigned NAK:1;
236 unsigned TESTJ:1;
237 unsigned TESTK:1;
238 unsigned PACKET:1;
239 unsigned FORCEHS:1;
240 unsigned FORCEFS:1;
241 unsigned FIFOACC:1;
242 unsigned FORCEHST:1;
243 };
244 struct
245 {
246 uint8_t w;
247 };
248
249} __USBHS_TESTMODE_t;
250
251/* COUNT0 - Indicates the amount of data received in endpoint 0 */
252typedef union
253{
254 struct __attribute__((packed))
255 {
256 unsigned RXCNT:7;
257 unsigned :1;
258 };
259 struct
260 {
261 uint8_t w;
262 };
263
264} __USBHS_COUNT0_t;
265
266/* TYPE0 - Operating speed of target device */
267typedef union
268{
269 struct __attribute__((packed))
270 {
271 unsigned :6;
272 unsigned SPEED:2;
273 };
274 struct
275 {
276 uint8_t w;
277 };
278
279} __USBHS_TYPE0_t;
280
281/* DEVCTL - Module control register */
282typedef union
283{
284 struct __attribute__((packed))
285 {
286 unsigned SESSION:1;
287 unsigned HOSTREQ:1;
288 unsigned HOSTMODE:1;
289 unsigned VBUS:2;
290 unsigned LSDEV:1;
291 unsigned FSDEV:1;
292 unsigned BDEV:1;
293 };
294 struct
295 {
296 uint8_t w;
297 };
298
299} __USBHS_DEVCTL_t;
300
301/* CSR0L Device - Endpoint Device Mode Control Status Register */
302typedef union
303{
304 struct __attribute__((packed))
305 {
306 unsigned RXPKTRDY:1;
307 unsigned TXPKTRDY:1;
308 unsigned SENTSTALL:1;
309 unsigned DATAEND:1;
310 unsigned SETUPEND:1;
311 unsigned SENDSTALL:1;
312 unsigned SVCRPR:1;
313 unsigned SVSSETEND:1;
314 };
315 struct
316 {
317 uint8_t w;
318 };
319
320} __USBHS_CSR0L_DEVICE_t;
321
322/* CSR0L Host - Endpoint Host Mode Control Status Register */
323typedef union
324{
325 struct __attribute__((packed))
326 {
327 unsigned RXPKTRDY:1;
328 unsigned TXPKTRDY:1;
329 unsigned RXSTALL:1;
330 unsigned SETUPPKT:1;
331 unsigned ERROR:1;
332 unsigned REQPKT:1;
333 unsigned STATPKT:1;
334 unsigned NAKTMOUT:1;
335 };
336 struct
337 {
338 uint8_t w;
339 };
340
341} __USBHS_CSR0L_HOST_t;
342
343/* TXCSRL Device - Endpoint Transmit Control Status Register Low */
344typedef union
345{
346 struct __attribute__((packed))
347 {
348 unsigned TXPKTRDY:1;
349 unsigned FIFOONE:1;
350 unsigned UNDERRUN:1;
351 unsigned FLUSH:1;
352 unsigned SENDSTALL:1;
353 unsigned SENTSTALL:1;
354 unsigned CLRDT:1;
355 unsigned INCOMPTX:1;
356 };
357 struct
358 {
359 uint8_t w;
360 };
361
362} __USBHS_TXCSRL_DEVICE_t;
363
364/* TXCSRL Host - Endpoint Transmit Control Status Register Low */
365typedef union
366{
367 struct __attribute__((packed))
368 {
369 unsigned TXPKTRDY:1;
370 unsigned FIFONE:1;
371 unsigned ERROR:1;
372 unsigned FLUSH:1;
373 unsigned SETUPPKT:1;
374 unsigned RXSTALL:1;
375 unsigned CLRDT:1;
376 unsigned INCOMPTX:1;
377 };
378 struct
379 {
380 uint8_t w;
381 };
382
383} __USBHS_TXCSRL_HOST_t;
384
385/* TXCSRH Device - Endpoint Transmit Control Status Register High */
386typedef union
387{
388 struct __attribute__((packed))
389 {
390 unsigned :2;
391 unsigned DMAREQMD:1;
392 unsigned FRCDATTG:1;
393 unsigned DMAREQENL:1;
394 unsigned MODE:1;
395 unsigned ISO:1;
396 unsigned AUTOSET:1;
397 };
398 struct
399 {
400 uint8_t w;
401 };
402
403} __USBHS_TXCSRH_DEVICE_t;
404
405/* TXCSRH Host - Endpoint Transmit Control Status Register High */
406typedef union
407{
408 struct __attribute__((packed))
409 {
410 unsigned DATATGGL:1;
411 unsigned DTWREN:1;
412 unsigned DMAREQMD:1;
413 unsigned FRCDATTG:1;
414 unsigned DMAREQEN:1;
415 unsigned MODE:1;
416 unsigned :1;
417 unsigned AUOTSET:1;
418 };
419 struct
420 {
421 uint8_t w;
422 };
423
424} __USBHS_TXCSRH_HOST_t;
425
426/* CSR0H Device - Endpoint 0 Control Status Register High */
427typedef union
428{
429 struct __attribute__((packed))
430 {
431 unsigned FLSHFIFO:1;
432 unsigned :7;
433 };
434 struct
435 {
436 uint8_t w;
437 };
438
439} __USBHS_CSR0H_DEVICE_t;
440
441/* CSR0H Host - Endpoint 0 Control Status Register High */
442typedef union
443{
444 struct __attribute__((packed))
445 {
446 unsigned FLSHFIFO:1;
447 unsigned DATATGGL:1;
448 unsigned DTWREN:1;
449 unsigned DISPING:1;
450 unsigned :4;
451 };
452 struct
453 {
454 uint8_t w;
455 };
456
457} __USBHS_CSR0H_HOST_t;
458
459/* RXMAXP - Receive Endpoint Max packet size. */
460typedef union
461{
462 struct __attribute__((packed))
463 {
464 unsigned RXMAXP:11;
465 unsigned MULT:5;
466 };
467 struct
468 {
469 uint16_t w;
470 };
471
472} __USBHS_RXMAXP_t;
473
474/* RXCSRL Device - Receive endpoint Control Status Register */
475typedef union
476{
477 struct __attribute__((packed))
478 {
479 unsigned RXPKTRDY:1;
480 unsigned FIFOFULL:1;
481 unsigned OVERRUN:1;
482 unsigned DATAERR:1;
483 unsigned FLUSH:1;
484 unsigned SENDSTALL:1;
485 unsigned SENTSTALL:1;
486 unsigned CLRDT:1;
487 };
488 struct
489 {
490 uint8_t w;
491 };
492
493} __USBHS_RXCSRL_DEVICE_t;
494
495/* RXCSRL Host - Receive endpoint Control Status Register */
496typedef union
497{
498 struct __attribute__((packed))
499 {
500 unsigned RXPKTRDY:1;
501 unsigned FIFOFULL:1;
502 unsigned ERROR:1;
503 unsigned DERRNAKT:1;
504 unsigned FLUSH:1;
505 unsigned REQPKT:1;
506 unsigned RXSTALL:1;
507 unsigned CLRDT:1;
508 };
509 struct
510 {
511 uint8_t w;
512 };
513
514} __USBHS_RXCSRL_HOST_t;
515
516/* RXCSRH Device - Receive endpoint Control Status Register */
517typedef union
518{
519 struct __attribute__((packed))
520 {
521 unsigned INCOMPRX:1;
522 unsigned :2;
523 unsigned DMAREQMODE:1;
524 unsigned DISNYET:1;
525 unsigned DMAREQEN:1;
526 unsigned ISO:1;
527 unsigned AUTOCLR:1;
528 };
529 struct
530 {
531 uint8_t w;
532 };
533
534} __USBHS_RXCSRH_DEVICE_t;
535
536/* RXCSRH Host - Receive endpoint Control Status Register */
537typedef union
538{
539 struct __attribute__((packed))
540 {
541 unsigned INCOMPRX:1;
542 unsigned DATATGGL:1;
543 unsigned DATATWEN:1;
544 unsigned DMAREQMD:1;
545 unsigned PIDERR:1;
546 unsigned DMAREQEN:1;
547 unsigned AUTORQ:1;
548 unsigned AUOTCLR:1;
549 };
550 struct
551 {
552 uint8_t w;
553 };
554
555} __USBHS_RXCSRH_HOST_t;
556
557/* RXCOUNT - Amount of data pending in RX FIFO */
558typedef union
559{
560 struct __attribute__((packed))
561 {
562 unsigned RXCNT:14;
563 unsigned :2;
564 };
565 struct
566 {
567 uint16_t w;
568 };
569
570} __USBHS_RXCOUNT_t;
571
572/* TXTYPE - Specifies the target transmit endpoint */
573typedef union
574{
575 struct __attribute__((packed))
576 {
577 unsigned TEP:4;
578 unsigned PROTOCOL:2;
579 unsigned SPEED:2;
580 };
581 struct
582 {
583 uint8_t w;
584 };
585
586} __USBHS_TXTYPE_t;
587
588/* RXTYPE - Specifies the target receive endpoint */
589typedef union
590{
591 struct __attribute__((packed))
592 {
593 unsigned TEP:4;
594 unsigned PROTOCOL:2;
595 unsigned SPEED:2;
596 };
597 struct
598 {
599 uint8_t w;
600 };
601
602} __USBHS_RXTYPE_t;
603
604/* TXINTERVAL - Defines the polling interval */
605typedef struct
606{
607 uint8_t TXINTERV;
608
609} __USBHS_TXINTERVAL_t;
610
611/* RXINTERVAL - Defines the polling interval */
612typedef struct
613{
614 uint8_t RXINTERV;
615
616} __USBHS_RXINTERVAL_t;
617
618/* TXMAXP - Maximum amount of data that can be transferred through a TX endpoint
619 * */
620
621typedef union
622{
623 struct __attribute__((packed))
624 {
625 unsigned TXMAXP:11;
626 unsigned MULT:5;
627 };
628 uint16_t w;
629
630} __USBHS_TXMAXP_t;
631
632/* TXFIFOSZ - Size of the transmit endpoint FIFO */
633typedef struct __attribute__((packed))
634{
635 unsigned TXFIFOSZ:4;
636 unsigned TXDPB:1;
637 unsigned :3;
638
639} __USBHS_TXFIFOSZ_t;
640
641/* RXFIFOSZ - Size of the receive endpoint FIFO */
642typedef struct __attribute__((packed))
643{
644 unsigned RXFIFOSZ:4;
645 unsigned RXDPB:1;
646 unsigned :3;
647
648} __USBHS_RXFIFOSZ_t;
649
650/* TXFIFOADD - Start address of the transmit endpoint FIFO */
651typedef union
652{
653 struct __attribute__((packed))
654 {
655 unsigned TXFIFOAD:13;
656 unsigned :3;
657 };
658 uint16_t w;
659
660} __USBHS_TXFIFOADD_t;
661
662/* RXFIFOADD - Start address of the receive endpoint FIFO */
663typedef union
664{
665 struct __attribute__((packed))
666 {
667 unsigned RXFIFOAD:13;
668 unsigned :3;
669 };
670 uint16_t w;
671
672} __USBHS_RXFIFOADD_t;
673
674/* SOFTRST - Asserts NRSTO and NRSTOX */
675typedef union
676{
677 struct __attribute__((packed))
678 {
679 unsigned NRST:1;
680 unsigned NRSTX:1;
681 unsigned :6;
682 };
683 uint8_t w;
684
685} __USBHS_SOFTRST_t;
686
687/* TXFUNCADDR - Target address of transmit endpoint */
688typedef union
689{
690 struct __attribute__((packed))
691 {
692 unsigned TXFADDR:7;
693 unsigned :1;
694 };
695 uint8_t w;
696
697} __USBHS_TXFUNCADDR_t;
698
699/* RXFUNCADDR - Target address of receive endpoint */
700typedef union
701{
702 struct __attribute__((packed))
703 {
704 unsigned RXFADDR:7;
705 unsigned :1;
706 };
707 uint8_t w;
708
709} __USBHS_RXFUNCADDR_t;
710
711/* TXHUBADDR - Address of the hub to which the target transmit device endpoint
712 * is connected */
713typedef union
714{
715 struct __attribute__((packed))
716 {
717 unsigned TXHUBADDR:7;
718 unsigned MULTTRAN:1;
719 };
720 uint8_t w;
721
722} __USBHS_TXHUBADDR_t;
723
724/* RXHUBADDR - Address of the hub to which the target receive device endpoint is
725 * connected */
726typedef union
727{
728 struct __attribute__((packed))
729 {
730 unsigned RXHUBADDR:7;
731 unsigned MULTTRAN:1;
732 };
733 uint8_t w;
734
735} __USBHS_RXHUBADDR_t;
736
737/* TXHUBPORT - Address of the hub to which the target transmit device endpoint
738 * is connected. */
739typedef union
740{
741 struct __attribute__((packed))
742 {
743 unsigned TXHUBPRT:7;
744 unsigned :1;
745 };
746
747 uint8_t w;
748
749} __USBHS_TXHUBPORT_t;
750
751/* RXHUBPORT - Address of the hub to which the target receive device endpoint
752 * is connected. */
753typedef union
754{
755 struct __attribute__((packed))
756 {
757 unsigned RXHUBPRT:7;
758 unsigned :1;
759 };
760
761 uint8_t w;
762
763} __USBHS_RXHUBPORT_t;
764
765/* DMACONTROL - Configures a DMA channel */
766typedef union
767{
768 struct __attribute__((packed))
769 {
770 unsigned DMAEN:1;
771 unsigned DMADIR:1;
772 unsigned DMAMODE:1;
773 unsigned DMAIE:1;
774 unsigned DMAEP:4;
775 unsigned DMAERR:1;
776 unsigned DMABRSTM:2;
777 unsigned:21;
778 };
779
780 uint32_t w;
781
782} __USBHS_DMACNTL_t;
783
784/* Endpoint Control and Status Register Set */
785typedef struct __attribute__((packed))
786{
787 volatile __USBHS_TXMAXP_t TXMAXPbits;
788 union
789 {
790 struct
791 {
792 union
793 {
794 volatile __USBHS_CSR0L_DEVICE_t CSR0L_DEVICEbits;
795 volatile __USBHS_CSR0L_HOST_t CSR0L_HOSTbits;
796 };
797 union
798 {
799 volatile __USBHS_CSR0H_DEVICE_t CSR0H_DEVICEbits;
800 volatile __USBHS_CSR0H_HOST_t CSR0H_HOSTbits;
801 };
802 };
803
804 struct
805 {
806 union
807 {
808 volatile __USBHS_TXCSRL_DEVICE_t TXCSRL_DEVICEbits;
809 volatile __USBHS_TXCSRL_HOST_t TXCSRL_HOSTbits;
810 };
811
812 union
813 {
814 volatile __USBHS_TXCSRH_DEVICE_t TXCSRH_DEVICEbits;
815 volatile __USBHS_TXCSRH_HOST_t TXCSRH_HOSTbits;
816 };
817 };
818 };
819
820 volatile __USBHS_RXMAXP_t RXMAXPbits;
821
822 union
823 {
824 volatile __USBHS_RXCSRL_DEVICE_t RXCSRL_DEVICEbits;
825 volatile __USBHS_RXCSRL_HOST_t RXCSRL_HOSTbits;
826 };
827
828 union
829 {
830 volatile __USBHS_RXCSRH_DEVICE_t RXCSRH_DEVICEbits;
831 volatile __USBHS_RXCSRH_HOST_t RXCSRH_HOSTbits;
832 };
833
834 union
835 {
836 volatile __USBHS_COUNT0_t COUNT0bits;
837 volatile __USBHS_RXCOUNT_t RXCOUNTbits;
838 };
839
840 union
841 {
842 volatile __USBHS_TYPE0_t TYPE0bits;
843 volatile __USBHS_TXTYPE_t TXTYPEbits;
844 };
845
846 union
847 {
848 volatile uint8_t NAKLIMIT0;
849 volatile __USBHS_TXINTERVAL_t TXINTERVALbits;
850 };
851
852 volatile __USBHS_RXTYPE_t RXTYPEbits;
853 volatile __USBHS_RXINTERVAL_t RXINTERVALbits;
854 unsigned :8;
855 union
856 {
857 volatile uint8_t CONFIGDATA;
858 volatile uint8_t FIFOSIZE;
859 };
860
861} __USBHS_EPCSR_t;
862
863/* Set of registers that configure the multi-point option */
864typedef struct __attribute__((packed))
865{
866 volatile __USBHS_TXFUNCADDR_t TXFUNCADDRbits;
867 unsigned :8;
868 volatile __USBHS_TXHUBADDR_t TXHUBADDRbits;
869 volatile __USBHS_TXHUBPORT_t TXHUBPORTbits;
870 volatile __USBHS_RXFUNCADDR_t RXFUNCADDRbits;
871 unsigned :8;
872 volatile __USBHS_RXHUBADDR_t RXHUBADDRbits;
873 volatile __USBHS_RXHUBPORT_t RXHUBPORTbits;
874
875} __USBHS_TARGET_ADDR_t;
876
877/* Set of registers that configure the DMA channel */
878typedef struct __attribute__((packed))
879{
880 volatile __USBHS_DMACNTL_t DMACNTLbits;
881 volatile uint32_t DMAADDR;
882 volatile uint32_t DMACOUNT;
883 volatile uint32_t pad;
884} __USBHS_DMA_CHANNEL_t;
885
886/* USBHS module register set */
887typedef struct __attribute__((aligned(4),packed))
888{
889 volatile __USBHS_FADDR_t FADDRbits;
890 volatile __USBHS_POWER_t POWERbits;
891 volatile uint16_t INTRTX;
892 volatile uint16_t INTRRX;
893 volatile __USBHS_INTRTXE_t INTRTXEbits;
894 volatile __USBHS_INTRRXE_t INTRRXEbits;
895 volatile uint8_t INTRUSB;
896 volatile __USBHS_INTRUSBE_t INTRUSBEbits;
897 volatile __USBHS_FRAME_t FRAMEbits;
898 volatile __USBHS_INDEX_t INDEXbits;
899 volatile __USBHS_TESTMODE_t TESTMODEbits;
900 volatile __USBHS_EPCSR_t INDEXED_EPCSR;
901 volatile uint32_t FIFO[16];
902 volatile __USBHS_DEVCTL_t DEVCTLbits;
903 volatile uint8_t MISC;
904 volatile __USBHS_TXFIFOSZ_t TXFIFOSZbits;
905 volatile __USBHS_RXFIFOSZ_t RXFIFOSZbits;
906
907 volatile __USBHS_TXFIFOADD_t TXFIFOADDbits;
908 volatile __USBHS_RXFIFOADD_t RXFIFOADDbits;
909
910 volatile uint32_t VCONTROL;
911 volatile uint16_t HWVERS;
912 volatile uint8_t padding1[10];
913 volatile uint8_t EPINFO;
914 volatile uint8_t RAMINFO;
915 volatile uint8_t LINKINFO;
916 volatile uint8_t VPLEN;
917 volatile uint8_t HS_EOF1;
918 volatile uint8_t FS_EOF1;
919 volatile uint8_t LS_EOF1;
920
921 volatile __USBHS_SOFTRST_t SOFTRSTbits;
922
923 volatile __USBHS_TARGET_ADDR_t TADDR[16];
924 volatile __USBHS_EPCSR_t EPCSR[16];
925 volatile uint32_t DMA_INTR;
926 volatile __USBHS_DMA_CHANNEL_t DMA_CHANNEL[8];
927 volatile uint32_t RQPKTXOUNT[16];
928
929} usbhs_registers_t;
930
931#endif
__USBHS_DMA_CHANNEL_t
Definition usbhs_registers.h:879
__USBHS_EPCSR_t
Definition usbhs_registers.h:786
__USBHS_RXFIFOSZ_t
Definition usbhs_registers.h:643
__USBHS_RXINTERVAL_t
Definition usbhs_registers.h:613
__USBHS_TARGET_ADDR_t
Definition usbhs_registers.h:865
__USBHS_TXFIFOSZ_t
Definition usbhs_registers.h:634
__USBHS_TXINTERVAL_t
Definition usbhs_registers.h:606
usbhs_registers_t
Definition usbhs_registers.h:888
__USBHS_COUNT0_t
Definition usbhs_registers.h:253
__USBHS_CSR0H_DEVICE_t
Definition usbhs_registers.h:428
__USBHS_CSR0H_HOST_t
Definition usbhs_registers.h:443
__USBHS_CSR0L_DEVICE_t
Definition usbhs_registers.h:303
__USBHS_CSR0L_HOST_t
Definition usbhs_registers.h:324
__USBHS_DEVCTL_t
Definition usbhs_registers.h:283
__USBHS_DMACNTL_t
Definition usbhs_registers.h:767
__USBHS_FADDR_t
Definition usbhs_registers.h:103
__USBHS_FRAME_t
Definition usbhs_registers.h:202
__USBHS_INDEX_t
Definition usbhs_registers.h:217
__USBHS_INTRRXE_t
Definition usbhs_registers.h:159
__USBHS_INTRTXE_t
Definition usbhs_registers.h:137
__USBHS_INTRUSBE_t
Definition usbhs_registers.h:181
__USBHS_POWER_t
Definition usbhs_registers.h:116
__USBHS_RXCOUNT_t
Definition usbhs_registers.h:559
__USBHS_RXCSRH_DEVICE_t
Definition usbhs_registers.h:518
__USBHS_RXCSRH_HOST_t
Definition usbhs_registers.h:538
__USBHS_RXCSRL_DEVICE_t
Definition usbhs_registers.h:476
__USBHS_RXCSRL_HOST_t
Definition usbhs_registers.h:497
__USBHS_RXFIFOADD_t
Definition usbhs_registers.h:664
__USBHS_RXFUNCADDR_t
Definition usbhs_registers.h:701
__USBHS_RXHUBADDR_t
Definition usbhs_registers.h:727
__USBHS_RXHUBPORT_t
Definition usbhs_registers.h:754
__USBHS_RXMAXP_t
Definition usbhs_registers.h:461
__USBHS_RXTYPE_t
Definition usbhs_registers.h:590
__USBHS_SOFTRST_t
Definition usbhs_registers.h:676
__USBHS_TESTMODE_t
Definition usbhs_registers.h:232
__USBHS_TXCSRH_DEVICE_t
Definition usbhs_registers.h:387
__USBHS_TXCSRH_HOST_t
Definition usbhs_registers.h:407
__USBHS_TXCSRL_DEVICE_t
Definition usbhs_registers.h:345
__USBHS_TXCSRL_HOST_t
Definition usbhs_registers.h:366
__USBHS_TXFIFOADD_t
Definition usbhs_registers.h:652
__USBHS_TXFUNCADDR_t
Definition usbhs_registers.h:689
__USBHS_TXHUBADDR_t
Definition usbhs_registers.h:714
__USBHS_TXHUBPORT_t
Definition usbhs_registers.h:740
__USBHS_TXMAXP_t
Definition usbhs_registers.h:622
__USBHS_TXTYPE_t
Definition usbhs_registers.h:574
__USBHS_TYPE0_t
Definition usbhs_registers.h:268