ADC Register Masks

Macros
#define	ADC0_BASE   (0x4003B000u)
#define	ADC0   ((ADC_Type *)ADC0_BASE)
#define	ADC1_BASE   (0x400BB000u)
#define	ADC1   ((ADC_Type *)ADC1_BASE)
#define	ADC_BASE_ADDRS   { ADC0_BASE, ADC1_BASE }
#define	ADC_BASE_PTRS   { ADC0, ADC1 }
#define	ADC_IRQS   { ADC0_IRQn, ADC1_IRQn }
#define	ADC_PGA_PGAG_MASK   0xF0000u
#define	ADC_PGA_PGAG_SHIFT   16
#define	ADC_PGA_PGAG(x)   (((uint32_t)(((uint32_t)(x))<<ADC_PGA_PGAG_SHIFT))&ADC_PGA_PGAG_MASK)
#define	ADC_PGA_PGAEN_MASK   0x800000u
#define	ADC_PGA_PGAEN_SHIFT   23
#define	ADC_SC1_COUNT   (2U)
#define	ADC_R_COUNT   (2U)
#define	ADC_SC1_COUNT   (2U)
#define	ADC_R_COUNT   (2U)
#define	ADC_SC1_COUNT   (2U)
#define	ADC_R_COUNT   (2U)
#define	ADC_SC1_COUNT   (2U)
#define	ADC_R_COUNT   (2U)

SC1 - ADC Status and Control Registers 1
#define	ADC_SC1_ADCH_MASK   (0x1FU)
#define	ADC_SC1_ADCH_SHIFT   (0U)
#define	ADC_SC1_ADCH(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
#define	ADC_SC1_DIFF_MASK   (0x20U)
#define	ADC_SC1_DIFF_SHIFT   (5U)
#define	ADC_SC1_DIFF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
#define	ADC_SC1_AIEN_MASK   (0x40U)
#define	ADC_SC1_AIEN_SHIFT   (6U)
#define	ADC_SC1_AIEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
#define	ADC_SC1_COCO_MASK   (0x80U)
#define	ADC_SC1_COCO_SHIFT   (7U)
#define	ADC_SC1_COCO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
#define	ADC_SC1_ADCH_MASK   0x1Fu
#define	ADC_SC1_ADCH_SHIFT   0
#define	ADC_SC1_ADCH(x)   (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
#define	ADC_SC1_DIFF_MASK   0x20u
#define	ADC_SC1_DIFF_SHIFT   5
#define	ADC_SC1_AIEN_MASK   0x40u
#define	ADC_SC1_AIEN_SHIFT   6
#define	ADC_SC1_COCO_MASK   0x80u
#define	ADC_SC1_COCO_SHIFT   7
#define	ADC_SC1_ADCH_MASK   (0x1FU)
#define	ADC_SC1_ADCH_SHIFT   (0U)
#define	ADC_SC1_ADCH(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
#define	ADC_SC1_DIFF_MASK   (0x20U)
#define	ADC_SC1_DIFF_SHIFT   (5U)
#define	ADC_SC1_DIFF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
#define	ADC_SC1_AIEN_MASK   (0x40U)
#define	ADC_SC1_AIEN_SHIFT   (6U)
#define	ADC_SC1_AIEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
#define	ADC_SC1_COCO_MASK   (0x80U)
#define	ADC_SC1_COCO_SHIFT   (7U)
#define	ADC_SC1_COCO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
#define	ADC_SC1_ADCH_MASK   (0x1FU)
#define	ADC_SC1_ADCH_SHIFT   (0U)
#define	ADC_SC1_ADCH(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
#define	ADC_SC1_DIFF_MASK   (0x20U)
#define	ADC_SC1_DIFF_SHIFT   (5U)
#define	ADC_SC1_DIFF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
#define	ADC_SC1_AIEN_MASK   (0x40U)
#define	ADC_SC1_AIEN_SHIFT   (6U)
#define	ADC_SC1_AIEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
#define	ADC_SC1_COCO_MASK   (0x80U)
#define	ADC_SC1_COCO_SHIFT   (7U)
#define	ADC_SC1_COCO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
#define	ADC_SC1_ADCH_MASK   (0x1FU)
#define	ADC_SC1_ADCH_SHIFT   (0U)
#define	ADC_SC1_ADCH(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
#define	ADC_SC1_DIFF_MASK   (0x20U)
#define	ADC_SC1_DIFF_SHIFT   (5U)
#define	ADC_SC1_DIFF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
#define	ADC_SC1_AIEN_MASK   (0x40U)
#define	ADC_SC1_AIEN_SHIFT   (6U)
#define	ADC_SC1_AIEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
#define	ADC_SC1_COCO_MASK   (0x80U)
#define	ADC_SC1_COCO_SHIFT   (7U)
#define	ADC_SC1_COCO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
#define	ADC_SC1_ADCH_MASK   (0x1FU)
#define	ADC_SC1_ADCH_SHIFT   (0U)
#define	ADC_SC1_ADCH(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
#define	ADC_SC1_DIFF_MASK   (0x20U)
#define	ADC_SC1_DIFF_SHIFT   (5U)
#define	ADC_SC1_DIFF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
#define	ADC_SC1_AIEN_MASK   (0x40U)
#define	ADC_SC1_AIEN_SHIFT   (6U)
#define	ADC_SC1_AIEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
#define	ADC_SC1_COCO_MASK   (0x80U)
#define	ADC_SC1_COCO_SHIFT   (7U)
#define	ADC_SC1_COCO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)

SC1 - ADC Status and Control Registers 1
#define	ADC_SC1_COUNT   (2U)

CFG1 - ADC Configuration Register 1
#define	ADC_CFG1_ADICLK_MASK   (0x3U)
#define	ADC_CFG1_ADICLK_SHIFT   (0U)
#define	ADC_CFG1_ADICLK(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
#define	ADC_CFG1_MODE_MASK   (0xCU)
#define	ADC_CFG1_MODE_SHIFT   (2U)
#define	ADC_CFG1_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
#define	ADC_CFG1_ADLSMP_MASK   (0x10U)
#define	ADC_CFG1_ADLSMP_SHIFT   (4U)
#define	ADC_CFG1_ADLSMP(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
#define	ADC_CFG1_ADIV_MASK   (0x60U)
#define	ADC_CFG1_ADIV_SHIFT   (5U)
#define	ADC_CFG1_ADIV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
#define	ADC_CFG1_ADLPC_MASK   (0x80U)
#define	ADC_CFG1_ADLPC_SHIFT   (7U)
#define	ADC_CFG1_ADLPC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
#define	ADC_CFG1_ADICLK_MASK   0x3u
#define	ADC_CFG1_ADICLK_SHIFT   0
#define	ADC_CFG1_ADICLK(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
#define	ADC_CFG1_MODE_MASK   0xCu
#define	ADC_CFG1_MODE_SHIFT   2
#define	ADC_CFG1_MODE(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
#define	ADC_CFG1_ADLSMP_MASK   0x10u
#define	ADC_CFG1_ADLSMP_SHIFT   4
#define	ADC_CFG1_ADIV_MASK   0x60u
#define	ADC_CFG1_ADIV_SHIFT   5
#define	ADC_CFG1_ADIV(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
#define	ADC_CFG1_ADLPC_MASK   0x80u
#define	ADC_CFG1_ADLPC_SHIFT   7
#define	ADC_CFG1_ADICLK_MASK   (0x3U)
#define	ADC_CFG1_ADICLK_SHIFT   (0U)
#define	ADC_CFG1_ADICLK(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
#define	ADC_CFG1_MODE_MASK   (0xCU)
#define	ADC_CFG1_MODE_SHIFT   (2U)
#define	ADC_CFG1_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
#define	ADC_CFG1_ADLSMP_MASK   (0x10U)
#define	ADC_CFG1_ADLSMP_SHIFT   (4U)
#define	ADC_CFG1_ADLSMP(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
#define	ADC_CFG1_ADIV_MASK   (0x60U)
#define	ADC_CFG1_ADIV_SHIFT   (5U)
#define	ADC_CFG1_ADIV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
#define	ADC_CFG1_ADLPC_MASK   (0x80U)
#define	ADC_CFG1_ADLPC_SHIFT   (7U)
#define	ADC_CFG1_ADLPC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
#define	ADC_CFG1_ADICLK_MASK   (0x3U)
#define	ADC_CFG1_ADICLK_SHIFT   (0U)
#define	ADC_CFG1_ADICLK(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
#define	ADC_CFG1_MODE_MASK   (0xCU)
#define	ADC_CFG1_MODE_SHIFT   (2U)
#define	ADC_CFG1_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
#define	ADC_CFG1_ADLSMP_MASK   (0x10U)
#define	ADC_CFG1_ADLSMP_SHIFT   (4U)
#define	ADC_CFG1_ADLSMP(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
#define	ADC_CFG1_ADIV_MASK   (0x60U)
#define	ADC_CFG1_ADIV_SHIFT   (5U)
#define	ADC_CFG1_ADIV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
#define	ADC_CFG1_ADLPC_MASK   (0x80U)
#define	ADC_CFG1_ADLPC_SHIFT   (7U)
#define	ADC_CFG1_ADLPC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
#define	ADC_CFG1_ADICLK_MASK   (0x3U)
#define	ADC_CFG1_ADICLK_SHIFT   (0U)
#define	ADC_CFG1_ADICLK(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
#define	ADC_CFG1_MODE_MASK   (0xCU)
#define	ADC_CFG1_MODE_SHIFT   (2U)
#define	ADC_CFG1_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
#define	ADC_CFG1_ADLSMP_MASK   (0x10U)
#define	ADC_CFG1_ADLSMP_SHIFT   (4U)
#define	ADC_CFG1_ADLSMP(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
#define	ADC_CFG1_ADIV_MASK   (0x60U)
#define	ADC_CFG1_ADIV_SHIFT   (5U)
#define	ADC_CFG1_ADIV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
#define	ADC_CFG1_ADLPC_MASK   (0x80U)
#define	ADC_CFG1_ADLPC_SHIFT   (7U)
#define	ADC_CFG1_ADLPC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
#define	ADC_CFG1_ADICLK_MASK   (0x3U)
#define	ADC_CFG1_ADICLK_SHIFT   (0U)
#define	ADC_CFG1_ADICLK(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
#define	ADC_CFG1_MODE_MASK   (0xCU)
#define	ADC_CFG1_MODE_SHIFT   (2U)
#define	ADC_CFG1_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
#define	ADC_CFG1_ADLSMP_MASK   (0x10U)
#define	ADC_CFG1_ADLSMP_SHIFT   (4U)
#define	ADC_CFG1_ADLSMP(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
#define	ADC_CFG1_ADIV_MASK   (0x60U)
#define	ADC_CFG1_ADIV_SHIFT   (5U)
#define	ADC_CFG1_ADIV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
#define	ADC_CFG1_ADLPC_MASK   (0x80U)
#define	ADC_CFG1_ADLPC_SHIFT   (7U)
#define	ADC_CFG1_ADLPC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)

CFG2 - ADC Configuration Register 2
#define	ADC_CFG2_ADLSTS_MASK   (0x3U)
#define	ADC_CFG2_ADLSTS_SHIFT   (0U)
#define	ADC_CFG2_ADLSTS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
#define	ADC_CFG2_ADHSC_MASK   (0x4U)
#define	ADC_CFG2_ADHSC_SHIFT   (2U)
#define	ADC_CFG2_ADHSC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
#define	ADC_CFG2_ADACKEN_MASK   (0x8U)
#define	ADC_CFG2_ADACKEN_SHIFT   (3U)
#define	ADC_CFG2_ADACKEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
#define	ADC_CFG2_MUXSEL_MASK   (0x10U)
#define	ADC_CFG2_MUXSEL_SHIFT   (4U)
#define	ADC_CFG2_MUXSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
#define	ADC_CFG2_ADLSTS_MASK   0x3u
#define	ADC_CFG2_ADLSTS_SHIFT   0
#define	ADC_CFG2_ADLSTS(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
#define	ADC_CFG2_ADHSC_MASK   0x4u
#define	ADC_CFG2_ADHSC_SHIFT   2
#define	ADC_CFG2_ADACKEN_MASK   0x8u
#define	ADC_CFG2_ADACKEN_SHIFT   3
#define	ADC_CFG2_MUXSEL_MASK   0x10u
#define	ADC_CFG2_MUXSEL_SHIFT   4
#define	ADC_CFG2_ADLSTS_MASK   (0x3U)
#define	ADC_CFG2_ADLSTS_SHIFT   (0U)
#define	ADC_CFG2_ADLSTS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
#define	ADC_CFG2_ADHSC_MASK   (0x4U)
#define	ADC_CFG2_ADHSC_SHIFT   (2U)
#define	ADC_CFG2_ADHSC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
#define	ADC_CFG2_ADACKEN_MASK   (0x8U)
#define	ADC_CFG2_ADACKEN_SHIFT   (3U)
#define	ADC_CFG2_ADACKEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
#define	ADC_CFG2_MUXSEL_MASK   (0x10U)
#define	ADC_CFG2_MUXSEL_SHIFT   (4U)
#define	ADC_CFG2_MUXSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
#define	ADC_CFG2_ADLSTS_MASK   (0x3U)
#define	ADC_CFG2_ADLSTS_SHIFT   (0U)
#define	ADC_CFG2_ADLSTS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
#define	ADC_CFG2_ADHSC_MASK   (0x4U)
#define	ADC_CFG2_ADHSC_SHIFT   (2U)
#define	ADC_CFG2_ADHSC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
#define	ADC_CFG2_ADACKEN_MASK   (0x8U)
#define	ADC_CFG2_ADACKEN_SHIFT   (3U)
#define	ADC_CFG2_ADACKEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
#define	ADC_CFG2_MUXSEL_MASK   (0x10U)
#define	ADC_CFG2_MUXSEL_SHIFT   (4U)
#define	ADC_CFG2_MUXSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
#define	ADC_CFG2_ADLSTS_MASK   (0x3U)
#define	ADC_CFG2_ADLSTS_SHIFT   (0U)
#define	ADC_CFG2_ADLSTS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
#define	ADC_CFG2_ADHSC_MASK   (0x4U)
#define	ADC_CFG2_ADHSC_SHIFT   (2U)
#define	ADC_CFG2_ADHSC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
#define	ADC_CFG2_ADACKEN_MASK   (0x8U)
#define	ADC_CFG2_ADACKEN_SHIFT   (3U)
#define	ADC_CFG2_ADACKEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
#define	ADC_CFG2_MUXSEL_MASK   (0x10U)
#define	ADC_CFG2_MUXSEL_SHIFT   (4U)
#define	ADC_CFG2_MUXSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
#define	ADC_CFG2_ADLSTS_MASK   (0x3U)
#define	ADC_CFG2_ADLSTS_SHIFT   (0U)
#define	ADC_CFG2_ADLSTS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
#define	ADC_CFG2_ADHSC_MASK   (0x4U)
#define	ADC_CFG2_ADHSC_SHIFT   (2U)
#define	ADC_CFG2_ADHSC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
#define	ADC_CFG2_ADACKEN_MASK   (0x8U)
#define	ADC_CFG2_ADACKEN_SHIFT   (3U)
#define	ADC_CFG2_ADACKEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
#define	ADC_CFG2_MUXSEL_MASK   (0x10U)
#define	ADC_CFG2_MUXSEL_SHIFT   (4U)
#define	ADC_CFG2_MUXSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)

R - ADC Data Result Register
#define	ADC_R_D_MASK   (0xFFFFU)
#define	ADC_R_D_SHIFT   (0U)
#define	ADC_R_D(x)   (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
#define	ADC_R_D_MASK   0xFFFFu
#define	ADC_R_D_SHIFT   0
#define	ADC_R_D(x)   (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
#define	ADC_R_D_MASK   (0xFFFFU)
#define	ADC_R_D_SHIFT   (0U)
#define	ADC_R_D(x)   (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
#define	ADC_R_D_MASK   (0xFFFFU)
#define	ADC_R_D_SHIFT   (0U)
#define	ADC_R_D(x)   (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
#define	ADC_R_D_MASK   (0xFFFFU)
#define	ADC_R_D_SHIFT   (0U)
#define	ADC_R_D(x)   (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
#define	ADC_R_D_MASK   (0xFFFFU)
#define	ADC_R_D_SHIFT   (0U)
#define	ADC_R_D(x)   (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)

R - ADC Data Result Register
#define	ADC_R_COUNT   (2U)

CV1 - Compare Value Registers
#define	ADC_CV1_CV_MASK   (0xFFFFU)
#define	ADC_CV1_CV_SHIFT   (0U)
#define	ADC_CV1_CV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
#define	ADC_CV1_CV_MASK   0xFFFFu
#define	ADC_CV1_CV_SHIFT   0
#define	ADC_CV1_CV(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
#define	ADC_CV1_CV_MASK   (0xFFFFU)
#define	ADC_CV1_CV_SHIFT   (0U)
#define	ADC_CV1_CV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
#define	ADC_CV1_CV_MASK   (0xFFFFU)
#define	ADC_CV1_CV_SHIFT   (0U)
#define	ADC_CV1_CV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
#define	ADC_CV1_CV_MASK   (0xFFFFU)
#define	ADC_CV1_CV_SHIFT   (0U)
#define	ADC_CV1_CV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
#define	ADC_CV1_CV_MASK   (0xFFFFU)
#define	ADC_CV1_CV_SHIFT   (0U)
#define	ADC_CV1_CV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)

CV2 - Compare Value Registers
#define	ADC_CV2_CV_MASK   (0xFFFFU)
#define	ADC_CV2_CV_SHIFT   (0U)
#define	ADC_CV2_CV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
#define	ADC_CV2_CV_MASK   0xFFFFu
#define	ADC_CV2_CV_SHIFT   0
#define	ADC_CV2_CV(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
#define	ADC_CV2_CV_MASK   (0xFFFFU)
#define	ADC_CV2_CV_SHIFT   (0U)
#define	ADC_CV2_CV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
#define	ADC_CV2_CV_MASK   (0xFFFFU)
#define	ADC_CV2_CV_SHIFT   (0U)
#define	ADC_CV2_CV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
#define	ADC_CV2_CV_MASK   (0xFFFFU)
#define	ADC_CV2_CV_SHIFT   (0U)
#define	ADC_CV2_CV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
#define	ADC_CV2_CV_MASK   (0xFFFFU)
#define	ADC_CV2_CV_SHIFT   (0U)
#define	ADC_CV2_CV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)

SC2 - Status and Control Register 2
#define	ADC_SC2_REFSEL_MASK   (0x3U)
#define	ADC_SC2_REFSEL_SHIFT   (0U)
#define	ADC_SC2_REFSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
#define	ADC_SC2_DMAEN_MASK   (0x4U)
#define	ADC_SC2_DMAEN_SHIFT   (2U)
#define	ADC_SC2_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
#define	ADC_SC2_ACREN_MASK   (0x8U)
#define	ADC_SC2_ACREN_SHIFT   (3U)
#define	ADC_SC2_ACREN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
#define	ADC_SC2_ACFGT_MASK   (0x10U)
#define	ADC_SC2_ACFGT_SHIFT   (4U)
#define	ADC_SC2_ACFGT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
#define	ADC_SC2_ACFE_MASK   (0x20U)
#define	ADC_SC2_ACFE_SHIFT   (5U)
#define	ADC_SC2_ACFE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
#define	ADC_SC2_ADTRG_MASK   (0x40U)
#define	ADC_SC2_ADTRG_SHIFT   (6U)
#define	ADC_SC2_ADTRG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
#define	ADC_SC2_ADACT_MASK   (0x80U)
#define	ADC_SC2_ADACT_SHIFT   (7U)
#define	ADC_SC2_ADACT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
#define	ADC_SC2_REFSEL_MASK   0x3u
#define	ADC_SC2_REFSEL_SHIFT   0
#define	ADC_SC2_REFSEL(x)   (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
#define	ADC_SC2_DMAEN_MASK   0x4u
#define	ADC_SC2_DMAEN_SHIFT   2
#define	ADC_SC2_ACREN_MASK   0x8u
#define	ADC_SC2_ACREN_SHIFT   3
#define	ADC_SC2_ACFGT_MASK   0x10u
#define	ADC_SC2_ACFGT_SHIFT   4
#define	ADC_SC2_ACFE_MASK   0x20u
#define	ADC_SC2_ACFE_SHIFT   5
#define	ADC_SC2_ADTRG_MASK   0x40u
#define	ADC_SC2_ADTRG_SHIFT   6
#define	ADC_SC2_ADACT_MASK   0x80u
#define	ADC_SC2_ADACT_SHIFT   7
#define	ADC_SC2_REFSEL_MASK   (0x3U)
#define	ADC_SC2_REFSEL_SHIFT   (0U)
#define	ADC_SC2_REFSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
#define	ADC_SC2_DMAEN_MASK   (0x4U)
#define	ADC_SC2_DMAEN_SHIFT   (2U)
#define	ADC_SC2_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
#define	ADC_SC2_ACREN_MASK   (0x8U)
#define	ADC_SC2_ACREN_SHIFT   (3U)
#define	ADC_SC2_ACREN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
#define	ADC_SC2_ACFGT_MASK   (0x10U)
#define	ADC_SC2_ACFGT_SHIFT   (4U)
#define	ADC_SC2_ACFGT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
#define	ADC_SC2_ACFE_MASK   (0x20U)
#define	ADC_SC2_ACFE_SHIFT   (5U)
#define	ADC_SC2_ACFE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
#define	ADC_SC2_ADTRG_MASK   (0x40U)
#define	ADC_SC2_ADTRG_SHIFT   (6U)
#define	ADC_SC2_ADTRG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
#define	ADC_SC2_ADACT_MASK   (0x80U)
#define	ADC_SC2_ADACT_SHIFT   (7U)
#define	ADC_SC2_ADACT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
#define	ADC_SC2_REFSEL_MASK   (0x3U)
#define	ADC_SC2_REFSEL_SHIFT   (0U)
#define	ADC_SC2_REFSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
#define	ADC_SC2_DMAEN_MASK   (0x4U)
#define	ADC_SC2_DMAEN_SHIFT   (2U)
#define	ADC_SC2_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
#define	ADC_SC2_ACREN_MASK   (0x8U)
#define	ADC_SC2_ACREN_SHIFT   (3U)
#define	ADC_SC2_ACREN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
#define	ADC_SC2_ACFGT_MASK   (0x10U)
#define	ADC_SC2_ACFGT_SHIFT   (4U)
#define	ADC_SC2_ACFGT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
#define	ADC_SC2_ACFE_MASK   (0x20U)
#define	ADC_SC2_ACFE_SHIFT   (5U)
#define	ADC_SC2_ACFE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
#define	ADC_SC2_ADTRG_MASK   (0x40U)
#define	ADC_SC2_ADTRG_SHIFT   (6U)
#define	ADC_SC2_ADTRG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
#define	ADC_SC2_ADACT_MASK   (0x80U)
#define	ADC_SC2_ADACT_SHIFT   (7U)
#define	ADC_SC2_ADACT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
#define	ADC_SC2_REFSEL_MASK   (0x3U)
#define	ADC_SC2_REFSEL_SHIFT   (0U)
#define	ADC_SC2_REFSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
#define	ADC_SC2_DMAEN_MASK   (0x4U)
#define	ADC_SC2_DMAEN_SHIFT   (2U)
#define	ADC_SC2_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
#define	ADC_SC2_ACREN_MASK   (0x8U)
#define	ADC_SC2_ACREN_SHIFT   (3U)
#define	ADC_SC2_ACREN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
#define	ADC_SC2_ACFGT_MASK   (0x10U)
#define	ADC_SC2_ACFGT_SHIFT   (4U)
#define	ADC_SC2_ACFGT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
#define	ADC_SC2_ACFE_MASK   (0x20U)
#define	ADC_SC2_ACFE_SHIFT   (5U)
#define	ADC_SC2_ACFE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
#define	ADC_SC2_ADTRG_MASK   (0x40U)
#define	ADC_SC2_ADTRG_SHIFT   (6U)
#define	ADC_SC2_ADTRG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
#define	ADC_SC2_ADACT_MASK   (0x80U)
#define	ADC_SC2_ADACT_SHIFT   (7U)
#define	ADC_SC2_ADACT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
#define	ADC_SC2_REFSEL_MASK   (0x3U)
#define	ADC_SC2_REFSEL_SHIFT   (0U)
#define	ADC_SC2_REFSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
#define	ADC_SC2_DMAEN_MASK   (0x4U)
#define	ADC_SC2_DMAEN_SHIFT   (2U)
#define	ADC_SC2_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
#define	ADC_SC2_ACREN_MASK   (0x8U)
#define	ADC_SC2_ACREN_SHIFT   (3U)
#define	ADC_SC2_ACREN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
#define	ADC_SC2_ACFGT_MASK   (0x10U)
#define	ADC_SC2_ACFGT_SHIFT   (4U)
#define	ADC_SC2_ACFGT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
#define	ADC_SC2_ACFE_MASK   (0x20U)
#define	ADC_SC2_ACFE_SHIFT   (5U)
#define	ADC_SC2_ACFE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
#define	ADC_SC2_ADTRG_MASK   (0x40U)
#define	ADC_SC2_ADTRG_SHIFT   (6U)
#define	ADC_SC2_ADTRG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
#define	ADC_SC2_ADACT_MASK   (0x80U)
#define	ADC_SC2_ADACT_SHIFT   (7U)
#define	ADC_SC2_ADACT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)

SC3 - Status and Control Register 3
#define	ADC_SC3_AVGS_MASK   (0x3U)
#define	ADC_SC3_AVGS_SHIFT   (0U)
#define	ADC_SC3_AVGS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
#define	ADC_SC3_AVGE_MASK   (0x4U)
#define	ADC_SC3_AVGE_SHIFT   (2U)
#define	ADC_SC3_AVGE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
#define	ADC_SC3_ADCO_MASK   (0x8U)
#define	ADC_SC3_ADCO_SHIFT   (3U)
#define	ADC_SC3_ADCO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
#define	ADC_SC3_CALF_MASK   (0x40U)
#define	ADC_SC3_CALF_SHIFT   (6U)
#define	ADC_SC3_CALF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
#define	ADC_SC3_CAL_MASK   (0x80U)
#define	ADC_SC3_CAL_SHIFT   (7U)
#define	ADC_SC3_CAL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
#define	ADC_SC3_AVGS_MASK   0x3u
#define	ADC_SC3_AVGS_SHIFT   0
#define	ADC_SC3_AVGS(x)   (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
#define	ADC_SC3_AVGE_MASK   0x4u
#define	ADC_SC3_AVGE_SHIFT   2
#define	ADC_SC3_ADCO_MASK   0x8u
#define	ADC_SC3_ADCO_SHIFT   3
#define	ADC_SC3_CALF_MASK   0x40u
#define	ADC_SC3_CALF_SHIFT   6
#define	ADC_SC3_CAL_MASK   0x80u
#define	ADC_SC3_CAL_SHIFT   7
#define	ADC_SC3_AVGS_MASK   (0x3U)
#define	ADC_SC3_AVGS_SHIFT   (0U)
#define	ADC_SC3_AVGS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
#define	ADC_SC3_AVGE_MASK   (0x4U)
#define	ADC_SC3_AVGE_SHIFT   (2U)
#define	ADC_SC3_AVGE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
#define	ADC_SC3_ADCO_MASK   (0x8U)
#define	ADC_SC3_ADCO_SHIFT   (3U)
#define	ADC_SC3_ADCO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
#define	ADC_SC3_CALF_MASK   (0x40U)
#define	ADC_SC3_CALF_SHIFT   (6U)
#define	ADC_SC3_CALF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
#define	ADC_SC3_CAL_MASK   (0x80U)
#define	ADC_SC3_CAL_SHIFT   (7U)
#define	ADC_SC3_CAL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
#define	ADC_SC3_AVGS_MASK   (0x3U)
#define	ADC_SC3_AVGS_SHIFT   (0U)
#define	ADC_SC3_AVGS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
#define	ADC_SC3_AVGE_MASK   (0x4U)
#define	ADC_SC3_AVGE_SHIFT   (2U)
#define	ADC_SC3_AVGE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
#define	ADC_SC3_ADCO_MASK   (0x8U)
#define	ADC_SC3_ADCO_SHIFT   (3U)
#define	ADC_SC3_ADCO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
#define	ADC_SC3_CALF_MASK   (0x40U)
#define	ADC_SC3_CALF_SHIFT   (6U)
#define	ADC_SC3_CALF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
#define	ADC_SC3_CAL_MASK   (0x80U)
#define	ADC_SC3_CAL_SHIFT   (7U)
#define	ADC_SC3_CAL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
#define	ADC_SC3_AVGS_MASK   (0x3U)
#define	ADC_SC3_AVGS_SHIFT   (0U)
#define	ADC_SC3_AVGS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
#define	ADC_SC3_AVGE_MASK   (0x4U)
#define	ADC_SC3_AVGE_SHIFT   (2U)
#define	ADC_SC3_AVGE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
#define	ADC_SC3_ADCO_MASK   (0x8U)
#define	ADC_SC3_ADCO_SHIFT   (3U)
#define	ADC_SC3_ADCO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
#define	ADC_SC3_CALF_MASK   (0x40U)
#define	ADC_SC3_CALF_SHIFT   (6U)
#define	ADC_SC3_CALF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
#define	ADC_SC3_CAL_MASK   (0x80U)
#define	ADC_SC3_CAL_SHIFT   (7U)
#define	ADC_SC3_CAL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
#define	ADC_SC3_AVGS_MASK   (0x3U)
#define	ADC_SC3_AVGS_SHIFT   (0U)
#define	ADC_SC3_AVGS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
#define	ADC_SC3_AVGE_MASK   (0x4U)
#define	ADC_SC3_AVGE_SHIFT   (2U)
#define	ADC_SC3_AVGE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
#define	ADC_SC3_ADCO_MASK   (0x8U)
#define	ADC_SC3_ADCO_SHIFT   (3U)
#define	ADC_SC3_ADCO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
#define	ADC_SC3_CALF_MASK   (0x40U)
#define	ADC_SC3_CALF_SHIFT   (6U)
#define	ADC_SC3_CALF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
#define	ADC_SC3_CAL_MASK   (0x80U)
#define	ADC_SC3_CAL_SHIFT   (7U)
#define	ADC_SC3_CAL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)

OFS - ADC Offset Correction Register
#define	ADC_OFS_OFS_MASK   (0xFFFFU)
#define	ADC_OFS_OFS_SHIFT   (0U)
#define	ADC_OFS_OFS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
#define	ADC_OFS_OFS_MASK   0xFFFFu
#define	ADC_OFS_OFS_SHIFT   0
#define	ADC_OFS_OFS(x)   (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
#define	ADC_OFS_OFS_MASK   (0xFFFFU)
#define	ADC_OFS_OFS_SHIFT   (0U)
#define	ADC_OFS_OFS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
#define	ADC_OFS_OFS_MASK   (0xFFFFU)
#define	ADC_OFS_OFS_SHIFT   (0U)
#define	ADC_OFS_OFS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
#define	ADC_OFS_OFS_MASK   (0xFFFFU)
#define	ADC_OFS_OFS_SHIFT   (0U)
#define	ADC_OFS_OFS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
#define	ADC_OFS_OFS_MASK   (0xFFFFU)
#define	ADC_OFS_OFS_SHIFT   (0U)
#define	ADC_OFS_OFS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)

PG - ADC Plus-Side Gain Register
#define	ADC_PG_PG_MASK   (0xFFFFU)
#define	ADC_PG_PG_SHIFT   (0U)
#define	ADC_PG_PG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
#define	ADC_PG_PG_MASK   0xFFFFu
#define	ADC_PG_PG_SHIFT   0
#define	ADC_PG_PG(x)   (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
#define	ADC_PG_PG_MASK   (0xFFFFU)
#define	ADC_PG_PG_SHIFT   (0U)
#define	ADC_PG_PG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
#define	ADC_PG_PG_MASK   (0xFFFFU)
#define	ADC_PG_PG_SHIFT   (0U)
#define	ADC_PG_PG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
#define	ADC_PG_PG_MASK   (0xFFFFU)
#define	ADC_PG_PG_SHIFT   (0U)
#define	ADC_PG_PG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
#define	ADC_PG_PG_MASK   (0xFFFFU)
#define	ADC_PG_PG_SHIFT   (0U)
#define	ADC_PG_PG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)

MG - ADC Minus-Side Gain Register
#define	ADC_MG_MG_MASK   (0xFFFFU)
#define	ADC_MG_MG_SHIFT   (0U)
#define	ADC_MG_MG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
#define	ADC_MG_MG_MASK   0xFFFFu
#define	ADC_MG_MG_SHIFT   0
#define	ADC_MG_MG(x)   (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
#define	ADC_MG_MG_MASK   (0xFFFFU)
#define	ADC_MG_MG_SHIFT   (0U)
#define	ADC_MG_MG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
#define	ADC_MG_MG_MASK   (0xFFFFU)
#define	ADC_MG_MG_SHIFT   (0U)
#define	ADC_MG_MG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
#define	ADC_MG_MG_MASK   (0xFFFFU)
#define	ADC_MG_MG_SHIFT   (0U)
#define	ADC_MG_MG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
#define	ADC_MG_MG_MASK   (0xFFFFU)
#define	ADC_MG_MG_SHIFT   (0U)
#define	ADC_MG_MG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)

CLPD - ADC Plus-Side General Calibration Value Register
#define	ADC_CLPD_CLPD_MASK   (0x3FU)
#define	ADC_CLPD_CLPD_SHIFT   (0U)
#define	ADC_CLPD_CLPD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
#define	ADC_CLPD_CLPD_MASK   0x3Fu
#define	ADC_CLPD_CLPD_SHIFT   0
#define	ADC_CLPD_CLPD(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
#define	ADC_CLPD_CLPD_MASK   (0x3FU)
#define	ADC_CLPD_CLPD_SHIFT   (0U)
#define	ADC_CLPD_CLPD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
#define	ADC_CLPD_CLPD_MASK   (0x3FU)
#define	ADC_CLPD_CLPD_SHIFT   (0U)
#define	ADC_CLPD_CLPD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
#define	ADC_CLPD_CLPD_MASK   (0x3FU)
#define	ADC_CLPD_CLPD_SHIFT   (0U)
#define	ADC_CLPD_CLPD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
#define	ADC_CLPD_CLPD_MASK   (0x3FU)
#define	ADC_CLPD_CLPD_SHIFT   (0U)
#define	ADC_CLPD_CLPD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)

CLPS - ADC Plus-Side General Calibration Value Register
#define	ADC_CLPS_CLPS_MASK   (0x3FU)
#define	ADC_CLPS_CLPS_SHIFT   (0U)
#define	ADC_CLPS_CLPS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
#define	ADC_CLPS_CLPS_MASK   0x3Fu
#define	ADC_CLPS_CLPS_SHIFT   0
#define	ADC_CLPS_CLPS(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
#define	ADC_CLPS_CLPS_MASK   (0x3FU)
#define	ADC_CLPS_CLPS_SHIFT   (0U)
#define	ADC_CLPS_CLPS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
#define	ADC_CLPS_CLPS_MASK   (0x3FU)
#define	ADC_CLPS_CLPS_SHIFT   (0U)
#define	ADC_CLPS_CLPS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
#define	ADC_CLPS_CLPS_MASK   (0x3FU)
#define	ADC_CLPS_CLPS_SHIFT   (0U)
#define	ADC_CLPS_CLPS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
#define	ADC_CLPS_CLPS_MASK   (0x3FU)
#define	ADC_CLPS_CLPS_SHIFT   (0U)
#define	ADC_CLPS_CLPS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)

CLP4 - ADC Plus-Side General Calibration Value Register
#define	ADC_CLP4_CLP4_MASK   (0x3FFU)
#define	ADC_CLP4_CLP4_SHIFT   (0U)
#define	ADC_CLP4_CLP4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
#define	ADC_CLP4_CLP4_MASK   0x3FFu
#define	ADC_CLP4_CLP4_SHIFT   0
#define	ADC_CLP4_CLP4(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
#define	ADC_CLP4_CLP4_MASK   (0x3FFU)
#define	ADC_CLP4_CLP4_SHIFT   (0U)
#define	ADC_CLP4_CLP4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
#define	ADC_CLP4_CLP4_MASK   (0x3FFU)
#define	ADC_CLP4_CLP4_SHIFT   (0U)
#define	ADC_CLP4_CLP4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
#define	ADC_CLP4_CLP4_MASK   (0x3FFU)
#define	ADC_CLP4_CLP4_SHIFT   (0U)
#define	ADC_CLP4_CLP4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
#define	ADC_CLP4_CLP4_MASK   (0x3FFU)
#define	ADC_CLP4_CLP4_SHIFT   (0U)
#define	ADC_CLP4_CLP4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)

CLP3 - ADC Plus-Side General Calibration Value Register
#define	ADC_CLP3_CLP3_MASK   (0x1FFU)
#define	ADC_CLP3_CLP3_SHIFT   (0U)
#define	ADC_CLP3_CLP3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
#define	ADC_CLP3_CLP3_MASK   0x1FFu
#define	ADC_CLP3_CLP3_SHIFT   0
#define	ADC_CLP3_CLP3(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
#define	ADC_CLP3_CLP3_MASK   (0x1FFU)
#define	ADC_CLP3_CLP3_SHIFT   (0U)
#define	ADC_CLP3_CLP3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
#define	ADC_CLP3_CLP3_MASK   (0x1FFU)
#define	ADC_CLP3_CLP3_SHIFT   (0U)
#define	ADC_CLP3_CLP3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
#define	ADC_CLP3_CLP3_MASK   (0x1FFU)
#define	ADC_CLP3_CLP3_SHIFT   (0U)
#define	ADC_CLP3_CLP3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
#define	ADC_CLP3_CLP3_MASK   (0x1FFU)
#define	ADC_CLP3_CLP3_SHIFT   (0U)
#define	ADC_CLP3_CLP3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)

CLP2 - ADC Plus-Side General Calibration Value Register
#define	ADC_CLP2_CLP2_MASK   (0xFFU)
#define	ADC_CLP2_CLP2_SHIFT   (0U)
#define	ADC_CLP2_CLP2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
#define	ADC_CLP2_CLP2_MASK   0xFFu
#define	ADC_CLP2_CLP2_SHIFT   0
#define	ADC_CLP2_CLP2(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
#define	ADC_CLP2_CLP2_MASK   (0xFFU)
#define	ADC_CLP2_CLP2_SHIFT   (0U)
#define	ADC_CLP2_CLP2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
#define	ADC_CLP2_CLP2_MASK   (0xFFU)
#define	ADC_CLP2_CLP2_SHIFT   (0U)
#define	ADC_CLP2_CLP2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
#define	ADC_CLP2_CLP2_MASK   (0xFFU)
#define	ADC_CLP2_CLP2_SHIFT   (0U)
#define	ADC_CLP2_CLP2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
#define	ADC_CLP2_CLP2_MASK   (0xFFU)
#define	ADC_CLP2_CLP2_SHIFT   (0U)
#define	ADC_CLP2_CLP2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)

CLP1 - ADC Plus-Side General Calibration Value Register
#define	ADC_CLP1_CLP1_MASK   (0x7FU)
#define	ADC_CLP1_CLP1_SHIFT   (0U)
#define	ADC_CLP1_CLP1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
#define	ADC_CLP1_CLP1_MASK   0x7Fu
#define	ADC_CLP1_CLP1_SHIFT   0
#define	ADC_CLP1_CLP1(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
#define	ADC_CLP1_CLP1_MASK   (0x7FU)
#define	ADC_CLP1_CLP1_SHIFT   (0U)
#define	ADC_CLP1_CLP1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
#define	ADC_CLP1_CLP1_MASK   (0x7FU)
#define	ADC_CLP1_CLP1_SHIFT   (0U)
#define	ADC_CLP1_CLP1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
#define	ADC_CLP1_CLP1_MASK   (0x7FU)
#define	ADC_CLP1_CLP1_SHIFT   (0U)
#define	ADC_CLP1_CLP1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
#define	ADC_CLP1_CLP1_MASK   (0x7FU)
#define	ADC_CLP1_CLP1_SHIFT   (0U)
#define	ADC_CLP1_CLP1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)

CLP0 - ADC Plus-Side General Calibration Value Register
#define	ADC_CLP0_CLP0_MASK   (0x3FU)
#define	ADC_CLP0_CLP0_SHIFT   (0U)
#define	ADC_CLP0_CLP0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
#define	ADC_CLP0_CLP0_MASK   0x3Fu
#define	ADC_CLP0_CLP0_SHIFT   0
#define	ADC_CLP0_CLP0(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
#define	ADC_CLP0_CLP0_MASK   (0x3FU)
#define	ADC_CLP0_CLP0_SHIFT   (0U)
#define	ADC_CLP0_CLP0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
#define	ADC_CLP0_CLP0_MASK   (0x3FU)
#define	ADC_CLP0_CLP0_SHIFT   (0U)
#define	ADC_CLP0_CLP0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
#define	ADC_CLP0_CLP0_MASK   (0x3FU)
#define	ADC_CLP0_CLP0_SHIFT   (0U)
#define	ADC_CLP0_CLP0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
#define	ADC_CLP0_CLP0_MASK   (0x3FU)
#define	ADC_CLP0_CLP0_SHIFT   (0U)
#define	ADC_CLP0_CLP0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)

PGA - ADC PGA Register
#define	ADC_PGA_PGAG_MASK   (0xF0000U)
#define	ADC_PGA_PGAG_SHIFT   (16U)
#define	ADC_PGA_PGAG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PGA_PGAG_SHIFT)) & ADC_PGA_PGAG_MASK)
#define	ADC_PGA_PGALPb_MASK   (0x100000U)
#define	ADC_PGA_PGALPb_SHIFT   (20U)
#define	ADC_PGA_PGALPb(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PGA_PGALPb_SHIFT)) & ADC_PGA_PGALPb_MASK)
#define	ADC_PGA_PGAEN_MASK   (0x800000U)
#define	ADC_PGA_PGAEN_SHIFT   (23U)
#define	ADC_PGA_PGAEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PGA_PGAEN_SHIFT)) & ADC_PGA_PGAEN_MASK)

CLMD - ADC Minus-Side General Calibration Value Register
#define	ADC_CLMD_CLMD_MASK   (0x3FU)
#define	ADC_CLMD_CLMD_SHIFT   (0U)
#define	ADC_CLMD_CLMD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
#define	ADC_CLMD_CLMD_MASK   0x3Fu
#define	ADC_CLMD_CLMD_SHIFT   0
#define	ADC_CLMD_CLMD(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
#define	ADC_CLMD_CLMD_MASK   (0x3FU)
#define	ADC_CLMD_CLMD_SHIFT   (0U)
#define	ADC_CLMD_CLMD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
#define	ADC_CLMD_CLMD_MASK   (0x3FU)
#define	ADC_CLMD_CLMD_SHIFT   (0U)
#define	ADC_CLMD_CLMD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
#define	ADC_CLMD_CLMD_MASK   (0x3FU)
#define	ADC_CLMD_CLMD_SHIFT   (0U)
#define	ADC_CLMD_CLMD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
#define	ADC_CLMD_CLMD_MASK   (0x3FU)
#define	ADC_CLMD_CLMD_SHIFT   (0U)
#define	ADC_CLMD_CLMD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)

CLMS - ADC Minus-Side General Calibration Value Register
#define	ADC_CLMS_CLMS_MASK   (0x3FU)
#define	ADC_CLMS_CLMS_SHIFT   (0U)
#define	ADC_CLMS_CLMS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
#define	ADC_CLMS_CLMS_MASK   0x3Fu
#define	ADC_CLMS_CLMS_SHIFT   0
#define	ADC_CLMS_CLMS(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
#define	ADC_CLMS_CLMS_MASK   (0x3FU)
#define	ADC_CLMS_CLMS_SHIFT   (0U)
#define	ADC_CLMS_CLMS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
#define	ADC_CLMS_CLMS_MASK   (0x3FU)
#define	ADC_CLMS_CLMS_SHIFT   (0U)
#define	ADC_CLMS_CLMS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
#define	ADC_CLMS_CLMS_MASK   (0x3FU)
#define	ADC_CLMS_CLMS_SHIFT   (0U)
#define	ADC_CLMS_CLMS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
#define	ADC_CLMS_CLMS_MASK   (0x3FU)
#define	ADC_CLMS_CLMS_SHIFT   (0U)
#define	ADC_CLMS_CLMS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)

CLM4 - ADC Minus-Side General Calibration Value Register
#define	ADC_CLM4_CLM4_MASK   (0x3FFU)
#define	ADC_CLM4_CLM4_SHIFT   (0U)
#define	ADC_CLM4_CLM4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
#define	ADC_CLM4_CLM4_MASK   0x3FFu
#define	ADC_CLM4_CLM4_SHIFT   0
#define	ADC_CLM4_CLM4(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
#define	ADC_CLM4_CLM4_MASK   (0x3FFU)
#define	ADC_CLM4_CLM4_SHIFT   (0U)
#define	ADC_CLM4_CLM4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
#define	ADC_CLM4_CLM4_MASK   (0x3FFU)
#define	ADC_CLM4_CLM4_SHIFT   (0U)
#define	ADC_CLM4_CLM4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
#define	ADC_CLM4_CLM4_MASK   (0x3FFU)
#define	ADC_CLM4_CLM4_SHIFT   (0U)
#define	ADC_CLM4_CLM4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
#define	ADC_CLM4_CLM4_MASK   (0x3FFU)
#define	ADC_CLM4_CLM4_SHIFT   (0U)
#define	ADC_CLM4_CLM4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)

CLM3 - ADC Minus-Side General Calibration Value Register
#define	ADC_CLM3_CLM3_MASK   (0x1FFU)
#define	ADC_CLM3_CLM3_SHIFT   (0U)
#define	ADC_CLM3_CLM3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
#define	ADC_CLM3_CLM3_MASK   0x1FFu
#define	ADC_CLM3_CLM3_SHIFT   0
#define	ADC_CLM3_CLM3(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
#define	ADC_CLM3_CLM3_MASK   (0x1FFU)
#define	ADC_CLM3_CLM3_SHIFT   (0U)
#define	ADC_CLM3_CLM3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
#define	ADC_CLM3_CLM3_MASK   (0x1FFU)
#define	ADC_CLM3_CLM3_SHIFT   (0U)
#define	ADC_CLM3_CLM3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
#define	ADC_CLM3_CLM3_MASK   (0x1FFU)
#define	ADC_CLM3_CLM3_SHIFT   (0U)
#define	ADC_CLM3_CLM3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
#define	ADC_CLM3_CLM3_MASK   (0x1FFU)
#define	ADC_CLM3_CLM3_SHIFT   (0U)
#define	ADC_CLM3_CLM3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)

CLM2 - ADC Minus-Side General Calibration Value Register
#define	ADC_CLM2_CLM2_MASK   (0xFFU)
#define	ADC_CLM2_CLM2_SHIFT   (0U)
#define	ADC_CLM2_CLM2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
#define	ADC_CLM2_CLM2_MASK   0xFFu
#define	ADC_CLM2_CLM2_SHIFT   0
#define	ADC_CLM2_CLM2(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
#define	ADC_CLM2_CLM2_MASK   (0xFFU)
#define	ADC_CLM2_CLM2_SHIFT   (0U)
#define	ADC_CLM2_CLM2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
#define	ADC_CLM2_CLM2_MASK   (0xFFU)
#define	ADC_CLM2_CLM2_SHIFT   (0U)
#define	ADC_CLM2_CLM2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
#define	ADC_CLM2_CLM2_MASK   (0xFFU)
#define	ADC_CLM2_CLM2_SHIFT   (0U)
#define	ADC_CLM2_CLM2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
#define	ADC_CLM2_CLM2_MASK   (0xFFU)
#define	ADC_CLM2_CLM2_SHIFT   (0U)
#define	ADC_CLM2_CLM2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)

CLM1 - ADC Minus-Side General Calibration Value Register
#define	ADC_CLM1_CLM1_MASK   (0x7FU)
#define	ADC_CLM1_CLM1_SHIFT   (0U)
#define	ADC_CLM1_CLM1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
#define	ADC_CLM1_CLM1_MASK   0x7Fu
#define	ADC_CLM1_CLM1_SHIFT   0
#define	ADC_CLM1_CLM1(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
#define	ADC_CLM1_CLM1_MASK   (0x7FU)
#define	ADC_CLM1_CLM1_SHIFT   (0U)
#define	ADC_CLM1_CLM1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
#define	ADC_CLM1_CLM1_MASK   (0x7FU)
#define	ADC_CLM1_CLM1_SHIFT   (0U)
#define	ADC_CLM1_CLM1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
#define	ADC_CLM1_CLM1_MASK   (0x7FU)
#define	ADC_CLM1_CLM1_SHIFT   (0U)
#define	ADC_CLM1_CLM1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
#define	ADC_CLM1_CLM1_MASK   (0x7FU)
#define	ADC_CLM1_CLM1_SHIFT   (0U)
#define	ADC_CLM1_CLM1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)

CLM0 - ADC Minus-Side General Calibration Value Register
#define	ADC_CLM0_CLM0_MASK   (0x3FU)
#define	ADC_CLM0_CLM0_SHIFT   (0U)
#define	ADC_CLM0_CLM0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
#define	ADC_CLM0_CLM0_MASK   0x3Fu
#define	ADC_CLM0_CLM0_SHIFT   0
#define	ADC_CLM0_CLM0(x)   (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
#define	ADC_CLM0_CLM0_MASK   (0x3FU)
#define	ADC_CLM0_CLM0_SHIFT   (0U)
#define	ADC_CLM0_CLM0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
#define	ADC_CLM0_CLM0_MASK   (0x3FU)
#define	ADC_CLM0_CLM0_SHIFT   (0U)
#define	ADC_CLM0_CLM0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
#define	ADC_CLM0_CLM0_MASK   (0x3FU)
#define	ADC_CLM0_CLM0_SHIFT   (0U)
#define	ADC_CLM0_CLM0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
#define	ADC_CLM0_CLM0_MASK   (0x3FU)
#define	ADC_CLM0_CLM0_SHIFT   (0U)
#define	ADC_CLM0_CLM0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)

Macro Definition Documentation

ADC0

#define ADC0   ((ADC_Type *)ADC0_BASE)

Peripheral ADC0 base pointer

ADC0_BASE

#define ADC0_BASE   (0x4003B000u)

Peripheral ADC0 base address

ADC1

#define ADC1   ((ADC_Type *)ADC1_BASE)

Peripheral ADC1 base pointer

ADC1_BASE

#define ADC1_BASE   (0x400BB000u)

Peripheral ADC1 base address

ADC_BASE_ADDRS

#define ADC_BASE_ADDRS   { ADC0_BASE, ADC1_BASE }

Array initializer of ADC peripheral base addresses

ADC_BASE_PTRS

#define ADC_BASE_PTRS   { ADC0, ADC1 }

Array initializer of ADC peripheral base pointers

ADC_CFG1_ADICLK [1/6]

#define ADC_CFG1_ADICLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)

ADICLK - Input Clock Select 0b00..Bus clock 0b01..Alternate clock 2 (ALTCLK2) 0b10..Alternate clock (ALTCLK) 0b11..Asynchronous clock (ADACK)

ADICLK - Input Clock Select 0b00..Bus clock 0b01..Bus clock divided by 2(BUSCLK/2) 0b10..Alternate clock (ALTCLK) 0b11..Asynchronous clock (ADACK)

ADC_CFG1_ADICLK [2/6]

#define ADC_CFG1_ADICLK

(

x

)

(((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)

ADICLK - Input Clock Select 0b00..Bus clock 0b01..Alternate clock 2 (ALTCLK2) 0b10..Alternate clock (ALTCLK) 0b11..Asynchronous clock (ADACK)

ADICLK - Input Clock Select 0b00..Bus clock 0b01..Bus clock divided by 2(BUSCLK/2) 0b10..Alternate clock (ALTCLK) 0b11..Asynchronous clock (ADACK)

ADC_CFG1_ADICLK [3/6]

#define ADC_CFG1_ADICLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)

ADICLK - Input Clock Select 0b00..Bus clock 0b01..Alternate clock 2 (ALTCLK2) 0b10..Alternate clock (ALTCLK) 0b11..Asynchronous clock (ADACK)

ADICLK - Input Clock Select 0b00..Bus clock 0b01..Bus clock divided by 2(BUSCLK/2) 0b10..Alternate clock (ALTCLK) 0b11..Asynchronous clock (ADACK)

ADC_CFG1_ADICLK [4/6]

#define ADC_CFG1_ADICLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)

ADICLK - Input Clock Select 0b00..Bus clock 0b01..Bus clock divided by 2(BUSCLK/2) 0b10..Alternate clock (ALTCLK) 0b11..Asynchronous clock (ADACK)

ADICLK - Input Clock Select 0b00..Bus clock 0b01..Alternate clock 2 (ALTCLK2) 0b10..Alternate clock (ALTCLK) 0b11..Asynchronous clock (ADACK)

ADC_CFG1_ADICLK [5/6]

#define ADC_CFG1_ADICLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)

ADICLK - Input Clock Select 0b00..Bus clock 0b01..Bus clock divided by 2(BUSCLK/2) 0b10..Alternate clock (ALTCLK) 0b11..Asynchronous clock (ADACK)

ADICLK - Input Clock Select 0b00..Bus clock 0b01..Alternate clock 2 (ALTCLK2) 0b10..Alternate clock (ALTCLK) 0b11..Asynchronous clock (ADACK)

ADC_CFG1_ADICLK [6/6]

#define ADC_CFG1_ADICLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)

ADICLK - Input Clock Select 0b00..Bus clock 0b01..Alternate clock 2 (ALTCLK2) 0b10..Alternate clock (ALTCLK) 0b11..Asynchronous clock (ADACK)

ADC_CFG1_ADIV [1/6]

#define ADC_CFG1_ADIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)

ADIV - Clock Divide Select 0b00..The divide ratio is 1 and the clock rate is input clock. 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.

ADC_CFG1_ADIV [2/6]

#define ADC_CFG1_ADIV

(

x

)

(((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)

ADIV - Clock Divide Select 0b00..The divide ratio is 1 and the clock rate is input clock. 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.

ADC_CFG1_ADIV [3/6]

#define ADC_CFG1_ADIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)

ADIV - Clock Divide Select 0b00..The divide ratio is 1 and the clock rate is input clock. 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.

ADC_CFG1_ADIV [4/6]

#define ADC_CFG1_ADIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)

ADIV - Clock Divide Select 0b00..The divide ratio is 1 and the clock rate is input clock. 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.

ADC_CFG1_ADIV [5/6]

#define ADC_CFG1_ADIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)

ADIV - Clock Divide Select 0b00..The divide ratio is 1 and the clock rate is input clock. 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.

ADC_CFG1_ADIV [6/6]

#define ADC_CFG1_ADIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)

ADIV - Clock Divide Select 0b00..The divide ratio is 1 and the clock rate is input clock. 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.

ADC_CFG1_ADLPC [1/5]

#define ADC_CFG1_ADLPC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)

ADLPC - Low-Power Configuration 0b0..Normal power configuration. 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.

ADC_CFG1_ADLPC [2/5]

#define ADC_CFG1_ADLPC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)

ADLPC - Low-Power Configuration 0b0..Normal power configuration. 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.

ADC_CFG1_ADLPC [3/5]

#define ADC_CFG1_ADLPC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)

ADLPC - Low-Power Configuration 0b0..Normal power configuration. 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.

ADC_CFG1_ADLPC [4/5]

#define ADC_CFG1_ADLPC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)

ADLPC - Low-Power Configuration 0b0..Normal power configuration. 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.

ADC_CFG1_ADLPC [5/5]

#define ADC_CFG1_ADLPC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)

ADLPC - Low-Power Configuration 0b0..Normal power configuration. 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.

ADC_CFG1_ADLSMP [1/5]

#define ADC_CFG1_ADLSMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)

ADLSMP - Sample Time Configuration 0b0..Short sample time. 0b1..Long sample time.

ADC_CFG1_ADLSMP [2/5]

#define ADC_CFG1_ADLSMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)

ADLSMP - Sample Time Configuration 0b0..Short sample time. 0b1..Long sample time.

ADC_CFG1_ADLSMP [3/5]

#define ADC_CFG1_ADLSMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)

ADLSMP - Sample Time Configuration 0b0..Short sample time. 0b1..Long sample time.

ADC_CFG1_ADLSMP [4/5]

#define ADC_CFG1_ADLSMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)

ADLSMP - Sample Time Configuration 0b0..Short sample time. 0b1..Long sample time.

ADC_CFG1_ADLSMP [5/5]

#define ADC_CFG1_ADLSMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)

ADLSMP - Sample Time Configuration 0b0..Short sample time. 0b1..Long sample time.

ADC_CFG1_MODE [1/6]

#define ADC_CFG1_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)

MODE - Conversion mode selection 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output

ADC_CFG1_MODE [2/6]

#define ADC_CFG1_MODE

(

x

)

(((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)

MODE - Conversion mode selection 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output

ADC_CFG1_MODE [3/6]

#define ADC_CFG1_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)

MODE - Conversion mode selection 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output

ADC_CFG1_MODE [4/6]

#define ADC_CFG1_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)

MODE - Conversion mode selection 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output

ADC_CFG1_MODE [5/6]

#define ADC_CFG1_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)

MODE - Conversion mode selection 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output

ADC_CFG1_MODE [6/6]

#define ADC_CFG1_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)

MODE - Conversion mode selection 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output

ADC_CFG2_ADACKEN [1/5]

#define ADC_CFG2_ADACKEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)

ADACKEN - Asynchronous Clock Output Enable 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.

ADC_CFG2_ADACKEN [2/5]

#define ADC_CFG2_ADACKEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)

ADACKEN - Asynchronous Clock Output Enable 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.

ADC_CFG2_ADACKEN [3/5]

#define ADC_CFG2_ADACKEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)

ADACKEN - Asynchronous Clock Output Enable 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.

ADC_CFG2_ADACKEN [4/5]

#define ADC_CFG2_ADACKEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)

ADACKEN - Asynchronous Clock Output Enable 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.

ADC_CFG2_ADACKEN [5/5]

#define ADC_CFG2_ADACKEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)

ADACKEN - Asynchronous Clock Output Enable 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.

ADC_CFG2_ADHSC [1/5]

#define ADC_CFG2_ADHSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)

ADHSC - High-Speed Configuration 0b0..Normal conversion sequence selected. 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.

ADC_CFG2_ADHSC [2/5]

#define ADC_CFG2_ADHSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)

ADHSC - High-Speed Configuration 0b0..Normal conversion sequence selected. 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.

ADC_CFG2_ADHSC [3/5]

#define ADC_CFG2_ADHSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)

ADHSC - High-Speed Configuration 0b0..Normal conversion sequence selected. 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.

ADC_CFG2_ADHSC [4/5]

#define ADC_CFG2_ADHSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)

ADHSC - High-Speed Configuration 0b0..Normal conversion sequence selected. 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.

ADC_CFG2_ADHSC [5/5]

#define ADC_CFG2_ADHSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)

ADHSC - High-Speed Configuration 0b0..Normal conversion sequence selected. 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.

ADC_CFG2_ADLSTS [1/6]

#define ADC_CFG2_ADLSTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)

ADLSTS - Long Sample Time Select 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time. 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time. 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.

ADC_CFG2_ADLSTS [2/6]

#define ADC_CFG2_ADLSTS

(

x

)

(((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)

ADLSTS - Long Sample Time Select 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time. 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time. 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.

ADC_CFG2_ADLSTS [3/6]

#define ADC_CFG2_ADLSTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)

ADLSTS - Long Sample Time Select 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time. 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time. 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.

ADC_CFG2_ADLSTS [4/6]

#define ADC_CFG2_ADLSTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)

ADLSTS - Long Sample Time Select 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time. 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time. 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.

ADC_CFG2_ADLSTS [5/6]

#define ADC_CFG2_ADLSTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)

ADLSTS - Long Sample Time Select 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time. 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time. 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.

ADC_CFG2_ADLSTS [6/6]

#define ADC_CFG2_ADLSTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)

ADLSTS - Long Sample Time Select 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time. 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time. 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.

ADC_CFG2_MUXSEL [1/5]

#define ADC_CFG2_MUXSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)

MUXSEL - ADC Mux Select 0b0..ADxxa channels are selected. 0b1..ADxxb channels are selected.

ADC_CFG2_MUXSEL [2/5]

#define ADC_CFG2_MUXSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)

MUXSEL - ADC Mux Select 0b0..ADxxa channels are selected. 0b1..ADxxb channels are selected.

ADC_CFG2_MUXSEL [3/5]

#define ADC_CFG2_MUXSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)

MUXSEL - ADC Mux Select 0b0..ADxxa channels are selected. 0b1..ADxxb channels are selected.

ADC_CFG2_MUXSEL [4/5]

#define ADC_CFG2_MUXSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)

MUXSEL - ADC Mux Select 0b0..ADxxa channels are selected. 0b1..ADxxb channels are selected.

ADC_CFG2_MUXSEL [5/5]

#define ADC_CFG2_MUXSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)

MUXSEL - ADC Mux Select 0b0..ADxxa channels are selected. 0b1..ADxxb channels are selected.

ADC_IRQS

#define ADC_IRQS   { ADC0_IRQn, ADC1_IRQn }

Interrupt vectors for the ADC peripheral type

ADC_SC1_ADCH [1/6]

#define ADC_SC1_ADCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)

ADCH - Input channel select 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. 0b11000..Reserved. 0b11001..Reserved. 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. 0b11100..Reserved. 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. 0b11111..Module is disabled.

ADC_SC1_ADCH [2/6]

#define ADC_SC1_ADCH

(

x

)

(((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)

ADCH - Input channel select 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. 0b11000..Reserved. 0b11001..Reserved. 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. 0b11100..Reserved. 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. 0b11111..Module is disabled.

ADC_SC1_ADCH [3/6]

#define ADC_SC1_ADCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)

ADCH - Input channel select 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. 0b11000..Reserved. 0b11001..Reserved. 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. 0b11100..Reserved. 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. 0b11111..Module is disabled.

ADC_SC1_ADCH [4/6]

#define ADC_SC1_ADCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)

ADCH - Input channel select 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. 0b11000..Reserved. 0b11001..Reserved. 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. 0b11100..Reserved. 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. 0b11111..Module is disabled.

ADC_SC1_ADCH [5/6]

#define ADC_SC1_ADCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)

ADCH - Input channel select 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. 0b11000..Reserved. 0b11001..Reserved. 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. 0b11100..Reserved. 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. 0b11111..Module is disabled.

ADC_SC1_ADCH [6/6]

#define ADC_SC1_ADCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)

ADCH - Input channel select 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. 0b11000..Reserved. 0b11001..Reserved. 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. 0b11100..Reserved. 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. 0b11111..Module is disabled.

ADC_SC1_AIEN [1/5]

#define ADC_SC1_AIEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)

AIEN - Interrupt Enable 0b0..Conversion complete interrupt is disabled. 0b1..Conversion complete interrupt is enabled.

ADC_SC1_AIEN [2/5]

#define ADC_SC1_AIEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)

AIEN - Interrupt Enable 0b0..Conversion complete interrupt is disabled. 0b1..Conversion complete interrupt is enabled.

ADC_SC1_AIEN [3/5]

#define ADC_SC1_AIEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)

AIEN - Interrupt Enable 0b0..Conversion complete interrupt is disabled. 0b1..Conversion complete interrupt is enabled.

ADC_SC1_AIEN [4/5]

#define ADC_SC1_AIEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)

AIEN - Interrupt Enable 0b0..Conversion complete interrupt is disabled. 0b1..Conversion complete interrupt is enabled.

ADC_SC1_AIEN [5/5]

#define ADC_SC1_AIEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)

AIEN - Interrupt Enable 0b0..Conversion complete interrupt is disabled. 0b1..Conversion complete interrupt is enabled.

ADC_SC1_COCO [1/5]

#define ADC_SC1_COCO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)

COCO - Conversion Complete Flag 0b0..Conversion is not completed. 0b1..Conversion is completed.

ADC_SC1_COCO [2/5]

#define ADC_SC1_COCO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)

COCO - Conversion Complete Flag 0b0..Conversion is not completed. 0b1..Conversion is completed.

ADC_SC1_COCO [3/5]

#define ADC_SC1_COCO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)

COCO - Conversion Complete Flag 0b0..Conversion is not completed. 0b1..Conversion is completed.

ADC_SC1_COCO [4/5]

#define ADC_SC1_COCO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)

COCO - Conversion Complete Flag 0b0..Conversion is not completed. 0b1..Conversion is completed.

ADC_SC1_COCO [5/5]

#define ADC_SC1_COCO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)

COCO - Conversion Complete Flag 0b0..Conversion is not completed. 0b1..Conversion is completed.

ADC_SC1_DIFF [1/5]

#define ADC_SC1_DIFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)

DIFF - Differential Mode Enable 0b0..Single-ended conversions and input channels are selected. 0b1..Differential conversions and input channels are selected.

ADC_SC1_DIFF [2/5]

#define ADC_SC1_DIFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)

DIFF - Differential Mode Enable 0b0..Single-ended conversions and input channels are selected. 0b1..Differential conversions and input channels are selected.

ADC_SC1_DIFF [3/5]

#define ADC_SC1_DIFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)

DIFF - Differential Mode Enable 0b0..Single-ended conversions and input channels are selected. 0b1..Differential conversions and input channels are selected.

ADC_SC1_DIFF [4/5]

#define ADC_SC1_DIFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)

DIFF - Differential Mode Enable 0b0..Single-ended conversions and input channels are selected. 0b1..Differential conversions and input channels are selected.

ADC_SC1_DIFF [5/5]

#define ADC_SC1_DIFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)

DIFF - Differential Mode Enable 0b0..Single-ended conversions and input channels are selected. 0b1..Differential conversions and input channels are selected.

ADC_SC2_ACFE [1/5]

#define ADC_SC2_ACFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)

ACFE - Compare Function Enable 0b0..Compare function disabled. 0b1..Compare function enabled.

ADC_SC2_ACFE [2/5]

#define ADC_SC2_ACFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)

ACFE - Compare Function Enable 0b0..Compare function disabled. 0b1..Compare function enabled.

ADC_SC2_ACFE [3/5]

#define ADC_SC2_ACFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)

ACFE - Compare Function Enable 0b0..Compare function disabled. 0b1..Compare function enabled.

ADC_SC2_ACFE [4/5]

#define ADC_SC2_ACFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)

ACFE - Compare Function Enable 0b0..Compare function disabled. 0b1..Compare function enabled.

ADC_SC2_ACFE [5/5]

#define ADC_SC2_ACFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)

ACFE - Compare Function Enable 0b0..Compare function disabled. 0b1..Compare function enabled.

ADC_SC2_ACFGT [1/5]

#define ADC_SC2_ACFGT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)

ACFGT - Compare Function Greater Than Enable 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.

ADC_SC2_ACFGT [2/5]

#define ADC_SC2_ACFGT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)

ACFGT - Compare Function Greater Than Enable 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.

ADC_SC2_ACFGT [3/5]

#define ADC_SC2_ACFGT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)

ACFGT - Compare Function Greater Than Enable 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.

ADC_SC2_ACFGT [4/5]

#define ADC_SC2_ACFGT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)

ACFGT - Compare Function Greater Than Enable 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.

ADC_SC2_ACFGT [5/5]

#define ADC_SC2_ACFGT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)

ACFGT - Compare Function Greater Than Enable 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.

ADC_SC2_ACREN [1/5]

#define ADC_SC2_ACREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)

ACREN - Compare Function Range Enable 0b0..Range function disabled. Only CV1 is compared. 0b1..Range function enabled. Both CV1 and CV2 are compared.

ADC_SC2_ACREN [2/5]

#define ADC_SC2_ACREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)

ACREN - Compare Function Range Enable 0b0..Range function disabled. Only CV1 is compared. 0b1..Range function enabled. Both CV1 and CV2 are compared.

ADC_SC2_ACREN [3/5]

#define ADC_SC2_ACREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)

ACREN - Compare Function Range Enable 0b0..Range function disabled. Only CV1 is compared. 0b1..Range function enabled. Both CV1 and CV2 are compared.

ADC_SC2_ACREN [4/5]

#define ADC_SC2_ACREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)

ACREN - Compare Function Range Enable 0b0..Range function disabled. Only CV1 is compared. 0b1..Range function enabled. Both CV1 and CV2 are compared.

ADC_SC2_ACREN [5/5]

#define ADC_SC2_ACREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)

ACREN - Compare Function Range Enable 0b0..Range function disabled. Only CV1 is compared. 0b1..Range function enabled. Both CV1 and CV2 are compared.

ADC_SC2_ADACT [1/5]

#define ADC_SC2_ADACT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)

ADACT - Conversion Active 0b0..Conversion not in progress. 0b1..Conversion in progress.

ADC_SC2_ADACT [2/5]

#define ADC_SC2_ADACT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)

ADACT - Conversion Active 0b0..Conversion not in progress. 0b1..Conversion in progress.

ADC_SC2_ADACT [3/5]

#define ADC_SC2_ADACT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)

ADACT - Conversion Active 0b0..Conversion not in progress. 0b1..Conversion in progress.

ADC_SC2_ADACT [4/5]

#define ADC_SC2_ADACT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)

ADACT - Conversion Active 0b0..Conversion not in progress. 0b1..Conversion in progress.

ADC_SC2_ADACT [5/5]

#define ADC_SC2_ADACT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)

ADACT - Conversion Active 0b0..Conversion not in progress. 0b1..Conversion in progress.

ADC_SC2_ADTRG [1/5]

#define ADC_SC2_ADTRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)

ADTRG - Conversion Trigger Select 0b0..Software trigger selected. 0b1..Hardware trigger selected.

ADC_SC2_ADTRG [2/5]

#define ADC_SC2_ADTRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)

ADTRG - Conversion Trigger Select 0b0..Software trigger selected. 0b1..Hardware trigger selected.

ADC_SC2_ADTRG [3/5]

#define ADC_SC2_ADTRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)

ADTRG - Conversion Trigger Select 0b0..Software trigger selected. 0b1..Hardware trigger selected.

ADC_SC2_ADTRG [4/5]

#define ADC_SC2_ADTRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)

ADTRG - Conversion Trigger Select 0b0..Software trigger selected. 0b1..Hardware trigger selected.

ADC_SC2_ADTRG [5/5]

#define ADC_SC2_ADTRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)

ADTRG - Conversion Trigger Select 0b0..Software trigger selected. 0b1..Hardware trigger selected.

ADC_SC2_DMAEN [1/5]

#define ADC_SC2_DMAEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)

DMAEN - DMA Enable 0b0..DMA is disabled. 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.

ADC_SC2_DMAEN [2/5]

#define ADC_SC2_DMAEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)

DMAEN - DMA Enable 0b0..DMA is disabled. 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.

ADC_SC2_DMAEN [3/5]

#define ADC_SC2_DMAEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)

DMAEN - DMA Enable 0b0..DMA is disabled. 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.

ADC_SC2_DMAEN [4/5]

#define ADC_SC2_DMAEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)

DMAEN - DMA Enable 0b0..DMA is disabled. 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.

ADC_SC2_DMAEN [5/5]

#define ADC_SC2_DMAEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)

DMAEN - DMA Enable 0b0..DMA is disabled. 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.

ADC_SC2_REFSEL [1/6]

#define ADC_SC2_REFSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)

REFSEL - Voltage Reference Selection 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU 0b10..Reserved 0b11..Reserved

ADC_SC2_REFSEL [2/6]

#define ADC_SC2_REFSEL

(

x

)

(((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)

REFSEL - Voltage Reference Selection 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU 0b10..Reserved 0b11..Reserved

ADC_SC2_REFSEL [3/6]

#define ADC_SC2_REFSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)

REFSEL - Voltage Reference Selection 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU 0b10..Reserved 0b11..Reserved

ADC_SC2_REFSEL [4/6]

#define ADC_SC2_REFSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)

REFSEL - Voltage Reference Selection 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU 0b10..Reserved 0b11..Reserved

ADC_SC2_REFSEL [5/6]

#define ADC_SC2_REFSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)

REFSEL - Voltage Reference Selection 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU 0b10..Reserved 0b11..Reserved

ADC_SC2_REFSEL [6/6]

#define ADC_SC2_REFSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)

REFSEL - Voltage Reference Selection 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU 0b10..Reserved 0b11..Reserved

ADC_SC3_ADCO [1/5]

#define ADC_SC3_ADCO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)

ADCO - Continuous Conversion Enable 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.

ADC_SC3_ADCO [2/5]

#define ADC_SC3_ADCO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)

ADCO - Continuous Conversion Enable 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.

ADC_SC3_ADCO [3/5]

#define ADC_SC3_ADCO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)

ADCO - Continuous Conversion Enable 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.

ADC_SC3_ADCO [4/5]

#define ADC_SC3_ADCO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)

ADCO - Continuous Conversion Enable 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.

ADC_SC3_ADCO [5/5]

#define ADC_SC3_ADCO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)

ADCO - Continuous Conversion Enable 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.

ADC_SC3_AVGE [1/5]

#define ADC_SC3_AVGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)

AVGE - Hardware Average Enable 0b0..Hardware average function disabled. 0b1..Hardware average function enabled.

ADC_SC3_AVGE [2/5]

#define ADC_SC3_AVGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)

AVGE - Hardware Average Enable 0b0..Hardware average function disabled. 0b1..Hardware average function enabled.

ADC_SC3_AVGE [3/5]

#define ADC_SC3_AVGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)

AVGE - Hardware Average Enable 0b0..Hardware average function disabled. 0b1..Hardware average function enabled.

ADC_SC3_AVGE [4/5]

#define ADC_SC3_AVGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)

AVGE - Hardware Average Enable 0b0..Hardware average function disabled. 0b1..Hardware average function enabled.

ADC_SC3_AVGE [5/5]

#define ADC_SC3_AVGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)

AVGE - Hardware Average Enable 0b0..Hardware average function disabled. 0b1..Hardware average function enabled.

ADC_SC3_AVGS [1/6]

#define ADC_SC3_AVGS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)

AVGS - Hardware Average Select 0b00..4 samples averaged. 0b01..8 samples averaged. 0b10..16 samples averaged. 0b11..32 samples averaged.

ADC_SC3_AVGS [2/6]

#define ADC_SC3_AVGS

(

x

)

(((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)

AVGS - Hardware Average Select 0b00..4 samples averaged. 0b01..8 samples averaged. 0b10..16 samples averaged. 0b11..32 samples averaged.

ADC_SC3_AVGS [3/6]

#define ADC_SC3_AVGS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)

AVGS - Hardware Average Select 0b00..4 samples averaged. 0b01..8 samples averaged. 0b10..16 samples averaged. 0b11..32 samples averaged.

ADC_SC3_AVGS [4/6]

#define ADC_SC3_AVGS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)

AVGS - Hardware Average Select 0b00..4 samples averaged. 0b01..8 samples averaged. 0b10..16 samples averaged. 0b11..32 samples averaged.

ADC_SC3_AVGS [5/6]

#define ADC_SC3_AVGS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)

AVGS - Hardware Average Select 0b00..4 samples averaged. 0b01..8 samples averaged. 0b10..16 samples averaged. 0b11..32 samples averaged.

ADC_SC3_AVGS [6/6]

#define ADC_SC3_AVGS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)

AVGS - Hardware Average Select 0b00..4 samples averaged. 0b01..8 samples averaged. 0b10..16 samples averaged. 0b11..32 samples averaged.

ADC_SC3_CALF [1/5]

#define ADC_SC3_CALF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)

CALF - Calibration Failed Flag 0b0..Calibration completed normally. 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.

ADC_SC3_CALF [2/5]

#define ADC_SC3_CALF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)

CALF - Calibration Failed Flag 0b0..Calibration completed normally. 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.

ADC_SC3_CALF [3/5]

#define ADC_SC3_CALF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)

CALF - Calibration Failed Flag 0b0..Calibration completed normally. 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.

ADC_SC3_CALF [4/5]

#define ADC_SC3_CALF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)

CALF - Calibration Failed Flag 0b0..Calibration completed normally. 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.

ADC_SC3_CALF [5/5]

#define ADC_SC3_CALF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)

CALF - Calibration Failed Flag 0b0..Calibration completed normally. 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.