|
mikroSDK Reference Manual
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Topics | |
| Edma_request | |
| Device Peripheral Access Layer | |
| __IO uint32_t SDRAM_Type::AC |
Address and Control Register, array offset: 0x48, array step: 0x8
| __IO uint32_t { ... } ::AC |
Address and Control Register, array offset: 0x48, array step: 0x8
| __IO uint32_t { ... } ::AC |
Address and Control Register, array offset: 0x48, array step: 0x8
| __IO uint32_t SIM_Type::ADCOPT |
ADC Additional Option Register, offset: 0x1108
| __IO uint32_t USBPHY_Type::ANACTRL |
USB PHY Analog Control Register, offset: 0x100
| __IO uint32_t USBPHY_Type::ANACTRL_CLR |
USB PHY Analog Control Register, offset: 0x108
| __IO uint32_t USBPHY_Type::ANACTRL_SET |
USB PHY Analog Control Register, offset: 0x104
| __IO uint32_t USBPHY_Type::ANACTRL_TOG |
USB PHY Analog Control Register, offset: 0x10C
| __IO uint8_t UART_Type::AP7816A_T0 |
UART 7816 ATR Duration Timer Register A, offset: 0x3A
| __IO uint8_t UART_Type::AP7816B_T0 |
UART 7816 ATR Duration Timer Register B, offset: 0x3B
| __IO uint32_t { ... } ::ASYNCLISTADDR |
Current Asynchronous List Address Register, offset: 0x158
| __IO uint32_t USBHS_Type::ASYNCLISTADDR |
Current Asynchronous List Address Register, offset: 0x158
| __IO uint32_t { ... } ::ASYNCLISTADDR |
Current Asynchronous List Address Register, offset: 0x158
| __I uint32_t ENET_Type::ATSTMP |
Timestamp of Last Transmitted Frame, offset: 0x418
| __IO uint16_t { ... } ::ATTR |
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
| __IO uint16_t { ... } ::ATTR |
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
| __IO uint16_t { ... } ::ATTR |
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
| __IO uint16_t { ... } ::ATTR |
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
| __IO uint32_t LPUART_Type::BAUD |
LPUART Baud Rate Register, offset: 0x0
| __IO uint16_t AOI_Type::BFCRT01 |
Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4
| __IO uint16_t { ... } ::BFCRT01 |
Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4
| __IO uint16_t AOI_Type::BFCRT23 |
Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4
| __IO uint16_t { ... } ::BFCRT23 |
Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4
| __IO uint16_t { ... } ::BITER_ELINKNO |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKNO |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKNO |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKNO |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKYES |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKYES |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKYES |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKYES |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20
| __IO uint32_t USBHS_Type::BURSTSIZE |
Master Interface Data Burst Size Register, offset: 0x160
| __IO uint32_t { ... } ::C1 |
Channel n Control register 1, array offset: 0x10, array step: 0x28
| __IO uint32_t { ... } ::C1 |
Channel n Control register 1, array offset: 0x10, array step: 0x28
| __IO uint32_t { ... } ::C1 |
Channel n Control register 1, array offset: 0x10, array step: 0x28
| __IO uint32_t { ... } ::C1 |
Channel n Control register 1, array offset: 0x10, array step: 0x28
| __IO uint8_t MCG_Type::C11 |
MCG Control 11 Register, offset: 0x10
| __IO uint8_t MCG_Type::C9 |
MCG Control 9 Register, offset: 0xE
| __IO uint16_t HSADC_Type::CALIB |
HSADCs Calibration Configuration, offset: 0xAE
| __IO uint16_t HSADC_Type::CALVAL_A |
Calibration Values for ADCA Register, offset: 0xB0
| __IO uint16_t HSADC_Type::CALVAL_B |
Calibration Values for ADCB Register, offset: 0xB2
| __IO uint16_t { ... } ::CAPTCOMPA |
Capture Compare A Register, array offset: 0x36, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCOMPA |
Capture Compare A Register, array offset: 0x36, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCOMPB |
Capture Compare B Register, array offset: 0x3A, array step: 0x60
| __IO uint16_t { ... } ::CAPTCOMPB |
Capture Compare B Register, array offset: 0x3A, array step: 0x60
| __IO uint16_t { ... } ::CAPTCOMPX |
Capture Compare X Register, array offset: 0x3E, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCOMPX |
Capture Compare X Register, array offset: 0x3E, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLA |
Capture Control A Register, array offset: 0x34, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCTRLA |
Capture Control A Register, array offset: 0x34, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCTRLB |
Capture Control B Register, array offset: 0x38, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLB |
Capture Control B Register, array offset: 0x38, array step: 0x60
| __IO uint16_t PWM_Type::CAPTCTRLX |
Capture Control X Register, array offset: 0x3C, array step: 0x60
| __IO uint16_t { ... } ::CAPTCTRLX |
Capture Control X Register, array offset: 0x3C, array step: 0x60
| __IO uint32_t CAN_Type::CBT |
CAN Bit Timing Register, offset: 0x50
| __I uint32_t MSCM_Type::CFG1 |
Processor 0 Configuration 1 Register..Processor 1 Configuration 1 Register, array offset: 0x34, array step: 0x20
| __I uint32_t { ... } ::CFG1 |
Processor 0 Configuration 1 Register..Processor 1 Configuration 1 Register, array offset: 0x34, array step: 0x20
| __I uint32_t { ... } ::CFG3 |
Processor 0 Configuration 3 Register..Processor 1 Configuration 3 Register, array offset: 0x3C, array step: 0x20
| __I uint32_t MSCM_Type::CFG3 |
Processor 0 Configuration 3 Register..Processor 1 Configuration 3 Register, array offset: 0x3C, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKNO |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKNO |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKNO |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKNO |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKYES |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKYES |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKYES |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKYES |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t HSADC_Type::CLIST1 |
HSADC Channel List Register 1, offset: 0x8
| __IO uint16_t HSADC_Type::CLIST2 |
HSADC Channel List Register 2, offset: 0xA
| __IO uint16_t HSADC_Type::CLIST3 |
HSADC Channel List Register 3, offset: 0xC
| __IO uint16_t HSADC_Type::CLIST4 |
HSADC Channel List Register 4, offset: 0xE
| __IO uint8_t USB_Type::CLK_RECOVER_CTRL |
USB Clock recovery control, offset: 0x140
| __IO uint8_t USB_Type::CLK_RECOVER_INT_EN |
Clock recovery combined interrupt enable, offset: 0x154
| __IO uint8_t USB_Type::CLK_RECOVER_INT_STATUS |
Clock recovery separated interrupt status, offset: 0x15C
| __IO uint8_t USB_Type::CLK_RECOVER_IRC_EN |
IRC48M oscillator enable register, offset: 0x144
| __IO uint8_t EWM_Type::CLKCTRL |
Clock Control Register, offset: 0x4
| __IO uint32_t SIM_Type::CLKDIV3 |
System Clock Divider Register 3, offset: 0x1064
| __IO uint32_t SIM_Type::CLKDIV4 |
System Clock Divider Register 4, offset: 0x1068
| __IO uint32_t USBHSDCD_Type::CLOCK |
Clock register, offset: 0x4
| __IO uint32_t SDRAM_Type::CM |
Control Mask, array offset: 0x4C, array step: 0x8
| __IO uint32_t { ... } ::CM |
Control Mask, array offset: 0x4C, array step: 0x8
| __IO uint32_t { ... } ::CM |
Control Mask, array offset: 0x4C, array step: 0x8
| __IO uint32_t { ... } ::CnSC |
Channel (n) Status And Control, array offset: 0xC, array step: 0x8
| __IO uint32_t { ... } ::CnSC |
Channel (n) Status And Control, array offset: 0xC, array step: 0x8
| __IO uint32_t { ... } ::CnSC |
Channel (n) Status and Control, array offset: 0xC, array step: 0x8
| __IO uint32_t TPM_Type::CnSC |
Channel (n) Status and Control, array offset: 0xC, array step: 0x8
| __IO uint32_t { ... } ::CnSC |
Channel (n) Status And Control, array offset: 0xC, array step: 0x8
| __IO uint32_t { ... } ::CnSC |
Channel (n) Status and Control, array offset: 0xC, array step: 0x8
| __IO uint32_t { ... } ::CnSC |
Channel (n) Status And Control, array offset: 0xC, array step: 0x8
| __IO uint32_t TPM_Type::CNT |
Counter, offset: 0x4
| __I uint16_t { ... } ::CNT |
Counter Register, array offset: 0x0, array step: 0x60
| __I uint16_t PWM_Type::CNT |
Counter Register, array offset: 0x0, array step: 0x60
| __IO uint32_t { ... } ::CnV |
Channel (n) Value, array offset: 0x10, array step: 0x8
| __IO uint32_t { ... } ::CnV |
Channel (n) Value, array offset: 0x10, array step: 0x8
| __IO uint32_t TPM_Type::CnV |
Channel (n) Value, array offset: 0x10, array step: 0x8
| __IO uint32_t { ... } ::CnV |
Channel (n) Value, array offset: 0x10, array step: 0x8
| __IO uint32_t { ... } ::CnV |
Channel (n) Value, array offset: 0x10, array step: 0x8
| __IO uint32_t { ... } ::CnV |
Channel (n) Value, array offset: 0x10, array step: 0x8
| __IO uint32_t { ... } ::CnV |
Channel (n) Value, array offset: 0x10, array step: 0x8
| __IO uint32_t TPM_Type::COMBINE |
Combine Channel Register, offset: 0x64
| __IO uint32_t TPM_Type::CONF |
Configuration, offset: 0x84
| uint32_t USBHS_Type::CONFIGFLAG |
Configure Flag Register, offset: 0x180
| __IO uint32_t USBHSDCD_Type::CONTROL |
Control register, offset: 0x0
| __I uint32_t MSCM_Type::COUNT |
Processor 0 Count Register..Processor 1 Count Register, array offset: 0x2C, array step: 0x20
| __I uint32_t { ... } ::COUNT |
Processor 0 Count Register..Processor 1 Count Register, array offset: 0x2C, array step: 0x20
| __IO uint32_t MCM_Type::CPO |
Compute Operation Control Register, offset: 0x40
Compute Only Operation Control Register, offset: 0x34
| __I uint32_t MSCM_Type::CPxCFG1 |
Processor X Configuration 1 Register, offset: 0x14
| __I uint32_t MSCM_Type::CPxCFG3 |
Processor X Configuration 3 Register, offset: 0x1C
| __I uint32_t MSCM_Type::CPxCOUNT |
Processor X Count Register, offset: 0xC
| __I uint32_t MSCM_Type::CPxMASTER |
Processor X Master Register, offset: 0x8
| __I uint32_t MSCM_Type::CPxNUM |
Processor X Number Register, offset: 0x4
| __I uint32_t MSCM_Type::CPxTYPE |
Processor X Type Register, offset: 0x0
| __IO uint32_t { ... } ::CRS |
Control Register, array offset: 0x10, array step: 0x100
| __IO uint32_t { ... } ::CRS |
Control Register, array offset: 0x10, array step: 0x100
| __IO uint32_t { ... } ::CRS |
Control Register, array offset: 0x10, array step: 0x100
| __IO uint32_t { ... } ::CRS |
Control Register, array offset: 0x10, array step: 0x100
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10
| __IO uint32_t { ... } ::CSAR |
Chip Select Address Register, array offset: 0x0, array step: 0xC
| __IO uint32_t { ... } ::CSAR |
Chip Select Address Register, array offset: 0x0, array step: 0xC
| __IO uint32_t { ... } ::CSAR |
Chip Select Address Register, array offset: 0x0, array step: 0xC
| __IO uint32_t { ... } ::CSAR |
Chip Select Address Register, array offset: 0x0, array step: 0xC
| __IO uint32_t { ... } ::CSCR |
Chip Select Control Register, array offset: 0x8, array step: 0xC
| __IO uint32_t { ... } ::CSCR |
Chip Select Control Register, array offset: 0x8, array step: 0xC
| __IO uint32_t { ... } ::CSCR |
Chip Select Control Register, array offset: 0x8, array step: 0xC
| __IO uint32_t { ... } ::CSCR |
Chip Select Control Register, array offset: 0x8, array step: 0xC
| __IO uint32_t { ... } ::CSMR |
Chip Select Mask Register, array offset: 0x4, array step: 0xC
| __IO uint32_t { ... } ::CSMR |
Chip Select Mask Register, array offset: 0x4, array step: 0xC
| __IO uint32_t { ... } ::CSMR |
Chip Select Mask Register, array offset: 0x4, array step: 0xC
| __IO uint32_t { ... } ::CSMR |
Chip Select Mask Register, array offset: 0x4, array step: 0xC
| __IO uint16_t { ... } ::CSR |
TCD Control and Status, array offset: 0x101C, array step: 0x20
| __IO uint16_t { ... } ::CSR |
TCD Control and Status, array offset: 0x101C, array step: 0x20
| __IO uint16_t { ... } ::CSR |
TCD Control and Status, array offset: 0x101C, array step: 0x20
| __IO uint16_t { ... } ::CSR |
TCD Control and Status, array offset: 0x101C, array step: 0x20
| __IO uint32_t { ... } ::CTAR[2] |
Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4
| __IO uint32_t { ... } ::CTAR[2] |
Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4
| __IO uint32_t { ... } ::CTAR[2] |
Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4
| __IO uint32_t { ... } ::CTAR[2] |
Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4
| __IO uint32_t { ... } ::CTAR_SLAVE[1] |
Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4
| __IO uint32_t { ... } ::CTAR_SLAVE[1] |
Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4
| __IO uint32_t { ... } ::CTAR_SLAVE[1] |
Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4
| __IO uint32_t { ... } ::CTAR_SLAVE[1] |
Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4
| __IO uint32_t { ... } ::CTRL |
CRC Control register, offset: 0x8
| __IO uint32_t { ... } ::CTRL |
CRC Control register, offset: 0x8
| __IO uint32_t LPUART_Type::CTRL |
LPUART Control Register, offset: 0x8
| __IO uint16_t SDRAM_Type::CTRL |
Control Register, offset: 0x42
| __IO uint32_t USBPHY_Type::CTRL |
USB PHY General Control Register, offset: 0x30
| __IO uint32_t { ... } ::CTRL |
CRC Control register, offset: 0x8
| __IO uint32_t { ... } ::CTRL |
CRC Control register, offset: 0x8
| __IO uint16_t ENC_Type::CTRL |
Control Register, offset: 0x0
| __IO uint16_t PWM_Type::CTRL |
Control Register, array offset: 0x6, array step: 0x60
| __IO uint16_t { ... } ::CTRL |
Control Register, array offset: 0x6, array step: 0x60
| __IO uint16_t XBARA_Type::CTRL0 |
Crossbar A Control Register 0, offset: 0x3C
| __IO uint16_t HSADC_Type::CTRL1 |
HSADC Control Register 1, offset: 0x0
| __IO uint16_t XBARA_Type::CTRL1 |
Crossbar A Control Register 1, offset: 0x3E
| __IO uint16_t ENC_Type::CTRL2 |
Control 2 Register, offset: 0x1E
| __IO uint16_t HSADC_Type::CTRL2 |
HSADC Control Register 2, offset: 0x2
| __IO uint16_t { ... } ::CTRL2 |
Control 2 Register, array offset: 0x4, array step: 0x60
| __IO uint16_t PWM_Type::CTRL2 |
Control 2 Register, array offset: 0x4, array step: 0x60
| __IO uint16_t HSADC_Type::CTRL3 |
HSADC Control Register 3, offset: 0xA8
| __IO uint32_t USBPHY_Type::CTRL_CLR |
USB PHY General Control Register, offset: 0x38
| __IO uint32_t USBPHY_Type::CTRL_SET |
USB PHY General Control Register, offset: 0x34
| __IO uint32_t USBPHY_Type::CTRL_TOG |
USB PHY General Control Register, offset: 0x3C
| __IO uint8_t { ... } ::CTRLHU |
CRC_CTRLHU register., offset: 0xB
| __IO uint8_t { ... } ::CTRLHU |
CRC_CTRLHU register., offset: 0xB
| __IO uint8_t { ... } ::CTRLHU |
CRC_CTRLHU register., offset: 0xB
| __IO uint8_t { ... } ::CTRLHU |
CRC_CTRLHU register., offset: 0xB
| __I uint32_t { ... } ::CVAL |
Current Timer Value Register, array offset: 0x104, array step: 0x10
| __I uint32_t { ... } ::CVAL |
Current Timer Value Register, array offset: 0x104, array step: 0x10
| __I uint32_t { ... } ::CVAL |
Current Timer Value Register, array offset: 0x104, array step: 0x10
| __I uint32_t { ... } ::CVAL |
Current Timer Value Register, array offset: 0x104, array step: 0x10
| __I uint16_t { ... } ::CVAL0 |
Capture Value 0 Register, array offset: 0x40, array step: 0x60
| __I uint16_t PWM_Type::CVAL0 |
Capture Value 0 Register, array offset: 0x40, array step: 0x60
| __I uint16_t { ... } ::CVAL0CYC |
Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60
| __I uint16_t PWM_Type::CVAL0CYC |
Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60
| __I uint16_t { ... } ::CVAL1 |
Capture Value 1 Register, array offset: 0x44, array step: 0x60
| __I uint16_t PWM_Type::CVAL1 |
Capture Value 1 Register, array offset: 0x44, array step: 0x60
| __I uint16_t { ... } ::CVAL1CYC |
Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60
| __I uint16_t PWM_Type::CVAL1CYC |
Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60
| __I uint16_t PWM_Type::CVAL2 |
Capture Value 2 Register, array offset: 0x48, array step: 0x60
| __I uint16_t { ... } ::CVAL2 |
Capture Value 2 Register, array offset: 0x48, array step: 0x60
| __I uint16_t { ... } ::CVAL2CYC |
Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60
| __I uint16_t PWM_Type::CVAL2CYC |
Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60
| __I uint16_t { ... } ::CVAL3 |
Capture Value 3 Register, array offset: 0x4C, array step: 0x60
| __I uint16_t PWM_Type::CVAL3 |
Capture Value 3 Register, array offset: 0x4C, array step: 0x60
| __I uint16_t { ... } ::CVAL3CYC |
Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60
| __I uint16_t PWM_Type::CVAL3CYC |
Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60
| __I uint16_t { ... } ::CVAL4 |
Capture Value 4 Register, array offset: 0x50, array step: 0x60
| __I uint16_t PWM_Type::CVAL4 |
Capture Value 4 Register, array offset: 0x50, array step: 0x60
| __I uint16_t PWM_Type::CVAL4CYC |
Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60
| __I uint16_t { ... } ::CVAL4CYC |
Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60
| __I uint16_t PWM_Type::CVAL5 |
Capture Value 5 Register, array offset: 0x54, array step: 0x60
| __I uint16_t { ... } ::CVAL5 |
Capture Value 5 Register, array offset: 0x54, array step: 0x60
| __I uint16_t PWM_Type::CVAL5CYC |
Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60
| __I uint16_t { ... } ::CVAL5CYC |
Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60
| __IO uint32_t { ... } ::DADDR |
TCD Destination Address, array offset: 0x1010, array step: 0x20
| __IO uint32_t { ... } ::DADDR |
TCD Destination Address, array offset: 0x1010, array step: 0x20
| __IO uint32_t { ... } ::DADDR |
TCD Destination Address, array offset: 0x1010, array step: 0x20
| __IO uint32_t { ... } ::DADDR |
TCD Destination Address, array offset: 0x1010, array step: 0x20
| __IO uint32_t CRC_Type::DATA |
CRC Data register, offset: 0x0
| __IO uint32_t { ... } ::DATA |
CRC Data register, offset: 0x0
| __IO uint32_t { ... } ::DATA |
CRC Data register, offset: 0x0
| __IO uint32_t LPUART_Type::DATA |
LPUART Data Register, offset: 0xC
| __IO uint32_t TSI_Type::DATA |
TSI DATA Register, offset: 0x4
| __IO uint32_t { ... } ::DATA |
CRC Data register, offset: 0x0
| __IO uint32_t { ... } ::DATA |
CRC Data register, offset: 0x0
| __IO uint32_t { ... } ::DATA_L |
Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8
| __IO uint32_t { ... } ::DATA_LM |
Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10
| __IO uint32_t FMC_Type::DATA_LM |
Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10
| __IO uint32_t { ... } ::DATA_LM |
Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10
| __IO uint32_t { ... } ::DATA_ML |
Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10
| __IO uint32_t FMC_Type::DATA_ML |
Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10
| __IO uint32_t { ... } ::DATA_ML |
Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10
| __IO uint32_t FMC_Type::DATA_MU |
Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10
| __IO uint32_t { ... } ::DATA_MU |
Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10
| __IO uint32_t { ... } ::DATA_MU |
Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10
| __IO uint32_t { ... } ::DATA_U |
Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8
| __IO uint32_t { ... } ::DATA_UM |
Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10
| __IO uint32_t FMC_Type::DATA_UM |
Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10
| __IO uint32_t { ... } ::DATA_UM |
Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10
| __IO uint16_t { ... } ::DATAH |
CRC_DATAH register., offset: 0x2
| __IO uint16_t CRC_Type::DATAH |
CRC_DATAH register., offset: 0x2
| __IO uint16_t { ... } ::DATAH |
CRC_DATAH register., offset: 0x2
| __IO uint16_t { ... } ::DATAH |
CRC_DATAH register., offset: 0x2
| __IO uint16_t { ... } ::DATAH |
CRC_DATAH register., offset: 0x2
| __IO uint8_t { ... } ::DATAHL |
CRC_DATAHL register., offset: 0x2
| __IO uint8_t CRC_Type::DATAHL |
CRC_DATAHL register., offset: 0x2
| __IO uint8_t { ... } ::DATAHL |
CRC_DATAHL register., offset: 0x2
| __IO uint8_t { ... } ::DATAHL |
CRC_DATAHL register., offset: 0x2
| __IO uint8_t { ... } ::DATAHL |
CRC_DATAHL register., offset: 0x2
| __IO uint8_t CRC_Type::DATAHU |
CRC_DATAHU register., offset: 0x3
| __IO uint8_t { ... } ::DATAHU |
CRC_DATAHU register., offset: 0x3
| __IO uint8_t { ... } ::DATAHU |
CRC_DATAHU register., offset: 0x3
| __IO uint8_t { ... } ::DATAHU |
CRC_DATAHU register., offset: 0x3
| __IO uint8_t { ... } ::DATAHU |
CRC_DATAHU register., offset: 0x3
| __IO uint16_t { ... } ::DATAL |
CRC_DATAL register., offset: 0x0
| __IO uint16_t CRC_Type::DATAL |
CRC_DATAL register., offset: 0x0
| __IO uint16_t { ... } ::DATAL |
CRC_DATAL register., offset: 0x0
| __IO uint16_t { ... } ::DATAL |
CRC_DATAL register., offset: 0x0
| __IO uint16_t { ... } ::DATAL |
CRC_DATAL register., offset: 0x0
| __IO uint8_t { ... } ::DATALL |
CRC_DATALL register., offset: 0x0
| __IO uint8_t CRC_Type::DATALL |
CRC_DATALL register., offset: 0x0
| __IO uint8_t { ... } ::DATALL |
CRC_DATALL register., offset: 0x0
| __IO uint8_t { ... } ::DATALL |
CRC_DATALL register., offset: 0x0
| __IO uint8_t { ... } ::DATALL |
CRC_DATALL register., offset: 0x0
| __IO uint8_t CRC_Type::DATALU |
CRC_DATALU register., offset: 0x1
| __IO uint8_t { ... } ::DATALU |
CRC_DATALU register., offset: 0x1
| __IO uint8_t { ... } ::DATALU |
CRC_DATALU register., offset: 0x1
| __IO uint8_t { ... } ::DATALU |
CRC_DATALU register., offset: 0x1
| __IO uint8_t { ... } ::DATALU |
CRC_DATALU register., offset: 0x1
| __IO uint8_t { ... } ::DATH |
DAC Data High Register, array offset: 0x1, array step: 0x2
| __IO uint8_t { ... } ::DATH |
DAC Data High Register, array offset: 0x1, array step: 0x2
| __IO uint8_t { ... } ::DATH |
DAC Data High Register, array offset: 0x1, array step: 0x2
| __IO uint8_t { ... } ::DATH |
DAC Data High Register, array offset: 0x1, array step: 0x2
| __IO uint8_t { ... } ::DATL |
DAC Data Low Register, array offset: 0x0, array step: 0x2
| __IO uint8_t { ... } ::DATL |
DAC Data Low Register, array offset: 0x0, array step: 0x2
| __IO uint8_t { ... } ::DATL |
DAC Data Low Register, array offset: 0x0, array step: 0x2
| __IO uint8_t { ... } ::DATL |
DAC Data Low Register, array offset: 0x0, array step: 0x2
| __I uint32_t USBHS_Type::DCCPARAMS |
Device Controller Capability Parameters, offset: 0x124
| __IO uint8_t DMA_Type::DCHPRI16 |
Channel n Priority Register, offset: 0x113
| __IO uint8_t DMA_Type::DCHPRI17 |
Channel n Priority Register, offset: 0x112
| __IO uint8_t DMA_Type::DCHPRI18 |
Channel n Priority Register, offset: 0x111
| __IO uint8_t DMA_Type::DCHPRI19 |
Channel n Priority Register, offset: 0x110
| __IO uint8_t DMA_Type::DCHPRI20 |
Channel n Priority Register, offset: 0x117
| __IO uint8_t DMA_Type::DCHPRI21 |
Channel n Priority Register, offset: 0x116
| __IO uint8_t DMA_Type::DCHPRI22 |
Channel n Priority Register, offset: 0x115
| __IO uint8_t DMA_Type::DCHPRI23 |
Channel n Priority Register, offset: 0x114
| __IO uint8_t DMA_Type::DCHPRI24 |
Channel n Priority Register, offset: 0x11B
| __IO uint8_t DMA_Type::DCHPRI25 |
Channel n Priority Register, offset: 0x11A
| __IO uint8_t DMA_Type::DCHPRI26 |
Channel n Priority Register, offset: 0x119
| __IO uint8_t DMA_Type::DCHPRI27 |
Channel n Priority Register, offset: 0x118
| __IO uint8_t DMA_Type::DCHPRI28 |
Channel n Priority Register, offset: 0x11F
| __IO uint8_t DMA_Type::DCHPRI29 |
Channel n Priority Register, offset: 0x11E
| __IO uint8_t DMA_Type::DCHPRI30 |
Channel n Priority Register, offset: 0x11D
| __IO uint8_t DMA_Type::DCHPRI31 |
Channel n Priority Register, offset: 0x11C
| __I uint16_t USBHS_Type::DCIVERSION |
Device Controller Interface Version, offset: 0x122
| __I uint32_t USBPHY_Type::DEBUG0_STATUS |
UTMI Debug Status Register 0, offset: 0x60
| __IO uint32_t USBPHY_Type::DEBUG1 |
UTMI Debug Status Register 1, offset: 0x70
| __IO uint32_t USBPHY_Type::DEBUG1_CLR |
UTMI Debug Status Register 1, offset: 0x78
| __IO uint32_t USBPHY_Type::DEBUG1_SET |
UTMI Debug Status Register 1, offset: 0x74
| __IO uint32_t USBPHY_Type::DEBUG1_TOG |
UTMI Debug Status Register 1, offset: 0x7C
| __IO uint32_t USBPHY_Type::DEBUG_CLR |
USB PHY Debug Register, offset: 0x58
| __IO uint32_t USBPHY_Type::DEBUG_SET |
USB PHY Debug Register, offset: 0x54
| __IO uint32_t USBPHY_Type::DEBUG_TOG |
USB PHY Debug Register, offset: 0x5C
| __IO uint32_t USBPHY_Type::DEBUGr |
USB PHY Debug Register, offset: 0x50
| __IO uint32_t USBHS_Type::DEVICEADDR |
Device Address Register, offset: 0x154
| __IO uint32_t { ... } ::DEVICEADDR |
Device Address Register, offset: 0x154
| __IO uint32_t { ... } ::DEVICEADDR |
Device Address Register, offset: 0x154
| __IO uint16_t PWM_Type::DISMAP[1] |
Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2
| __IO uint16_t { ... } ::DISMAP[1] |
Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2
| __IO uint8_t OSC_Type::DIV |
OSC_DIV, offset: 0x2
| __IO uint32_t { ... } ::DLAST_SGA |
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
| __IO uint32_t { ... } ::DLAST_SGA |
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
| __IO uint32_t { ... } ::DLAST_SGA |
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
| __IO uint32_t { ... } ::DLAST_SGA |
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
| __IO uint32_t { ... } ::DLY[2] |
Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4
| __IO uint32_t { ... } ::DLY[2] |
Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4
| __IO uint32_t { ... } ::DLY[2] |
Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4
| __IO uint32_t { ... } ::DLY[2] |
Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4
| __IO uint16_t PWM_Type::DMAEN |
DMA Enable Register, array offset: 0x28, array step: 0x60
| __IO uint16_t { ... } ::DMAEN |
DMA Enable Register, array offset: 0x28, array step: 0x60
| __IO uint16_t { ... } ::DOFF |
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
| __IO uint16_t { ... } ::DOFF |
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
| __IO uint16_t { ... } ::DOFF |
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
| __IO uint16_t { ... } ::DOFF |
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
| __IO uint16_t { ... } ::DTCNT0 |
Deadtime Count Register 0, array offset: 0x30, array step: 0x60
| __IO uint16_t PWM_Type::DTCNT0 |
Deadtime Count Register 0, array offset: 0x30, array step: 0x60
| __IO uint16_t PWM_Type::DTCNT1 |
Deadtime Count Register 1, array offset: 0x32, array step: 0x60
| __IO uint16_t { ... } ::DTCNT1 |
Deadtime Count Register 1, array offset: 0x32, array step: 0x60
| __IO uint16_t PWM_Type::DTSRCSEL |
PWM Source Select Register, offset: 0x186
| __I uint32_t { ... } ::EAR |
Error Address Register, slave port n, array offset: 0x10, array step: 0x8
| __I uint32_t { ... } ::EAR |
Error Address Register, slave port n, array offset: 0x10, array step: 0x8
| __I uint32_t { ... } ::EAR |
Error Address Register, slave port n, array offset: 0x10, array step: 0x8
| __I uint32_t { ... } ::EAR |
Error Address Register, slave port n, array offset: 0x10, array step: 0x8
| __IO uint32_t DMA_Type::EARS |
Enable Asynchronous Request in Stop Register, offset: 0x44
| __I uint32_t { ... } ::EDR |
Error Detail Register, slave port n, array offset: 0x14, array step: 0x8
| __I uint32_t { ... } ::EDR |
Error Detail Register, slave port n, array offset: 0x14, array step: 0x8
| __I uint32_t { ... } ::EDR |
Error Detail Register, slave port n, array offset: 0x14, array step: 0x8
| __I uint32_t { ... } ::EDR |
Error Detail Register, slave port n, array offset: 0x14, array step: 0x8
| __IO uint8_t { ... } ::ENDPT |
Endpoint Control register, array offset: 0xC0, array step: 0x4
| __IO uint8_t { ... } ::ENDPT |
Endpoint Control register, array offset: 0xC0, array step: 0x4
| __IO uint8_t { ... } ::ENDPT |
Endpoint Control register, array offset: 0xC0, array step: 0x4
| __IO uint32_t USBHS_Type::ENDPTNAK |
Endpoint NAK Register, offset: 0x178
| __IO uint32_t USBHS_Type::ENDPTNAKEN |
Endpoint NAK Enable Register, offset: 0x17C
| __I uint32_t TRNG_Type::ENT[16] |
RNG TRNG Entropy Read Register, array offset: 0x40, array step: 0x4
| __IO uint32_t USBHS_Type::EPCOMPLETE |
Endpoint Complete Register, offset: 0x1BC
| __IO uint32_t USBHS_Type::EPCR |
Endpoint Control Register n, array offset: 0x1C4, array step: 0x4
| __IO uint32_t USBHS_Type::EPCR0 |
Endpoint Control Register 0, offset: 0x1C0
| __IO uint32_t USBHS_Type::EPFLUSH |
Endpoint Flush Register, offset: 0x1B4
| __IO uint32_t USBHS_Type::EPLISTADDR |
Endpoint List Address Register, offset: 0x158
| __IO uint32_t { ... } ::EPLISTADDR |
Endpoint List Address Register, offset: 0x158
| __IO uint32_t { ... } ::EPLISTADDR |
Endpoint List Address Register, offset: 0x158
| __IO uint32_t USBHS_Type::EPPRIME |
Endpoint Initialization Register, offset: 0x1B0
| __IO uint32_t USBHS_Type::EPSETUPSR |
Endpoint Setup Status Register, offset: 0x1AC
| __I uint32_t USBHS_Type::EPSR |
Endpoint Status Register, offset: 0x1B8
| __I uint8_t FTFE_Type::FACSN |
Flash Access Segment Number Register, offset: 0x2B
| __I uint8_t FTFE_Type::FACSS |
Flash Access Segment Size Register, offset: 0x28
| __I uint32_t MCM_Type::FADR |
Fault address register, offset: 0x20
| __I uint32_t MCM_Type::FATR |
Fault attributes register, offset: 0x24
| __IO uint8_t FTFE_Type::FCCOB0 |
Flash Common Command Object Registers, offset: 0x7
| __IO uint8_t FTFE_Type::FCCOB1 |
Flash Common Command Object Registers, offset: 0x6
| __IO uint8_t FTFE_Type::FCCOB2 |
Flash Common Command Object Registers, offset: 0x5
| __IO uint8_t FTFE_Type::FCCOB3 |
Flash Common Command Object Registers, offset: 0x4
| __IO uint8_t FTFE_Type::FCCOB4 |
Flash Common Command Object Registers, offset: 0xB
| __IO uint8_t FTFE_Type::FCCOB5 |
Flash Common Command Object Registers, offset: 0xA
| __IO uint8_t FTFE_Type::FCCOB6 |
Flash Common Command Object Registers, offset: 0x9
| __IO uint8_t FTFE_Type::FCCOB7 |
Flash Common Command Object Registers, offset: 0x8
| __IO uint8_t FTFE_Type::FCCOB8 |
Flash Common Command Object Registers, offset: 0xF
| __IO uint8_t FTFE_Type::FCCOB9 |
Flash Common Command Object Registers, offset: 0xE
| __IO uint8_t FTFE_Type::FCCOBA |
Flash Common Command Object Registers, offset: 0xD
| __IO uint8_t FTFE_Type::FCCOBB |
Flash Common Command Object Registers, offset: 0xC
| __IO uint8_t FTFE_Type::FCNFG |
Flash Configuration Register, offset: 0x1
| __IO uint16_t PWM_Type::FCTRL |
Fault Control Register, offset: 0x18C
| __IO uint16_t PWM_Type::FCTRL2 |
Fault Control 2 Register, offset: 0x194
| __IO uint8_t FTFE_Type::FDPROT |
Data Flash Protection Register, offset: 0x17
| __I uint32_t MCM_Type::FDR |
Fault data register, offset: 0x28
| __IO uint8_t FTFE_Type::FEPROT |
EEPROM Protection Register, offset: 0x16
| __IO uint16_t PWM_Type::FFILT |
Fault Filter Register, offset: 0x190
| __IO uint16_t ENC_Type::FILT |
Input Filter Register, offset: 0x2
| __IO uint8_t LLWU_Type::FILT3 |
LLWU Pin Filter 3 register, offset: 0x10
| __IO uint8_t LLWU_Type::FILT4 |
LLWU Pin Filter 4 register, offset: 0x11
| __IO uint32_t TPM_Type::FILTER |
Filter Control, offset: 0x78
| __I uint8_t FTFE_Type::FOPT |
Flash Option Register, offset: 0x3
| __IO uint8_t FTFE_Type::FPROT0 |
Program Flash Protection Registers, offset: 0x13
| __IO uint8_t FTFE_Type::FPROT1 |
Program Flash Protection Registers, offset: 0x12
| __IO uint8_t FTFE_Type::FPROT2 |
Program Flash Protection Registers, offset: 0x11
| __IO uint8_t FTFE_Type::FPROT3 |
Program Flash Protection Registers, offset: 0x10
| __IO uint16_t { ... } ::FRACVAL1 |
Fractional Value Register 1, array offset: 0xC, array step: 0x60
| __IO uint16_t PWM_Type::FRACVAL1 |
Fractional Value Register 1, array offset: 0xC, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL2 |
Fractional Value Register 2, array offset: 0x10, array step: 0x60
| __IO uint16_t PWM_Type::FRACVAL2 |
Fractional Value Register 2, array offset: 0x10, array step: 0x60
| __IO uint16_t PWM_Type::FRACVAL3 |
Fractional Value Register 3, array offset: 0x14, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL3 |
Fractional Value Register 3, array offset: 0x14, array step: 0x60
| __IO uint16_t PWM_Type::FRACVAL4 |
Fractional Value Register 4, array offset: 0x18, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL4 |
Fractional Value Register 4, array offset: 0x18, array step: 0x60
| __IO uint16_t PWM_Type::FRACVAL5 |
Fractional Value Register 5, array offset: 0x1C, array step: 0x60
| __IO uint16_t { ... } ::FRACVAL5 |
Fractional Value Register 5, array offset: 0x1C, array step: 0x60
| __IO uint16_t PWM_Type::FRCTRL |
Fractional Control Register, array offset: 0x20, array step: 0x60
| __IO uint16_t { ... } ::FRCTRL |
Fractional Control Register, array offset: 0x20, array step: 0x60
| __IO uint32_t USBHS_Type::FRINDEX |
Frame Index Register, offset: 0x14C
| __I uint32_t { ... } ::FRQCNT |
RNG Frequency Count Register, offset: 0x1C
| __I uint32_t TRNG_Type::FRQCNT |
RNG Frequency Count Register, offset: 0x1C
| __IO uint32_t TRNG_Type::FRQMAX |
RNG Frequency Count Maximum Limit Register, offset: 0x1C
| __IO uint32_t { ... } ::FRQMAX |
RNG Frequency Count Maximum Limit Register, offset: 0x1C
| __IO uint32_t TRNG_Type::FRQMIN |
RNG Frequency Count Minimum Limit Register, offset: 0x18
| __I uint8_t FTFE_Type::FSEC |
Flash Security Register, offset: 0x2
| __IO uint8_t FTFE_Type::FSTAT |
Flash Status Register, offset: 0x0
| __IO uint16_t PWM_Type::FSTS |
Fault Status Register, offset: 0x18E
| __IO uint16_t PWM_Type::FTST |
Fault Test Register, offset: 0x192
| __IO uint32_t { ... } ::GPOLY |
CRC Polynomial register, offset: 0x4
| __IO uint32_t { ... } ::GPOLY |
CRC Polynomial register, offset: 0x4
| __IO uint32_t { ... } ::GPOLY |
CRC Polynomial register, offset: 0x4
| __IO uint32_t { ... } ::GPOLY |
CRC Polynomial register, offset: 0x4
| __IO uint16_t { ... } ::GPOLYH |
CRC_GPOLYH register., offset: 0x6
| __IO uint16_t { ... } ::GPOLYH |
CRC_GPOLYH register., offset: 0x6
| __IO uint16_t { ... } ::GPOLYH |
CRC_GPOLYH register., offset: 0x6
| __IO uint16_t { ... } ::GPOLYH |
CRC_GPOLYH register., offset: 0x6
| __IO uint8_t { ... } ::GPOLYHL |
CRC_GPOLYHL register., offset: 0x6
| __IO uint8_t { ... } ::GPOLYHL |
CRC_GPOLYHL register., offset: 0x6
| __IO uint8_t { ... } ::GPOLYHL |
CRC_GPOLYHL register., offset: 0x6
| __IO uint8_t { ... } ::GPOLYHL |
CRC_GPOLYHL register., offset: 0x6
| __IO uint8_t { ... } ::GPOLYHU |
CRC_GPOLYHU register., offset: 0x7
| __IO uint8_t { ... } ::GPOLYHU |
CRC_GPOLYHU register., offset: 0x7
| __IO uint8_t { ... } ::GPOLYHU |
CRC_GPOLYHU register., offset: 0x7
| __IO uint8_t { ... } ::GPOLYHU |
CRC_GPOLYHU register., offset: 0x7
| __IO uint16_t { ... } ::GPOLYL |
CRC_GPOLYL register., offset: 0x4
| __IO uint16_t { ... } ::GPOLYL |
CRC_GPOLYL register., offset: 0x4
| __IO uint16_t { ... } ::GPOLYL |
CRC_GPOLYL register., offset: 0x4
| __IO uint16_t { ... } ::GPOLYL |
CRC_GPOLYL register., offset: 0x4
| __IO uint8_t { ... } ::GPOLYLL |
CRC_GPOLYLL register., offset: 0x4
| __IO uint8_t { ... } ::GPOLYLL |
CRC_GPOLYLL register., offset: 0x4
| __IO uint8_t { ... } ::GPOLYLL |
CRC_GPOLYLL register., offset: 0x4
| __IO uint8_t { ... } ::GPOLYLL |
CRC_GPOLYLL register., offset: 0x4
| __IO uint8_t { ... } ::GPOLYLU |
CRC_GPOLYLU register., offset: 0x5
| __IO uint8_t { ... } ::GPOLYLU |
CRC_GPOLYLU register., offset: 0x5
| __IO uint8_t { ... } ::GPOLYLU |
CRC_GPOLYLU register., offset: 0x5
| __IO uint8_t { ... } ::GPOLYLU |
CRC_GPOLYLU register., offset: 0x5
| __IO uint32_t USBHS_Type::GPTIMER0CTL |
General Purpose Timer n Control Register, offset: 0x84
| __IO uint32_t USBHS_Type::GPTIMER0LD |
General Purpose Timer n Load Register, offset: 0x80
| __IO uint32_t USBHS_Type::GPTIMER1CTL |
General Purpose Timer n Control Register, offset: 0x8C
| __IO uint32_t USBHS_Type::GPTIMER1LD |
General Purpose Timer n Load Register, offset: 0x88
| __I uint32_t USBHS_Type::HCCPARAMS |
Host Controller Capability Parameters Register, offset: 0x108
| __I uint32_t USBHS_Type::HCIVERSION |
Host Controller Interface Version and Capability Registers Length Register, offset: 0x100
| __I uint32_t USBHS_Type::HCSPARAMS |
Host Controller Structural Parameters Register, offset: 0x104
| __IO uint16_t HSADC_Type::HILIM[16] |
HSADC High Limit Registers, array offset: 0x5C, array step: 0x2
| __IO uint16_t HSADC_Type::HILIMSTAT |
HSADC High Limit Status Register, offset: 0x18
| __I uint32_t DMA_Type::HRS |
Hardware Request Status Register, offset: 0x34
| __IO uint8_t PMC_Type::HVDSC1 |
High Voltage Detect Status And Control 1 register, offset: 0xB
| __I uint32_t USBHS_Type::HWDEVICE |
Device Hardware Parameters Register, offset: 0xC
| __I uint32_t USBHS_Type::HWGENERAL |
General Hardware Parameters Register, offset: 0x4
| __I uint32_t USBHS_Type::HWHOST |
Host Hardware Parameters Register, offset: 0x8
| __I uint32_t USBHS_Type::HWRXBUF |
Receive Buffer Hardware Parameters Register, offset: 0x14
| __I uint32_t USBHS_Type::HWTXBUF |
Transmit Buffer Hardware Parameters Register, offset: 0x10
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10
| __I uint32_t USBHS_Type::ID |
Identification Register, offset: 0x0
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10
| __I uint32_t ENET_Type::IEEE_R_ALIGN |
Frames Received with Alignment Error Statistic Register, offset: 0x2D4
| __I uint32_t ENET_Type::IEEE_R_CRC |
Frames Received with CRC Error Statistic Register, offset: 0x2D0
| __I uint32_t ENET_Type::IEEE_R_DROP |
Frames not Counted Correctly Statistic Register, offset: 0x2C8
| __I uint32_t ENET_Type::IEEE_R_FDXFC |
Flow Control Pause Frames Received Statistic Register, offset: 0x2DC
| __I uint32_t ENET_Type::IEEE_R_FRAME_OK |
Frames Received OK Statistic Register, offset: 0x2CC
| __I uint32_t ENET_Type::IEEE_R_MACERR |
Receive FIFO Overflow Count Statistic Register, offset: 0x2D8
| __I uint32_t ENET_Type::IEEE_T_1COL |
Frames Transmitted with Single Collision Statistic Register, offset: 0x250
| __I uint32_t ENET_Type::IEEE_T_CSERR |
Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268
| __I uint32_t ENET_Type::IEEE_T_DEF |
Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258
| uint32_t ENET_Type::IEEE_T_DROP |
IEEE_T_DROP Reserved Statistic Register, offset: 0x248
Reserved Statistic Register, offset: 0x248
| __I uint32_t ENET_Type::IEEE_T_EXCOL |
Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260
| __I uint32_t ENET_Type::IEEE_T_FDXFC |
Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270
| __I uint32_t ENET_Type::IEEE_T_FRAME_OK |
Frames Transmitted OK Statistic Register, offset: 0x24C
| __I uint32_t ENET_Type::IEEE_T_LCOL |
Frames Transmitted with Late Collision Statistic Register, offset: 0x25C
| __I uint32_t ENET_Type::IEEE_T_MACERR |
Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264
| __I uint32_t ENET_Type::IEEE_T_MCOL |
Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254
| __I uint32_t ENET_Type::IEEE_T_SQE |
, offset: 0x26C
Reserved Statistic Register, offset: 0x26C
| __I uint16_t ENC_Type::IMR |
Input Monitor Register, offset: 0x1A
| __IO uint16_t PWM_Type::INIT |
Initial Count Register, array offset: 0x2, array step: 0x60
| __IO uint16_t { ... } ::INIT |
Initial Count Register, array offset: 0x2, array step: 0x60
| __IO uint32_t { ... } ::INT |
DAC Interval n register, array offset: 0x154, array step: 0x8
| __IO uint32_t { ... } ::INT |
DAC Interval n register, array offset: 0x154, array step: 0x8
| __IO uint32_t { ... } ::INT |
DAC Interval n register, array offset: 0x154, array step: 0x8
| __IO uint32_t { ... } ::INT |
DAC Interval n register, array offset: 0x154, array step: 0x8
| __IO uint32_t TRNG_Type::INT_CTRL |
RNG Interrupt Control Register, offset: 0xB4
| __IO uint32_t TRNG_Type::INT_MASK |
RNG Mask Register, offset: 0xB8
| __IO uint32_t TRNG_Type::INT_STATUS |
RNG Interrupt Status Register, offset: 0xBC
| __IO uint32_t { ... } ::INTC |
DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8
| __IO uint32_t { ... } ::INTC |
DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8
| __IO uint32_t { ... } ::INTC |
DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8
| __IO uint32_t { ... } ::INTC |
DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8
| __IO uint16_t PWM_Type::INTEN |
Interrupt Enable Register, array offset: 0x26, array step: 0x60
| __IO uint16_t { ... } ::INTEN |
Interrupt Enable Register, array offset: 0x26, array step: 0x60
| __IO uint32_t MCM_Type::ISCR |
Interrupt Status Register, offset: 0x10
Interrupt Status and Control Register, offset: 0x10
| __IO uint16_t ENC_Type::LCOMP |
Lower Position Compare Register, offset: 0x26
| __IO uint32_t { ... } ::LDVAL |
Timer Load Value Register, array offset: 0x100, array step: 0x10
| __IO uint32_t { ... } ::LDVAL |
Timer Load Value Register, array offset: 0x100, array step: 0x10
| __IO uint32_t { ... } ::LDVAL |
Timer Load Value Register, array offset: 0x100, array step: 0x10
| __IO uint32_t { ... } ::LDVAL |
Timer Load Value Register, array offset: 0x100, array step: 0x10
| __IO uint16_t ENC_Type::LINIT |
Lower Initialization Register, offset: 0x18
| __I uint32_t MCM_Type::LMEM[5] |
Local Memory General Descriptor Register, array offset: 0x400, array step: 0x4
| __IO uint16_t ENC_Type::LMOD |
Lower Modulus Register, offset: 0x22
| __IO uint16_t HSADC_Type::LOLIM[16] |
HSADC Low Limit Registers, array offset: 0x3C, array step: 0x2
| __IO uint16_t HSADC_Type::LOLIMSTAT |
HSADC Low Limit Status Register, offset: 0x16
| __IO uint16_t ENC_Type::LPOS |
Lower Position Counter Register, offset: 0x10
| __I uint16_t ENC_Type::LPOSH |
Lower Position Hold Register, offset: 0x14
| __I uint32_t PIT_Type::LTMR64H |
PIT Upper Lifetime Timer Register, offset: 0xE0
| __I uint32_t PIT_Type::LTMR64L |
PIT Lower Lifetime Timer Register, offset: 0xE4
| __IO uint16_t PWM_Type::MASK |
Mask Register, offset: 0x182
| __I uint32_t MSCM_Type::MASTER |
Processor 0 Master Register..Processor 1 Master Register, array offset: 0x28, array step: 0x20
| __I uint32_t { ... } ::MASTER |
Processor 0 Master Register..Processor 1 Master Register, array offset: 0x28, array step: 0x20
| __IO uint32_t LPUART_Type::MATCH |
LPUART Match Address Register, offset: 0x10
| __IO uint32_t RTC_Type::MCHR |
RTC Monotonic Counter High Register, offset: 0x2C
| __IO uint32_t RTC_Type::MCLR |
RTC Monotonic Counter Low Register, offset: 0x28
| __IO uint32_t TRNG_Type::MCTL |
RNG Miscellaneous Control Register, offset: 0x0
| __IO uint16_t PWM_Type::MCTRL |
Master Control Register 0, offset: 0x188
| __IO uint16_t PWM_Type::MCTRL2 |
Master Control Register 1, offset: 0x18A
| __IO uint32_t RTC_Type::MER |
RTC Monotonic Enable Register, offset: 0x24
| __I uint8_t LLWU_Type::MF5 |
LLWU Module Flag 5 register, offset: 0xD
| __IO uint32_t AXBS_Type::MGPCR6 |
Master General Purpose Control Register, offset: 0xE00
| __IO uint32_t SIM_Type::MISCTRL0 |
Miscellaneous Control Register 0, offset: 0x106C
| __IO uint32_t SIM_Type::MISCTRL1 |
Miscellaneous Control Register 1, offset: 0x1070
| __IO uint32_t TPM_Type::MOD |
Modulo, offset: 0x8
| __IO uint32_t LPUART_Type::MODIR |
LPUART Modem IrDA Register, offset: 0x14
| __IO uint16_t HSADC_Type::MUX67_SEL |
MUX6_7 Selection Controls Register, offset: 0xBA
| __IO uint32_t { ... } ::NBYTES_MLNO |
TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLNO |
TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLNO |
TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLNO |
TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFNO |
TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFNO |
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFNO |
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFNO |
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFYES |
TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFYES |
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFYES |
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFYES |
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20
| __I uint32_t MSCM_Type::NUM |
Processor 0 Number Register..Processor 1 Number Register, array offset: 0x24, array step: 0x20
| __I uint32_t { ... } ::NUM |
Processor 0 Number Register..Processor 1 Number Register, array offset: 0x24, array step: 0x20
| __I uint32_t MSCM_Type::OCMDR[3] |
On-Chip Memory Descriptor Register, array offset: 0x400, array step: 0x4
| __IO uint16_t PWM_Type::OCTRL |
Output Control Register, array offset: 0x22, array step: 0x60
| __IO uint16_t { ... } ::OCTRL |
Output Control Register, array offset: 0x22, array step: 0x60
| __IO uint16_t HSADC_Type::OFFST[16] |
HSADC Offset Register, array offset: 0x7C, array step: 0x2
| __IO uint32_t USBHS_Type::OTGSC |
On-the-Go Status and Control Register, offset: 0x1A4
| __IO uint16_t PWM_Type::OUTEN |
Output Enable Register, offset: 0x180
| __IO uint32_t AIPS_Type::PACRU |
Peripheral Access Control Register, offset: 0x80
| __IO uint32_t LMEM_Type::PCCCR |
Cache control register, offset: 0x0
| __IO uint32_t LMEM_Type::PCCCVR |
Cache read/write value register, offset: 0xC
| __IO uint32_t LMEM_Type::PCCLCR |
Cache line control register, offset: 0x4
| __IO uint32_t LMEM_Type::PCCRMR |
Cache regions mode register, offset: 0x20
| __IO uint32_t LMEM_Type::PCCSAR |
Cache search address register, offset: 0x8
| __I uint32_t MCM_Type::PCT |
Processor core type, offset: 0x0
| __IO uint8_t LLWU_Type::PE5 |
LLWU Pin Enable 5 register, offset: 0x4
| __IO uint8_t LLWU_Type::PE6 |
LLWU Pin Enable 6 register, offset: 0x5
| __IO uint8_t LLWU_Type::PE7 |
LLWU Pin Enable 7 register, offset: 0x6
| __IO uint8_t LLWU_Type::PE8 |
LLWU Pin Enable 8 register, offset: 0x7
| __IO uint32_t { ... } ::PERIODICLISTBASE |
Periodic Frame List Base Address Register, offset: 0x154
| __IO uint32_t USBHS_Type::PERIODICLISTBASE |
Periodic Frame List Base Address Register, offset: 0x154
| __IO uint32_t { ... } ::PERIODICLISTBASE |
Periodic Frame List Base Address Register, offset: 0x154
| __IO uint8_t LLWU_Type::PF1 |
LLWU Pin Flag 1 register, offset: 0x9
| __IO uint8_t LLWU_Type::PF2 |
LLWU Pin Flag 2 register, offset: 0xA
| __IO uint8_t LLWU_Type::PF3 |
LLWU Pin Flag 3 register, offset: 0xB
| __IO uint8_t LLWU_Type::PF4 |
LLWU Pin Flag 4 register, offset: 0xC
| __IO uint32_t FMC_Type::PFB01CR |
Flash Bank 0-1 Control Register, offset: 0x4
| __IO uint32_t FMC_Type::PFB23CR |
Flash Bank 2-3 Control Register, offset: 0x8
| __I uint32_t TRNG_Type::PKRCNT10 |
RNG Statistical Check Poker Count 1 and 0 Register, offset: 0x80
| __I uint32_t TRNG_Type::PKRCNT32 |
RNG Statistical Check Poker Count 3 and 2 Register, offset: 0x84
| __I uint32_t TRNG_Type::PKRCNT54 |
RNG Statistical Check Poker Count 5 and 4 Register, offset: 0x88
| __I uint32_t TRNG_Type::PKRCNT76 |
RNG Statistical Check Poker Count 7 and 6 Register, offset: 0x8C
| __I uint32_t TRNG_Type::PKRCNT98 |
RNG Statistical Check Poker Count 9 and 8 Register, offset: 0x90
| __I uint32_t TRNG_Type::PKRCNTBA |
RNG Statistical Check Poker Count B and A Register, offset: 0x94
| __I uint32_t TRNG_Type::PKRCNTDC |
RNG Statistical Check Poker Count D and C Register, offset: 0x98
| __I uint32_t TRNG_Type::PKRCNTFE |
RNG Statistical Check Poker Count F and E Register, offset: 0x9C
| __IO uint32_t { ... } ::PKRMAX |
RNG Poker Maximum Limit Register, offset: 0xC
| __IO uint32_t TRNG_Type::PKRMAX |
RNG Poker Maximum Limit Register, offset: 0xC
| __IO uint32_t TRNG_Type::PKRRNG |
RNG Poker Range Register, offset: 0x8
| __I uint32_t { ... } ::PKRSQ |
RNG Poker Square Calculation Result Register, offset: 0xC
| __I uint32_t TRNG_Type::PKRSQ |
RNG Poker Square Calculation Result Register, offset: 0xC
| __IO uint32_t USBPHY_Type::PLL_SIC |
USB PHY PLL Control/Status Register, offset: 0xA0
| __IO uint32_t USBPHY_Type::PLL_SIC_CLR |
USB PHY PLL Control/Status Register, offset: 0xA8
| __IO uint32_t USBPHY_Type::PLL_SIC_SET |
USB PHY PLL Control/Status Register, offset: 0xA4
| __IO uint32_t USBPHY_Type::PLL_SIC_TOG |
USB PHY PLL Control/Status Register, offset: 0xAC
| __IO uint32_t TPM_Type::POL |
Channel Polarity, offset: 0x70
| __IO uint32_t USBHS_Type::PORTSC1 |
Port Status and Control Registers, offset: 0x184
| __IO uint16_t ENC_Type::POSD |
Position Difference Counter Register, offset: 0x6
| __I uint16_t ENC_Type::POSDH |
Position Difference Hold Register, offset: 0x8
| __IO uint32_t { ... } ::PRS |
Priority Registers Slave, array offset: 0x0, array step: 0x100
| __IO uint32_t { ... } ::PRS |
Priority Registers Slave, array offset: 0x0, array step: 0x100
| __IO uint32_t { ... } ::PRS |
Priority Registers Slave, array offset: 0x0, array step: 0x100
| __IO uint32_t { ... } ::PRS |
Priority Registers Slave, array offset: 0x0, array step: 0x100
| __IO uint32_t { ... } ::PUSHR |
PUSH TX FIFO Register In Master Mode, offset: 0x34
| __IO uint32_t { ... } ::PUSHR |
PUSH TX FIFO Register In Master Mode, offset: 0x34
| __IO uint32_t { ... } ::PUSHR |
PUSH TX FIFO Register In Master Mode, offset: 0x34
| __IO uint32_t { ... } ::PUSHR |
PUSH TX FIFO Register In Master Mode, offset: 0x34
| __IO uint32_t { ... } ::PUSHR_SLAVE |
PUSH TX FIFO Register In Slave Mode, offset: 0x34
| __IO uint32_t { ... } ::PUSHR_SLAVE |
PUSH TX FIFO Register In Slave Mode, offset: 0x34
| __IO uint32_t { ... } ::PUSHR_SLAVE |
PUSH TX FIFO Register In Slave Mode, offset: 0x34
| __IO uint32_t { ... } ::PUSHR_SLAVE |
PUSH TX FIFO Register In Slave Mode, offset: 0x34
| __IO uint32_t USBPHY_Type::PWD |
USB PHY Power-Down Register, offset: 0x0
| __IO uint32_t USBPHY_Type::PWD_CLR |
USB PHY Power-Down Register, offset: 0x8
| __IO uint32_t USBPHY_Type::PWD_SET |
USB PHY Power-Down Register, offset: 0x4
| __IO uint32_t USBPHY_Type::PWD_TOG |
USB PHY Power-Down Register, offset: 0xC
| __IO uint16_t HSADC_Type::PWR |
HSADC Power Control Register, offset: 0x9C
| __IO uint16_t HSADC_Type::PWR2 |
HSADC Power Control Register 2, offset: 0xA6
| __IO uint32_t SIM_Type::PWRC |
Power Control Register, offset: 0x1104
| __IO uint32_t TPM_Type::QDCTRL |
Quadrature Decoder Control and Status, offset: 0x80
| __I uint16_t HSADC_Type::RDY |
HSADC Ready Register, offset: 0x14
| __IO uint16_t ENC_Type::REV |
Revolution Counter Register, offset: 0xA
| __I uint16_t ENC_Type::REVH |
Revolution Hold Register, offset: 0xC
| __I uint32_t ENET_Type::RMON_R_BC_PKT |
Rx Broadcast Packets Statistic Register, offset: 0x288
| __I uint32_t ENET_Type::RMON_R_CRC_ALIGN |
Rx Packets with CRC/Align Error Statistic Register, offset: 0x290
| __I uint32_t ENET_Type::RMON_R_FRAG |
Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C
| __I uint32_t ENET_Type::RMON_R_JAB |
Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0
| __I uint32_t ENET_Type::RMON_R_MC_PKT |
Rx Multicast Packets Statistic Register, offset: 0x28C
| __I uint32_t ENET_Type::RMON_R_OVERSIZE |
Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298
| __I uint32_t ENET_Type::RMON_R_P1024TO2047 |
Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC
| __I uint32_t ENET_Type::RMON_R_P128TO255 |
Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0
| __I uint32_t ENET_Type::RMON_R_P256TO511 |
Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4
| __I uint32_t ENET_Type::RMON_R_P512TO1023 |
Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8
| __I uint32_t ENET_Type::RMON_R_P64 |
Rx 64-Byte Packets Statistic Register, offset: 0x2A8
| __I uint32_t ENET_Type::RMON_R_P65TO127 |
Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC
| __I uint32_t ENET_Type::RMON_R_P_GTE2048 |
Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0
| __I uint32_t ENET_Type::RMON_R_PACKETS |
Rx Packet Count Statistic Register, offset: 0x284
| uint32_t ENET_Type::RMON_R_RESVD_0 |
Reserved Statistic Register, offset: 0x2A4
| __I uint32_t ENET_Type::RMON_R_UNDERSIZE |
Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294
| __I uint32_t ENET_Type::RMON_T_BC_PKT |
Tx Broadcast Packets Statistic Register, offset: 0x208
| __I uint32_t ENET_Type::RMON_T_COL |
Tx Collision Count Statistic Register, offset: 0x224
| __I uint32_t ENET_Type::RMON_T_CRC_ALIGN |
Tx Packets with CRC/Align Error Statistic Register, offset: 0x210
| uint32_t ENET_Type::RMON_T_DROP |
Reserved Statistic Register, offset: 0x200
| __I uint32_t ENET_Type::RMON_T_FRAG |
Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C
| __I uint32_t ENET_Type::RMON_T_JAB |
Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220
| __I uint32_t ENET_Type::RMON_T_MC_PKT |
Tx Multicast Packets Statistic Register, offset: 0x20C
| __I uint32_t ENET_Type::RMON_T_OVERSIZE |
Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218
| __I uint32_t ENET_Type::RMON_T_P1024TO2047 |
Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C
| __I uint32_t ENET_Type::RMON_T_P128TO255 |
Tx 128- to 255-byte Packets Statistic Register, offset: 0x230
| __I uint32_t ENET_Type::RMON_T_P256TO511 |
Tx 256- to 511-byte Packets Statistic Register, offset: 0x234
| __I uint32_t ENET_Type::RMON_T_P512TO1023 |
Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238
| __I uint32_t ENET_Type::RMON_T_P64 |
Tx 64-Byte Packets Statistic Register, offset: 0x228
| __I uint32_t ENET_Type::RMON_T_P65TO127 |
Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C
| __I uint32_t ENET_Type::RMON_T_P_GTE2048 |
Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240
| __I uint32_t ENET_Type::RMON_T_PACKETS |
Tx Packet Count Statistic Register, offset: 0x204
| __I uint32_t ENET_Type::RMON_T_UNDERSIZE |
Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214
| __IO uint16_t HSADC_Type::RSLT[16] |
HSADC Result Registers with sign extension, array offset: 0x1C, array step: 0x2
| __IO uint32_t USBPHY_Type::RX |
USB PHY Receiver Control Register, offset: 0x20
| __IO uint32_t USBPHY_Type::RX_CLR |
USB PHY Receiver Control Register, offset: 0x28
| __IO uint32_t USBPHY_Type::RX_SET |
USB PHY Receiver Control Register, offset: 0x24
| __IO uint32_t USBPHY_Type::RX_TOG |
USB PHY Receiver Control Register, offset: 0x2C
| __IO uint32_t { ... } ::S |
Channel n Status register, array offset: 0x14, array step: 0x28
| __IO uint32_t { ... } ::S |
Channel n Status register, array offset: 0x14, array step: 0x28
| __IO uint32_t { ... } ::S |
Channel n Status register, array offset: 0x14, array step: 0x28
| __IO uint32_t { ... } ::S |
Channel n Status register, array offset: 0x14, array step: 0x28
| __I uint8_t MCG_Type::S2 |
MCG Status 2 Register, offset: 0x12
| __I uint8_t FTFE_Type::SACCH0 |
Supervisor-only Access Registers, offset: 0x23
| __I uint8_t FTFE_Type::SACCH1 |
Supervisor-only Access Registers, offset: 0x22
| __I uint8_t FTFE_Type::SACCH2 |
Supervisor-only Access Registers, offset: 0x21
| __I uint8_t FTFE_Type::SACCH3 |
Supervisor-only Access Registers, offset: 0x20
| __I uint8_t FTFE_Type::SACCL0 |
Supervisor-only Access Registers, offset: 0x27
| __I uint8_t FTFE_Type::SACCL1 |
Supervisor-only Access Registers, offset: 0x26
| __I uint8_t FTFE_Type::SACCL2 |
Supervisor-only Access Registers, offset: 0x25
| __I uint8_t FTFE_Type::SACCL3 |
Supervisor-only Access Registers, offset: 0x24
| __IO uint32_t { ... } ::SADDR |
TCD Source Address, array offset: 0x1000, array step: 0x20
| __IO uint32_t { ... } ::SADDR |
TCD Source Address, array offset: 0x1000, array step: 0x20
| __IO uint32_t { ... } ::SADDR |
TCD Source Address, array offset: 0x1000, array step: 0x20
| __IO uint32_t { ... } ::SADDR |
TCD Source Address, array offset: 0x1000, array step: 0x20
| __IO uint16_t HSADC_Type::SAMPTIM |
HSADC Sampling Time Configuration Register, offset: 0xAC
| __IO uint32_t TRNG_Type::SBLIM |
RNG Sparse Bit Limit Register, offset: 0x14
| __IO uint32_t { ... } ::SBLIM |
RNG Sparse Bit Limit Register, offset: 0x14
| __IO uint32_t TPM_Type::SC |
Status and Control, offset: 0x0
| __IO uint16_t HSADC_Type::SCINTEN |
HSADC Scan Interrupt Enable Register, offset: 0xAA
| __I uint32_t TRNG_Type::SCMC |
RNG Statistical Check Monobit Count Register, offset: 0x20
| __I uint32_t { ... } ::SCMC |
RNG Statistical Check Monobit Count Register, offset: 0x20
| __IO uint32_t TRNG_Type::SCMISC |
RNG Statistical Check Miscellaneous Register, offset: 0x4
| __IO uint32_t { ... } ::SCML |
RNG Statistical Check Monobit Limit Register, offset: 0x20
| __IO uint32_t TRNG_Type::SCML |
RNG Statistical Check Monobit Limit Register, offset: 0x20
| __I uint32_t { ... } ::SCR1C |
RNG Statistical Check Run Length 1 Count Register, offset: 0x24
| __I uint32_t TRNG_Type::SCR1C |
RNG Statistical Check Run Length 1 Count Register, offset: 0x24
| __IO uint32_t { ... } ::SCR1L |
RNG Statistical Check Run Length 1 Limit Register, offset: 0x24
| __IO uint32_t TRNG_Type::SCR1L |
RNG Statistical Check Run Length 1 Limit Register, offset: 0x24
| __I uint32_t { ... } ::SCR2C |
RNG Statistical Check Run Length 2 Count Register, offset: 0x28
| __I uint32_t TRNG_Type::SCR2C |
RNG Statistical Check Run Length 2 Count Register, offset: 0x28
| __IO uint32_t TRNG_Type::SCR2L |
RNG Statistical Check Run Length 2 Limit Register, offset: 0x28
| __IO uint32_t { ... } ::SCR2L |
RNG Statistical Check Run Length 2 Limit Register, offset: 0x28
| __I uint32_t TRNG_Type::SCR3C |
RNG Statistical Check Run Length 3 Count Register, offset: 0x2C
| __I uint32_t { ... } ::SCR3C |
RNG Statistical Check Run Length 3 Count Register, offset: 0x2C
| __IO uint32_t TRNG_Type::SCR3L |
RNG Statistical Check Run Length 3 Limit Register, offset: 0x2C
| __IO uint32_t { ... } ::SCR3L |
RNG Statistical Check Run Length 3 Limit Register, offset: 0x2C
| __I uint32_t TRNG_Type::SCR4C |
RNG Statistical Check Run Length 4 Count Register, offset: 0x30
| __I uint32_t { ... } ::SCR4C |
RNG Statistical Check Run Length 4 Count Register, offset: 0x30
| __IO uint32_t TRNG_Type::SCR4L |
RNG Statistical Check Run Length 4 Limit Register, offset: 0x30
| __IO uint32_t { ... } ::SCR4L |
RNG Statistical Check Run Length 4 Limit Register, offset: 0x30
| __I uint32_t TRNG_Type::SCR5C |
RNG Statistical Check Run Length 5 Count Register, offset: 0x34
| __I uint32_t { ... } ::SCR5C |
RNG Statistical Check Run Length 5 Count Register, offset: 0x34
| __IO uint32_t TRNG_Type::SCR5L |
RNG Statistical Check Run Length 5 Limit Register, offset: 0x34
| __IO uint32_t { ... } ::SCR5L |
RNG Statistical Check Run Length 5 Limit Register, offset: 0x34
| __I uint32_t { ... } ::SCR6PC |
RNG Statistical Check Run Length 6+ Count Register, offset: 0x38
| __I uint32_t TRNG_Type::SCR6PC |
RNG Statistical Check Run Length 6+ Count Register, offset: 0x38
| __IO uint32_t { ... } ::SCR6PL |
RNG Statistical Check Run Length 6+ Limit Register, offset: 0x38
| __IO uint32_t TRNG_Type::SCR6PL |
RNG Statistical Check Run Length 6+ Limit Register, offset: 0x38
| __IO uint16_t HSADC_Type::SCTRL |
HSADC Scan Control Register, offset: 0xA4
| __IO uint32_t TRNG_Type::SDCTL |
RNG Seed Control Register, offset: 0x10
| __IO uint16_t HSADC_Type::SDIS |
HSADC Sample Disable Register, offset: 0x10
| __IO uint32_t TRNG_Type::SEC_CFG |
RNG Security Configuration Register, offset: 0xB0
| __IO uint16_t XBARA_Type::SEL0 |
Crossbar A Select Register 0, offset: 0x0
| __IO uint16_t XBARB_Type::SEL0 |
Crossbar B Select Register 0, offset: 0x0
| __IO uint16_t XBARA_Type::SEL1 |
Crossbar A Select Register 1, offset: 0x2
| __IO uint16_t XBARB_Type::SEL1 |
Crossbar B Select Register 1, offset: 0x2
| __IO uint16_t XBARA_Type::SEL10 |
Crossbar A Select Register 10, offset: 0x14
| __IO uint16_t XBARA_Type::SEL11 |
Crossbar A Select Register 11, offset: 0x16
| __IO uint16_t XBARA_Type::SEL12 |
Crossbar A Select Register 12, offset: 0x18
| __IO uint16_t XBARA_Type::SEL13 |
Crossbar A Select Register 13, offset: 0x1A
| __IO uint16_t XBARA_Type::SEL14 |
Crossbar A Select Register 14, offset: 0x1C
| __IO uint16_t XBARA_Type::SEL15 |
Crossbar A Select Register 15, offset: 0x1E
| __IO uint16_t XBARA_Type::SEL16 |
Crossbar A Select Register 16, offset: 0x20
| __IO uint16_t XBARA_Type::SEL17 |
Crossbar A Select Register 17, offset: 0x22
| __IO uint16_t XBARA_Type::SEL18 |
Crossbar A Select Register 18, offset: 0x24
| __IO uint16_t XBARA_Type::SEL19 |
Crossbar A Select Register 19, offset: 0x26
| __IO uint16_t XBARA_Type::SEL2 |
Crossbar A Select Register 2, offset: 0x4
| __IO uint16_t XBARB_Type::SEL2 |
Crossbar B Select Register 2, offset: 0x4
| __IO uint16_t XBARA_Type::SEL20 |
Crossbar A Select Register 20, offset: 0x28
| __IO uint16_t XBARA_Type::SEL21 |
Crossbar A Select Register 21, offset: 0x2A
| __IO uint16_t XBARA_Type::SEL22 |
Crossbar A Select Register 22, offset: 0x2C
| __IO uint16_t XBARA_Type::SEL23 |
Crossbar A Select Register 23, offset: 0x2E
| __IO uint16_t XBARA_Type::SEL24 |
Crossbar A Select Register 24, offset: 0x30
| __IO uint16_t XBARA_Type::SEL25 |
Crossbar A Select Register 25, offset: 0x32
| __IO uint16_t XBARA_Type::SEL26 |
Crossbar A Select Register 26, offset: 0x34
| __IO uint16_t XBARA_Type::SEL27 |
Crossbar A Select Register 27, offset: 0x36
| __IO uint16_t XBARA_Type::SEL28 |
Crossbar A Select Register 28, offset: 0x38
| __IO uint16_t XBARA_Type::SEL29 |
Crossbar A Select Register 29, offset: 0x3A
| __IO uint16_t XBARA_Type::SEL3 |
Crossbar A Select Register 3, offset: 0x6
| __IO uint16_t XBARB_Type::SEL3 |
Crossbar B Select Register 3, offset: 0x6
| __IO uint16_t XBARA_Type::SEL4 |
Crossbar A Select Register 4, offset: 0x8
| __IO uint16_t XBARB_Type::SEL4 |
Crossbar B Select Register 4, offset: 0x8
| __IO uint16_t XBARA_Type::SEL5 |
Crossbar A Select Register 5, offset: 0xA
| __IO uint16_t XBARB_Type::SEL5 |
Crossbar B Select Register 5, offset: 0xA
| __IO uint16_t XBARA_Type::SEL6 |
Crossbar A Select Register 6, offset: 0xC
| __IO uint16_t XBARB_Type::SEL6 |
Crossbar B Select Register 6, offset: 0xC
| __IO uint16_t XBARA_Type::SEL7 |
Crossbar A Select Register 7, offset: 0xE
| __IO uint16_t XBARB_Type::SEL7 |
Crossbar B Select Register 7, offset: 0xE
| __IO uint16_t XBARA_Type::SEL8 |
Crossbar A Select Register 8, offset: 0x10
| __IO uint16_t XBARA_Type::SEL9 |
Crossbar A Select Register 9, offset: 0x12
| __IO uint32_t USBDCD_Type::SIGNAL_OVERRIDE |
Signal Override Register, offset: 0xC
| __IO uint32_t USBHSDCD_Type::SIGNAL_OVERRIDE |
Signal Override Register, offset: 0xC
| __IO uint32_t { ... } ::SLAST |
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
| __IO uint32_t { ... } ::SLAST |
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
| __IO uint32_t { ... } ::SLAST |
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
| __IO uint32_t { ... } ::SLAST |
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
| __IO uint16_t { ... } ::SOFF |
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
| __IO uint16_t { ... } ::SOFF |
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
| __IO uint16_t { ... } ::SOFF |
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
| __IO uint16_t { ... } ::SOFF |
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
| __IO uint32_t SIM_Type::SOPT8 |
System Options Register 8, offset: 0x101C
| __IO uint32_t SIM_Type::SOPT9 |
System Options Register 9, offset: 0x1020
| __IO uint8_t RCM_Type::SSRS0 |
Sticky System Reset Status Register 0, offset: 0x8
| __IO uint8_t RCM_Type::SSRS1 |
Sticky System Reset Status Register 1, offset: 0x9
| __IO uint32_t LPUART_Type::STAT |
LPUART Status Register, offset: 0x4
| __IO uint16_t HSADC_Type::STAT |
HSADC Status Register, offset: 0x12
| __IO uint32_t TPM_Type::STATUS |
Capture and Compare Status, offset: 0x50
| __I uint32_t USBHSDCD_Type::STATUS |
Status register, offset: 0x8
| __IO uint32_t USBPHY_Type::STATUS |
USB PHY Status Register, offset: 0x40
| __I uint32_t TRNG_Type::STATUS |
RNG Status Register, offset: 0x3C
| __IO uint8_t SMC_Type::STOPCTRL |
Stop Control Register, offset: 0x2
| __IO uint16_t { ... } ::STS |
Status Register, array offset: 0x24, array step: 0x60
| __IO uint16_t PWM_Type::STS |
Status Register, array offset: 0x24, array step: 0x60
| __IO uint16_t PWM_Type::SWCOUT |
Software Controlled Output Register, offset: 0x184
| __IO uint32_t FMC_Type::TAGVDW0S |
Cache Tag Storage, array offset: 0x100, array step: 0x4
| __IO uint32_t FMC_Type::TAGVDW1S |
Cache Tag Storage, array offset: 0x110, array step: 0x4
| __IO uint32_t FMC_Type::TAGVDW2S |
Cache Tag Storage, array offset: 0x120, array step: 0x4
| __IO uint32_t FMC_Type::TAGVDW3S |
Cache Tag Storage, array offset: 0x130, array step: 0x4
| __IO uint32_t { ... } ::TCCR |
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8
| __IO uint32_t { ... } ::TCCR |
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8
| __IO uint32_t { ... } ::TCCR |
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8
| __IO uint32_t { ... } ::TCCR |
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8
| __IO uint32_t { ... } ::TCSR |
Timer Control Status Register, array offset: 0x608, array step: 0x8
| __IO uint32_t { ... } ::TCSR |
Timer Control Status Register, array offset: 0x608, array step: 0x8
| __IO uint32_t { ... } ::TCSR |
Timer Control Status Register, array offset: 0x608, array step: 0x8
| __IO uint32_t { ... } ::TCSR |
Timer Control Status Register, array offset: 0x608, array step: 0x8
| __IO uint32_t { ... } ::TCTRL |
Timer Control Register, array offset: 0x108, array step: 0x10
| __IO uint32_t { ... } ::TCTRL |
Timer Control Register, array offset: 0x108, array step: 0x10
| __IO uint32_t { ... } ::TCTRL |
Timer Control Register, array offset: 0x108, array step: 0x10
| __IO uint32_t { ... } ::TCTRL |
Timer Control Register, array offset: 0x108, array step: 0x10
| __IO uint16_t PWM_Type::TCTRL |
Output Trigger Control Register, array offset: 0x2A, array step: 0x60
| __IO uint16_t { ... } ::TCTRL |
Output Trigger Control Register, array offset: 0x2A, array step: 0x60
| __IO uint32_t { ... } ::TFLG |
Timer Flag Register, array offset: 0x10C, array step: 0x10
| __IO uint32_t { ... } ::TFLG |
Timer Flag Register, array offset: 0x10C, array step: 0x10
| __IO uint32_t { ... } ::TFLG |
Timer Flag Register, array offset: 0x10C, array step: 0x10
| __IO uint32_t { ... } ::TFLG |
Timer Flag Register, array offset: 0x10C, array step: 0x10
| __IO uint32_t USBHSDCD_Type::TIMER0 |
TIMER0 register, offset: 0x10
| __IO uint32_t USBHSDCD_Type::TIMER1 |
TIMER1 register, offset: 0x14
| __IO uint32_t { ... } ::TIMER2_BC11 |
TIMER2_BC11 register, offset: 0x18
| __IO uint32_t USBDCD_Type::TIMER2_BC11 |
TIMER2_BC11 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC11 |
TIMER2_BC11 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC11 |
TIMER2_BC11 register, offset: 0x18
| __IO uint32_t USBHSDCD_Type::TIMER2_BC11 |
TIMER2_BC11 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC11 |
TIMER2_BC11 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC11 |
TIMER2_BC11 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC12 |
TIMER2_BC12 register, offset: 0x18
| __IO uint32_t USBDCD_Type::TIMER2_BC12 |
TIMER2_BC12 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC12 |
TIMER2_BC12 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC12 |
TIMER2_BC12 register, offset: 0x18
| __IO uint32_t USBHSDCD_Type::TIMER2_BC12 |
TIMER2_BC12 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC12 |
TIMER2_BC12 register, offset: 0x18
| __IO uint32_t { ... } ::TIMER2_BC12 |
TIMER2_BC12 register, offset: 0x18
| __I uint32_t TRNG_Type::TOTSAM |
RNG Total Samples Register, offset: 0x14
| __I uint32_t { ... } ::TOTSAM |
RNG Total Samples Register, offset: 0x14
| __IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN |
USB PHY Trim Override Enable Register, offset: 0x130
| __IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_CLR |
USB PHY Trim Override Enable Register, offset: 0x138
| __IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_SET |
USB PHY Trim Override Enable Register, offset: 0x134
| __IO uint32_t USBPHY_Type::TRIM_OVERRIDE_EN_TOG |
USB PHY Trim Override Enable Register, offset: 0x13C
| __IO uint32_t TSI_Type::TSHD |
TSI Threshold Register, offset: 0x8
| __IO uint16_t ENC_Type::TST |
Test Register, offset: 0x1C
| __I uint32_t USBHS_Type::TTCTRL |
Host TT Asynchronous Buffer Control, offset: 0x15C
| __I uint32_t RTC_Type::TTSR |
RTC Tamper Time Seconds Register, offset: 0x20
| __IO uint32_t USBPHY_Type::TX |
USB PHY Transmitter Control Register, offset: 0x10
| __IO uint32_t USBPHY_Type::TX_CLR |
USB PHY Transmitter Control Register, offset: 0x18
| __IO uint32_t USBPHY_Type::TX_SET |
USB PHY Transmitter Control Register, offset: 0x14
| __IO uint32_t USBPHY_Type::TX_TOG |
USB PHY Transmitter Control Register, offset: 0x1C
| __IO uint32_t USBHS_Type::TXFILLTUNING |
Transmit FIFO Tuning Control Register, offset: 0x164
| __I uint32_t MSCM_Type::TYPE |
Processor 0 Type Register..Processor 1 Type Register, array offset: 0x20, array step: 0x20
| __I uint32_t { ... } ::TYPE |
Processor 0 Type Register..Processor 1 Type Register, array offset: 0x20, array step: 0x20
| __IO uint16_t ENC_Type::UCOMP |
Upper Position Compare Register, offset: 0x24
| __IO uint16_t ENC_Type::UINIT |
Upper Initialization Register, offset: 0x16
| __IO uint16_t ENC_Type::UMOD |
Upper Modulus Register, offset: 0x20
| __IO uint16_t ENC_Type::UPOS |
Upper Position Counter Register, offset: 0xE
| __I uint16_t ENC_Type::UPOSH |
Upper Position Hold Register, offset: 0x12
| __I uint32_t USBPHY_Type::USB1_CHRG_DET_STAT |
USB PHY Charger Detect Status Register, offset: 0xF0
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK |
USB PHY Loopback Control/Status Register, offset: 0x110
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_CLR |
USB PHY Loopback Control/Status Register, offset: 0x118
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT |
USB PHY Loopback Packet Number Select Register, offset: 0x120
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_CLR |
USB PHY Loopback Packet Number Select Register, offset: 0x128
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_SET |
USB PHY Loopback Packet Number Select Register, offset: 0x124
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_HSFSCNT_TOG |
USB PHY Loopback Packet Number Select Register, offset: 0x12C
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_SET |
USB PHY Loopback Control/Status Register, offset: 0x114
| __IO uint32_t USBPHY_Type::USB1_LOOPBACK_TOG |
USB PHY Loopback Control/Status Register, offset: 0x11C
| __I uint32_t USBPHY_Type::USB1_VBUS_DET_STAT |
USB PHY VBUS Detector Status Register, offset: 0xD0
| __IO uint32_t USBPHY_Type::USB1_VBUS_DETECT |
USB PHY VBUS Detect Control Register, offset: 0xC0
| __IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_CLR |
USB PHY VBUS Detect Control Register, offset: 0xC8
| __IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_SET |
USB PHY VBUS Detect Control Register, offset: 0xC4
| __IO uint32_t USBPHY_Type::USB1_VBUS_DETECT_TOG |
USB PHY VBUS Detect Control Register, offset: 0xCC
| __IO uint32_t USBHS_Type::USB_SBUSCFG |
System Bus Interface Configuration Register, offset: 0x90
| __IO uint32_t USBHS_Type::USBCMD |
USB Command Register, offset: 0x140
| __IO uint32_t USBHS_Type::USBGENCTRL |
USB General Control Register, offset: 0x200
| __IO uint32_t USBHS_Type::USBINTR |
USB Interrupt Enable Register, offset: 0x148
| __IO uint32_t USBHS_Type::USBMODE |
USB Mode Register, offset: 0x1A8
| __IO uint32_t SIM_Type::USBPHYCTL |
USB PHY Control Register, offset: 0x8
| __IO uint32_t USBHS_Type::USBSTS |
USB Status Register, offset: 0x144
| __IO uint16_t { ... } ::VAL0 |
Value Register 0, array offset: 0xA, array step: 0x60
| __IO uint16_t PWM_Type::VAL0 |
Value Register 0, array offset: 0xA, array step: 0x60
| __IO uint16_t PWM_Type::VAL1 |
Value Register 1, array offset: 0xE, array step: 0x60
| __IO uint16_t { ... } ::VAL1 |
Value Register 1, array offset: 0xE, array step: 0x60
| __IO uint16_t PWM_Type::VAL2 |
Value Register 2, array offset: 0x12, array step: 0x60
| __IO uint16_t { ... } ::VAL2 |
Value Register 2, array offset: 0x12, array step: 0x60
| __IO uint16_t PWM_Type::VAL3 |
Value Register 3, array offset: 0x16, array step: 0x60
| __IO uint16_t { ... } ::VAL3 |
Value Register 3, array offset: 0x16, array step: 0x60
| __IO uint16_t PWM_Type::VAL4 |
Value Register 4, array offset: 0x1A, array step: 0x60
| __IO uint16_t { ... } ::VAL4 |
Value Register 4, array offset: 0x1A, array step: 0x60
| __IO uint16_t { ... } ::VAL5 |
Value Register 5, array offset: 0x1E, array step: 0x60
| __IO uint16_t PWM_Type::VAL5 |
Value Register 5, array offset: 0x1E, array step: 0x60
| __I uint32_t USBPHY_Type::VERSION |
UTMI RTL Version, offset: 0x80
| __I uint32_t TRNG_Type::VID1 |
RNG Version ID Register (MS), offset: 0xF0
| __I uint32_t TRNG_Type::VID2 |
RNG Version ID Register (LS), offset: 0xF4
| __IO uint32_t SIM_Type::WDOGC |
WDOG Control Register, offset: 0x1100
| __IO uint8_t UART_Type::WGP7816_T1 |
UART 7816 Wait and Guard Parameter Register, offset: 0x3E
| __IO uint32_t { ... } ::WORD0 |
Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10
| __IO uint32_t { ... } ::WORD0 |
Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10
| __IO uint32_t { ... } ::WORD0 |
Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10
| __IO uint32_t { ... } ::WORD0 |
Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10
| __IO uint32_t { ... } ::WORD1 |
Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10
| __IO uint32_t { ... } ::WORD1 |
Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10
| __IO uint32_t { ... } ::WORD1 |
Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10
| __IO uint32_t { ... } ::WORD1 |
Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10
| __IO uint8_t UART_Type::WP7816 |
UART 7816 Wait Parameter Register, offset: 0x1B
| __IO uint8_t { ... } ::WP7816A_T0 |
UART 7816 Wait Parameter Register A, offset: 0x3C
| __IO uint8_t UART_Type::WP7816A_T0 |
UART 7816 Wait Parameter Register A, offset: 0x3C
| __IO uint8_t { ... } ::WP7816A_T0 |
UART 7816 Wait Parameter Register A, offset: 0x3C
| __IO uint8_t { ... } ::WP7816A_T0 |
UART 7816 Wait Parameter Register A, offset: 0x3C
| __IO uint8_t UART_Type::WP7816A_T1 |
UART 7816 Wait Parameter Register A, offset: 0x3C
| __IO uint8_t { ... } ::WP7816A_T1 |
UART 7816 Wait Parameter Register A, offset: 0x3C
| __IO uint8_t { ... } ::WP7816A_T1 |
UART 7816 Wait Parameter Register A, offset: 0x3C
| __IO uint8_t { ... } ::WP7816A_T1 |
UART 7816 Wait Parameter Register A, offset: 0x3C
| __IO uint8_t { ... } ::WP7816B_T0 |
UART 7816 Wait Parameter Register B, offset: 0x3D
| __IO uint8_t UART_Type::WP7816B_T0 |
UART 7816 Wait Parameter Register B, offset: 0x3D
| __IO uint8_t { ... } ::WP7816B_T0 |
UART 7816 Wait Parameter Register B, offset: 0x3D
| __IO uint8_t { ... } ::WP7816B_T0 |
UART 7816 Wait Parameter Register B, offset: 0x3D
| __IO uint8_t { ... } ::WP7816B_T1 |
UART 7816 Wait Parameter Register B, offset: 0x3D
| __IO uint8_t UART_Type::WP7816B_T1 |
UART 7816 Wait Parameter Register B, offset: 0x3D
| __IO uint8_t { ... } ::WP7816B_T1 |
UART 7816 Wait Parameter Register B, offset: 0x3D
| __IO uint8_t { ... } ::WP7816B_T1 |
UART 7816 Wait Parameter Register B, offset: 0x3D
| __IO uint8_t UART_Type::WP7816C_T1 |
UART 7816 Wait Parameter Register C, offset: 0x3F
| __IO uint8_t { ... } ::WP7816T0 |
UART 7816 Wait Parameter Register, offset: 0x1B
| __IO uint8_t { ... } ::WP7816T1 |
UART 7816 Wait Parameter Register, offset: 0x1B
| __IO uint16_t ENC_Type::WTR |
Watchdog Timeout Register, offset: 0x4
| __I uint8_t FTFE_Type::XACCH0 |
Execute-only Access Registers, offset: 0x1B
| __I uint8_t FTFE_Type::XACCH1 |
Execute-only Access Registers, offset: 0x1A
| __I uint8_t FTFE_Type::XACCH2 |
Execute-only Access Registers, offset: 0x19
| __I uint8_t FTFE_Type::XACCH3 |
Execute-only Access Registers, offset: 0x18
| __I uint8_t FTFE_Type::XACCL0 |
Execute-only Access Registers, offset: 0x1F
| __I uint8_t FTFE_Type::XACCL1 |
Execute-only Access Registers, offset: 0x1E
| __I uint8_t FTFE_Type::XACCL2 |
Execute-only Access Registers, offset: 0x1D
| __I uint8_t FTFE_Type::XACCL3 |
Execute-only Access Registers, offset: 0x1C
| __IO uint16_t HSADC_Type::ZXCTRL1 |
HSADC Zero Crossing Control 1 Register, offset: 0x4
| __IO uint16_t HSADC_Type::ZXCTRL2 |
HSADC Zero Crossing Control 2 Register, offset: 0x6
| __IO uint16_t HSADC_Type::ZXSTAT |
HSADC Zero Crossing Status Register, offset: 0x1A