|
|
uint8_t | ADC_Type::RESERVED_0 [4] |
| |
|
uint8_t | AIPS_Type::RESERVED_2 [16] |
| |
| __IO uint32_t | AIPS_Type::PACRU |
| |
| __IO uint32_t AXBS_Type::PRS | |
| |
|
uint8_t AXBS_Type::RESERVED_0 [12] | |
| |
| __IO uint32_t AXBS_Type::CRS | |
| |
|
uint8_t AXBS_Type::RESERVED_1 [236] | |
| |
|
struct { | |
| |
| } | AXBS_Type::SLAVE [5] | |
| |
| __IO uint32_t CAN_Type::CS | |
| |
| __IO uint32_t CAN_Type::ID | |
| |
| __IO uint32_t CAN_Type::WORD0 | |
| |
| __IO uint32_t CAN_Type::WORD1 | |
| |
|
struct { | |
| |
| } | CAN_Type::MB [16] | |
| |
| __IO uint16_t CRC_Type::DATAL | |
| |
| __IO uint16_t CRC_Type::DATAH | |
| |
|
struct { | |
| |
| } CRC_Type::ACCESS16BIT | |
| |
| __IO uint32_t CRC_Type::DATA | |
| |
| __IO uint8_t CRC_Type::DATALL | |
| |
| __IO uint8_t CRC_Type::DATALU | |
| |
| __IO uint8_t CRC_Type::DATAHL | |
| |
| __IO uint8_t CRC_Type::DATAHU | |
| |
|
struct { | |
| |
| } CRC_Type::ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint16_t CRC_Type::GPOLYL | |
| |
| __IO uint16_t CRC_Type::GPOLYH | |
| |
|
struct { | |
| |
| } CRC_Type::GPOLY_ACCESS16BIT | |
| |
| __IO uint32_t CRC_Type::GPOLY | |
| |
| __IO uint8_t CRC_Type::GPOLYLL | |
| |
| __IO uint8_t CRC_Type::GPOLYLU | |
| |
| __IO uint8_t CRC_Type::GPOLYHL | |
| |
| __IO uint8_t CRC_Type::GPOLYHU | |
| |
|
struct { | |
| |
| } CRC_Type::GPOLY_ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t CRC_Type::CTRL | |
| |
|
uint8_t CRC_Type::RESERVED_0 [3] | |
| |
| __IO uint8_t CRC_Type::CTRLHU | |
| |
|
struct { | |
| |
| } CRC_Type::CTRL_ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint8_t DAC_Type::DATL | |
| |
| __IO uint8_t DAC_Type::DATH | |
| |
|
struct { | |
| |
| } | DAC_Type::DAT [16] | |
| |
| __I uint32_t | DMA_Type::HRS |
| |
| __IO uint32_t DMA_Type::SADDR | |
| |
| __IO uint16_t DMA_Type::SOFF | |
| |
| __IO uint16_t DMA_Type::ATTR | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLNO | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLOFFNO | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLOFFYES | |
| |
|
union { | |
| |
| } | | |
| |
| __IO uint32_t DMA_Type::SLAST | |
| |
| __IO uint32_t DMA_Type::DADDR | |
| |
| __IO uint16_t DMA_Type::DOFF | |
| |
| __IO uint16_t DMA_Type::CITER_ELINKNO | |
| |
| __IO uint16_t DMA_Type::CITER_ELINKYES | |
| |
|
union { | |
| |
| } | | |
| |
| __IO uint32_t DMA_Type::DLAST_SGA | |
| |
| __IO uint16_t DMA_Type::CSR | |
| |
| __IO uint16_t DMA_Type::BITER_ELINKNO | |
| |
| __IO uint16_t DMA_Type::BITER_ELINKYES | |
| |
|
union { | |
| |
| } | | |
| |
|
struct { | |
| |
| } | DMA_Type::TCD [16] | |
| |
| __I uint32_t | ENET_Type::RMON_T_PACKETS |
| |
| __I uint32_t | ENET_Type::RMON_T_BC_PKT |
| |
| __I uint32_t | ENET_Type::RMON_T_MC_PKT |
| |
| __I uint32_t | ENET_Type::RMON_T_CRC_ALIGN |
| |
| __I uint32_t | ENET_Type::RMON_T_UNDERSIZE |
| |
| __I uint32_t | ENET_Type::RMON_T_OVERSIZE |
| |
| __I uint32_t | ENET_Type::RMON_T_FRAG |
| |
| __I uint32_t | ENET_Type::RMON_T_JAB |
| |
| __I uint32_t | ENET_Type::RMON_T_COL |
| |
| __I uint32_t | ENET_Type::RMON_T_P64 |
| |
| __I uint32_t | ENET_Type::RMON_T_P65TO127 |
| |
| __I uint32_t | ENET_Type::RMON_T_P128TO255 |
| |
| __I uint32_t | ENET_Type::RMON_T_P256TO511 |
| |
| __I uint32_t | ENET_Type::RMON_T_P512TO1023 |
| |
| __I uint32_t | ENET_Type::RMON_T_P1024TO2047 |
| |
| __I uint32_t | ENET_Type::RMON_T_P_GTE2048 |
| |
| __I uint32_t | ENET_Type::IEEE_T_FRAME_OK |
| |
| __I uint32_t | ENET_Type::IEEE_T_1COL |
| |
| __I uint32_t | ENET_Type::IEEE_T_MCOL |
| |
| __I uint32_t | ENET_Type::IEEE_T_DEF |
| |
| __I uint32_t | ENET_Type::IEEE_T_LCOL |
| |
| __I uint32_t | ENET_Type::IEEE_T_EXCOL |
| |
| __I uint32_t | ENET_Type::IEEE_T_MACERR |
| |
| __I uint32_t | ENET_Type::IEEE_T_CSERR |
| |
| __I uint32_t | ENET_Type::IEEE_T_FDXFC |
| |
| __I uint32_t | ENET_Type::RMON_R_PACKETS |
| |
| __I uint32_t | ENET_Type::RMON_R_BC_PKT |
| |
| __I uint32_t | ENET_Type::RMON_R_MC_PKT |
| |
| __I uint32_t | ENET_Type::RMON_R_CRC_ALIGN |
| |
| __I uint32_t | ENET_Type::RMON_R_UNDERSIZE |
| |
| __I uint32_t | ENET_Type::RMON_R_OVERSIZE |
| |
| __I uint32_t | ENET_Type::RMON_R_FRAG |
| |
| __I uint32_t | ENET_Type::RMON_R_JAB |
| |
|
uint8_t | ENET_Type::RESERVED_17 [4] |
| |
| __I uint32_t | ENET_Type::RMON_R_P64 |
| |
| __I uint32_t | ENET_Type::RMON_R_P65TO127 |
| |
| __I uint32_t | ENET_Type::RMON_R_P128TO255 |
| |
| __I uint32_t | ENET_Type::RMON_R_P256TO511 |
| |
| __I uint32_t | ENET_Type::RMON_R_P512TO1023 |
| |
| __I uint32_t | ENET_Type::RMON_R_P1024TO2047 |
| |
| __I uint32_t | ENET_Type::RMON_R_P_GTE2048 |
| |
| __I uint32_t | ENET_Type::IEEE_R_DROP |
| |
| __I uint32_t | ENET_Type::IEEE_R_FRAME_OK |
| |
| __I uint32_t | ENET_Type::IEEE_R_CRC |
| |
| __I uint32_t | ENET_Type::IEEE_R_ALIGN |
| |
| __I uint32_t | ENET_Type::IEEE_R_MACERR |
| |
| __I uint32_t | ENET_Type::IEEE_R_FDXFC |
| |
|
uint8_t | ENET_Type::RESERVED_18 [284] |
| |
| __I uint32_t | ENET_Type::ATSTMP |
| |
|
uint8_t | ENET_Type::RESERVED_19 [488] |
| |
| __IO uint32_t ENET_Type::TCSR | |
| |
| __IO uint32_t ENET_Type::TCCR | |
| |
|
struct { | |
| |
| } | ENET_Type::CHANNEL [4] | |
| |
| __IO uint32_t FB_Type::CSAR | |
| |
| __IO uint32_t FB_Type::CSMR | |
| |
| __IO uint32_t FB_Type::CSCR | |
| |
|
struct { | |
| |
| } | FB_Type::CS [6] | |
| |
| __IO uint32_t | FMC_Type::TAGVDW0S [4] |
| |
| __IO uint32_t | FMC_Type::TAGVDW1S [4] |
| |
| __IO uint32_t | FMC_Type::TAGVDW2S [4] |
| |
| __IO uint32_t | FMC_Type::TAGVDW3S [4] |
| |
| __IO uint32_t FMC_Type::DATA_U | |
| |
| __IO uint32_t FMC_Type::DATA_L | |
| |
|
struct { | |
| |
| } | FMC_Type::SET [4][4] | |
| |
| __IO uint8_t | FTFE_Type::FSTAT |
| |
| __IO uint8_t | FTFE_Type::FCNFG |
| |
| __I uint8_t | FTFE_Type::FSEC |
| |
| __I uint8_t | FTFE_Type::FOPT |
| |
| __IO uint8_t | FTFE_Type::FCCOB3 |
| |
| __IO uint8_t | FTFE_Type::FCCOB2 |
| |
| __IO uint8_t | FTFE_Type::FCCOB1 |
| |
| __IO uint8_t | FTFE_Type::FCCOB0 |
| |
| __IO uint8_t | FTFE_Type::FCCOB7 |
| |
| __IO uint8_t | FTFE_Type::FCCOB6 |
| |
| __IO uint8_t | FTFE_Type::FCCOB5 |
| |
| __IO uint8_t | FTFE_Type::FCCOB4 |
| |
| __IO uint8_t | FTFE_Type::FCCOBB |
| |
| __IO uint8_t | FTFE_Type::FCCOBA |
| |
| __IO uint8_t | FTFE_Type::FCCOB9 |
| |
| __IO uint8_t | FTFE_Type::FCCOB8 |
| |
| __IO uint8_t | FTFE_Type::FPROT3 |
| |
| __IO uint8_t | FTFE_Type::FPROT2 |
| |
| __IO uint8_t | FTFE_Type::FPROT1 |
| |
| __IO uint8_t | FTFE_Type::FPROT0 |
| |
|
uint8_t | FTFE_Type::RESERVED_0 [2] |
| |
| __IO uint8_t | FTFE_Type::FEPROT |
| |
| __IO uint8_t | FTFE_Type::FDPROT |
| |
| __IO uint32_t FTM_Type::CnSC | |
| |
| __IO uint32_t FTM_Type::CnV | |
| |
|
struct { | |
| |
| } | FTM_Type::CONTROLS [8] | |
| |
| __IO uint32_t | MCM_Type::ISCR |
| |
| __IO uint32_t PDB_Type::C1 | |
| |
| __IO uint32_t PDB_Type::S | |
| |
| __IO uint32_t PDB_Type::DLY [2] | |
| |
|
uint8_t PDB_Type::RESERVED_0 [24] | |
| |
|
struct { | |
| |
| } | PDB_Type::CH [2] | |
| |
| __IO uint32_t PDB_Type::INTC | |
| |
| __IO uint32_t PDB_Type::INT | |
| |
|
struct { | |
| |
| } | PDB_Type::DAC [2] | |
| |
| __IO uint32_t PIT_Type::LDVAL | |
| |
| __I uint32_t PIT_Type::CVAL | |
| |
| __IO uint32_t PIT_Type::TCTRL | |
| |
| __IO uint32_t PIT_Type::TFLG | |
| |
|
struct { | |
| |
| } | PIT_Type::CHANNEL [4] | |
| |
| __IO uint32_t SPI_Type::CTAR [2] | |
| |
| __IO uint32_t SPI_Type::CTAR_SLAVE [1] | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t SPI_Type::PUSHR | |
| |
| __IO uint32_t SPI_Type::PUSHR_SLAVE | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t SYSMPU_Type::EAR | |
| |
| __I uint32_t SYSMPU_Type::EDR | |
| |
|
struct { | |
| |
| } | SYSMPU_Type::SP [5] | |
| |
| __IO uint8_t UART_Type::WP7816T0 | |
| |
| __IO uint8_t UART_Type::WP7816T1 | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint8_t USB_Type::ENDPT | |
| |
|
uint8_t USB_Type::RESERVED_0 [3] | |
| |
|
struct { | |
| |
| } | USB_Type::ENDPOINT [16] | |
| |
|
uint8_t | USB_Type::RESERVED_26 [43] |
| |
| __IO uint8_t | USB_Type::CLK_RECOVER_CTRL |
| |
|
uint8_t | USB_Type::RESERVED_27 [3] |
| |
| __IO uint8_t | USB_Type::CLK_RECOVER_IRC_EN |
| |
|
uint8_t | USB_Type::RESERVED_28 [23] |
| |
| __IO uint8_t | USB_Type::CLK_RECOVER_INT_STATUS |
| |
| __IO uint32_t USBDCD_Type::TIMER2_BC11 | |
| |
| __IO uint32_t USBDCD_Type::TIMER2_BC12 | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t AXBS_Type::PRS | |
| |
|
uint8_t AXBS_Type::RESERVED_0 [12] | |
| |
| __IO uint32_t AXBS_Type::CRS | |
| |
|
uint8_t AXBS_Type::RESERVED_1 [236] | |
| |
|
struct { | |
| |
| } | AXBS_Type::SLAVE [5] | |
| |
|
uint8_t | AXBS_Type::RESERVED_6 [252] |
| |
| __IO uint32_t | AXBS_Type::MGPCR6 |
| |
| __IO uint32_t CAN_Type::CS | |
| |
| __IO uint32_t CAN_Type::ID | |
| |
| __IO uint32_t CAN_Type::WORD0 | |
| |
| __IO uint32_t CAN_Type::WORD1 | |
| |
|
struct { | |
| |
| } | CAN_Type::MB [16] | |
| |
| __IO uint16_t CRC_Type::DATAL | |
| |
| __IO uint16_t CRC_Type::DATAH | |
| |
|
struct { | |
| |
| } CRC_Type::ACCESS16BIT | |
| |
| __IO uint32_t CRC_Type::DATA | |
| |
| __IO uint8_t CRC_Type::DATALL | |
| |
| __IO uint8_t CRC_Type::DATALU | |
| |
| __IO uint8_t CRC_Type::DATAHL | |
| |
| __IO uint8_t CRC_Type::DATAHU | |
| |
|
struct { | |
| |
| } CRC_Type::ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint16_t CRC_Type::GPOLYL | |
| |
| __IO uint16_t CRC_Type::GPOLYH | |
| |
|
struct { | |
| |
| } CRC_Type::GPOLY_ACCESS16BIT | |
| |
| __IO uint32_t CRC_Type::GPOLY | |
| |
| __IO uint8_t CRC_Type::GPOLYLL | |
| |
| __IO uint8_t CRC_Type::GPOLYLU | |
| |
| __IO uint8_t CRC_Type::GPOLYHL | |
| |
| __IO uint8_t CRC_Type::GPOLYHU | |
| |
|
struct { | |
| |
| } CRC_Type::GPOLY_ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t CRC_Type::CTRL | |
| |
|
uint8_t CRC_Type::RESERVED_0 [3] | |
| |
| __IO uint8_t CRC_Type::CTRLHU | |
| |
|
struct { | |
| |
| } CRC_Type::CTRL_ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint8_t DAC_Type::DATL | |
| |
| __IO uint8_t DAC_Type::DATH | |
| |
|
struct { | |
| |
| } | DAC_Type::DAT [16] | |
| |
| __IO uint32_t | DMA_Type::EARS |
| |
| __IO uint8_t | DMA_Type::DCHPRI19 |
| |
| __IO uint8_t | DMA_Type::DCHPRI18 |
| |
| __IO uint8_t | DMA_Type::DCHPRI17 |
| |
| __IO uint8_t | DMA_Type::DCHPRI16 |
| |
| __IO uint8_t | DMA_Type::DCHPRI23 |
| |
| __IO uint8_t | DMA_Type::DCHPRI22 |
| |
| __IO uint8_t | DMA_Type::DCHPRI21 |
| |
| __IO uint8_t | DMA_Type::DCHPRI20 |
| |
| __IO uint8_t | DMA_Type::DCHPRI27 |
| |
| __IO uint8_t | DMA_Type::DCHPRI26 |
| |
| __IO uint8_t | DMA_Type::DCHPRI25 |
| |
| __IO uint8_t | DMA_Type::DCHPRI24 |
| |
| __IO uint8_t | DMA_Type::DCHPRI31 |
| |
| __IO uint8_t | DMA_Type::DCHPRI30 |
| |
| __IO uint8_t | DMA_Type::DCHPRI29 |
| |
| __IO uint8_t | DMA_Type::DCHPRI28 |
| |
|
uint8_t | DMA_Type::RESERVED_7 [3808] |
| |
| __IO uint32_t DMA_Type::SADDR | |
| |
| __IO uint16_t DMA_Type::SOFF | |
| |
| __IO uint16_t DMA_Type::ATTR | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLNO | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLOFFNO | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLOFFYES | |
| |
|
union { | |
| |
| } | | |
| |
| __IO uint32_t DMA_Type::SLAST | |
| |
| __IO uint32_t DMA_Type::DADDR | |
| |
| __IO uint16_t DMA_Type::DOFF | |
| |
| __IO uint16_t DMA_Type::CITER_ELINKNO | |
| |
| __IO uint16_t DMA_Type::CITER_ELINKYES | |
| |
|
union { | |
| |
| } | | |
| |
| __IO uint32_t DMA_Type::DLAST_SGA | |
| |
| __IO uint16_t DMA_Type::CSR | |
| |
| __IO uint16_t DMA_Type::BITER_ELINKNO | |
| |
| __IO uint16_t DMA_Type::BITER_ELINKYES | |
| |
|
union { | |
| |
| } | | |
| |
|
struct { | |
| |
| } | DMA_Type::TCD [32] | |
| |
| uint32_t | ENET_Type::RMON_T_DROP |
| |
| uint32_t | ENET_Type::IEEE_T_DROP |
| |
| __I uint32_t | ENET_Type::IEEE_T_SQE |
| |
| uint32_t | ENET_Type::RMON_R_RESVD_0 |
| |
| __IO uint32_t ENET_Type::TCSR | |
| |
| __IO uint32_t ENET_Type::TCCR | |
| |
|
struct { | |
| |
| } | ENET_Type::CHANNEL [4] | |
| |
| __IO uint32_t FB_Type::CSAR | |
| |
| __IO uint32_t FB_Type::CSMR | |
| |
| __IO uint32_t FB_Type::CSCR | |
| |
|
struct { | |
| |
| } | FB_Type::CS [6] | |
| |
| __IO uint32_t | FMC_Type::PFB01CR |
| |
| __IO uint32_t | FMC_Type::PFB23CR |
| |
| __IO uint32_t FMC_Type::DATA_UM | |
| |
| __IO uint32_t FMC_Type::DATA_MU | |
| |
| __IO uint32_t FMC_Type::DATA_ML | |
| |
| __IO uint32_t FMC_Type::DATA_LM | |
| |
|
struct { | |
| |
| } | FMC_Type::SET [4][4] | |
| |
| __I uint8_t | FTFE_Type::XACCH3 |
| |
| __I uint8_t | FTFE_Type::XACCH2 |
| |
| __I uint8_t | FTFE_Type::XACCH1 |
| |
| __I uint8_t | FTFE_Type::XACCH0 |
| |
| __I uint8_t | FTFE_Type::XACCL3 |
| |
| __I uint8_t | FTFE_Type::XACCL2 |
| |
| __I uint8_t | FTFE_Type::XACCL1 |
| |
| __I uint8_t | FTFE_Type::XACCL0 |
| |
| __I uint8_t | FTFE_Type::SACCH3 |
| |
| __I uint8_t | FTFE_Type::SACCH2 |
| |
| __I uint8_t | FTFE_Type::SACCH1 |
| |
| __I uint8_t | FTFE_Type::SACCH0 |
| |
| __I uint8_t | FTFE_Type::SACCL3 |
| |
| __I uint8_t | FTFE_Type::SACCL2 |
| |
| __I uint8_t | FTFE_Type::SACCL1 |
| |
| __I uint8_t | FTFE_Type::SACCL0 |
| |
| __I uint8_t | FTFE_Type::FACSS |
| |
|
uint8_t | FTFE_Type::RESERVED_1 [2] |
| |
| __I uint8_t | FTFE_Type::FACSN |
| |
| __IO uint32_t FTM_Type::CnSC | |
| |
| __IO uint32_t FTM_Type::CnV | |
| |
|
struct { | |
| |
| } | FTM_Type::CONTROLS [8] | |
| |
| __IO uint8_t | LLWU_Type::PE5 |
| |
| __IO uint8_t | LLWU_Type::PE6 |
| |
| __IO uint8_t | LLWU_Type::PE7 |
| |
| __IO uint8_t | LLWU_Type::PE8 |
| |
| __IO uint8_t | LLWU_Type::PF1 |
| |
| __IO uint8_t | LLWU_Type::PF2 |
| |
| __IO uint8_t | LLWU_Type::PF3 |
| |
| __IO uint8_t | LLWU_Type::PF4 |
| |
| __I uint8_t | LLWU_Type::MF5 |
| |
| __IO uint8_t | LLWU_Type::FILT3 |
| |
| __IO uint8_t | LLWU_Type::FILT4 |
| |
| __IO uint32_t | LMEM_Type::PCCCR |
| |
| __IO uint32_t | LMEM_Type::PCCLCR |
| |
| __IO uint32_t | LMEM_Type::PCCSAR |
| |
| __IO uint32_t | LMEM_Type::PCCCVR |
| |
|
uint8_t | LMEM_Type::RESERVED_0 [16] |
| |
| __IO uint32_t | LMEM_Type::PCCRMR |
| |
| __IO uint32_t | LPUART_Type::BAUD |
| |
| __IO uint32_t | LPUART_Type::STAT |
| |
| __IO uint32_t | LPUART_Type::CTRL |
| |
| __IO uint32_t | LPUART_Type::DATA |
| |
| __IO uint32_t | LPUART_Type::MATCH |
| |
| __IO uint32_t | LPUART_Type::MODIR |
| |
| __IO uint8_t | MCG_Type::C9 |
| |
|
uint8_t | MCG_Type::RESERVED_2 [1] |
| |
| __IO uint8_t | MCG_Type::C11 |
| |
|
uint8_t | MCG_Type::RESERVED_3 [1] |
| |
| __I uint8_t | MCG_Type::S2 |
| |
| __I uint32_t | MCM_Type::FADR |
| |
| __I uint32_t | MCM_Type::FATR |
| |
| __I uint32_t | MCM_Type::FDR |
| |
|
uint8_t | MCM_Type::RESERVED_2 [12] |
| |
| __IO uint32_t | MCM_Type::CPO |
| |
|
uint8_t | OSC_Type::RESERVED_0 [1] |
| |
| __IO uint8_t | OSC_Type::DIV |
| |
| __IO uint32_t PDB_Type::C1 | |
| |
| __IO uint32_t PDB_Type::S | |
| |
| __IO uint32_t PDB_Type::DLY [2] | |
| |
|
uint8_t PDB_Type::RESERVED_0 [24] | |
| |
|
struct { | |
| |
| } | PDB_Type::CH [2] | |
| |
| __IO uint32_t PDB_Type::INTC | |
| |
| __IO uint32_t PDB_Type::INT | |
| |
|
struct { | |
| |
| } | PDB_Type::DAC [2] | |
| |
| __I uint32_t | PIT_Type::LTMR64H |
| |
| __I uint32_t | PIT_Type::LTMR64L |
| |
|
uint8_t | PIT_Type::RESERVED_1 [24] |
| |
| __IO uint32_t PIT_Type::LDVAL | |
| |
| __I uint32_t PIT_Type::CVAL | |
| |
| __IO uint32_t PIT_Type::TCTRL | |
| |
| __IO uint32_t PIT_Type::TFLG | |
| |
|
struct { | |
| |
| } | PIT_Type::CHANNEL [4] | |
| |
| __IO uint8_t | RCM_Type::SSRS0 |
| |
| __IO uint8_t | RCM_Type::SSRS1 |
| |
| __I uint32_t | RTC_Type::TTSR |
| |
| __IO uint32_t | RTC_Type::MER |
| |
| __IO uint32_t | RTC_Type::MCLR |
| |
| __IO uint32_t | RTC_Type::MCHR |
| |
|
uint8_t | SDRAM_Type::RESERVED_0 [66] |
| |
| __IO uint16_t | SDRAM_Type::CTRL |
| |
|
uint8_t | SDRAM_Type::RESERVED_1 [4] |
| |
| __IO uint32_t SDRAM_Type::AC | |
| |
| __IO uint32_t SDRAM_Type::CM | |
| |
|
struct { | |
| |
| } | SDRAM_Type::BLOCK [2] | |
| |
| __IO uint32_t | SIM_Type::USBPHYCTL |
| |
| __IO uint32_t | SIM_Type::SOPT8 |
| |
| __IO uint32_t | SIM_Type::SOPT9 |
| |
| __IO uint32_t | SIM_Type::CLKDIV3 |
| |
| __IO uint32_t | SIM_Type::CLKDIV4 |
| |
| __IO uint8_t | SMC_Type::STOPCTRL |
| |
| __IO uint32_t SPI_Type::CTAR [2] | |
| |
| __IO uint32_t SPI_Type::CTAR_SLAVE [1] | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t SPI_Type::PUSHR | |
| |
| __IO uint32_t SPI_Type::PUSHR_SLAVE | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t SYSMPU_Type::EAR | |
| |
| __I uint32_t SYSMPU_Type::EDR | |
| |
|
struct { | |
| |
| } | SYSMPU_Type::SP [5] | |
| |
| __IO uint32_t | TPM_Type::SC |
| |
| __IO uint32_t | TPM_Type::CNT |
| |
| __IO uint32_t | TPM_Type::MOD |
| |
| __IO uint32_t TPM_Type::CnSC | |
| |
| __IO uint32_t TPM_Type::CnV | |
| |
|
struct { | |
| |
| } | TPM_Type::CONTROLS [2] | |
| |
|
uint8_t | TPM_Type::RESERVED_0 [52] |
| |
| __IO uint32_t | TPM_Type::STATUS |
| |
|
uint8_t | TPM_Type::RESERVED_1 [16] |
| |
| __IO uint32_t | TPM_Type::COMBINE |
| |
|
uint8_t | TPM_Type::RESERVED_2 [8] |
| |
| __IO uint32_t | TPM_Type::POL |
| |
|
uint8_t | TPM_Type::RESERVED_3 [4] |
| |
| __IO uint32_t | TPM_Type::FILTER |
| |
|
uint8_t | TPM_Type::RESERVED_4 [4] |
| |
| __IO uint32_t | TPM_Type::QDCTRL |
| |
| __IO uint32_t | TPM_Type::CONF |
| |
| __IO uint32_t | TSI_Type::DATA |
| |
| __IO uint32_t | TSI_Type::TSHD |
| |
| __IO uint8_t | UART_Type::WP7816 |
| |
| __IO uint8_t | UART_Type::AP7816A_T0 |
| |
| __IO uint8_t | UART_Type::AP7816B_T0 |
| |
| __IO uint8_t UART_Type::WP7816A_T0 | |
| |
| __IO uint8_t UART_Type::WP7816B_T0 | |
| |
|
struct { | |
| |
| } UART_Type::TYPE0 | |
| |
| __IO uint8_t UART_Type::WP7816A_T1 | |
| |
| __IO uint8_t UART_Type::WP7816B_T1 | |
| |
|
struct { | |
| |
| } UART_Type::TYPE1 | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint8_t | UART_Type::WGP7816_T1 |
| |
| __IO uint8_t | UART_Type::WP7816C_T1 |
| |
| __IO uint8_t USB_Type::ENDPT | |
| |
|
uint8_t USB_Type::RESERVED_0 [3] | |
| |
|
struct { | |
| |
| } | USB_Type::ENDPOINT [16] | |
| |
| __IO uint8_t | USB_Type::CLK_RECOVER_INT_EN |
| |
|
uint8_t | USB_Type::RESERVED_29 [7] |
| |
| __IO uint32_t | USBDCD_Type::SIGNAL_OVERRIDE |
| |
| __IO uint32_t USBDCD_Type::TIMER2_BC11 | |
| |
| __IO uint32_t USBDCD_Type::TIMER2_BC12 | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t | USBHS_Type::ID |
| |
| __I uint32_t | USBHS_Type::HWGENERAL |
| |
| __I uint32_t | USBHS_Type::HWHOST |
| |
| __I uint32_t | USBHS_Type::HWDEVICE |
| |
| __I uint32_t | USBHS_Type::HWTXBUF |
| |
| __I uint32_t | USBHS_Type::HWRXBUF |
| |
|
uint8_t | USBHS_Type::RESERVED_0 [104] |
| |
| __IO uint32_t | USBHS_Type::GPTIMER0LD |
| |
| __IO uint32_t | USBHS_Type::GPTIMER0CTL |
| |
| __IO uint32_t | USBHS_Type::GPTIMER1LD |
| |
| __IO uint32_t | USBHS_Type::GPTIMER1CTL |
| |
| __IO uint32_t | USBHS_Type::USB_SBUSCFG |
| |
|
uint8_t | USBHS_Type::RESERVED_1 [108] |
| |
| __I uint32_t | USBHS_Type::HCIVERSION |
| |
| __I uint32_t | USBHS_Type::HCSPARAMS |
| |
| __I uint32_t | USBHS_Type::HCCPARAMS |
| |
|
uint8_t | USBHS_Type::RESERVED_2 [22] |
| |
| __I uint16_t | USBHS_Type::DCIVERSION |
| |
| __I uint32_t | USBHS_Type::DCCPARAMS |
| |
|
uint8_t | USBHS_Type::RESERVED_3 [24] |
| |
| __IO uint32_t | USBHS_Type::USBCMD |
| |
| __IO uint32_t | USBHS_Type::USBSTS |
| |
| __IO uint32_t | USBHS_Type::USBINTR |
| |
| __IO uint32_t | USBHS_Type::FRINDEX |
| |
|
uint8_t | USBHS_Type::RESERVED_4 [4] |
| |
| __IO uint32_t USBHS_Type::DEVICEADDR | |
| |
| __IO uint32_t USBHS_Type::PERIODICLISTBASE | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t USBHS_Type::ASYNCLISTADDR | |
| |
| __IO uint32_t USBHS_Type::EPLISTADDR | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t | USBHS_Type::TTCTRL |
| |
| __IO uint32_t | USBHS_Type::BURSTSIZE |
| |
| __IO uint32_t | USBHS_Type::TXFILLTUNING |
| |
|
uint8_t | USBHS_Type::RESERVED_5 [16] |
| |
| __IO uint32_t | USBHS_Type::ENDPTNAK |
| |
| __IO uint32_t | USBHS_Type::ENDPTNAKEN |
| |
| uint32_t | USBHS_Type::CONFIGFLAG |
| |
| __IO uint32_t | USBHS_Type::PORTSC1 |
| |
|
uint8_t | USBHS_Type::RESERVED_6 [28] |
| |
| __IO uint32_t | USBHS_Type::OTGSC |
| |
| __IO uint32_t | USBHS_Type::USBMODE |
| |
| __IO uint32_t | USBHS_Type::EPSETUPSR |
| |
| __IO uint32_t | USBHS_Type::EPPRIME |
| |
| __IO uint32_t | USBHS_Type::EPFLUSH |
| |
| __I uint32_t | USBHS_Type::EPSR |
| |
| __IO uint32_t | USBHS_Type::EPCOMPLETE |
| |
| __IO uint32_t | USBHS_Type::EPCR0 |
| |
| __IO uint32_t | USBHS_Type::EPCR [7] |
| |
|
uint8_t | USBHS_Type::RESERVED_7 [32] |
| |
| __IO uint32_t | USBHS_Type::USBGENCTRL |
| |
| __IO uint32_t | USBHSDCD_Type::CONTROL |
| |
| __IO uint32_t | USBHSDCD_Type::CLOCK |
| |
| __I uint32_t | USBHSDCD_Type::STATUS |
| |
| __IO uint32_t | USBHSDCD_Type::SIGNAL_OVERRIDE |
| |
| __IO uint32_t | USBHSDCD_Type::TIMER0 |
| |
| __IO uint32_t | USBHSDCD_Type::TIMER1 |
| |
| __IO uint32_t USBHSDCD_Type::TIMER2_BC11 | |
| |
| __IO uint32_t USBHSDCD_Type::TIMER2_BC12 | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t | USBPHY_Type::PWD |
| |
| __IO uint32_t | USBPHY_Type::PWD_SET |
| |
| __IO uint32_t | USBPHY_Type::PWD_CLR |
| |
| __IO uint32_t | USBPHY_Type::PWD_TOG |
| |
| __IO uint32_t | USBPHY_Type::TX |
| |
| __IO uint32_t | USBPHY_Type::TX_SET |
| |
| __IO uint32_t | USBPHY_Type::TX_CLR |
| |
| __IO uint32_t | USBPHY_Type::TX_TOG |
| |
| __IO uint32_t | USBPHY_Type::RX |
| |
| __IO uint32_t | USBPHY_Type::RX_SET |
| |
| __IO uint32_t | USBPHY_Type::RX_CLR |
| |
| __IO uint32_t | USBPHY_Type::RX_TOG |
| |
| __IO uint32_t | USBPHY_Type::CTRL |
| |
| __IO uint32_t | USBPHY_Type::CTRL_SET |
| |
| __IO uint32_t | USBPHY_Type::CTRL_CLR |
| |
| __IO uint32_t | USBPHY_Type::CTRL_TOG |
| |
| __IO uint32_t | USBPHY_Type::STATUS |
| |
|
uint8_t | USBPHY_Type::RESERVED_0 [12] |
| |
| __IO uint32_t | USBPHY_Type::DEBUGr |
| |
| __IO uint32_t | USBPHY_Type::DEBUG_SET |
| |
| __IO uint32_t | USBPHY_Type::DEBUG_CLR |
| |
| __IO uint32_t | USBPHY_Type::DEBUG_TOG |
| |
| __I uint32_t | USBPHY_Type::DEBUG0_STATUS |
| |
|
uint8_t | USBPHY_Type::RESERVED_1 [12] |
| |
| __IO uint32_t | USBPHY_Type::DEBUG1 |
| |
| __IO uint32_t | USBPHY_Type::DEBUG1_SET |
| |
| __IO uint32_t | USBPHY_Type::DEBUG1_CLR |
| |
| __IO uint32_t | USBPHY_Type::DEBUG1_TOG |
| |
| __I uint32_t | USBPHY_Type::VERSION |
| |
|
uint8_t | USBPHY_Type::RESERVED_2 [28] |
| |
| __IO uint32_t | USBPHY_Type::PLL_SIC |
| |
| __IO uint32_t | USBPHY_Type::PLL_SIC_SET |
| |
| __IO uint32_t | USBPHY_Type::PLL_SIC_CLR |
| |
| __IO uint32_t | USBPHY_Type::PLL_SIC_TOG |
| |
|
uint8_t | USBPHY_Type::RESERVED_3 [16] |
| |
| __IO uint32_t | USBPHY_Type::USB1_VBUS_DETECT |
| |
| __IO uint32_t | USBPHY_Type::USB1_VBUS_DETECT_SET |
| |
| __IO uint32_t | USBPHY_Type::USB1_VBUS_DETECT_CLR |
| |
| __IO uint32_t | USBPHY_Type::USB1_VBUS_DETECT_TOG |
| |
| __I uint32_t | USBPHY_Type::USB1_VBUS_DET_STAT |
| |
|
uint8_t | USBPHY_Type::RESERVED_4 [28] |
| |
| __I uint32_t | USBPHY_Type::USB1_CHRG_DET_STAT |
| |
|
uint8_t | USBPHY_Type::RESERVED_5 [12] |
| |
| __IO uint32_t | USBPHY_Type::ANACTRL |
| |
| __IO uint32_t | USBPHY_Type::ANACTRL_SET |
| |
| __IO uint32_t | USBPHY_Type::ANACTRL_CLR |
| |
| __IO uint32_t | USBPHY_Type::ANACTRL_TOG |
| |
| __IO uint32_t | USBPHY_Type::USB1_LOOPBACK |
| |
| __IO uint32_t | USBPHY_Type::USB1_LOOPBACK_SET |
| |
| __IO uint32_t | USBPHY_Type::USB1_LOOPBACK_CLR |
| |
| __IO uint32_t | USBPHY_Type::USB1_LOOPBACK_TOG |
| |
| __IO uint32_t | USBPHY_Type::USB1_LOOPBACK_HSFSCNT |
| |
| __IO uint32_t | USBPHY_Type::USB1_LOOPBACK_HSFSCNT_SET |
| |
| __IO uint32_t | USBPHY_Type::USB1_LOOPBACK_HSFSCNT_CLR |
| |
| __IO uint32_t | USBPHY_Type::USB1_LOOPBACK_HSFSCNT_TOG |
| |
| __IO uint32_t | USBPHY_Type::TRIM_OVERRIDE_EN |
| |
| __IO uint32_t | USBPHY_Type::TRIM_OVERRIDE_EN_SET |
| |
| __IO uint32_t | USBPHY_Type::TRIM_OVERRIDE_EN_CLR |
| |
| __IO uint32_t | USBPHY_Type::TRIM_OVERRIDE_EN_TOG |
| |
| __IO uint32_t AXBS_Type::PRS | |
| |
|
uint8_t AXBS_Type::RESERVED_0 [12] | |
| |
| __IO uint32_t AXBS_Type::CRS | |
| |
|
uint8_t AXBS_Type::RESERVED_1 [236] | |
| |
|
struct { | |
| |
| } | AXBS_Type::SLAVE [5] | |
| |
| __IO uint32_t CAN_Type::CS | |
| |
| __IO uint32_t CAN_Type::ID | |
| |
| __IO uint32_t CAN_Type::WORD0 | |
| |
| __IO uint32_t CAN_Type::WORD1 | |
| |
|
struct { | |
| |
| } | CAN_Type::MB [16] | |
| |
| __IO uint16_t CRC_Type::DATAL | |
| |
| __IO uint16_t CRC_Type::DATAH | |
| |
|
struct { | |
| |
| } CRC_Type::ACCESS16BIT | |
| |
| __IO uint32_t CRC_Type::DATA | |
| |
| __IO uint8_t CRC_Type::DATALL | |
| |
| __IO uint8_t CRC_Type::DATALU | |
| |
| __IO uint8_t CRC_Type::DATAHL | |
| |
| __IO uint8_t CRC_Type::DATAHU | |
| |
|
struct { | |
| |
| } CRC_Type::ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint16_t CRC_Type::GPOLYL | |
| |
| __IO uint16_t CRC_Type::GPOLYH | |
| |
|
struct { | |
| |
| } CRC_Type::GPOLY_ACCESS16BIT | |
| |
| __IO uint32_t CRC_Type::GPOLY | |
| |
| __IO uint8_t CRC_Type::GPOLYLL | |
| |
| __IO uint8_t CRC_Type::GPOLYLU | |
| |
| __IO uint8_t CRC_Type::GPOLYHL | |
| |
| __IO uint8_t CRC_Type::GPOLYHU | |
| |
|
struct { | |
| |
| } CRC_Type::GPOLY_ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t CRC_Type::CTRL | |
| |
|
uint8_t CRC_Type::RESERVED_0 [3] | |
| |
| __IO uint8_t CRC_Type::CTRLHU | |
| |
|
struct { | |
| |
| } CRC_Type::CTRL_ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint8_t DAC_Type::DATL | |
| |
| __IO uint8_t DAC_Type::DATH | |
| |
|
struct { | |
| |
| } | DAC_Type::DAT [16] | |
| |
| __IO uint32_t DMA_Type::SADDR | |
| |
| __IO uint16_t DMA_Type::SOFF | |
| |
| __IO uint16_t DMA_Type::ATTR | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLNO | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLOFFNO | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLOFFYES | |
| |
|
union { | |
| |
| } | | |
| |
| __IO uint32_t DMA_Type::SLAST | |
| |
| __IO uint32_t DMA_Type::DADDR | |
| |
| __IO uint16_t DMA_Type::DOFF | |
| |
| __IO uint16_t DMA_Type::CITER_ELINKNO | |
| |
| __IO uint16_t DMA_Type::CITER_ELINKYES | |
| |
|
union { | |
| |
| } | | |
| |
| __IO uint32_t DMA_Type::DLAST_SGA | |
| |
| __IO uint16_t DMA_Type::CSR | |
| |
| __IO uint16_t DMA_Type::BITER_ELINKNO | |
| |
| __IO uint16_t DMA_Type::BITER_ELINKYES | |
| |
|
union { | |
| |
| } | | |
| |
|
struct { | |
| |
| } | DMA_Type::TCD [32] | |
| |
| __IO uint32_t ENET_Type::TCSR | |
| |
| __IO uint32_t ENET_Type::TCCR | |
| |
|
struct { | |
| |
| } | ENET_Type::CHANNEL [4] | |
| |
| __IO uint32_t FB_Type::CSAR | |
| |
| __IO uint32_t FB_Type::CSMR | |
| |
| __IO uint32_t FB_Type::CSCR | |
| |
|
struct { | |
| |
| } | FB_Type::CS [6] | |
| |
| __IO uint32_t FMC_Type::DATA_UM | |
| |
| __IO uint32_t FMC_Type::DATA_MU | |
| |
| __IO uint32_t FMC_Type::DATA_ML | |
| |
| __IO uint32_t FMC_Type::DATA_LM | |
| |
|
struct { | |
| |
| } | FMC_Type::SET [4][4] | |
| |
| __IO uint32_t FTM_Type::CnSC | |
| |
| __IO uint32_t FTM_Type::CnV | |
| |
|
struct { | |
| |
| } | FTM_Type::CONTROLS [8] | |
| |
| __IO uint32_t PDB_Type::C1 | |
| |
| __IO uint32_t PDB_Type::S | |
| |
| __IO uint32_t PDB_Type::DLY [2] | |
| |
|
uint8_t PDB_Type::RESERVED_0 [24] | |
| |
|
struct { | |
| |
| } | PDB_Type::CH [2] | |
| |
| __IO uint32_t PDB_Type::INTC | |
| |
| __IO uint32_t PDB_Type::INT | |
| |
|
struct { | |
| |
| } | PDB_Type::DAC [2] | |
| |
| __IO uint32_t PIT_Type::LDVAL | |
| |
| __I uint32_t PIT_Type::CVAL | |
| |
| __IO uint32_t PIT_Type::TCTRL | |
| |
| __IO uint32_t PIT_Type::TFLG | |
| |
|
struct { | |
| |
| } | PIT_Type::CHANNEL [4] | |
| |
| __IO uint32_t SDRAM_Type::AC | |
| |
| __IO uint32_t SDRAM_Type::CM | |
| |
|
struct { | |
| |
| } | SDRAM_Type::BLOCK [2] | |
| |
| __IO uint32_t SPI_Type::CTAR [2] | |
| |
| __IO uint32_t SPI_Type::CTAR_SLAVE [1] | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t SPI_Type::PUSHR | |
| |
| __IO uint32_t SPI_Type::PUSHR_SLAVE | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t SYSMPU_Type::EAR | |
| |
| __I uint32_t SYSMPU_Type::EDR | |
| |
|
struct { | |
| |
| } | SYSMPU_Type::SP [5] | |
| |
| __IO uint32_t TPM_Type::CnSC | |
| |
| __IO uint32_t TPM_Type::CnV | |
| |
|
struct { | |
| |
| } | TPM_Type::CONTROLS [2] | |
| |
| __IO uint8_t UART_Type::WP7816A_T0 | |
| |
| __IO uint8_t UART_Type::WP7816B_T0 | |
| |
|
struct { | |
| |
| } UART_Type::TYPE0 | |
| |
| __IO uint8_t UART_Type::WP7816A_T1 | |
| |
| __IO uint8_t UART_Type::WP7816B_T1 | |
| |
|
struct { | |
| |
| } UART_Type::TYPE1 | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint8_t USB_Type::ENDPT | |
| |
|
uint8_t USB_Type::RESERVED_0 [3] | |
| |
|
struct { | |
| |
| } | USB_Type::ENDPOINT [16] | |
| |
| __IO uint32_t USBDCD_Type::TIMER2_BC11 | |
| |
| __IO uint32_t USBDCD_Type::TIMER2_BC12 | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t USBHS_Type::DEVICEADDR | |
| |
| __IO uint32_t USBHS_Type::PERIODICLISTBASE | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t USBHS_Type::ASYNCLISTADDR | |
| |
| __IO uint32_t USBHS_Type::EPLISTADDR | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t USBHSDCD_Type::TIMER2_BC11 | |
| |
| __IO uint32_t USBHSDCD_Type::TIMER2_BC12 | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint16_t AOI_Type::BFCRT01 | |
| |
| __IO uint16_t AOI_Type::BFCRT23 | |
| |
|
struct { | |
| |
| } | AOI_Type::BFCRT [4] | |
| |
| __IO uint32_t AXBS_Type::PRS | |
| |
|
uint8_t AXBS_Type::RESERVED_0 [12] | |
| |
| __IO uint32_t AXBS_Type::CRS | |
| |
|
uint8_t AXBS_Type::RESERVED_1 [236] | |
| |
|
struct { | |
| |
| } | AXBS_Type::SLAVE [7] | |
| |
| __IO uint32_t | CAN_Type::CBT |
| |
| __IO uint32_t CAN_Type::CS | |
| |
| __IO uint32_t CAN_Type::ID | |
| |
| __IO uint32_t CAN_Type::WORD0 | |
| |
| __IO uint32_t CAN_Type::WORD1 | |
| |
|
struct { | |
| |
| } | CAN_Type::MB [16] | |
| |
| __IO uint16_t CRC_Type::DATAL | |
| |
| __IO uint16_t CRC_Type::DATAH | |
| |
|
struct { | |
| |
| } CRC_Type::ACCESS16BIT | |
| |
| __IO uint32_t CRC_Type::DATA | |
| |
| __IO uint8_t CRC_Type::DATALL | |
| |
| __IO uint8_t CRC_Type::DATALU | |
| |
| __IO uint8_t CRC_Type::DATAHL | |
| |
| __IO uint8_t CRC_Type::DATAHU | |
| |
|
struct { | |
| |
| } CRC_Type::ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint16_t CRC_Type::GPOLYL | |
| |
| __IO uint16_t CRC_Type::GPOLYH | |
| |
|
struct { | |
| |
| } CRC_Type::GPOLY_ACCESS16BIT | |
| |
| __IO uint32_t CRC_Type::GPOLY | |
| |
| __IO uint8_t CRC_Type::GPOLYLL | |
| |
| __IO uint8_t CRC_Type::GPOLYLU | |
| |
| __IO uint8_t CRC_Type::GPOLYHL | |
| |
| __IO uint8_t CRC_Type::GPOLYHU | |
| |
|
struct { | |
| |
| } CRC_Type::GPOLY_ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t CRC_Type::CTRL | |
| |
|
uint8_t CRC_Type::RESERVED_0 [3] | |
| |
| __IO uint8_t CRC_Type::CTRLHU | |
| |
|
struct { | |
| |
| } CRC_Type::CTRL_ACCESS8BIT | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint8_t DAC_Type::DATL | |
| |
| __IO uint8_t DAC_Type::DATH | |
| |
|
struct { | |
| |
| } | DAC_Type::DAT [16] | |
| |
| __IO uint32_t DMA_Type::SADDR | |
| |
| __IO uint16_t DMA_Type::SOFF | |
| |
| __IO uint16_t DMA_Type::ATTR | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLNO | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLOFFNO | |
| |
| __IO uint32_t DMA_Type::NBYTES_MLOFFYES | |
| |
|
union { | |
| |
| } | | |
| |
| __IO uint32_t DMA_Type::SLAST | |
| |
| __IO uint32_t DMA_Type::DADDR | |
| |
| __IO uint16_t DMA_Type::DOFF | |
| |
| __IO uint16_t DMA_Type::CITER_ELINKNO | |
| |
| __IO uint16_t DMA_Type::CITER_ELINKYES | |
| |
|
union { | |
| |
| } | | |
| |
| __IO uint32_t DMA_Type::DLAST_SGA | |
| |
| __IO uint16_t DMA_Type::CSR | |
| |
| __IO uint16_t DMA_Type::BITER_ELINKNO | |
| |
| __IO uint16_t DMA_Type::BITER_ELINKYES | |
| |
|
union { | |
| |
| } | | |
| |
|
struct { | |
| |
| } | DMA_Type::TCD [32] | |
| |
| __IO uint16_t | ENC_Type::CTRL |
| |
| __IO uint16_t | ENC_Type::FILT |
| |
| __IO uint16_t | ENC_Type::WTR |
| |
| __IO uint16_t | ENC_Type::POSD |
| |
| __I uint16_t | ENC_Type::POSDH |
| |
| __IO uint16_t | ENC_Type::REV |
| |
| __I uint16_t | ENC_Type::REVH |
| |
| __IO uint16_t | ENC_Type::UPOS |
| |
| __IO uint16_t | ENC_Type::LPOS |
| |
| __I uint16_t | ENC_Type::UPOSH |
| |
| __I uint16_t | ENC_Type::LPOSH |
| |
| __IO uint16_t | ENC_Type::UINIT |
| |
| __IO uint16_t | ENC_Type::LINIT |
| |
| __I uint16_t | ENC_Type::IMR |
| |
| __IO uint16_t | ENC_Type::TST |
| |
| __IO uint16_t | ENC_Type::CTRL2 |
| |
| __IO uint16_t | ENC_Type::UMOD |
| |
| __IO uint16_t | ENC_Type::LMOD |
| |
| __IO uint16_t | ENC_Type::UCOMP |
| |
| __IO uint16_t | ENC_Type::LCOMP |
| |
| __IO uint32_t ENET_Type::TCSR | |
| |
| __IO uint32_t ENET_Type::TCCR | |
| |
|
struct { | |
| |
| } | ENET_Type::CHANNEL [4] | |
| |
| __IO uint8_t | EWM_Type::CLKCTRL |
| |
| __IO uint32_t FB_Type::CSAR | |
| |
| __IO uint32_t FB_Type::CSMR | |
| |
| __IO uint32_t FB_Type::CSCR | |
| |
|
struct { | |
| |
| } | FB_Type::CS [6] | |
| |
| __IO uint32_t FTM_Type::CnSC | |
| |
| __IO uint32_t FTM_Type::CnV | |
| |
|
struct { | |
| |
| } | FTM_Type::CONTROLS [8] | |
| |
| __IO uint16_t | HSADC_Type::CTRL1 |
| |
| __IO uint16_t | HSADC_Type::CTRL2 |
| |
| __IO uint16_t | HSADC_Type::ZXCTRL1 |
| |
| __IO uint16_t | HSADC_Type::ZXCTRL2 |
| |
| __IO uint16_t | HSADC_Type::CLIST1 |
| |
| __IO uint16_t | HSADC_Type::CLIST2 |
| |
| __IO uint16_t | HSADC_Type::CLIST3 |
| |
| __IO uint16_t | HSADC_Type::CLIST4 |
| |
| __IO uint16_t | HSADC_Type::SDIS |
| |
| __IO uint16_t | HSADC_Type::STAT |
| |
| __I uint16_t | HSADC_Type::RDY |
| |
| __IO uint16_t | HSADC_Type::LOLIMSTAT |
| |
| __IO uint16_t | HSADC_Type::HILIMSTAT |
| |
| __IO uint16_t | HSADC_Type::ZXSTAT |
| |
| __IO uint16_t | HSADC_Type::RSLT [16] |
| |
| __IO uint16_t | HSADC_Type::LOLIM [16] |
| |
| __IO uint16_t | HSADC_Type::HILIM [16] |
| |
| __IO uint16_t | HSADC_Type::OFFST [16] |
| |
| __IO uint16_t | HSADC_Type::PWR |
| |
|
uint8_t | HSADC_Type::RESERVED_0 [6] |
| |
| __IO uint16_t | HSADC_Type::SCTRL |
| |
| __IO uint16_t | HSADC_Type::PWR2 |
| |
| __IO uint16_t | HSADC_Type::CTRL3 |
| |
| __IO uint16_t | HSADC_Type::SCINTEN |
| |
| __IO uint16_t | HSADC_Type::SAMPTIM |
| |
| __IO uint16_t | HSADC_Type::CALIB |
| |
| __IO uint16_t | HSADC_Type::CALVAL_A |
| |
| __IO uint16_t | HSADC_Type::CALVAL_B |
| |
|
uint8_t | HSADC_Type::RESERVED_1 [6] |
| |
| __IO uint16_t | HSADC_Type::MUX67_SEL |
| |
| __I uint32_t | MCM_Type::PCT |
| |
| __I uint32_t | MCM_Type::LMEM [5] |
| |
| __I uint32_t | MSCM_Type::CPxTYPE |
| |
| __I uint32_t | MSCM_Type::CPxNUM |
| |
| __I uint32_t | MSCM_Type::CPxMASTER |
| |
| __I uint32_t | MSCM_Type::CPxCOUNT |
| |
|
uint8_t | MSCM_Type::RESERVED_0 [4] |
| |
| __I uint32_t | MSCM_Type::CPxCFG1 |
| |
|
uint8_t | MSCM_Type::RESERVED_1 [4] |
| |
| __I uint32_t | MSCM_Type::CPxCFG3 |
| |
| __I uint32_t MSCM_Type::TYPE | |
| |
| __I uint32_t MSCM_Type::NUM | |
| |
| __I uint32_t MSCM_Type::MASTER | |
| |
| __I uint32_t MSCM_Type::COUNT | |
| |
|
uint8_t MSCM_Type::RESERVED_0 [4] | |
| |
| __I uint32_t MSCM_Type::CFG1 | |
| |
|
uint8_t MSCM_Type::RESERVED_1 [4] | |
| |
| __I uint32_t MSCM_Type::CFG3 | |
| |
|
struct { | |
| |
| } | MSCM_Type::CP [2] | |
| |
|
uint8_t | MSCM_Type::RESERVED_2 [928] |
| |
| __I uint32_t | MSCM_Type::OCMDR [3] |
| |
| __IO uint32_t PDB_Type::C1 | |
| |
| __IO uint32_t PDB_Type::S | |
| |
| __IO uint32_t PDB_Type::DLY [2] | |
| |
|
uint8_t PDB_Type::RESERVED_0 [24] | |
| |
|
struct { | |
| |
| } | PDB_Type::CH [2] | |
| |
| __IO uint32_t PDB_Type::INTC | |
| |
| __IO uint32_t PDB_Type::INT | |
| |
|
struct { | |
| |
| } | PDB_Type::DAC [1] | |
| |
| __IO uint32_t PIT_Type::LDVAL | |
| |
| __I uint32_t PIT_Type::CVAL | |
| |
| __IO uint32_t PIT_Type::TCTRL | |
| |
| __IO uint32_t PIT_Type::TFLG | |
| |
|
struct { | |
| |
| } | PIT_Type::CHANNEL [4] | |
| |
|
uint8_t | PMC_Type::RESERVED_0 [8] |
| |
| __IO uint8_t | PMC_Type::HVDSC1 |
| |
| __I uint16_t PWM_Type::CNT | |
| |
| __IO uint16_t PWM_Type::INIT | |
| |
| __IO uint16_t PWM_Type::CTRL2 | |
| |
| __IO uint16_t PWM_Type::CTRL | |
| |
|
uint8_t PWM_Type::RESERVED_0 [2] | |
| |
| __IO uint16_t PWM_Type::VAL0 | |
| |
| __IO uint16_t PWM_Type::FRACVAL1 | |
| |
| __IO uint16_t PWM_Type::VAL1 | |
| |
| __IO uint16_t PWM_Type::FRACVAL2 | |
| |
| __IO uint16_t PWM_Type::VAL2 | |
| |
| __IO uint16_t PWM_Type::FRACVAL3 | |
| |
| __IO uint16_t PWM_Type::VAL3 | |
| |
| __IO uint16_t PWM_Type::FRACVAL4 | |
| |
| __IO uint16_t PWM_Type::VAL4 | |
| |
| __IO uint16_t PWM_Type::FRACVAL5 | |
| |
| __IO uint16_t PWM_Type::VAL5 | |
| |
| __IO uint16_t PWM_Type::FRCTRL | |
| |
| __IO uint16_t PWM_Type::OCTRL | |
| |
| __IO uint16_t PWM_Type::STS | |
| |
| __IO uint16_t PWM_Type::INTEN | |
| |
| __IO uint16_t PWM_Type::DMAEN | |
| |
| __IO uint16_t PWM_Type::TCTRL | |
| |
| __IO uint16_t PWM_Type::DISMAP [1] | |
| |
|
uint8_t PWM_Type::RESERVED_1 [2] | |
| |
| __IO uint16_t PWM_Type::DTCNT0 | |
| |
| __IO uint16_t PWM_Type::DTCNT1 | |
| |
| __IO uint16_t PWM_Type::CAPTCTRLA | |
| |
| __IO uint16_t PWM_Type::CAPTCOMPA | |
| |
| __IO uint16_t PWM_Type::CAPTCTRLB | |
| |
| __IO uint16_t PWM_Type::CAPTCOMPB | |
| |
| __IO uint16_t PWM_Type::CAPTCTRLX | |
| |
| __IO uint16_t PWM_Type::CAPTCOMPX | |
| |
| __I uint16_t PWM_Type::CVAL0 | |
| |
| __I uint16_t PWM_Type::CVAL0CYC | |
| |
| __I uint16_t PWM_Type::CVAL1 | |
| |
| __I uint16_t PWM_Type::CVAL1CYC | |
| |
| __I uint16_t PWM_Type::CVAL2 | |
| |
| __I uint16_t PWM_Type::CVAL2CYC | |
| |
| __I uint16_t PWM_Type::CVAL3 | |
| |
| __I uint16_t PWM_Type::CVAL3CYC | |
| |
| __I uint16_t PWM_Type::CVAL4 | |
| |
| __I uint16_t PWM_Type::CVAL4CYC | |
| |
| __I uint16_t PWM_Type::CVAL5 | |
| |
| __I uint16_t PWM_Type::CVAL5CYC | |
| |
|
uint8_t PWM_Type::RESERVED_2 [8] | |
| |
|
struct { | |
| |
| } | PWM_Type::SM [4] | |
| |
| __IO uint16_t | PWM_Type::OUTEN |
| |
| __IO uint16_t | PWM_Type::MASK |
| |
| __IO uint16_t | PWM_Type::SWCOUT |
| |
| __IO uint16_t | PWM_Type::DTSRCSEL |
| |
| __IO uint16_t | PWM_Type::MCTRL |
| |
| __IO uint16_t | PWM_Type::MCTRL2 |
| |
| __IO uint16_t | PWM_Type::FCTRL |
| |
| __IO uint16_t | PWM_Type::FSTS |
| |
| __IO uint16_t | PWM_Type::FFILT |
| |
| __IO uint16_t | PWM_Type::FTST |
| |
| __IO uint16_t | PWM_Type::FCTRL2 |
| |
|
uint8_t | SIM_Type::RESERVED_4 [4] |
| |
| __IO uint32_t | SIM_Type::MISCTRL0 |
| |
| __IO uint32_t | SIM_Type::MISCTRL1 |
| |
|
uint8_t | SIM_Type::RESERVED_5 [140] |
| |
| __IO uint32_t | SIM_Type::WDOGC |
| |
| __IO uint32_t | SIM_Type::PWRC |
| |
| __IO uint32_t | SIM_Type::ADCOPT |
| |
| __IO uint32_t SPI_Type::CTAR [2] | |
| |
| __IO uint32_t SPI_Type::CTAR_SLAVE [1] | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t SPI_Type::PUSHR | |
| |
| __IO uint32_t SPI_Type::PUSHR_SLAVE | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t SYSMPU_Type::EAR | |
| |
| __I uint32_t SYSMPU_Type::EDR | |
| |
|
struct { | |
| |
| } | SYSMPU_Type::SP [5] | |
| |
| __IO uint32_t | TRNG_Type::MCTL |
| |
| __IO uint32_t | TRNG_Type::SCMISC |
| |
| __IO uint32_t | TRNG_Type::PKRRNG |
| |
| __IO uint32_t TRNG_Type::PKRMAX | |
| |
| __I uint32_t TRNG_Type::PKRSQ | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t | TRNG_Type::SDCTL |
| |
| __IO uint32_t TRNG_Type::SBLIM | |
| |
| __I uint32_t TRNG_Type::TOTSAM | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint32_t | TRNG_Type::FRQMIN |
| |
| __I uint32_t TRNG_Type::FRQCNT | |
| |
| __IO uint32_t TRNG_Type::FRQMAX | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t TRNG_Type::SCMC | |
| |
| __IO uint32_t TRNG_Type::SCML | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t TRNG_Type::SCR1C | |
| |
| __IO uint32_t TRNG_Type::SCR1L | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t TRNG_Type::SCR2C | |
| |
| __IO uint32_t TRNG_Type::SCR2L | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t TRNG_Type::SCR3C | |
| |
| __IO uint32_t TRNG_Type::SCR3L | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t TRNG_Type::SCR4C | |
| |
| __IO uint32_t TRNG_Type::SCR4L | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t TRNG_Type::SCR5C | |
| |
| __IO uint32_t TRNG_Type::SCR5L | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t TRNG_Type::SCR6PC | |
| |
| __IO uint32_t TRNG_Type::SCR6PL | |
| |
|
union { | |
| |
| }; | | |
| |
| __I uint32_t | TRNG_Type::STATUS |
| |
| __I uint32_t | TRNG_Type::ENT [16] |
| |
| __I uint32_t | TRNG_Type::PKRCNT10 |
| |
| __I uint32_t | TRNG_Type::PKRCNT32 |
| |
| __I uint32_t | TRNG_Type::PKRCNT54 |
| |
| __I uint32_t | TRNG_Type::PKRCNT76 |
| |
| __I uint32_t | TRNG_Type::PKRCNT98 |
| |
| __I uint32_t | TRNG_Type::PKRCNTBA |
| |
| __I uint32_t | TRNG_Type::PKRCNTDC |
| |
| __I uint32_t | TRNG_Type::PKRCNTFE |
| |
|
uint8_t | TRNG_Type::RESERVED_0 [16] |
| |
| __IO uint32_t | TRNG_Type::SEC_CFG |
| |
| __IO uint32_t | TRNG_Type::INT_CTRL |
| |
| __IO uint32_t | TRNG_Type::INT_MASK |
| |
| __IO uint32_t | TRNG_Type::INT_STATUS |
| |
|
uint8_t | TRNG_Type::RESERVED_1 [48] |
| |
| __I uint32_t | TRNG_Type::VID1 |
| |
| __I uint32_t | TRNG_Type::VID2 |
| |
| __IO uint8_t UART_Type::WP7816A_T0 | |
| |
| __IO uint8_t UART_Type::WP7816B_T0 | |
| |
|
struct { | |
| |
| } UART_Type::TYPE0 | |
| |
| __IO uint8_t UART_Type::WP7816A_T1 | |
| |
| __IO uint8_t UART_Type::WP7816B_T1 | |
| |
|
struct { | |
| |
| } UART_Type::TYPE1 | |
| |
|
union { | |
| |
| }; | | |
| |
| __IO uint16_t | XBARA_Type::SEL0 |
| |
| __IO uint16_t | XBARA_Type::SEL1 |
| |
| __IO uint16_t | XBARA_Type::SEL2 |
| |
| __IO uint16_t | XBARA_Type::SEL3 |
| |
| __IO uint16_t | XBARA_Type::SEL4 |
| |
| __IO uint16_t | XBARA_Type::SEL5 |
| |
| __IO uint16_t | XBARA_Type::SEL6 |
| |
| __IO uint16_t | XBARA_Type::SEL7 |
| |
| __IO uint16_t | XBARA_Type::SEL8 |
| |
| __IO uint16_t | XBARA_Type::SEL9 |
| |
| __IO uint16_t | XBARA_Type::SEL10 |
| |
| __IO uint16_t | XBARA_Type::SEL11 |
| |
| __IO uint16_t | XBARA_Type::SEL12 |
| |
| __IO uint16_t | XBARA_Type::SEL13 |
| |
| __IO uint16_t | XBARA_Type::SEL14 |
| |
| __IO uint16_t | XBARA_Type::SEL15 |
| |
| __IO uint16_t | XBARA_Type::SEL16 |
| |
| __IO uint16_t | XBARA_Type::SEL17 |
| |
| __IO uint16_t | XBARA_Type::SEL18 |
| |
| __IO uint16_t | XBARA_Type::SEL19 |
| |
| __IO uint16_t | XBARA_Type::SEL20 |
| |
| __IO uint16_t | XBARA_Type::SEL21 |
| |
| __IO uint16_t | XBARA_Type::SEL22 |
| |
| __IO uint16_t | XBARA_Type::SEL23 |
| |
| __IO uint16_t | XBARA_Type::SEL24 |
| |
| __IO uint16_t | XBARA_Type::SEL25 |
| |
| __IO uint16_t | XBARA_Type::SEL26 |
| |
| __IO uint16_t | XBARA_Type::SEL27 |
| |
| __IO uint16_t | XBARA_Type::SEL28 |
| |
| __IO uint16_t | XBARA_Type::SEL29 |
| |
| __IO uint16_t | XBARA_Type::CTRL0 |
| |
| __IO uint16_t | XBARA_Type::CTRL1 |
| |
| __IO uint16_t | XBARB_Type::SEL0 |
| |
| __IO uint16_t | XBARB_Type::SEL1 |
| |
| __IO uint16_t | XBARB_Type::SEL2 |
| |
| __IO uint16_t | XBARB_Type::SEL3 |
| |
| __IO uint16_t | XBARB_Type::SEL4 |
| |
| __IO uint16_t | XBARB_Type::SEL5 |
| |
| __IO uint16_t | XBARB_Type::SEL6 |
| |
| __IO uint16_t | XBARB_Type::SEL7 |
| |
