mikroSDK Reference Manual
Macros
AIPS Register Masks
Mapping Information » Device Peripheral Access Layer » ADC Peripheral Access Layer » AIPS Peripheral Access Layer

Macros

#define AIPS0_BASE   (0x40000000u)
 
#define AIPS0   ((AIPS_Type *)AIPS0_BASE)
 
#define AIPS1_BASE   (0x40080000u)
 
#define AIPS1   ((AIPS_Type *)AIPS1_BASE)
 
#define AIPS_BASE_ADDRS   { AIPS0_BASE, AIPS1_BASE }
 
#define AIPS_BASE_PTRS   { AIPS0, AIPS1 }
 

MPRA - Master Privilege Register A

#define AIPS_MPRA_MPL5_MASK   (0x100U)
 
#define AIPS_MPRA_MPL5_SHIFT   (8U)
 
#define AIPS_MPRA_MPL5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
 
#define AIPS_MPRA_MTW5_MASK   (0x200U)
 
#define AIPS_MPRA_MTW5_SHIFT   (9U)
 
#define AIPS_MPRA_MTW5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
 
#define AIPS_MPRA_MTR5_MASK   (0x400U)
 
#define AIPS_MPRA_MTR5_SHIFT   (10U)
 
#define AIPS_MPRA_MTR5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
 
#define AIPS_MPRA_MPL4_MASK   (0x1000U)
 
#define AIPS_MPRA_MPL4_SHIFT   (12U)
 
#define AIPS_MPRA_MPL4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
 
#define AIPS_MPRA_MTW4_MASK   (0x2000U)
 
#define AIPS_MPRA_MTW4_SHIFT   (13U)
 
#define AIPS_MPRA_MTW4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
 
#define AIPS_MPRA_MTR4_MASK   (0x4000U)
 
#define AIPS_MPRA_MTR4_SHIFT   (14U)
 
#define AIPS_MPRA_MTR4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
 
#define AIPS_MPRA_MPL5_MASK   0x100u
 
#define AIPS_MPRA_MPL5_SHIFT   8
 
#define AIPS_MPRA_MTW5_MASK   0x200u
 
#define AIPS_MPRA_MTW5_SHIFT   9
 
#define AIPS_MPRA_MTR5_MASK   0x400u
 
#define AIPS_MPRA_MTR5_SHIFT   10
 
#define AIPS_MPRA_MPL4_MASK   0x1000u
 
#define AIPS_MPRA_MPL4_SHIFT   12
 
#define AIPS_MPRA_MTW4_MASK   0x2000u
 
#define AIPS_MPRA_MTW4_SHIFT   13
 
#define AIPS_MPRA_MTR4_MASK   0x4000u
 
#define AIPS_MPRA_MTR4_SHIFT   14
 
#define AIPS_MPRA_MPL5_MASK   (0x100U)
 
#define AIPS_MPRA_MPL5_SHIFT   (8U)
 
#define AIPS_MPRA_MPL5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
 
#define AIPS_MPRA_MTW5_MASK   (0x200U)
 
#define AIPS_MPRA_MTW5_SHIFT   (9U)
 
#define AIPS_MPRA_MTW5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
 
#define AIPS_MPRA_MTR5_MASK   (0x400U)
 
#define AIPS_MPRA_MTR5_SHIFT   (10U)
 
#define AIPS_MPRA_MTR5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
 
#define AIPS_MPRA_MPL4_MASK   (0x1000U)
 
#define AIPS_MPRA_MPL4_SHIFT   (12U)
 
#define AIPS_MPRA_MPL4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
 
#define AIPS_MPRA_MTW4_MASK   (0x2000U)
 
#define AIPS_MPRA_MTW4_SHIFT   (13U)
 
#define AIPS_MPRA_MTW4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
 
#define AIPS_MPRA_MTR4_MASK   (0x4000U)
 
#define AIPS_MPRA_MTR4_SHIFT   (14U)
 
#define AIPS_MPRA_MTR4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
 
#define AIPS_MPRA_MPL6_MASK   (0x10U)
 
#define AIPS_MPRA_MPL6_SHIFT   (4U)
 
#define AIPS_MPRA_MPL6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
 
#define AIPS_MPRA_MTW6_MASK   (0x20U)
 
#define AIPS_MPRA_MTW6_SHIFT   (5U)
 
#define AIPS_MPRA_MTW6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
 
#define AIPS_MPRA_MTR6_MASK   (0x40U)
 
#define AIPS_MPRA_MTR6_SHIFT   (6U)
 
#define AIPS_MPRA_MTR6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
 
#define AIPS_MPRA_MPL5_MASK   (0x100U)
 
#define AIPS_MPRA_MPL5_SHIFT   (8U)
 
#define AIPS_MPRA_MPL5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
 
#define AIPS_MPRA_MTW5_MASK   (0x200U)
 
#define AIPS_MPRA_MTW5_SHIFT   (9U)
 
#define AIPS_MPRA_MTW5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
 
#define AIPS_MPRA_MTR5_MASK   (0x400U)
 
#define AIPS_MPRA_MTR5_SHIFT   (10U)
 
#define AIPS_MPRA_MTR5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
 
#define AIPS_MPRA_MPL4_MASK   (0x1000U)
 
#define AIPS_MPRA_MPL4_SHIFT   (12U)
 
#define AIPS_MPRA_MPL4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
 
#define AIPS_MPRA_MTW4_MASK   (0x2000U)
 
#define AIPS_MPRA_MTW4_SHIFT   (13U)
 
#define AIPS_MPRA_MTW4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
 
#define AIPS_MPRA_MTR4_MASK   (0x4000U)
 
#define AIPS_MPRA_MTR4_SHIFT   (14U)
 
#define AIPS_MPRA_MTR4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
 
#define AIPS_MPRA_MPL6_MASK   (0x10U)
 
#define AIPS_MPRA_MPL6_SHIFT   (4U)
 
#define AIPS_MPRA_MPL6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
 
#define AIPS_MPRA_MTW6_MASK   (0x20U)
 
#define AIPS_MPRA_MTW6_SHIFT   (5U)
 
#define AIPS_MPRA_MTW6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
 
#define AIPS_MPRA_MTR6_MASK   (0x40U)
 
#define AIPS_MPRA_MTR6_SHIFT   (6U)
 
#define AIPS_MPRA_MTR6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
 
#define AIPS_MPRA_MPL5_MASK   (0x100U)
 
#define AIPS_MPRA_MPL5_SHIFT   (8U)
 
#define AIPS_MPRA_MPL5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
 
#define AIPS_MPRA_MTW5_MASK   (0x200U)
 
#define AIPS_MPRA_MTW5_SHIFT   (9U)
 
#define AIPS_MPRA_MTW5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
 
#define AIPS_MPRA_MTR5_MASK   (0x400U)
 
#define AIPS_MPRA_MTR5_SHIFT   (10U)
 
#define AIPS_MPRA_MTR5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
 
#define AIPS_MPRA_MPL4_MASK   (0x1000U)
 
#define AIPS_MPRA_MPL4_SHIFT   (12U)
 
#define AIPS_MPRA_MPL4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
 
#define AIPS_MPRA_MTW4_MASK   (0x2000U)
 
#define AIPS_MPRA_MTW4_SHIFT   (13U)
 
#define AIPS_MPRA_MTW4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
 
#define AIPS_MPRA_MTR4_MASK   (0x4000U)
 
#define AIPS_MPRA_MTR4_SHIFT   (14U)
 
#define AIPS_MPRA_MTR4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
 

MPRA - Master Privilege Register A

#define AIPS_MPRA_MPL3_MASK   (0x10000U)
 
#define AIPS_MPRA_MPL3_SHIFT   (16U)
 
#define AIPS_MPRA_MPL3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
 
#define AIPS_MPRA_MTW3_MASK   (0x20000U)
 
#define AIPS_MPRA_MTW3_SHIFT   (17U)
 
#define AIPS_MPRA_MTW3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
 
#define AIPS_MPRA_MTR3_MASK   (0x40000U)
 
#define AIPS_MPRA_MTR3_SHIFT   (18U)
 
#define AIPS_MPRA_MTR3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
 
#define AIPS_MPRA_MPL2_MASK   (0x100000U)
 
#define AIPS_MPRA_MPL2_SHIFT   (20U)
 
#define AIPS_MPRA_MPL2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
 
#define AIPS_MPRA_MTW2_MASK   (0x200000U)
 
#define AIPS_MPRA_MTW2_SHIFT   (21U)
 
#define AIPS_MPRA_MTW2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
 
#define AIPS_MPRA_MTR2_MASK   (0x400000U)
 
#define AIPS_MPRA_MTR2_SHIFT   (22U)
 
#define AIPS_MPRA_MTR2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
 
#define AIPS_MPRA_MPL1_MASK   (0x1000000U)
 
#define AIPS_MPRA_MPL1_SHIFT   (24U)
 
#define AIPS_MPRA_MPL1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
 
#define AIPS_MPRA_MTW1_MASK   (0x2000000U)
 
#define AIPS_MPRA_MTW1_SHIFT   (25U)
 
#define AIPS_MPRA_MTW1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
 
#define AIPS_MPRA_MTR1_MASK   (0x4000000U)
 
#define AIPS_MPRA_MTR1_SHIFT   (26U)
 
#define AIPS_MPRA_MTR1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
 
#define AIPS_MPRA_MPL0_MASK   (0x10000000U)
 
#define AIPS_MPRA_MPL0_SHIFT   (28U)
 
#define AIPS_MPRA_MPL0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
 
#define AIPS_MPRA_MTW0_MASK   (0x20000000U)
 
#define AIPS_MPRA_MTW0_SHIFT   (29U)
 
#define AIPS_MPRA_MTW0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
 
#define AIPS_MPRA_MTR0_MASK   (0x40000000U)
 
#define AIPS_MPRA_MTR0_SHIFT   (30U)
 
#define AIPS_MPRA_MTR0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
 
#define AIPS_MPRA_MPL3_MASK   0x10000u
 
#define AIPS_MPRA_MPL3_SHIFT   16
 
#define AIPS_MPRA_MTW3_MASK   0x20000u
 
#define AIPS_MPRA_MTW3_SHIFT   17
 
#define AIPS_MPRA_MTR3_MASK   0x40000u
 
#define AIPS_MPRA_MTR3_SHIFT   18
 
#define AIPS_MPRA_MPL2_MASK   0x100000u
 
#define AIPS_MPRA_MPL2_SHIFT   20
 
#define AIPS_MPRA_MTW2_MASK   0x200000u
 
#define AIPS_MPRA_MTW2_SHIFT   21
 
#define AIPS_MPRA_MTR2_MASK   0x400000u
 
#define AIPS_MPRA_MTR2_SHIFT   22
 
#define AIPS_MPRA_MPL1_MASK   0x1000000u
 
#define AIPS_MPRA_MPL1_SHIFT   24
 
#define AIPS_MPRA_MTW1_MASK   0x2000000u
 
#define AIPS_MPRA_MTW1_SHIFT   25
 
#define AIPS_MPRA_MTR1_MASK   0x4000000u
 
#define AIPS_MPRA_MTR1_SHIFT   26
 
#define AIPS_MPRA_MPL0_MASK   0x10000000u
 
#define AIPS_MPRA_MPL0_SHIFT   28
 
#define AIPS_MPRA_MTW0_MASK   0x20000000u
 
#define AIPS_MPRA_MTW0_SHIFT   29
 
#define AIPS_MPRA_MTR0_MASK   0x40000000u
 
#define AIPS_MPRA_MTR0_SHIFT   30
 
#define AIPS_MPRA_MPL3_MASK   (0x10000U)
 
#define AIPS_MPRA_MPL3_SHIFT   (16U)
 
#define AIPS_MPRA_MPL3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
 
#define AIPS_MPRA_MTW3_MASK   (0x20000U)
 
#define AIPS_MPRA_MTW3_SHIFT   (17U)
 
#define AIPS_MPRA_MTW3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
 
#define AIPS_MPRA_MTR3_MASK   (0x40000U)
 
#define AIPS_MPRA_MTR3_SHIFT   (18U)
 
#define AIPS_MPRA_MTR3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
 
#define AIPS_MPRA_MPL2_MASK   (0x100000U)
 
#define AIPS_MPRA_MPL2_SHIFT   (20U)
 
#define AIPS_MPRA_MPL2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
 
#define AIPS_MPRA_MTW2_MASK   (0x200000U)
 
#define AIPS_MPRA_MTW2_SHIFT   (21U)
 
#define AIPS_MPRA_MTW2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
 
#define AIPS_MPRA_MTR2_MASK   (0x400000U)
 
#define AIPS_MPRA_MTR2_SHIFT   (22U)
 
#define AIPS_MPRA_MTR2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
 
#define AIPS_MPRA_MPL1_MASK   (0x1000000U)
 
#define AIPS_MPRA_MPL1_SHIFT   (24U)
 
#define AIPS_MPRA_MPL1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
 
#define AIPS_MPRA_MTW1_MASK   (0x2000000U)
 
#define AIPS_MPRA_MTW1_SHIFT   (25U)
 
#define AIPS_MPRA_MTW1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
 
#define AIPS_MPRA_MTR1_MASK   (0x4000000U)
 
#define AIPS_MPRA_MTR1_SHIFT   (26U)
 
#define AIPS_MPRA_MTR1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
 
#define AIPS_MPRA_MPL0_MASK   (0x10000000U)
 
#define AIPS_MPRA_MPL0_SHIFT   (28U)
 
#define AIPS_MPRA_MPL0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
 
#define AIPS_MPRA_MTW0_MASK   (0x20000000U)
 
#define AIPS_MPRA_MTW0_SHIFT   (29U)
 
#define AIPS_MPRA_MTW0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
 
#define AIPS_MPRA_MTR0_MASK   (0x40000000U)
 
#define AIPS_MPRA_MTR0_SHIFT   (30U)
 
#define AIPS_MPRA_MTR0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
 
#define AIPS_MPRA_MPL3_MASK   (0x10000U)
 
#define AIPS_MPRA_MPL3_SHIFT   (16U)
 
#define AIPS_MPRA_MPL3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
 
#define AIPS_MPRA_MTW3_MASK   (0x20000U)
 
#define AIPS_MPRA_MTW3_SHIFT   (17U)
 
#define AIPS_MPRA_MTW3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
 
#define AIPS_MPRA_MTR3_MASK   (0x40000U)
 
#define AIPS_MPRA_MTR3_SHIFT   (18U)
 
#define AIPS_MPRA_MTR3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
 
#define AIPS_MPRA_MPL2_MASK   (0x100000U)
 
#define AIPS_MPRA_MPL2_SHIFT   (20U)
 
#define AIPS_MPRA_MPL2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
 
#define AIPS_MPRA_MTW2_MASK   (0x200000U)
 
#define AIPS_MPRA_MTW2_SHIFT   (21U)
 
#define AIPS_MPRA_MTW2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
 
#define AIPS_MPRA_MTR2_MASK   (0x400000U)
 
#define AIPS_MPRA_MTR2_SHIFT   (22U)
 
#define AIPS_MPRA_MTR2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
 
#define AIPS_MPRA_MPL1_MASK   (0x1000000U)
 
#define AIPS_MPRA_MPL1_SHIFT   (24U)
 
#define AIPS_MPRA_MPL1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
 
#define AIPS_MPRA_MTW1_MASK   (0x2000000U)
 
#define AIPS_MPRA_MTW1_SHIFT   (25U)
 
#define AIPS_MPRA_MTW1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
 
#define AIPS_MPRA_MTR1_MASK   (0x4000000U)
 
#define AIPS_MPRA_MTR1_SHIFT   (26U)
 
#define AIPS_MPRA_MTR1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
 
#define AIPS_MPRA_MPL0_MASK   (0x10000000U)
 
#define AIPS_MPRA_MPL0_SHIFT   (28U)
 
#define AIPS_MPRA_MPL0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
 
#define AIPS_MPRA_MTW0_MASK   (0x20000000U)
 
#define AIPS_MPRA_MTW0_SHIFT   (29U)
 
#define AIPS_MPRA_MTW0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
 
#define AIPS_MPRA_MTR0_MASK   (0x40000000U)
 
#define AIPS_MPRA_MTR0_SHIFT   (30U)
 
#define AIPS_MPRA_MTR0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
 
#define AIPS_MPRA_MPL3_MASK   (0x10000U)
 
#define AIPS_MPRA_MPL3_SHIFT   (16U)
 
#define AIPS_MPRA_MPL3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
 
#define AIPS_MPRA_MTW3_MASK   (0x20000U)
 
#define AIPS_MPRA_MTW3_SHIFT   (17U)
 
#define AIPS_MPRA_MTW3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
 
#define AIPS_MPRA_MTR3_MASK   (0x40000U)
 
#define AIPS_MPRA_MTR3_SHIFT   (18U)
 
#define AIPS_MPRA_MTR3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
 
#define AIPS_MPRA_MPL2_MASK   (0x100000U)
 
#define AIPS_MPRA_MPL2_SHIFT   (20U)
 
#define AIPS_MPRA_MPL2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
 
#define AIPS_MPRA_MTW2_MASK   (0x200000U)
 
#define AIPS_MPRA_MTW2_SHIFT   (21U)
 
#define AIPS_MPRA_MTW2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
 
#define AIPS_MPRA_MTR2_MASK   (0x400000U)
 
#define AIPS_MPRA_MTR2_SHIFT   (22U)
 
#define AIPS_MPRA_MTR2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
 
#define AIPS_MPRA_MPL1_MASK   (0x1000000U)
 
#define AIPS_MPRA_MPL1_SHIFT   (24U)
 
#define AIPS_MPRA_MPL1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
 
#define AIPS_MPRA_MTW1_MASK   (0x2000000U)
 
#define AIPS_MPRA_MTW1_SHIFT   (25U)
 
#define AIPS_MPRA_MTW1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
 
#define AIPS_MPRA_MTR1_MASK   (0x4000000U)
 
#define AIPS_MPRA_MTR1_SHIFT   (26U)
 
#define AIPS_MPRA_MTR1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
 
#define AIPS_MPRA_MPL0_MASK   (0x10000000U)
 
#define AIPS_MPRA_MPL0_SHIFT   (28U)
 
#define AIPS_MPRA_MPL0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
 
#define AIPS_MPRA_MTW0_MASK   (0x20000000U)
 
#define AIPS_MPRA_MTW0_SHIFT   (29U)
 
#define AIPS_MPRA_MTW0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
 
#define AIPS_MPRA_MTR0_MASK   (0x40000000U)
 
#define AIPS_MPRA_MTR0_SHIFT   (30U)
 
#define AIPS_MPRA_MTR0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
 
#define AIPS_MPRA_MPL3_MASK   (0x10000U)
 
#define AIPS_MPRA_MPL3_SHIFT   (16U)
 
#define AIPS_MPRA_MPL3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
 
#define AIPS_MPRA_MTW3_MASK   (0x20000U)
 
#define AIPS_MPRA_MTW3_SHIFT   (17U)
 
#define AIPS_MPRA_MTW3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
 
#define AIPS_MPRA_MTR3_MASK   (0x40000U)
 
#define AIPS_MPRA_MTR3_SHIFT   (18U)
 
#define AIPS_MPRA_MTR3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
 
#define AIPS_MPRA_MPL2_MASK   (0x100000U)
 
#define AIPS_MPRA_MPL2_SHIFT   (20U)
 
#define AIPS_MPRA_MPL2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
 
#define AIPS_MPRA_MTW2_MASK   (0x200000U)
 
#define AIPS_MPRA_MTW2_SHIFT   (21U)
 
#define AIPS_MPRA_MTW2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
 
#define AIPS_MPRA_MTR2_MASK   (0x400000U)
 
#define AIPS_MPRA_MTR2_SHIFT   (22U)
 
#define AIPS_MPRA_MTR2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
 
#define AIPS_MPRA_MPL1_MASK   (0x1000000U)
 
#define AIPS_MPRA_MPL1_SHIFT   (24U)
 
#define AIPS_MPRA_MPL1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
 
#define AIPS_MPRA_MTW1_MASK   (0x2000000U)
 
#define AIPS_MPRA_MTW1_SHIFT   (25U)
 
#define AIPS_MPRA_MTW1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
 
#define AIPS_MPRA_MTR1_MASK   (0x4000000U)
 
#define AIPS_MPRA_MTR1_SHIFT   (26U)
 
#define AIPS_MPRA_MTR1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
 
#define AIPS_MPRA_MPL0_MASK   (0x10000000U)
 
#define AIPS_MPRA_MPL0_SHIFT   (28U)
 
#define AIPS_MPRA_MPL0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
 
#define AIPS_MPRA_MTW0_MASK   (0x20000000U)
 
#define AIPS_MPRA_MTW0_SHIFT   (29U)
 
#define AIPS_MPRA_MTW0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
 
#define AIPS_MPRA_MTR0_MASK   (0x40000000U)
 
#define AIPS_MPRA_MTR0_SHIFT   (30U)
 
#define AIPS_MPRA_MTR0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
 

PACRA - Peripheral Access Control Register

#define AIPS_PACRA_TP7_MASK   (0x1U)
 
#define AIPS_PACRA_TP7_SHIFT   (0U)
 
#define AIPS_PACRA_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
 
#define AIPS_PACRA_WP7_MASK   (0x2U)
 
#define AIPS_PACRA_WP7_SHIFT   (1U)
 
#define AIPS_PACRA_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
 
#define AIPS_PACRA_SP7_MASK   (0x4U)
 
#define AIPS_PACRA_SP7_SHIFT   (2U)
 
#define AIPS_PACRA_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
 
#define AIPS_PACRA_TP6_MASK   (0x10U)
 
#define AIPS_PACRA_TP6_SHIFT   (4U)
 
#define AIPS_PACRA_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
 
#define AIPS_PACRA_WP6_MASK   (0x20U)
 
#define AIPS_PACRA_WP6_SHIFT   (5U)
 
#define AIPS_PACRA_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
 
#define AIPS_PACRA_SP6_MASK   (0x40U)
 
#define AIPS_PACRA_SP6_SHIFT   (6U)
 
#define AIPS_PACRA_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
 
#define AIPS_PACRA_TP5_MASK   (0x100U)
 
#define AIPS_PACRA_TP5_SHIFT   (8U)
 
#define AIPS_PACRA_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
 
#define AIPS_PACRA_WP5_MASK   (0x200U)
 
#define AIPS_PACRA_WP5_SHIFT   (9U)
 
#define AIPS_PACRA_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
 
#define AIPS_PACRA_SP5_MASK   (0x400U)
 
#define AIPS_PACRA_SP5_SHIFT   (10U)
 
#define AIPS_PACRA_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
 
#define AIPS_PACRA_TP4_MASK   (0x1000U)
 
#define AIPS_PACRA_TP4_SHIFT   (12U)
 
#define AIPS_PACRA_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
 
#define AIPS_PACRA_WP4_MASK   (0x2000U)
 
#define AIPS_PACRA_WP4_SHIFT   (13U)
 
#define AIPS_PACRA_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
 
#define AIPS_PACRA_SP4_MASK   (0x4000U)
 
#define AIPS_PACRA_SP4_SHIFT   (14U)
 
#define AIPS_PACRA_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
 
#define AIPS_PACRA_TP3_MASK   (0x10000U)
 
#define AIPS_PACRA_TP3_SHIFT   (16U)
 
#define AIPS_PACRA_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
 
#define AIPS_PACRA_WP3_MASK   (0x20000U)
 
#define AIPS_PACRA_WP3_SHIFT   (17U)
 
#define AIPS_PACRA_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
 
#define AIPS_PACRA_SP3_MASK   (0x40000U)
 
#define AIPS_PACRA_SP3_SHIFT   (18U)
 
#define AIPS_PACRA_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
 
#define AIPS_PACRA_TP2_MASK   (0x100000U)
 
#define AIPS_PACRA_TP2_SHIFT   (20U)
 
#define AIPS_PACRA_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
 
#define AIPS_PACRA_WP2_MASK   (0x200000U)
 
#define AIPS_PACRA_WP2_SHIFT   (21U)
 
#define AIPS_PACRA_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
 
#define AIPS_PACRA_SP2_MASK   (0x400000U)
 
#define AIPS_PACRA_SP2_SHIFT   (22U)
 
#define AIPS_PACRA_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
 
#define AIPS_PACRA_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRA_TP1_SHIFT   (24U)
 
#define AIPS_PACRA_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
 
#define AIPS_PACRA_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRA_WP1_SHIFT   (25U)
 
#define AIPS_PACRA_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
 
#define AIPS_PACRA_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRA_SP1_SHIFT   (26U)
 
#define AIPS_PACRA_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
 
#define AIPS_PACRA_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRA_TP0_SHIFT   (28U)
 
#define AIPS_PACRA_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
 
#define AIPS_PACRA_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRA_WP0_SHIFT   (29U)
 
#define AIPS_PACRA_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
 
#define AIPS_PACRA_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRA_SP0_SHIFT   (30U)
 
#define AIPS_PACRA_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
 
#define AIPS_PACRA_TP7_MASK   0x1u
 
#define AIPS_PACRA_TP7_SHIFT   0
 
#define AIPS_PACRA_WP7_MASK   0x2u
 
#define AIPS_PACRA_WP7_SHIFT   1
 
#define AIPS_PACRA_SP7_MASK   0x4u
 
#define AIPS_PACRA_SP7_SHIFT   2
 
#define AIPS_PACRA_TP6_MASK   0x10u
 
#define AIPS_PACRA_TP6_SHIFT   4
 
#define AIPS_PACRA_WP6_MASK   0x20u
 
#define AIPS_PACRA_WP6_SHIFT   5
 
#define AIPS_PACRA_SP6_MASK   0x40u
 
#define AIPS_PACRA_SP6_SHIFT   6
 
#define AIPS_PACRA_TP5_MASK   0x100u
 
#define AIPS_PACRA_TP5_SHIFT   8
 
#define AIPS_PACRA_WP5_MASK   0x200u
 
#define AIPS_PACRA_WP5_SHIFT   9
 
#define AIPS_PACRA_SP5_MASK   0x400u
 
#define AIPS_PACRA_SP5_SHIFT   10
 
#define AIPS_PACRA_TP4_MASK   0x1000u
 
#define AIPS_PACRA_TP4_SHIFT   12
 
#define AIPS_PACRA_WP4_MASK   0x2000u
 
#define AIPS_PACRA_WP4_SHIFT   13
 
#define AIPS_PACRA_SP4_MASK   0x4000u
 
#define AIPS_PACRA_SP4_SHIFT   14
 
#define AIPS_PACRA_TP3_MASK   0x10000u
 
#define AIPS_PACRA_TP3_SHIFT   16
 
#define AIPS_PACRA_WP3_MASK   0x20000u
 
#define AIPS_PACRA_WP3_SHIFT   17
 
#define AIPS_PACRA_SP3_MASK   0x40000u
 
#define AIPS_PACRA_SP3_SHIFT   18
 
#define AIPS_PACRA_TP2_MASK   0x100000u
 
#define AIPS_PACRA_TP2_SHIFT   20
 
#define AIPS_PACRA_WP2_MASK   0x200000u
 
#define AIPS_PACRA_WP2_SHIFT   21
 
#define AIPS_PACRA_SP2_MASK   0x400000u
 
#define AIPS_PACRA_SP2_SHIFT   22
 
#define AIPS_PACRA_TP1_MASK   0x1000000u
 
#define AIPS_PACRA_TP1_SHIFT   24
 
#define AIPS_PACRA_WP1_MASK   0x2000000u
 
#define AIPS_PACRA_WP1_SHIFT   25
 
#define AIPS_PACRA_SP1_MASK   0x4000000u
 
#define AIPS_PACRA_SP1_SHIFT   26
 
#define AIPS_PACRA_TP0_MASK   0x10000000u
 
#define AIPS_PACRA_TP0_SHIFT   28
 
#define AIPS_PACRA_WP0_MASK   0x20000000u
 
#define AIPS_PACRA_WP0_SHIFT   29
 
#define AIPS_PACRA_SP0_MASK   0x40000000u
 
#define AIPS_PACRA_SP0_SHIFT   30
 
#define AIPS_PACRA_TP7_MASK   (0x1U)
 
#define AIPS_PACRA_TP7_SHIFT   (0U)
 
#define AIPS_PACRA_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
 
#define AIPS_PACRA_WP7_MASK   (0x2U)
 
#define AIPS_PACRA_WP7_SHIFT   (1U)
 
#define AIPS_PACRA_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
 
#define AIPS_PACRA_SP7_MASK   (0x4U)
 
#define AIPS_PACRA_SP7_SHIFT   (2U)
 
#define AIPS_PACRA_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
 
#define AIPS_PACRA_TP6_MASK   (0x10U)
 
#define AIPS_PACRA_TP6_SHIFT   (4U)
 
#define AIPS_PACRA_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
 
#define AIPS_PACRA_WP6_MASK   (0x20U)
 
#define AIPS_PACRA_WP6_SHIFT   (5U)
 
#define AIPS_PACRA_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
 
#define AIPS_PACRA_SP6_MASK   (0x40U)
 
#define AIPS_PACRA_SP6_SHIFT   (6U)
 
#define AIPS_PACRA_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
 
#define AIPS_PACRA_TP5_MASK   (0x100U)
 
#define AIPS_PACRA_TP5_SHIFT   (8U)
 
#define AIPS_PACRA_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
 
#define AIPS_PACRA_WP5_MASK   (0x200U)
 
#define AIPS_PACRA_WP5_SHIFT   (9U)
 
#define AIPS_PACRA_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
 
#define AIPS_PACRA_SP5_MASK   (0x400U)
 
#define AIPS_PACRA_SP5_SHIFT   (10U)
 
#define AIPS_PACRA_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
 
#define AIPS_PACRA_TP4_MASK   (0x1000U)
 
#define AIPS_PACRA_TP4_SHIFT   (12U)
 
#define AIPS_PACRA_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
 
#define AIPS_PACRA_WP4_MASK   (0x2000U)
 
#define AIPS_PACRA_WP4_SHIFT   (13U)
 
#define AIPS_PACRA_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
 
#define AIPS_PACRA_SP4_MASK   (0x4000U)
 
#define AIPS_PACRA_SP4_SHIFT   (14U)
 
#define AIPS_PACRA_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
 
#define AIPS_PACRA_TP3_MASK   (0x10000U)
 
#define AIPS_PACRA_TP3_SHIFT   (16U)
 
#define AIPS_PACRA_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
 
#define AIPS_PACRA_WP3_MASK   (0x20000U)
 
#define AIPS_PACRA_WP3_SHIFT   (17U)
 
#define AIPS_PACRA_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
 
#define AIPS_PACRA_SP3_MASK   (0x40000U)
 
#define AIPS_PACRA_SP3_SHIFT   (18U)
 
#define AIPS_PACRA_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
 
#define AIPS_PACRA_TP2_MASK   (0x100000U)
 
#define AIPS_PACRA_TP2_SHIFT   (20U)
 
#define AIPS_PACRA_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
 
#define AIPS_PACRA_WP2_MASK   (0x200000U)
 
#define AIPS_PACRA_WP2_SHIFT   (21U)
 
#define AIPS_PACRA_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
 
#define AIPS_PACRA_SP2_MASK   (0x400000U)
 
#define AIPS_PACRA_SP2_SHIFT   (22U)
 
#define AIPS_PACRA_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
 
#define AIPS_PACRA_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRA_TP1_SHIFT   (24U)
 
#define AIPS_PACRA_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
 
#define AIPS_PACRA_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRA_WP1_SHIFT   (25U)
 
#define AIPS_PACRA_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
 
#define AIPS_PACRA_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRA_SP1_SHIFT   (26U)
 
#define AIPS_PACRA_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
 
#define AIPS_PACRA_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRA_TP0_SHIFT   (28U)
 
#define AIPS_PACRA_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
 
#define AIPS_PACRA_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRA_WP0_SHIFT   (29U)
 
#define AIPS_PACRA_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
 
#define AIPS_PACRA_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRA_SP0_SHIFT   (30U)
 
#define AIPS_PACRA_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
 
#define AIPS_PACRA_TP7_MASK   (0x1U)
 
#define AIPS_PACRA_TP7_SHIFT   (0U)
 
#define AIPS_PACRA_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
 
#define AIPS_PACRA_WP7_MASK   (0x2U)
 
#define AIPS_PACRA_WP7_SHIFT   (1U)
 
#define AIPS_PACRA_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
 
#define AIPS_PACRA_SP7_MASK   (0x4U)
 
#define AIPS_PACRA_SP7_SHIFT   (2U)
 
#define AIPS_PACRA_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
 
#define AIPS_PACRA_TP6_MASK   (0x10U)
 
#define AIPS_PACRA_TP6_SHIFT   (4U)
 
#define AIPS_PACRA_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
 
#define AIPS_PACRA_WP6_MASK   (0x20U)
 
#define AIPS_PACRA_WP6_SHIFT   (5U)
 
#define AIPS_PACRA_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
 
#define AIPS_PACRA_SP6_MASK   (0x40U)
 
#define AIPS_PACRA_SP6_SHIFT   (6U)
 
#define AIPS_PACRA_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
 
#define AIPS_PACRA_TP5_MASK   (0x100U)
 
#define AIPS_PACRA_TP5_SHIFT   (8U)
 
#define AIPS_PACRA_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
 
#define AIPS_PACRA_WP5_MASK   (0x200U)
 
#define AIPS_PACRA_WP5_SHIFT   (9U)
 
#define AIPS_PACRA_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
 
#define AIPS_PACRA_SP5_MASK   (0x400U)
 
#define AIPS_PACRA_SP5_SHIFT   (10U)
 
#define AIPS_PACRA_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
 
#define AIPS_PACRA_TP4_MASK   (0x1000U)
 
#define AIPS_PACRA_TP4_SHIFT   (12U)
 
#define AIPS_PACRA_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
 
#define AIPS_PACRA_WP4_MASK   (0x2000U)
 
#define AIPS_PACRA_WP4_SHIFT   (13U)
 
#define AIPS_PACRA_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
 
#define AIPS_PACRA_SP4_MASK   (0x4000U)
 
#define AIPS_PACRA_SP4_SHIFT   (14U)
 
#define AIPS_PACRA_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
 
#define AIPS_PACRA_TP3_MASK   (0x10000U)
 
#define AIPS_PACRA_TP3_SHIFT   (16U)
 
#define AIPS_PACRA_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
 
#define AIPS_PACRA_WP3_MASK   (0x20000U)
 
#define AIPS_PACRA_WP3_SHIFT   (17U)
 
#define AIPS_PACRA_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
 
#define AIPS_PACRA_SP3_MASK   (0x40000U)
 
#define AIPS_PACRA_SP3_SHIFT   (18U)
 
#define AIPS_PACRA_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
 
#define AIPS_PACRA_TP2_MASK   (0x100000U)
 
#define AIPS_PACRA_TP2_SHIFT   (20U)
 
#define AIPS_PACRA_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
 
#define AIPS_PACRA_WP2_MASK   (0x200000U)
 
#define AIPS_PACRA_WP2_SHIFT   (21U)
 
#define AIPS_PACRA_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
 
#define AIPS_PACRA_SP2_MASK   (0x400000U)
 
#define AIPS_PACRA_SP2_SHIFT   (22U)
 
#define AIPS_PACRA_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
 
#define AIPS_PACRA_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRA_TP1_SHIFT   (24U)
 
#define AIPS_PACRA_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
 
#define AIPS_PACRA_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRA_WP1_SHIFT   (25U)
 
#define AIPS_PACRA_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
 
#define AIPS_PACRA_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRA_SP1_SHIFT   (26U)
 
#define AIPS_PACRA_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
 
#define AIPS_PACRA_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRA_TP0_SHIFT   (28U)
 
#define AIPS_PACRA_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
 
#define AIPS_PACRA_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRA_WP0_SHIFT   (29U)
 
#define AIPS_PACRA_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
 
#define AIPS_PACRA_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRA_SP0_SHIFT   (30U)
 
#define AIPS_PACRA_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
 
#define AIPS_PACRA_TP7_MASK   (0x1U)
 
#define AIPS_PACRA_TP7_SHIFT   (0U)
 
#define AIPS_PACRA_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
 
#define AIPS_PACRA_WP7_MASK   (0x2U)
 
#define AIPS_PACRA_WP7_SHIFT   (1U)
 
#define AIPS_PACRA_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
 
#define AIPS_PACRA_SP7_MASK   (0x4U)
 
#define AIPS_PACRA_SP7_SHIFT   (2U)
 
#define AIPS_PACRA_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
 
#define AIPS_PACRA_TP6_MASK   (0x10U)
 
#define AIPS_PACRA_TP6_SHIFT   (4U)
 
#define AIPS_PACRA_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
 
#define AIPS_PACRA_WP6_MASK   (0x20U)
 
#define AIPS_PACRA_WP6_SHIFT   (5U)
 
#define AIPS_PACRA_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
 
#define AIPS_PACRA_SP6_MASK   (0x40U)
 
#define AIPS_PACRA_SP6_SHIFT   (6U)
 
#define AIPS_PACRA_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
 
#define AIPS_PACRA_TP5_MASK   (0x100U)
 
#define AIPS_PACRA_TP5_SHIFT   (8U)
 
#define AIPS_PACRA_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
 
#define AIPS_PACRA_WP5_MASK   (0x200U)
 
#define AIPS_PACRA_WP5_SHIFT   (9U)
 
#define AIPS_PACRA_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
 
#define AIPS_PACRA_SP5_MASK   (0x400U)
 
#define AIPS_PACRA_SP5_SHIFT   (10U)
 
#define AIPS_PACRA_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
 
#define AIPS_PACRA_TP4_MASK   (0x1000U)
 
#define AIPS_PACRA_TP4_SHIFT   (12U)
 
#define AIPS_PACRA_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
 
#define AIPS_PACRA_WP4_MASK   (0x2000U)
 
#define AIPS_PACRA_WP4_SHIFT   (13U)
 
#define AIPS_PACRA_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
 
#define AIPS_PACRA_SP4_MASK   (0x4000U)
 
#define AIPS_PACRA_SP4_SHIFT   (14U)
 
#define AIPS_PACRA_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
 
#define AIPS_PACRA_TP3_MASK   (0x10000U)
 
#define AIPS_PACRA_TP3_SHIFT   (16U)
 
#define AIPS_PACRA_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
 
#define AIPS_PACRA_WP3_MASK   (0x20000U)
 
#define AIPS_PACRA_WP3_SHIFT   (17U)
 
#define AIPS_PACRA_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
 
#define AIPS_PACRA_SP3_MASK   (0x40000U)
 
#define AIPS_PACRA_SP3_SHIFT   (18U)
 
#define AIPS_PACRA_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
 
#define AIPS_PACRA_TP2_MASK   (0x100000U)
 
#define AIPS_PACRA_TP2_SHIFT   (20U)
 
#define AIPS_PACRA_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
 
#define AIPS_PACRA_WP2_MASK   (0x200000U)
 
#define AIPS_PACRA_WP2_SHIFT   (21U)
 
#define AIPS_PACRA_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
 
#define AIPS_PACRA_SP2_MASK   (0x400000U)
 
#define AIPS_PACRA_SP2_SHIFT   (22U)
 
#define AIPS_PACRA_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
 
#define AIPS_PACRA_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRA_TP1_SHIFT   (24U)
 
#define AIPS_PACRA_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
 
#define AIPS_PACRA_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRA_WP1_SHIFT   (25U)
 
#define AIPS_PACRA_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
 
#define AIPS_PACRA_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRA_SP1_SHIFT   (26U)
 
#define AIPS_PACRA_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
 
#define AIPS_PACRA_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRA_TP0_SHIFT   (28U)
 
#define AIPS_PACRA_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
 
#define AIPS_PACRA_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRA_WP0_SHIFT   (29U)
 
#define AIPS_PACRA_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
 
#define AIPS_PACRA_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRA_SP0_SHIFT   (30U)
 
#define AIPS_PACRA_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
 
#define AIPS_PACRA_TP7_MASK   (0x1U)
 
#define AIPS_PACRA_TP7_SHIFT   (0U)
 
#define AIPS_PACRA_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
 
#define AIPS_PACRA_WP7_MASK   (0x2U)
 
#define AIPS_PACRA_WP7_SHIFT   (1U)
 
#define AIPS_PACRA_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
 
#define AIPS_PACRA_SP7_MASK   (0x4U)
 
#define AIPS_PACRA_SP7_SHIFT   (2U)
 
#define AIPS_PACRA_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
 
#define AIPS_PACRA_TP6_MASK   (0x10U)
 
#define AIPS_PACRA_TP6_SHIFT   (4U)
 
#define AIPS_PACRA_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
 
#define AIPS_PACRA_WP6_MASK   (0x20U)
 
#define AIPS_PACRA_WP6_SHIFT   (5U)
 
#define AIPS_PACRA_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
 
#define AIPS_PACRA_SP6_MASK   (0x40U)
 
#define AIPS_PACRA_SP6_SHIFT   (6U)
 
#define AIPS_PACRA_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
 
#define AIPS_PACRA_TP5_MASK   (0x100U)
 
#define AIPS_PACRA_TP5_SHIFT   (8U)
 
#define AIPS_PACRA_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
 
#define AIPS_PACRA_WP5_MASK   (0x200U)
 
#define AIPS_PACRA_WP5_SHIFT   (9U)
 
#define AIPS_PACRA_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
 
#define AIPS_PACRA_SP5_MASK   (0x400U)
 
#define AIPS_PACRA_SP5_SHIFT   (10U)
 
#define AIPS_PACRA_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
 
#define AIPS_PACRA_TP4_MASK   (0x1000U)
 
#define AIPS_PACRA_TP4_SHIFT   (12U)
 
#define AIPS_PACRA_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
 
#define AIPS_PACRA_WP4_MASK   (0x2000U)
 
#define AIPS_PACRA_WP4_SHIFT   (13U)
 
#define AIPS_PACRA_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
 
#define AIPS_PACRA_SP4_MASK   (0x4000U)
 
#define AIPS_PACRA_SP4_SHIFT   (14U)
 
#define AIPS_PACRA_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
 
#define AIPS_PACRA_TP3_MASK   (0x10000U)
 
#define AIPS_PACRA_TP3_SHIFT   (16U)
 
#define AIPS_PACRA_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
 
#define AIPS_PACRA_WP3_MASK   (0x20000U)
 
#define AIPS_PACRA_WP3_SHIFT   (17U)
 
#define AIPS_PACRA_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
 
#define AIPS_PACRA_SP3_MASK   (0x40000U)
 
#define AIPS_PACRA_SP3_SHIFT   (18U)
 
#define AIPS_PACRA_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
 
#define AIPS_PACRA_TP2_MASK   (0x100000U)
 
#define AIPS_PACRA_TP2_SHIFT   (20U)
 
#define AIPS_PACRA_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
 
#define AIPS_PACRA_WP2_MASK   (0x200000U)
 
#define AIPS_PACRA_WP2_SHIFT   (21U)
 
#define AIPS_PACRA_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
 
#define AIPS_PACRA_SP2_MASK   (0x400000U)
 
#define AIPS_PACRA_SP2_SHIFT   (22U)
 
#define AIPS_PACRA_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
 
#define AIPS_PACRA_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRA_TP1_SHIFT   (24U)
 
#define AIPS_PACRA_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
 
#define AIPS_PACRA_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRA_WP1_SHIFT   (25U)
 
#define AIPS_PACRA_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
 
#define AIPS_PACRA_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRA_SP1_SHIFT   (26U)
 
#define AIPS_PACRA_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
 
#define AIPS_PACRA_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRA_TP0_SHIFT   (28U)
 
#define AIPS_PACRA_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
 
#define AIPS_PACRA_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRA_WP0_SHIFT   (29U)
 
#define AIPS_PACRA_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
 
#define AIPS_PACRA_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRA_SP0_SHIFT   (30U)
 
#define AIPS_PACRA_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
 

PACRB - Peripheral Access Control Register

#define AIPS_PACRB_TP7_MASK   (0x1U)
 
#define AIPS_PACRB_TP7_SHIFT   (0U)
 
#define AIPS_PACRB_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
 
#define AIPS_PACRB_WP7_MASK   (0x2U)
 
#define AIPS_PACRB_WP7_SHIFT   (1U)
 
#define AIPS_PACRB_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
 
#define AIPS_PACRB_SP7_MASK   (0x4U)
 
#define AIPS_PACRB_SP7_SHIFT   (2U)
 
#define AIPS_PACRB_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
 
#define AIPS_PACRB_TP6_MASK   (0x10U)
 
#define AIPS_PACRB_TP6_SHIFT   (4U)
 
#define AIPS_PACRB_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
 
#define AIPS_PACRB_WP6_MASK   (0x20U)
 
#define AIPS_PACRB_WP6_SHIFT   (5U)
 
#define AIPS_PACRB_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
 
#define AIPS_PACRB_SP6_MASK   (0x40U)
 
#define AIPS_PACRB_SP6_SHIFT   (6U)
 
#define AIPS_PACRB_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
 
#define AIPS_PACRB_TP5_MASK   (0x100U)
 
#define AIPS_PACRB_TP5_SHIFT   (8U)
 
#define AIPS_PACRB_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
 
#define AIPS_PACRB_WP5_MASK   (0x200U)
 
#define AIPS_PACRB_WP5_SHIFT   (9U)
 
#define AIPS_PACRB_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
 
#define AIPS_PACRB_SP5_MASK   (0x400U)
 
#define AIPS_PACRB_SP5_SHIFT   (10U)
 
#define AIPS_PACRB_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
 
#define AIPS_PACRB_TP4_MASK   (0x1000U)
 
#define AIPS_PACRB_TP4_SHIFT   (12U)
 
#define AIPS_PACRB_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
 
#define AIPS_PACRB_WP4_MASK   (0x2000U)
 
#define AIPS_PACRB_WP4_SHIFT   (13U)
 
#define AIPS_PACRB_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
 
#define AIPS_PACRB_SP4_MASK   (0x4000U)
 
#define AIPS_PACRB_SP4_SHIFT   (14U)
 
#define AIPS_PACRB_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
 
#define AIPS_PACRB_TP3_MASK   (0x10000U)
 
#define AIPS_PACRB_TP3_SHIFT   (16U)
 
#define AIPS_PACRB_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
 
#define AIPS_PACRB_WP3_MASK   (0x20000U)
 
#define AIPS_PACRB_WP3_SHIFT   (17U)
 
#define AIPS_PACRB_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
 
#define AIPS_PACRB_SP3_MASK   (0x40000U)
 
#define AIPS_PACRB_SP3_SHIFT   (18U)
 
#define AIPS_PACRB_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
 
#define AIPS_PACRB_TP2_MASK   (0x100000U)
 
#define AIPS_PACRB_TP2_SHIFT   (20U)
 
#define AIPS_PACRB_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
 
#define AIPS_PACRB_WP2_MASK   (0x200000U)
 
#define AIPS_PACRB_WP2_SHIFT   (21U)
 
#define AIPS_PACRB_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
 
#define AIPS_PACRB_SP2_MASK   (0x400000U)
 
#define AIPS_PACRB_SP2_SHIFT   (22U)
 
#define AIPS_PACRB_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
 
#define AIPS_PACRB_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRB_TP1_SHIFT   (24U)
 
#define AIPS_PACRB_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
 
#define AIPS_PACRB_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRB_WP1_SHIFT   (25U)
 
#define AIPS_PACRB_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
 
#define AIPS_PACRB_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRB_SP1_SHIFT   (26U)
 
#define AIPS_PACRB_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
 
#define AIPS_PACRB_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRB_TP0_SHIFT   (28U)
 
#define AIPS_PACRB_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
 
#define AIPS_PACRB_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRB_WP0_SHIFT   (29U)
 
#define AIPS_PACRB_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
 
#define AIPS_PACRB_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRB_SP0_SHIFT   (30U)
 
#define AIPS_PACRB_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
 
#define AIPS_PACRB_TP7_MASK   0x1u
 
#define AIPS_PACRB_TP7_SHIFT   0
 
#define AIPS_PACRB_WP7_MASK   0x2u
 
#define AIPS_PACRB_WP7_SHIFT   1
 
#define AIPS_PACRB_SP7_MASK   0x4u
 
#define AIPS_PACRB_SP7_SHIFT   2
 
#define AIPS_PACRB_TP6_MASK   0x10u
 
#define AIPS_PACRB_TP6_SHIFT   4
 
#define AIPS_PACRB_WP6_MASK   0x20u
 
#define AIPS_PACRB_WP6_SHIFT   5
 
#define AIPS_PACRB_SP6_MASK   0x40u
 
#define AIPS_PACRB_SP6_SHIFT   6
 
#define AIPS_PACRB_TP5_MASK   0x100u
 
#define AIPS_PACRB_TP5_SHIFT   8
 
#define AIPS_PACRB_WP5_MASK   0x200u
 
#define AIPS_PACRB_WP5_SHIFT   9
 
#define AIPS_PACRB_SP5_MASK   0x400u
 
#define AIPS_PACRB_SP5_SHIFT   10
 
#define AIPS_PACRB_TP4_MASK   0x1000u
 
#define AIPS_PACRB_TP4_SHIFT   12
 
#define AIPS_PACRB_WP4_MASK   0x2000u
 
#define AIPS_PACRB_WP4_SHIFT   13
 
#define AIPS_PACRB_SP4_MASK   0x4000u
 
#define AIPS_PACRB_SP4_SHIFT   14
 
#define AIPS_PACRB_TP3_MASK   0x10000u
 
#define AIPS_PACRB_TP3_SHIFT   16
 
#define AIPS_PACRB_WP3_MASK   0x20000u
 
#define AIPS_PACRB_WP3_SHIFT   17
 
#define AIPS_PACRB_SP3_MASK   0x40000u
 
#define AIPS_PACRB_SP3_SHIFT   18
 
#define AIPS_PACRB_TP2_MASK   0x100000u
 
#define AIPS_PACRB_TP2_SHIFT   20
 
#define AIPS_PACRB_WP2_MASK   0x200000u
 
#define AIPS_PACRB_WP2_SHIFT   21
 
#define AIPS_PACRB_SP2_MASK   0x400000u
 
#define AIPS_PACRB_SP2_SHIFT   22
 
#define AIPS_PACRB_TP1_MASK   0x1000000u
 
#define AIPS_PACRB_TP1_SHIFT   24
 
#define AIPS_PACRB_WP1_MASK   0x2000000u
 
#define AIPS_PACRB_WP1_SHIFT   25
 
#define AIPS_PACRB_SP1_MASK   0x4000000u
 
#define AIPS_PACRB_SP1_SHIFT   26
 
#define AIPS_PACRB_TP0_MASK   0x10000000u
 
#define AIPS_PACRB_TP0_SHIFT   28
 
#define AIPS_PACRB_WP0_MASK   0x20000000u
 
#define AIPS_PACRB_WP0_SHIFT   29
 
#define AIPS_PACRB_SP0_MASK   0x40000000u
 
#define AIPS_PACRB_SP0_SHIFT   30
 
#define AIPS_PACRB_TP7_MASK   (0x1U)
 
#define AIPS_PACRB_TP7_SHIFT   (0U)
 
#define AIPS_PACRB_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
 
#define AIPS_PACRB_WP7_MASK   (0x2U)
 
#define AIPS_PACRB_WP7_SHIFT   (1U)
 
#define AIPS_PACRB_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
 
#define AIPS_PACRB_SP7_MASK   (0x4U)
 
#define AIPS_PACRB_SP7_SHIFT   (2U)
 
#define AIPS_PACRB_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
 
#define AIPS_PACRB_TP6_MASK   (0x10U)
 
#define AIPS_PACRB_TP6_SHIFT   (4U)
 
#define AIPS_PACRB_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
 
#define AIPS_PACRB_WP6_MASK   (0x20U)
 
#define AIPS_PACRB_WP6_SHIFT   (5U)
 
#define AIPS_PACRB_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
 
#define AIPS_PACRB_SP6_MASK   (0x40U)
 
#define AIPS_PACRB_SP6_SHIFT   (6U)
 
#define AIPS_PACRB_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
 
#define AIPS_PACRB_TP5_MASK   (0x100U)
 
#define AIPS_PACRB_TP5_SHIFT   (8U)
 
#define AIPS_PACRB_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
 
#define AIPS_PACRB_WP5_MASK   (0x200U)
 
#define AIPS_PACRB_WP5_SHIFT   (9U)
 
#define AIPS_PACRB_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
 
#define AIPS_PACRB_SP5_MASK   (0x400U)
 
#define AIPS_PACRB_SP5_SHIFT   (10U)
 
#define AIPS_PACRB_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
 
#define AIPS_PACRB_TP4_MASK   (0x1000U)
 
#define AIPS_PACRB_TP4_SHIFT   (12U)
 
#define AIPS_PACRB_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
 
#define AIPS_PACRB_WP4_MASK   (0x2000U)
 
#define AIPS_PACRB_WP4_SHIFT   (13U)
 
#define AIPS_PACRB_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
 
#define AIPS_PACRB_SP4_MASK   (0x4000U)
 
#define AIPS_PACRB_SP4_SHIFT   (14U)
 
#define AIPS_PACRB_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
 
#define AIPS_PACRB_TP3_MASK   (0x10000U)
 
#define AIPS_PACRB_TP3_SHIFT   (16U)
 
#define AIPS_PACRB_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
 
#define AIPS_PACRB_WP3_MASK   (0x20000U)
 
#define AIPS_PACRB_WP3_SHIFT   (17U)
 
#define AIPS_PACRB_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
 
#define AIPS_PACRB_SP3_MASK   (0x40000U)
 
#define AIPS_PACRB_SP3_SHIFT   (18U)
 
#define AIPS_PACRB_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
 
#define AIPS_PACRB_TP2_MASK   (0x100000U)
 
#define AIPS_PACRB_TP2_SHIFT   (20U)
 
#define AIPS_PACRB_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
 
#define AIPS_PACRB_WP2_MASK   (0x200000U)
 
#define AIPS_PACRB_WP2_SHIFT   (21U)
 
#define AIPS_PACRB_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
 
#define AIPS_PACRB_SP2_MASK   (0x400000U)
 
#define AIPS_PACRB_SP2_SHIFT   (22U)
 
#define AIPS_PACRB_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
 
#define AIPS_PACRB_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRB_TP1_SHIFT   (24U)
 
#define AIPS_PACRB_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
 
#define AIPS_PACRB_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRB_WP1_SHIFT   (25U)
 
#define AIPS_PACRB_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
 
#define AIPS_PACRB_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRB_SP1_SHIFT   (26U)
 
#define AIPS_PACRB_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
 
#define AIPS_PACRB_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRB_TP0_SHIFT   (28U)
 
#define AIPS_PACRB_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
 
#define AIPS_PACRB_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRB_WP0_SHIFT   (29U)
 
#define AIPS_PACRB_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
 
#define AIPS_PACRB_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRB_SP0_SHIFT   (30U)
 
#define AIPS_PACRB_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
 
#define AIPS_PACRB_TP7_MASK   (0x1U)
 
#define AIPS_PACRB_TP7_SHIFT   (0U)
 
#define AIPS_PACRB_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
 
#define AIPS_PACRB_WP7_MASK   (0x2U)
 
#define AIPS_PACRB_WP7_SHIFT   (1U)
 
#define AIPS_PACRB_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
 
#define AIPS_PACRB_SP7_MASK   (0x4U)
 
#define AIPS_PACRB_SP7_SHIFT   (2U)
 
#define AIPS_PACRB_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
 
#define AIPS_PACRB_TP6_MASK   (0x10U)
 
#define AIPS_PACRB_TP6_SHIFT   (4U)
 
#define AIPS_PACRB_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
 
#define AIPS_PACRB_WP6_MASK   (0x20U)
 
#define AIPS_PACRB_WP6_SHIFT   (5U)
 
#define AIPS_PACRB_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
 
#define AIPS_PACRB_SP6_MASK   (0x40U)
 
#define AIPS_PACRB_SP6_SHIFT   (6U)
 
#define AIPS_PACRB_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
 
#define AIPS_PACRB_TP5_MASK   (0x100U)
 
#define AIPS_PACRB_TP5_SHIFT   (8U)
 
#define AIPS_PACRB_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
 
#define AIPS_PACRB_WP5_MASK   (0x200U)
 
#define AIPS_PACRB_WP5_SHIFT   (9U)
 
#define AIPS_PACRB_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
 
#define AIPS_PACRB_SP5_MASK   (0x400U)
 
#define AIPS_PACRB_SP5_SHIFT   (10U)
 
#define AIPS_PACRB_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
 
#define AIPS_PACRB_TP4_MASK   (0x1000U)
 
#define AIPS_PACRB_TP4_SHIFT   (12U)
 
#define AIPS_PACRB_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
 
#define AIPS_PACRB_WP4_MASK   (0x2000U)
 
#define AIPS_PACRB_WP4_SHIFT   (13U)
 
#define AIPS_PACRB_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
 
#define AIPS_PACRB_SP4_MASK   (0x4000U)
 
#define AIPS_PACRB_SP4_SHIFT   (14U)
 
#define AIPS_PACRB_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
 
#define AIPS_PACRB_TP3_MASK   (0x10000U)
 
#define AIPS_PACRB_TP3_SHIFT   (16U)
 
#define AIPS_PACRB_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
 
#define AIPS_PACRB_WP3_MASK   (0x20000U)
 
#define AIPS_PACRB_WP3_SHIFT   (17U)
 
#define AIPS_PACRB_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
 
#define AIPS_PACRB_SP3_MASK   (0x40000U)
 
#define AIPS_PACRB_SP3_SHIFT   (18U)
 
#define AIPS_PACRB_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
 
#define AIPS_PACRB_TP2_MASK   (0x100000U)
 
#define AIPS_PACRB_TP2_SHIFT   (20U)
 
#define AIPS_PACRB_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
 
#define AIPS_PACRB_WP2_MASK   (0x200000U)
 
#define AIPS_PACRB_WP2_SHIFT   (21U)
 
#define AIPS_PACRB_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
 
#define AIPS_PACRB_SP2_MASK   (0x400000U)
 
#define AIPS_PACRB_SP2_SHIFT   (22U)
 
#define AIPS_PACRB_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
 
#define AIPS_PACRB_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRB_TP1_SHIFT   (24U)
 
#define AIPS_PACRB_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
 
#define AIPS_PACRB_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRB_WP1_SHIFT   (25U)
 
#define AIPS_PACRB_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
 
#define AIPS_PACRB_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRB_SP1_SHIFT   (26U)
 
#define AIPS_PACRB_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
 
#define AIPS_PACRB_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRB_TP0_SHIFT   (28U)
 
#define AIPS_PACRB_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
 
#define AIPS_PACRB_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRB_WP0_SHIFT   (29U)
 
#define AIPS_PACRB_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
 
#define AIPS_PACRB_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRB_SP0_SHIFT   (30U)
 
#define AIPS_PACRB_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
 
#define AIPS_PACRB_TP7_MASK   (0x1U)
 
#define AIPS_PACRB_TP7_SHIFT   (0U)
 
#define AIPS_PACRB_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
 
#define AIPS_PACRB_WP7_MASK   (0x2U)
 
#define AIPS_PACRB_WP7_SHIFT   (1U)
 
#define AIPS_PACRB_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
 
#define AIPS_PACRB_SP7_MASK   (0x4U)
 
#define AIPS_PACRB_SP7_SHIFT   (2U)
 
#define AIPS_PACRB_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
 
#define AIPS_PACRB_TP6_MASK   (0x10U)
 
#define AIPS_PACRB_TP6_SHIFT   (4U)
 
#define AIPS_PACRB_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
 
#define AIPS_PACRB_WP6_MASK   (0x20U)
 
#define AIPS_PACRB_WP6_SHIFT   (5U)
 
#define AIPS_PACRB_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
 
#define AIPS_PACRB_SP6_MASK   (0x40U)
 
#define AIPS_PACRB_SP6_SHIFT   (6U)
 
#define AIPS_PACRB_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
 
#define AIPS_PACRB_TP5_MASK   (0x100U)
 
#define AIPS_PACRB_TP5_SHIFT   (8U)
 
#define AIPS_PACRB_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
 
#define AIPS_PACRB_WP5_MASK   (0x200U)
 
#define AIPS_PACRB_WP5_SHIFT   (9U)
 
#define AIPS_PACRB_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
 
#define AIPS_PACRB_SP5_MASK   (0x400U)
 
#define AIPS_PACRB_SP5_SHIFT   (10U)
 
#define AIPS_PACRB_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
 
#define AIPS_PACRB_TP4_MASK   (0x1000U)
 
#define AIPS_PACRB_TP4_SHIFT   (12U)
 
#define AIPS_PACRB_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
 
#define AIPS_PACRB_WP4_MASK   (0x2000U)
 
#define AIPS_PACRB_WP4_SHIFT   (13U)
 
#define AIPS_PACRB_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
 
#define AIPS_PACRB_SP4_MASK   (0x4000U)
 
#define AIPS_PACRB_SP4_SHIFT   (14U)
 
#define AIPS_PACRB_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
 
#define AIPS_PACRB_TP3_MASK   (0x10000U)
 
#define AIPS_PACRB_TP3_SHIFT   (16U)
 
#define AIPS_PACRB_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
 
#define AIPS_PACRB_WP3_MASK   (0x20000U)
 
#define AIPS_PACRB_WP3_SHIFT   (17U)
 
#define AIPS_PACRB_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
 
#define AIPS_PACRB_SP3_MASK   (0x40000U)
 
#define AIPS_PACRB_SP3_SHIFT   (18U)
 
#define AIPS_PACRB_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
 
#define AIPS_PACRB_TP2_MASK   (0x100000U)
 
#define AIPS_PACRB_TP2_SHIFT   (20U)
 
#define AIPS_PACRB_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
 
#define AIPS_PACRB_WP2_MASK   (0x200000U)
 
#define AIPS_PACRB_WP2_SHIFT   (21U)
 
#define AIPS_PACRB_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
 
#define AIPS_PACRB_SP2_MASK   (0x400000U)
 
#define AIPS_PACRB_SP2_SHIFT   (22U)
 
#define AIPS_PACRB_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
 
#define AIPS_PACRB_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRB_TP1_SHIFT   (24U)
 
#define AIPS_PACRB_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
 
#define AIPS_PACRB_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRB_WP1_SHIFT   (25U)
 
#define AIPS_PACRB_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
 
#define AIPS_PACRB_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRB_SP1_SHIFT   (26U)
 
#define AIPS_PACRB_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
 
#define AIPS_PACRB_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRB_TP0_SHIFT   (28U)
 
#define AIPS_PACRB_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
 
#define AIPS_PACRB_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRB_WP0_SHIFT   (29U)
 
#define AIPS_PACRB_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
 
#define AIPS_PACRB_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRB_SP0_SHIFT   (30U)
 
#define AIPS_PACRB_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
 
#define AIPS_PACRB_TP7_MASK   (0x1U)
 
#define AIPS_PACRB_TP7_SHIFT   (0U)
 
#define AIPS_PACRB_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
 
#define AIPS_PACRB_WP7_MASK   (0x2U)
 
#define AIPS_PACRB_WP7_SHIFT   (1U)
 
#define AIPS_PACRB_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
 
#define AIPS_PACRB_SP7_MASK   (0x4U)
 
#define AIPS_PACRB_SP7_SHIFT   (2U)
 
#define AIPS_PACRB_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
 
#define AIPS_PACRB_TP6_MASK   (0x10U)
 
#define AIPS_PACRB_TP6_SHIFT   (4U)
 
#define AIPS_PACRB_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
 
#define AIPS_PACRB_WP6_MASK   (0x20U)
 
#define AIPS_PACRB_WP6_SHIFT   (5U)
 
#define AIPS_PACRB_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
 
#define AIPS_PACRB_SP6_MASK   (0x40U)
 
#define AIPS_PACRB_SP6_SHIFT   (6U)
 
#define AIPS_PACRB_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
 
#define AIPS_PACRB_TP5_MASK   (0x100U)
 
#define AIPS_PACRB_TP5_SHIFT   (8U)
 
#define AIPS_PACRB_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
 
#define AIPS_PACRB_WP5_MASK   (0x200U)
 
#define AIPS_PACRB_WP5_SHIFT   (9U)
 
#define AIPS_PACRB_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
 
#define AIPS_PACRB_SP5_MASK   (0x400U)
 
#define AIPS_PACRB_SP5_SHIFT   (10U)
 
#define AIPS_PACRB_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
 
#define AIPS_PACRB_TP4_MASK   (0x1000U)
 
#define AIPS_PACRB_TP4_SHIFT   (12U)
 
#define AIPS_PACRB_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
 
#define AIPS_PACRB_WP4_MASK   (0x2000U)
 
#define AIPS_PACRB_WP4_SHIFT   (13U)
 
#define AIPS_PACRB_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
 
#define AIPS_PACRB_SP4_MASK   (0x4000U)
 
#define AIPS_PACRB_SP4_SHIFT   (14U)
 
#define AIPS_PACRB_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
 
#define AIPS_PACRB_TP3_MASK   (0x10000U)
 
#define AIPS_PACRB_TP3_SHIFT   (16U)
 
#define AIPS_PACRB_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
 
#define AIPS_PACRB_WP3_MASK   (0x20000U)
 
#define AIPS_PACRB_WP3_SHIFT   (17U)
 
#define AIPS_PACRB_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
 
#define AIPS_PACRB_SP3_MASK   (0x40000U)
 
#define AIPS_PACRB_SP3_SHIFT   (18U)
 
#define AIPS_PACRB_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
 
#define AIPS_PACRB_TP2_MASK   (0x100000U)
 
#define AIPS_PACRB_TP2_SHIFT   (20U)
 
#define AIPS_PACRB_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
 
#define AIPS_PACRB_WP2_MASK   (0x200000U)
 
#define AIPS_PACRB_WP2_SHIFT   (21U)
 
#define AIPS_PACRB_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
 
#define AIPS_PACRB_SP2_MASK   (0x400000U)
 
#define AIPS_PACRB_SP2_SHIFT   (22U)
 
#define AIPS_PACRB_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
 
#define AIPS_PACRB_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRB_TP1_SHIFT   (24U)
 
#define AIPS_PACRB_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
 
#define AIPS_PACRB_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRB_WP1_SHIFT   (25U)
 
#define AIPS_PACRB_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
 
#define AIPS_PACRB_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRB_SP1_SHIFT   (26U)
 
#define AIPS_PACRB_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
 
#define AIPS_PACRB_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRB_TP0_SHIFT   (28U)
 
#define AIPS_PACRB_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
 
#define AIPS_PACRB_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRB_WP0_SHIFT   (29U)
 
#define AIPS_PACRB_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
 
#define AIPS_PACRB_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRB_SP0_SHIFT   (30U)
 
#define AIPS_PACRB_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
 

PACRC - Peripheral Access Control Register

#define AIPS_PACRC_TP7_MASK   (0x1U)
 
#define AIPS_PACRC_TP7_SHIFT   (0U)
 
#define AIPS_PACRC_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
 
#define AIPS_PACRC_WP7_MASK   (0x2U)
 
#define AIPS_PACRC_WP7_SHIFT   (1U)
 
#define AIPS_PACRC_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
 
#define AIPS_PACRC_SP7_MASK   (0x4U)
 
#define AIPS_PACRC_SP7_SHIFT   (2U)
 
#define AIPS_PACRC_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
 
#define AIPS_PACRC_TP6_MASK   (0x10U)
 
#define AIPS_PACRC_TP6_SHIFT   (4U)
 
#define AIPS_PACRC_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
 
#define AIPS_PACRC_WP6_MASK   (0x20U)
 
#define AIPS_PACRC_WP6_SHIFT   (5U)
 
#define AIPS_PACRC_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
 
#define AIPS_PACRC_SP6_MASK   (0x40U)
 
#define AIPS_PACRC_SP6_SHIFT   (6U)
 
#define AIPS_PACRC_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
 
#define AIPS_PACRC_TP5_MASK   (0x100U)
 
#define AIPS_PACRC_TP5_SHIFT   (8U)
 
#define AIPS_PACRC_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
 
#define AIPS_PACRC_WP5_MASK   (0x200U)
 
#define AIPS_PACRC_WP5_SHIFT   (9U)
 
#define AIPS_PACRC_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
 
#define AIPS_PACRC_SP5_MASK   (0x400U)
 
#define AIPS_PACRC_SP5_SHIFT   (10U)
 
#define AIPS_PACRC_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
 
#define AIPS_PACRC_TP4_MASK   (0x1000U)
 
#define AIPS_PACRC_TP4_SHIFT   (12U)
 
#define AIPS_PACRC_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
 
#define AIPS_PACRC_WP4_MASK   (0x2000U)
 
#define AIPS_PACRC_WP4_SHIFT   (13U)
 
#define AIPS_PACRC_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
 
#define AIPS_PACRC_SP4_MASK   (0x4000U)
 
#define AIPS_PACRC_SP4_SHIFT   (14U)
 
#define AIPS_PACRC_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
 
#define AIPS_PACRC_TP3_MASK   (0x10000U)
 
#define AIPS_PACRC_TP3_SHIFT   (16U)
 
#define AIPS_PACRC_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
 
#define AIPS_PACRC_WP3_MASK   (0x20000U)
 
#define AIPS_PACRC_WP3_SHIFT   (17U)
 
#define AIPS_PACRC_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
 
#define AIPS_PACRC_SP3_MASK   (0x40000U)
 
#define AIPS_PACRC_SP3_SHIFT   (18U)
 
#define AIPS_PACRC_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
 
#define AIPS_PACRC_TP2_MASK   (0x100000U)
 
#define AIPS_PACRC_TP2_SHIFT   (20U)
 
#define AIPS_PACRC_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
 
#define AIPS_PACRC_WP2_MASK   (0x200000U)
 
#define AIPS_PACRC_WP2_SHIFT   (21U)
 
#define AIPS_PACRC_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
 
#define AIPS_PACRC_SP2_MASK   (0x400000U)
 
#define AIPS_PACRC_SP2_SHIFT   (22U)
 
#define AIPS_PACRC_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
 
#define AIPS_PACRC_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRC_TP1_SHIFT   (24U)
 
#define AIPS_PACRC_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
 
#define AIPS_PACRC_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRC_WP1_SHIFT   (25U)
 
#define AIPS_PACRC_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
 
#define AIPS_PACRC_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRC_SP1_SHIFT   (26U)
 
#define AIPS_PACRC_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
 
#define AIPS_PACRC_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRC_TP0_SHIFT   (28U)
 
#define AIPS_PACRC_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
 
#define AIPS_PACRC_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRC_WP0_SHIFT   (29U)
 
#define AIPS_PACRC_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
 
#define AIPS_PACRC_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRC_SP0_SHIFT   (30U)
 
#define AIPS_PACRC_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
 
#define AIPS_PACRC_TP7_MASK   0x1u
 
#define AIPS_PACRC_TP7_SHIFT   0
 
#define AIPS_PACRC_WP7_MASK   0x2u
 
#define AIPS_PACRC_WP7_SHIFT   1
 
#define AIPS_PACRC_SP7_MASK   0x4u
 
#define AIPS_PACRC_SP7_SHIFT   2
 
#define AIPS_PACRC_TP6_MASK   0x10u
 
#define AIPS_PACRC_TP6_SHIFT   4
 
#define AIPS_PACRC_WP6_MASK   0x20u
 
#define AIPS_PACRC_WP6_SHIFT   5
 
#define AIPS_PACRC_SP6_MASK   0x40u
 
#define AIPS_PACRC_SP6_SHIFT   6
 
#define AIPS_PACRC_TP5_MASK   0x100u
 
#define AIPS_PACRC_TP5_SHIFT   8
 
#define AIPS_PACRC_WP5_MASK   0x200u
 
#define AIPS_PACRC_WP5_SHIFT   9
 
#define AIPS_PACRC_SP5_MASK   0x400u
 
#define AIPS_PACRC_SP5_SHIFT   10
 
#define AIPS_PACRC_TP4_MASK   0x1000u
 
#define AIPS_PACRC_TP4_SHIFT   12
 
#define AIPS_PACRC_WP4_MASK   0x2000u
 
#define AIPS_PACRC_WP4_SHIFT   13
 
#define AIPS_PACRC_SP4_MASK   0x4000u
 
#define AIPS_PACRC_SP4_SHIFT   14
 
#define AIPS_PACRC_TP3_MASK   0x10000u
 
#define AIPS_PACRC_TP3_SHIFT   16
 
#define AIPS_PACRC_WP3_MASK   0x20000u
 
#define AIPS_PACRC_WP3_SHIFT   17
 
#define AIPS_PACRC_SP3_MASK   0x40000u
 
#define AIPS_PACRC_SP3_SHIFT   18
 
#define AIPS_PACRC_TP2_MASK   0x100000u
 
#define AIPS_PACRC_TP2_SHIFT   20
 
#define AIPS_PACRC_WP2_MASK   0x200000u
 
#define AIPS_PACRC_WP2_SHIFT   21
 
#define AIPS_PACRC_SP2_MASK   0x400000u
 
#define AIPS_PACRC_SP2_SHIFT   22
 
#define AIPS_PACRC_TP1_MASK   0x1000000u
 
#define AIPS_PACRC_TP1_SHIFT   24
 
#define AIPS_PACRC_WP1_MASK   0x2000000u
 
#define AIPS_PACRC_WP1_SHIFT   25
 
#define AIPS_PACRC_SP1_MASK   0x4000000u
 
#define AIPS_PACRC_SP1_SHIFT   26
 
#define AIPS_PACRC_TP0_MASK   0x10000000u
 
#define AIPS_PACRC_TP0_SHIFT   28
 
#define AIPS_PACRC_WP0_MASK   0x20000000u
 
#define AIPS_PACRC_WP0_SHIFT   29
 
#define AIPS_PACRC_SP0_MASK   0x40000000u
 
#define AIPS_PACRC_SP0_SHIFT   30
 
#define AIPS_PACRC_TP7_MASK   (0x1U)
 
#define AIPS_PACRC_TP7_SHIFT   (0U)
 
#define AIPS_PACRC_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
 
#define AIPS_PACRC_WP7_MASK   (0x2U)
 
#define AIPS_PACRC_WP7_SHIFT   (1U)
 
#define AIPS_PACRC_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
 
#define AIPS_PACRC_SP7_MASK   (0x4U)
 
#define AIPS_PACRC_SP7_SHIFT   (2U)
 
#define AIPS_PACRC_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
 
#define AIPS_PACRC_TP6_MASK   (0x10U)
 
#define AIPS_PACRC_TP6_SHIFT   (4U)
 
#define AIPS_PACRC_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
 
#define AIPS_PACRC_WP6_MASK   (0x20U)
 
#define AIPS_PACRC_WP6_SHIFT   (5U)
 
#define AIPS_PACRC_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
 
#define AIPS_PACRC_SP6_MASK   (0x40U)
 
#define AIPS_PACRC_SP6_SHIFT   (6U)
 
#define AIPS_PACRC_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
 
#define AIPS_PACRC_TP5_MASK   (0x100U)
 
#define AIPS_PACRC_TP5_SHIFT   (8U)
 
#define AIPS_PACRC_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
 
#define AIPS_PACRC_WP5_MASK   (0x200U)
 
#define AIPS_PACRC_WP5_SHIFT   (9U)
 
#define AIPS_PACRC_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
 
#define AIPS_PACRC_SP5_MASK   (0x400U)
 
#define AIPS_PACRC_SP5_SHIFT   (10U)
 
#define AIPS_PACRC_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
 
#define AIPS_PACRC_TP4_MASK   (0x1000U)
 
#define AIPS_PACRC_TP4_SHIFT   (12U)
 
#define AIPS_PACRC_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
 
#define AIPS_PACRC_WP4_MASK   (0x2000U)
 
#define AIPS_PACRC_WP4_SHIFT   (13U)
 
#define AIPS_PACRC_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
 
#define AIPS_PACRC_SP4_MASK   (0x4000U)
 
#define AIPS_PACRC_SP4_SHIFT   (14U)
 
#define AIPS_PACRC_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
 
#define AIPS_PACRC_TP3_MASK   (0x10000U)
 
#define AIPS_PACRC_TP3_SHIFT   (16U)
 
#define AIPS_PACRC_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
 
#define AIPS_PACRC_WP3_MASK   (0x20000U)
 
#define AIPS_PACRC_WP3_SHIFT   (17U)
 
#define AIPS_PACRC_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
 
#define AIPS_PACRC_SP3_MASK   (0x40000U)
 
#define AIPS_PACRC_SP3_SHIFT   (18U)
 
#define AIPS_PACRC_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
 
#define AIPS_PACRC_TP2_MASK   (0x100000U)
 
#define AIPS_PACRC_TP2_SHIFT   (20U)
 
#define AIPS_PACRC_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
 
#define AIPS_PACRC_WP2_MASK   (0x200000U)
 
#define AIPS_PACRC_WP2_SHIFT   (21U)
 
#define AIPS_PACRC_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
 
#define AIPS_PACRC_SP2_MASK   (0x400000U)
 
#define AIPS_PACRC_SP2_SHIFT   (22U)
 
#define AIPS_PACRC_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
 
#define AIPS_PACRC_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRC_TP1_SHIFT   (24U)
 
#define AIPS_PACRC_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
 
#define AIPS_PACRC_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRC_WP1_SHIFT   (25U)
 
#define AIPS_PACRC_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
 
#define AIPS_PACRC_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRC_SP1_SHIFT   (26U)
 
#define AIPS_PACRC_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
 
#define AIPS_PACRC_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRC_TP0_SHIFT   (28U)
 
#define AIPS_PACRC_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
 
#define AIPS_PACRC_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRC_WP0_SHIFT   (29U)
 
#define AIPS_PACRC_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
 
#define AIPS_PACRC_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRC_SP0_SHIFT   (30U)
 
#define AIPS_PACRC_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
 
#define AIPS_PACRC_TP7_MASK   (0x1U)
 
#define AIPS_PACRC_TP7_SHIFT   (0U)
 
#define AIPS_PACRC_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
 
#define AIPS_PACRC_WP7_MASK   (0x2U)
 
#define AIPS_PACRC_WP7_SHIFT   (1U)
 
#define AIPS_PACRC_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
 
#define AIPS_PACRC_SP7_MASK   (0x4U)
 
#define AIPS_PACRC_SP7_SHIFT   (2U)
 
#define AIPS_PACRC_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
 
#define AIPS_PACRC_TP6_MASK   (0x10U)
 
#define AIPS_PACRC_TP6_SHIFT   (4U)
 
#define AIPS_PACRC_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
 
#define AIPS_PACRC_WP6_MASK   (0x20U)
 
#define AIPS_PACRC_WP6_SHIFT   (5U)
 
#define AIPS_PACRC_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
 
#define AIPS_PACRC_SP6_MASK   (0x40U)
 
#define AIPS_PACRC_SP6_SHIFT   (6U)
 
#define AIPS_PACRC_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
 
#define AIPS_PACRC_TP5_MASK   (0x100U)
 
#define AIPS_PACRC_TP5_SHIFT   (8U)
 
#define AIPS_PACRC_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
 
#define AIPS_PACRC_WP5_MASK   (0x200U)
 
#define AIPS_PACRC_WP5_SHIFT   (9U)
 
#define AIPS_PACRC_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
 
#define AIPS_PACRC_SP5_MASK   (0x400U)
 
#define AIPS_PACRC_SP5_SHIFT   (10U)
 
#define AIPS_PACRC_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
 
#define AIPS_PACRC_TP4_MASK   (0x1000U)
 
#define AIPS_PACRC_TP4_SHIFT   (12U)
 
#define AIPS_PACRC_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
 
#define AIPS_PACRC_WP4_MASK   (0x2000U)
 
#define AIPS_PACRC_WP4_SHIFT   (13U)
 
#define AIPS_PACRC_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
 
#define AIPS_PACRC_SP4_MASK   (0x4000U)
 
#define AIPS_PACRC_SP4_SHIFT   (14U)
 
#define AIPS_PACRC_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
 
#define AIPS_PACRC_TP3_MASK   (0x10000U)
 
#define AIPS_PACRC_TP3_SHIFT   (16U)
 
#define AIPS_PACRC_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
 
#define AIPS_PACRC_WP3_MASK   (0x20000U)
 
#define AIPS_PACRC_WP3_SHIFT   (17U)
 
#define AIPS_PACRC_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
 
#define AIPS_PACRC_SP3_MASK   (0x40000U)
 
#define AIPS_PACRC_SP3_SHIFT   (18U)
 
#define AIPS_PACRC_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
 
#define AIPS_PACRC_TP2_MASK   (0x100000U)
 
#define AIPS_PACRC_TP2_SHIFT   (20U)
 
#define AIPS_PACRC_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
 
#define AIPS_PACRC_WP2_MASK   (0x200000U)
 
#define AIPS_PACRC_WP2_SHIFT   (21U)
 
#define AIPS_PACRC_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
 
#define AIPS_PACRC_SP2_MASK   (0x400000U)
 
#define AIPS_PACRC_SP2_SHIFT   (22U)
 
#define AIPS_PACRC_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
 
#define AIPS_PACRC_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRC_TP1_SHIFT   (24U)
 
#define AIPS_PACRC_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
 
#define AIPS_PACRC_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRC_WP1_SHIFT   (25U)
 
#define AIPS_PACRC_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
 
#define AIPS_PACRC_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRC_SP1_SHIFT   (26U)
 
#define AIPS_PACRC_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
 
#define AIPS_PACRC_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRC_TP0_SHIFT   (28U)
 
#define AIPS_PACRC_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
 
#define AIPS_PACRC_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRC_WP0_SHIFT   (29U)
 
#define AIPS_PACRC_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
 
#define AIPS_PACRC_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRC_SP0_SHIFT   (30U)
 
#define AIPS_PACRC_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
 
#define AIPS_PACRC_TP7_MASK   (0x1U)
 
#define AIPS_PACRC_TP7_SHIFT   (0U)
 
#define AIPS_PACRC_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
 
#define AIPS_PACRC_WP7_MASK   (0x2U)
 
#define AIPS_PACRC_WP7_SHIFT   (1U)
 
#define AIPS_PACRC_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
 
#define AIPS_PACRC_SP7_MASK   (0x4U)
 
#define AIPS_PACRC_SP7_SHIFT   (2U)
 
#define AIPS_PACRC_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
 
#define AIPS_PACRC_TP6_MASK   (0x10U)
 
#define AIPS_PACRC_TP6_SHIFT   (4U)
 
#define AIPS_PACRC_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
 
#define AIPS_PACRC_WP6_MASK   (0x20U)
 
#define AIPS_PACRC_WP6_SHIFT   (5U)
 
#define AIPS_PACRC_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
 
#define AIPS_PACRC_SP6_MASK   (0x40U)
 
#define AIPS_PACRC_SP6_SHIFT   (6U)
 
#define AIPS_PACRC_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
 
#define AIPS_PACRC_TP5_MASK   (0x100U)
 
#define AIPS_PACRC_TP5_SHIFT   (8U)
 
#define AIPS_PACRC_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
 
#define AIPS_PACRC_WP5_MASK   (0x200U)
 
#define AIPS_PACRC_WP5_SHIFT   (9U)
 
#define AIPS_PACRC_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
 
#define AIPS_PACRC_SP5_MASK   (0x400U)
 
#define AIPS_PACRC_SP5_SHIFT   (10U)
 
#define AIPS_PACRC_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
 
#define AIPS_PACRC_TP4_MASK   (0x1000U)
 
#define AIPS_PACRC_TP4_SHIFT   (12U)
 
#define AIPS_PACRC_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
 
#define AIPS_PACRC_WP4_MASK   (0x2000U)
 
#define AIPS_PACRC_WP4_SHIFT   (13U)
 
#define AIPS_PACRC_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
 
#define AIPS_PACRC_SP4_MASK   (0x4000U)
 
#define AIPS_PACRC_SP4_SHIFT   (14U)
 
#define AIPS_PACRC_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
 
#define AIPS_PACRC_TP3_MASK   (0x10000U)
 
#define AIPS_PACRC_TP3_SHIFT   (16U)
 
#define AIPS_PACRC_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
 
#define AIPS_PACRC_WP3_MASK   (0x20000U)
 
#define AIPS_PACRC_WP3_SHIFT   (17U)
 
#define AIPS_PACRC_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
 
#define AIPS_PACRC_SP3_MASK   (0x40000U)
 
#define AIPS_PACRC_SP3_SHIFT   (18U)
 
#define AIPS_PACRC_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
 
#define AIPS_PACRC_TP2_MASK   (0x100000U)
 
#define AIPS_PACRC_TP2_SHIFT   (20U)
 
#define AIPS_PACRC_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
 
#define AIPS_PACRC_WP2_MASK   (0x200000U)
 
#define AIPS_PACRC_WP2_SHIFT   (21U)
 
#define AIPS_PACRC_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
 
#define AIPS_PACRC_SP2_MASK   (0x400000U)
 
#define AIPS_PACRC_SP2_SHIFT   (22U)
 
#define AIPS_PACRC_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
 
#define AIPS_PACRC_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRC_TP1_SHIFT   (24U)
 
#define AIPS_PACRC_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
 
#define AIPS_PACRC_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRC_WP1_SHIFT   (25U)
 
#define AIPS_PACRC_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
 
#define AIPS_PACRC_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRC_SP1_SHIFT   (26U)
 
#define AIPS_PACRC_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
 
#define AIPS_PACRC_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRC_TP0_SHIFT   (28U)
 
#define AIPS_PACRC_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
 
#define AIPS_PACRC_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRC_WP0_SHIFT   (29U)
 
#define AIPS_PACRC_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
 
#define AIPS_PACRC_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRC_SP0_SHIFT   (30U)
 
#define AIPS_PACRC_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
 
#define AIPS_PACRC_TP7_MASK   (0x1U)
 
#define AIPS_PACRC_TP7_SHIFT   (0U)
 
#define AIPS_PACRC_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
 
#define AIPS_PACRC_WP7_MASK   (0x2U)
 
#define AIPS_PACRC_WP7_SHIFT   (1U)
 
#define AIPS_PACRC_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
 
#define AIPS_PACRC_SP7_MASK   (0x4U)
 
#define AIPS_PACRC_SP7_SHIFT   (2U)
 
#define AIPS_PACRC_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
 
#define AIPS_PACRC_TP6_MASK   (0x10U)
 
#define AIPS_PACRC_TP6_SHIFT   (4U)
 
#define AIPS_PACRC_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
 
#define AIPS_PACRC_WP6_MASK   (0x20U)
 
#define AIPS_PACRC_WP6_SHIFT   (5U)
 
#define AIPS_PACRC_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
 
#define AIPS_PACRC_SP6_MASK   (0x40U)
 
#define AIPS_PACRC_SP6_SHIFT   (6U)
 
#define AIPS_PACRC_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
 
#define AIPS_PACRC_TP5_MASK   (0x100U)
 
#define AIPS_PACRC_TP5_SHIFT   (8U)
 
#define AIPS_PACRC_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
 
#define AIPS_PACRC_WP5_MASK   (0x200U)
 
#define AIPS_PACRC_WP5_SHIFT   (9U)
 
#define AIPS_PACRC_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
 
#define AIPS_PACRC_SP5_MASK   (0x400U)
 
#define AIPS_PACRC_SP5_SHIFT   (10U)
 
#define AIPS_PACRC_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
 
#define AIPS_PACRC_TP4_MASK   (0x1000U)
 
#define AIPS_PACRC_TP4_SHIFT   (12U)
 
#define AIPS_PACRC_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
 
#define AIPS_PACRC_WP4_MASK   (0x2000U)
 
#define AIPS_PACRC_WP4_SHIFT   (13U)
 
#define AIPS_PACRC_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
 
#define AIPS_PACRC_SP4_MASK   (0x4000U)
 
#define AIPS_PACRC_SP4_SHIFT   (14U)
 
#define AIPS_PACRC_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
 
#define AIPS_PACRC_TP3_MASK   (0x10000U)
 
#define AIPS_PACRC_TP3_SHIFT   (16U)
 
#define AIPS_PACRC_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
 
#define AIPS_PACRC_WP3_MASK   (0x20000U)
 
#define AIPS_PACRC_WP3_SHIFT   (17U)
 
#define AIPS_PACRC_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
 
#define AIPS_PACRC_SP3_MASK   (0x40000U)
 
#define AIPS_PACRC_SP3_SHIFT   (18U)
 
#define AIPS_PACRC_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
 
#define AIPS_PACRC_TP2_MASK   (0x100000U)
 
#define AIPS_PACRC_TP2_SHIFT   (20U)
 
#define AIPS_PACRC_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
 
#define AIPS_PACRC_WP2_MASK   (0x200000U)
 
#define AIPS_PACRC_WP2_SHIFT   (21U)
 
#define AIPS_PACRC_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
 
#define AIPS_PACRC_SP2_MASK   (0x400000U)
 
#define AIPS_PACRC_SP2_SHIFT   (22U)
 
#define AIPS_PACRC_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
 
#define AIPS_PACRC_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRC_TP1_SHIFT   (24U)
 
#define AIPS_PACRC_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
 
#define AIPS_PACRC_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRC_WP1_SHIFT   (25U)
 
#define AIPS_PACRC_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
 
#define AIPS_PACRC_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRC_SP1_SHIFT   (26U)
 
#define AIPS_PACRC_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
 
#define AIPS_PACRC_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRC_TP0_SHIFT   (28U)
 
#define AIPS_PACRC_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
 
#define AIPS_PACRC_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRC_WP0_SHIFT   (29U)
 
#define AIPS_PACRC_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
 
#define AIPS_PACRC_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRC_SP0_SHIFT   (30U)
 
#define AIPS_PACRC_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
 

PACRD - Peripheral Access Control Register

#define AIPS_PACRD_TP7_MASK   (0x1U)
 
#define AIPS_PACRD_TP7_SHIFT   (0U)
 
#define AIPS_PACRD_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
 
#define AIPS_PACRD_WP7_MASK   (0x2U)
 
#define AIPS_PACRD_WP7_SHIFT   (1U)
 
#define AIPS_PACRD_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
 
#define AIPS_PACRD_SP7_MASK   (0x4U)
 
#define AIPS_PACRD_SP7_SHIFT   (2U)
 
#define AIPS_PACRD_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
 
#define AIPS_PACRD_TP6_MASK   (0x10U)
 
#define AIPS_PACRD_TP6_SHIFT   (4U)
 
#define AIPS_PACRD_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
 
#define AIPS_PACRD_WP6_MASK   (0x20U)
 
#define AIPS_PACRD_WP6_SHIFT   (5U)
 
#define AIPS_PACRD_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
 
#define AIPS_PACRD_SP6_MASK   (0x40U)
 
#define AIPS_PACRD_SP6_SHIFT   (6U)
 
#define AIPS_PACRD_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
 
#define AIPS_PACRD_TP5_MASK   (0x100U)
 
#define AIPS_PACRD_TP5_SHIFT   (8U)
 
#define AIPS_PACRD_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
 
#define AIPS_PACRD_WP5_MASK   (0x200U)
 
#define AIPS_PACRD_WP5_SHIFT   (9U)
 
#define AIPS_PACRD_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
 
#define AIPS_PACRD_SP5_MASK   (0x400U)
 
#define AIPS_PACRD_SP5_SHIFT   (10U)
 
#define AIPS_PACRD_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
 
#define AIPS_PACRD_TP4_MASK   (0x1000U)
 
#define AIPS_PACRD_TP4_SHIFT   (12U)
 
#define AIPS_PACRD_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
 
#define AIPS_PACRD_WP4_MASK   (0x2000U)
 
#define AIPS_PACRD_WP4_SHIFT   (13U)
 
#define AIPS_PACRD_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
 
#define AIPS_PACRD_SP4_MASK   (0x4000U)
 
#define AIPS_PACRD_SP4_SHIFT   (14U)
 
#define AIPS_PACRD_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
 
#define AIPS_PACRD_TP3_MASK   (0x10000U)
 
#define AIPS_PACRD_TP3_SHIFT   (16U)
 
#define AIPS_PACRD_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
 
#define AIPS_PACRD_WP3_MASK   (0x20000U)
 
#define AIPS_PACRD_WP3_SHIFT   (17U)
 
#define AIPS_PACRD_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
 
#define AIPS_PACRD_SP3_MASK   (0x40000U)
 
#define AIPS_PACRD_SP3_SHIFT   (18U)
 
#define AIPS_PACRD_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
 
#define AIPS_PACRD_TP2_MASK   (0x100000U)
 
#define AIPS_PACRD_TP2_SHIFT   (20U)
 
#define AIPS_PACRD_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
 
#define AIPS_PACRD_WP2_MASK   (0x200000U)
 
#define AIPS_PACRD_WP2_SHIFT   (21U)
 
#define AIPS_PACRD_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
 
#define AIPS_PACRD_SP2_MASK   (0x400000U)
 
#define AIPS_PACRD_SP2_SHIFT   (22U)
 
#define AIPS_PACRD_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
 
#define AIPS_PACRD_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRD_TP1_SHIFT   (24U)
 
#define AIPS_PACRD_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
 
#define AIPS_PACRD_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRD_WP1_SHIFT   (25U)
 
#define AIPS_PACRD_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
 
#define AIPS_PACRD_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRD_SP1_SHIFT   (26U)
 
#define AIPS_PACRD_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
 
#define AIPS_PACRD_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRD_TP0_SHIFT   (28U)
 
#define AIPS_PACRD_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
 
#define AIPS_PACRD_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRD_WP0_SHIFT   (29U)
 
#define AIPS_PACRD_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
 
#define AIPS_PACRD_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRD_SP0_SHIFT   (30U)
 
#define AIPS_PACRD_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
 
#define AIPS_PACRD_TP7_MASK   0x1u
 
#define AIPS_PACRD_TP7_SHIFT   0
 
#define AIPS_PACRD_WP7_MASK   0x2u
 
#define AIPS_PACRD_WP7_SHIFT   1
 
#define AIPS_PACRD_SP7_MASK   0x4u
 
#define AIPS_PACRD_SP7_SHIFT   2
 
#define AIPS_PACRD_TP6_MASK   0x10u
 
#define AIPS_PACRD_TP6_SHIFT   4
 
#define AIPS_PACRD_WP6_MASK   0x20u
 
#define AIPS_PACRD_WP6_SHIFT   5
 
#define AIPS_PACRD_SP6_MASK   0x40u
 
#define AIPS_PACRD_SP6_SHIFT   6
 
#define AIPS_PACRD_TP5_MASK   0x100u
 
#define AIPS_PACRD_TP5_SHIFT   8
 
#define AIPS_PACRD_WP5_MASK   0x200u
 
#define AIPS_PACRD_WP5_SHIFT   9
 
#define AIPS_PACRD_SP5_MASK   0x400u
 
#define AIPS_PACRD_SP5_SHIFT   10
 
#define AIPS_PACRD_TP4_MASK   0x1000u
 
#define AIPS_PACRD_TP4_SHIFT   12
 
#define AIPS_PACRD_WP4_MASK   0x2000u
 
#define AIPS_PACRD_WP4_SHIFT   13
 
#define AIPS_PACRD_SP4_MASK   0x4000u
 
#define AIPS_PACRD_SP4_SHIFT   14
 
#define AIPS_PACRD_TP3_MASK   0x10000u
 
#define AIPS_PACRD_TP3_SHIFT   16
 
#define AIPS_PACRD_WP3_MASK   0x20000u
 
#define AIPS_PACRD_WP3_SHIFT   17
 
#define AIPS_PACRD_SP3_MASK   0x40000u
 
#define AIPS_PACRD_SP3_SHIFT   18
 
#define AIPS_PACRD_TP2_MASK   0x100000u
 
#define AIPS_PACRD_TP2_SHIFT   20
 
#define AIPS_PACRD_WP2_MASK   0x200000u
 
#define AIPS_PACRD_WP2_SHIFT   21
 
#define AIPS_PACRD_SP2_MASK   0x400000u
 
#define AIPS_PACRD_SP2_SHIFT   22
 
#define AIPS_PACRD_TP1_MASK   0x1000000u
 
#define AIPS_PACRD_TP1_SHIFT   24
 
#define AIPS_PACRD_WP1_MASK   0x2000000u
 
#define AIPS_PACRD_WP1_SHIFT   25
 
#define AIPS_PACRD_SP1_MASK   0x4000000u
 
#define AIPS_PACRD_SP1_SHIFT   26
 
#define AIPS_PACRD_TP0_MASK   0x10000000u
 
#define AIPS_PACRD_TP0_SHIFT   28
 
#define AIPS_PACRD_WP0_MASK   0x20000000u
 
#define AIPS_PACRD_WP0_SHIFT   29
 
#define AIPS_PACRD_SP0_MASK   0x40000000u
 
#define AIPS_PACRD_SP0_SHIFT   30
 
#define AIPS_PACRD_TP7_MASK   (0x1U)
 
#define AIPS_PACRD_TP7_SHIFT   (0U)
 
#define AIPS_PACRD_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
 
#define AIPS_PACRD_WP7_MASK   (0x2U)
 
#define AIPS_PACRD_WP7_SHIFT   (1U)
 
#define AIPS_PACRD_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
 
#define AIPS_PACRD_SP7_MASK   (0x4U)
 
#define AIPS_PACRD_SP7_SHIFT   (2U)
 
#define AIPS_PACRD_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
 
#define AIPS_PACRD_TP6_MASK   (0x10U)
 
#define AIPS_PACRD_TP6_SHIFT   (4U)
 
#define AIPS_PACRD_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
 
#define AIPS_PACRD_WP6_MASK   (0x20U)
 
#define AIPS_PACRD_WP6_SHIFT   (5U)
 
#define AIPS_PACRD_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
 
#define AIPS_PACRD_SP6_MASK   (0x40U)
 
#define AIPS_PACRD_SP6_SHIFT   (6U)
 
#define AIPS_PACRD_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
 
#define AIPS_PACRD_TP5_MASK   (0x100U)
 
#define AIPS_PACRD_TP5_SHIFT   (8U)
 
#define AIPS_PACRD_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
 
#define AIPS_PACRD_WP5_MASK   (0x200U)
 
#define AIPS_PACRD_WP5_SHIFT   (9U)
 
#define AIPS_PACRD_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
 
#define AIPS_PACRD_SP5_MASK   (0x400U)
 
#define AIPS_PACRD_SP5_SHIFT   (10U)
 
#define AIPS_PACRD_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
 
#define AIPS_PACRD_TP4_MASK   (0x1000U)
 
#define AIPS_PACRD_TP4_SHIFT   (12U)
 
#define AIPS_PACRD_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
 
#define AIPS_PACRD_WP4_MASK   (0x2000U)
 
#define AIPS_PACRD_WP4_SHIFT   (13U)
 
#define AIPS_PACRD_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
 
#define AIPS_PACRD_SP4_MASK   (0x4000U)
 
#define AIPS_PACRD_SP4_SHIFT   (14U)
 
#define AIPS_PACRD_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
 
#define AIPS_PACRD_TP3_MASK   (0x10000U)
 
#define AIPS_PACRD_TP3_SHIFT   (16U)
 
#define AIPS_PACRD_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
 
#define AIPS_PACRD_WP3_MASK   (0x20000U)
 
#define AIPS_PACRD_WP3_SHIFT   (17U)
 
#define AIPS_PACRD_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
 
#define AIPS_PACRD_SP3_MASK   (0x40000U)
 
#define AIPS_PACRD_SP3_SHIFT   (18U)
 
#define AIPS_PACRD_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
 
#define AIPS_PACRD_TP2_MASK   (0x100000U)
 
#define AIPS_PACRD_TP2_SHIFT   (20U)
 
#define AIPS_PACRD_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
 
#define AIPS_PACRD_WP2_MASK   (0x200000U)
 
#define AIPS_PACRD_WP2_SHIFT   (21U)
 
#define AIPS_PACRD_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
 
#define AIPS_PACRD_SP2_MASK   (0x400000U)
 
#define AIPS_PACRD_SP2_SHIFT   (22U)
 
#define AIPS_PACRD_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
 
#define AIPS_PACRD_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRD_TP1_SHIFT   (24U)
 
#define AIPS_PACRD_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
 
#define AIPS_PACRD_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRD_WP1_SHIFT   (25U)
 
#define AIPS_PACRD_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
 
#define AIPS_PACRD_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRD_SP1_SHIFT   (26U)
 
#define AIPS_PACRD_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
 
#define AIPS_PACRD_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRD_TP0_SHIFT   (28U)
 
#define AIPS_PACRD_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
 
#define AIPS_PACRD_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRD_WP0_SHIFT   (29U)
 
#define AIPS_PACRD_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
 
#define AIPS_PACRD_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRD_SP0_SHIFT   (30U)
 
#define AIPS_PACRD_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
 
#define AIPS_PACRD_TP7_MASK   (0x1U)
 
#define AIPS_PACRD_TP7_SHIFT   (0U)
 
#define AIPS_PACRD_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
 
#define AIPS_PACRD_WP7_MASK   (0x2U)
 
#define AIPS_PACRD_WP7_SHIFT   (1U)
 
#define AIPS_PACRD_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
 
#define AIPS_PACRD_SP7_MASK   (0x4U)
 
#define AIPS_PACRD_SP7_SHIFT   (2U)
 
#define AIPS_PACRD_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
 
#define AIPS_PACRD_TP6_MASK   (0x10U)
 
#define AIPS_PACRD_TP6_SHIFT   (4U)
 
#define AIPS_PACRD_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
 
#define AIPS_PACRD_WP6_MASK   (0x20U)
 
#define AIPS_PACRD_WP6_SHIFT   (5U)
 
#define AIPS_PACRD_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
 
#define AIPS_PACRD_SP6_MASK   (0x40U)
 
#define AIPS_PACRD_SP6_SHIFT   (6U)
 
#define AIPS_PACRD_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
 
#define AIPS_PACRD_TP5_MASK   (0x100U)
 
#define AIPS_PACRD_TP5_SHIFT   (8U)
 
#define AIPS_PACRD_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
 
#define AIPS_PACRD_WP5_MASK   (0x200U)
 
#define AIPS_PACRD_WP5_SHIFT   (9U)
 
#define AIPS_PACRD_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
 
#define AIPS_PACRD_SP5_MASK   (0x400U)
 
#define AIPS_PACRD_SP5_SHIFT   (10U)
 
#define AIPS_PACRD_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
 
#define AIPS_PACRD_TP4_MASK   (0x1000U)
 
#define AIPS_PACRD_TP4_SHIFT   (12U)
 
#define AIPS_PACRD_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
 
#define AIPS_PACRD_WP4_MASK   (0x2000U)
 
#define AIPS_PACRD_WP4_SHIFT   (13U)
 
#define AIPS_PACRD_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
 
#define AIPS_PACRD_SP4_MASK   (0x4000U)
 
#define AIPS_PACRD_SP4_SHIFT   (14U)
 
#define AIPS_PACRD_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
 
#define AIPS_PACRD_TP3_MASK   (0x10000U)
 
#define AIPS_PACRD_TP3_SHIFT   (16U)
 
#define AIPS_PACRD_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
 
#define AIPS_PACRD_WP3_MASK   (0x20000U)
 
#define AIPS_PACRD_WP3_SHIFT   (17U)
 
#define AIPS_PACRD_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
 
#define AIPS_PACRD_SP3_MASK   (0x40000U)
 
#define AIPS_PACRD_SP3_SHIFT   (18U)
 
#define AIPS_PACRD_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
 
#define AIPS_PACRD_TP2_MASK   (0x100000U)
 
#define AIPS_PACRD_TP2_SHIFT   (20U)
 
#define AIPS_PACRD_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
 
#define AIPS_PACRD_WP2_MASK   (0x200000U)
 
#define AIPS_PACRD_WP2_SHIFT   (21U)
 
#define AIPS_PACRD_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
 
#define AIPS_PACRD_SP2_MASK   (0x400000U)
 
#define AIPS_PACRD_SP2_SHIFT   (22U)
 
#define AIPS_PACRD_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
 
#define AIPS_PACRD_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRD_TP1_SHIFT   (24U)
 
#define AIPS_PACRD_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
 
#define AIPS_PACRD_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRD_WP1_SHIFT   (25U)
 
#define AIPS_PACRD_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
 
#define AIPS_PACRD_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRD_SP1_SHIFT   (26U)
 
#define AIPS_PACRD_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
 
#define AIPS_PACRD_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRD_TP0_SHIFT   (28U)
 
#define AIPS_PACRD_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
 
#define AIPS_PACRD_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRD_WP0_SHIFT   (29U)
 
#define AIPS_PACRD_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
 
#define AIPS_PACRD_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRD_SP0_SHIFT   (30U)
 
#define AIPS_PACRD_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
 
#define AIPS_PACRD_TP7_MASK   (0x1U)
 
#define AIPS_PACRD_TP7_SHIFT   (0U)
 
#define AIPS_PACRD_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
 
#define AIPS_PACRD_WP7_MASK   (0x2U)
 
#define AIPS_PACRD_WP7_SHIFT   (1U)
 
#define AIPS_PACRD_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
 
#define AIPS_PACRD_SP7_MASK   (0x4U)
 
#define AIPS_PACRD_SP7_SHIFT   (2U)
 
#define AIPS_PACRD_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
 
#define AIPS_PACRD_TP6_MASK   (0x10U)
 
#define AIPS_PACRD_TP6_SHIFT   (4U)
 
#define AIPS_PACRD_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
 
#define AIPS_PACRD_WP6_MASK   (0x20U)
 
#define AIPS_PACRD_WP6_SHIFT   (5U)
 
#define AIPS_PACRD_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
 
#define AIPS_PACRD_SP6_MASK   (0x40U)
 
#define AIPS_PACRD_SP6_SHIFT   (6U)
 
#define AIPS_PACRD_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
 
#define AIPS_PACRD_TP5_MASK   (0x100U)
 
#define AIPS_PACRD_TP5_SHIFT   (8U)
 
#define AIPS_PACRD_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
 
#define AIPS_PACRD_WP5_MASK   (0x200U)
 
#define AIPS_PACRD_WP5_SHIFT   (9U)
 
#define AIPS_PACRD_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
 
#define AIPS_PACRD_SP5_MASK   (0x400U)
 
#define AIPS_PACRD_SP5_SHIFT   (10U)
 
#define AIPS_PACRD_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
 
#define AIPS_PACRD_TP4_MASK   (0x1000U)
 
#define AIPS_PACRD_TP4_SHIFT   (12U)
 
#define AIPS_PACRD_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
 
#define AIPS_PACRD_WP4_MASK   (0x2000U)
 
#define AIPS_PACRD_WP4_SHIFT   (13U)
 
#define AIPS_PACRD_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
 
#define AIPS_PACRD_SP4_MASK   (0x4000U)
 
#define AIPS_PACRD_SP4_SHIFT   (14U)
 
#define AIPS_PACRD_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
 
#define AIPS_PACRD_TP3_MASK   (0x10000U)
 
#define AIPS_PACRD_TP3_SHIFT   (16U)
 
#define AIPS_PACRD_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
 
#define AIPS_PACRD_WP3_MASK   (0x20000U)
 
#define AIPS_PACRD_WP3_SHIFT   (17U)
 
#define AIPS_PACRD_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
 
#define AIPS_PACRD_SP3_MASK   (0x40000U)
 
#define AIPS_PACRD_SP3_SHIFT   (18U)
 
#define AIPS_PACRD_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
 
#define AIPS_PACRD_TP2_MASK   (0x100000U)
 
#define AIPS_PACRD_TP2_SHIFT   (20U)
 
#define AIPS_PACRD_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
 
#define AIPS_PACRD_WP2_MASK   (0x200000U)
 
#define AIPS_PACRD_WP2_SHIFT   (21U)
 
#define AIPS_PACRD_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
 
#define AIPS_PACRD_SP2_MASK   (0x400000U)
 
#define AIPS_PACRD_SP2_SHIFT   (22U)
 
#define AIPS_PACRD_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
 
#define AIPS_PACRD_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRD_TP1_SHIFT   (24U)
 
#define AIPS_PACRD_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
 
#define AIPS_PACRD_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRD_WP1_SHIFT   (25U)
 
#define AIPS_PACRD_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
 
#define AIPS_PACRD_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRD_SP1_SHIFT   (26U)
 
#define AIPS_PACRD_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
 
#define AIPS_PACRD_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRD_TP0_SHIFT   (28U)
 
#define AIPS_PACRD_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
 
#define AIPS_PACRD_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRD_WP0_SHIFT   (29U)
 
#define AIPS_PACRD_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
 
#define AIPS_PACRD_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRD_SP0_SHIFT   (30U)
 
#define AIPS_PACRD_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
 
#define AIPS_PACRD_TP7_MASK   (0x1U)
 
#define AIPS_PACRD_TP7_SHIFT   (0U)
 
#define AIPS_PACRD_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
 
#define AIPS_PACRD_WP7_MASK   (0x2U)
 
#define AIPS_PACRD_WP7_SHIFT   (1U)
 
#define AIPS_PACRD_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
 
#define AIPS_PACRD_SP7_MASK   (0x4U)
 
#define AIPS_PACRD_SP7_SHIFT   (2U)
 
#define AIPS_PACRD_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
 
#define AIPS_PACRD_TP6_MASK   (0x10U)
 
#define AIPS_PACRD_TP6_SHIFT   (4U)
 
#define AIPS_PACRD_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
 
#define AIPS_PACRD_WP6_MASK   (0x20U)
 
#define AIPS_PACRD_WP6_SHIFT   (5U)
 
#define AIPS_PACRD_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
 
#define AIPS_PACRD_SP6_MASK   (0x40U)
 
#define AIPS_PACRD_SP6_SHIFT   (6U)
 
#define AIPS_PACRD_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
 
#define AIPS_PACRD_TP5_MASK   (0x100U)
 
#define AIPS_PACRD_TP5_SHIFT   (8U)
 
#define AIPS_PACRD_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
 
#define AIPS_PACRD_WP5_MASK   (0x200U)
 
#define AIPS_PACRD_WP5_SHIFT   (9U)
 
#define AIPS_PACRD_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
 
#define AIPS_PACRD_SP5_MASK   (0x400U)
 
#define AIPS_PACRD_SP5_SHIFT   (10U)
 
#define AIPS_PACRD_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
 
#define AIPS_PACRD_TP4_MASK   (0x1000U)
 
#define AIPS_PACRD_TP4_SHIFT   (12U)
 
#define AIPS_PACRD_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
 
#define AIPS_PACRD_WP4_MASK   (0x2000U)
 
#define AIPS_PACRD_WP4_SHIFT   (13U)
 
#define AIPS_PACRD_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
 
#define AIPS_PACRD_SP4_MASK   (0x4000U)
 
#define AIPS_PACRD_SP4_SHIFT   (14U)
 
#define AIPS_PACRD_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
 
#define AIPS_PACRD_TP3_MASK   (0x10000U)
 
#define AIPS_PACRD_TP3_SHIFT   (16U)
 
#define AIPS_PACRD_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
 
#define AIPS_PACRD_WP3_MASK   (0x20000U)
 
#define AIPS_PACRD_WP3_SHIFT   (17U)
 
#define AIPS_PACRD_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
 
#define AIPS_PACRD_SP3_MASK   (0x40000U)
 
#define AIPS_PACRD_SP3_SHIFT   (18U)
 
#define AIPS_PACRD_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
 
#define AIPS_PACRD_TP2_MASK   (0x100000U)
 
#define AIPS_PACRD_TP2_SHIFT   (20U)
 
#define AIPS_PACRD_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
 
#define AIPS_PACRD_WP2_MASK   (0x200000U)
 
#define AIPS_PACRD_WP2_SHIFT   (21U)
 
#define AIPS_PACRD_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
 
#define AIPS_PACRD_SP2_MASK   (0x400000U)
 
#define AIPS_PACRD_SP2_SHIFT   (22U)
 
#define AIPS_PACRD_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
 
#define AIPS_PACRD_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRD_TP1_SHIFT   (24U)
 
#define AIPS_PACRD_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
 
#define AIPS_PACRD_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRD_WP1_SHIFT   (25U)
 
#define AIPS_PACRD_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
 
#define AIPS_PACRD_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRD_SP1_SHIFT   (26U)
 
#define AIPS_PACRD_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
 
#define AIPS_PACRD_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRD_TP0_SHIFT   (28U)
 
#define AIPS_PACRD_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
 
#define AIPS_PACRD_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRD_WP0_SHIFT   (29U)
 
#define AIPS_PACRD_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
 
#define AIPS_PACRD_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRD_SP0_SHIFT   (30U)
 
#define AIPS_PACRD_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
 

PACRE - Peripheral Access Control Register

#define AIPS_PACRE_TP7_MASK   (0x1U)
 
#define AIPS_PACRE_TP7_SHIFT   (0U)
 
#define AIPS_PACRE_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
 
#define AIPS_PACRE_WP7_MASK   (0x2U)
 
#define AIPS_PACRE_WP7_SHIFT   (1U)
 
#define AIPS_PACRE_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
 
#define AIPS_PACRE_SP7_MASK   (0x4U)
 
#define AIPS_PACRE_SP7_SHIFT   (2U)
 
#define AIPS_PACRE_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
 
#define AIPS_PACRE_TP6_MASK   (0x10U)
 
#define AIPS_PACRE_TP6_SHIFT   (4U)
 
#define AIPS_PACRE_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
 
#define AIPS_PACRE_WP6_MASK   (0x20U)
 
#define AIPS_PACRE_WP6_SHIFT   (5U)
 
#define AIPS_PACRE_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
 
#define AIPS_PACRE_SP6_MASK   (0x40U)
 
#define AIPS_PACRE_SP6_SHIFT   (6U)
 
#define AIPS_PACRE_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
 
#define AIPS_PACRE_TP5_MASK   (0x100U)
 
#define AIPS_PACRE_TP5_SHIFT   (8U)
 
#define AIPS_PACRE_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
 
#define AIPS_PACRE_WP5_MASK   (0x200U)
 
#define AIPS_PACRE_WP5_SHIFT   (9U)
 
#define AIPS_PACRE_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
 
#define AIPS_PACRE_SP5_MASK   (0x400U)
 
#define AIPS_PACRE_SP5_SHIFT   (10U)
 
#define AIPS_PACRE_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
 
#define AIPS_PACRE_TP4_MASK   (0x1000U)
 
#define AIPS_PACRE_TP4_SHIFT   (12U)
 
#define AIPS_PACRE_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
 
#define AIPS_PACRE_WP4_MASK   (0x2000U)
 
#define AIPS_PACRE_WP4_SHIFT   (13U)
 
#define AIPS_PACRE_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
 
#define AIPS_PACRE_SP4_MASK   (0x4000U)
 
#define AIPS_PACRE_SP4_SHIFT   (14U)
 
#define AIPS_PACRE_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
 
#define AIPS_PACRE_TP3_MASK   (0x10000U)
 
#define AIPS_PACRE_TP3_SHIFT   (16U)
 
#define AIPS_PACRE_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
 
#define AIPS_PACRE_WP3_MASK   (0x20000U)
 
#define AIPS_PACRE_WP3_SHIFT   (17U)
 
#define AIPS_PACRE_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
 
#define AIPS_PACRE_SP3_MASK   (0x40000U)
 
#define AIPS_PACRE_SP3_SHIFT   (18U)
 
#define AIPS_PACRE_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
 
#define AIPS_PACRE_TP2_MASK   (0x100000U)
 
#define AIPS_PACRE_TP2_SHIFT   (20U)
 
#define AIPS_PACRE_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
 
#define AIPS_PACRE_WP2_MASK   (0x200000U)
 
#define AIPS_PACRE_WP2_SHIFT   (21U)
 
#define AIPS_PACRE_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
 
#define AIPS_PACRE_SP2_MASK   (0x400000U)
 
#define AIPS_PACRE_SP2_SHIFT   (22U)
 
#define AIPS_PACRE_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
 
#define AIPS_PACRE_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRE_TP1_SHIFT   (24U)
 
#define AIPS_PACRE_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
 
#define AIPS_PACRE_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRE_WP1_SHIFT   (25U)
 
#define AIPS_PACRE_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
 
#define AIPS_PACRE_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRE_SP1_SHIFT   (26U)
 
#define AIPS_PACRE_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
 
#define AIPS_PACRE_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRE_TP0_SHIFT   (28U)
 
#define AIPS_PACRE_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
 
#define AIPS_PACRE_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRE_WP0_SHIFT   (29U)
 
#define AIPS_PACRE_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
 
#define AIPS_PACRE_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRE_SP0_SHIFT   (30U)
 
#define AIPS_PACRE_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
 
#define AIPS_PACRE_TP7_MASK   0x1u
 
#define AIPS_PACRE_TP7_SHIFT   0
 
#define AIPS_PACRE_WP7_MASK   0x2u
 
#define AIPS_PACRE_WP7_SHIFT   1
 
#define AIPS_PACRE_SP7_MASK   0x4u
 
#define AIPS_PACRE_SP7_SHIFT   2
 
#define AIPS_PACRE_TP6_MASK   0x10u
 
#define AIPS_PACRE_TP6_SHIFT   4
 
#define AIPS_PACRE_WP6_MASK   0x20u
 
#define AIPS_PACRE_WP6_SHIFT   5
 
#define AIPS_PACRE_SP6_MASK   0x40u
 
#define AIPS_PACRE_SP6_SHIFT   6
 
#define AIPS_PACRE_TP5_MASK   0x100u
 
#define AIPS_PACRE_TP5_SHIFT   8
 
#define AIPS_PACRE_WP5_MASK   0x200u
 
#define AIPS_PACRE_WP5_SHIFT   9
 
#define AIPS_PACRE_SP5_MASK   0x400u
 
#define AIPS_PACRE_SP5_SHIFT   10
 
#define AIPS_PACRE_TP4_MASK   0x1000u
 
#define AIPS_PACRE_TP4_SHIFT   12
 
#define AIPS_PACRE_WP4_MASK   0x2000u
 
#define AIPS_PACRE_WP4_SHIFT   13
 
#define AIPS_PACRE_SP4_MASK   0x4000u
 
#define AIPS_PACRE_SP4_SHIFT   14
 
#define AIPS_PACRE_TP3_MASK   0x10000u
 
#define AIPS_PACRE_TP3_SHIFT   16
 
#define AIPS_PACRE_WP3_MASK   0x20000u
 
#define AIPS_PACRE_WP3_SHIFT   17
 
#define AIPS_PACRE_SP3_MASK   0x40000u
 
#define AIPS_PACRE_SP3_SHIFT   18
 
#define AIPS_PACRE_TP2_MASK   0x100000u
 
#define AIPS_PACRE_TP2_SHIFT   20
 
#define AIPS_PACRE_WP2_MASK   0x200000u
 
#define AIPS_PACRE_WP2_SHIFT   21
 
#define AIPS_PACRE_SP2_MASK   0x400000u
 
#define AIPS_PACRE_SP2_SHIFT   22
 
#define AIPS_PACRE_TP1_MASK   0x1000000u
 
#define AIPS_PACRE_TP1_SHIFT   24
 
#define AIPS_PACRE_WP1_MASK   0x2000000u
 
#define AIPS_PACRE_WP1_SHIFT   25
 
#define AIPS_PACRE_SP1_MASK   0x4000000u
 
#define AIPS_PACRE_SP1_SHIFT   26
 
#define AIPS_PACRE_TP0_MASK   0x10000000u
 
#define AIPS_PACRE_TP0_SHIFT   28
 
#define AIPS_PACRE_WP0_MASK   0x20000000u
 
#define AIPS_PACRE_WP0_SHIFT   29
 
#define AIPS_PACRE_SP0_MASK   0x40000000u
 
#define AIPS_PACRE_SP0_SHIFT   30
 
#define AIPS_PACRE_TP7_MASK   (0x1U)
 
#define AIPS_PACRE_TP7_SHIFT   (0U)
 
#define AIPS_PACRE_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
 
#define AIPS_PACRE_WP7_MASK   (0x2U)
 
#define AIPS_PACRE_WP7_SHIFT   (1U)
 
#define AIPS_PACRE_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
 
#define AIPS_PACRE_SP7_MASK   (0x4U)
 
#define AIPS_PACRE_SP7_SHIFT   (2U)
 
#define AIPS_PACRE_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
 
#define AIPS_PACRE_TP6_MASK   (0x10U)
 
#define AIPS_PACRE_TP6_SHIFT   (4U)
 
#define AIPS_PACRE_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
 
#define AIPS_PACRE_WP6_MASK   (0x20U)
 
#define AIPS_PACRE_WP6_SHIFT   (5U)
 
#define AIPS_PACRE_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
 
#define AIPS_PACRE_SP6_MASK   (0x40U)
 
#define AIPS_PACRE_SP6_SHIFT   (6U)
 
#define AIPS_PACRE_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
 
#define AIPS_PACRE_TP5_MASK   (0x100U)
 
#define AIPS_PACRE_TP5_SHIFT   (8U)
 
#define AIPS_PACRE_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
 
#define AIPS_PACRE_WP5_MASK   (0x200U)
 
#define AIPS_PACRE_WP5_SHIFT   (9U)
 
#define AIPS_PACRE_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
 
#define AIPS_PACRE_SP5_MASK   (0x400U)
 
#define AIPS_PACRE_SP5_SHIFT   (10U)
 
#define AIPS_PACRE_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
 
#define AIPS_PACRE_TP4_MASK   (0x1000U)
 
#define AIPS_PACRE_TP4_SHIFT   (12U)
 
#define AIPS_PACRE_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
 
#define AIPS_PACRE_WP4_MASK   (0x2000U)
 
#define AIPS_PACRE_WP4_SHIFT   (13U)
 
#define AIPS_PACRE_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
 
#define AIPS_PACRE_SP4_MASK   (0x4000U)
 
#define AIPS_PACRE_SP4_SHIFT   (14U)
 
#define AIPS_PACRE_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
 
#define AIPS_PACRE_TP3_MASK   (0x10000U)
 
#define AIPS_PACRE_TP3_SHIFT   (16U)
 
#define AIPS_PACRE_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
 
#define AIPS_PACRE_WP3_MASK   (0x20000U)
 
#define AIPS_PACRE_WP3_SHIFT   (17U)
 
#define AIPS_PACRE_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
 
#define AIPS_PACRE_SP3_MASK   (0x40000U)
 
#define AIPS_PACRE_SP3_SHIFT   (18U)
 
#define AIPS_PACRE_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
 
#define AIPS_PACRE_TP2_MASK   (0x100000U)
 
#define AIPS_PACRE_TP2_SHIFT   (20U)
 
#define AIPS_PACRE_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
 
#define AIPS_PACRE_WP2_MASK   (0x200000U)
 
#define AIPS_PACRE_WP2_SHIFT   (21U)
 
#define AIPS_PACRE_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
 
#define AIPS_PACRE_SP2_MASK   (0x400000U)
 
#define AIPS_PACRE_SP2_SHIFT   (22U)
 
#define AIPS_PACRE_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
 
#define AIPS_PACRE_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRE_TP1_SHIFT   (24U)
 
#define AIPS_PACRE_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
 
#define AIPS_PACRE_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRE_WP1_SHIFT   (25U)
 
#define AIPS_PACRE_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
 
#define AIPS_PACRE_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRE_SP1_SHIFT   (26U)
 
#define AIPS_PACRE_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
 
#define AIPS_PACRE_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRE_TP0_SHIFT   (28U)
 
#define AIPS_PACRE_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
 
#define AIPS_PACRE_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRE_WP0_SHIFT   (29U)
 
#define AIPS_PACRE_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
 
#define AIPS_PACRE_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRE_SP0_SHIFT   (30U)
 
#define AIPS_PACRE_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
 
#define AIPS_PACRE_TP7_MASK   (0x1U)
 
#define AIPS_PACRE_TP7_SHIFT   (0U)
 
#define AIPS_PACRE_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
 
#define AIPS_PACRE_WP7_MASK   (0x2U)
 
#define AIPS_PACRE_WP7_SHIFT   (1U)
 
#define AIPS_PACRE_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
 
#define AIPS_PACRE_SP7_MASK   (0x4U)
 
#define AIPS_PACRE_SP7_SHIFT   (2U)
 
#define AIPS_PACRE_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
 
#define AIPS_PACRE_TP6_MASK   (0x10U)
 
#define AIPS_PACRE_TP6_SHIFT   (4U)
 
#define AIPS_PACRE_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
 
#define AIPS_PACRE_WP6_MASK   (0x20U)
 
#define AIPS_PACRE_WP6_SHIFT   (5U)
 
#define AIPS_PACRE_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
 
#define AIPS_PACRE_SP6_MASK   (0x40U)
 
#define AIPS_PACRE_SP6_SHIFT   (6U)
 
#define AIPS_PACRE_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
 
#define AIPS_PACRE_TP5_MASK   (0x100U)
 
#define AIPS_PACRE_TP5_SHIFT   (8U)
 
#define AIPS_PACRE_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
 
#define AIPS_PACRE_WP5_MASK   (0x200U)
 
#define AIPS_PACRE_WP5_SHIFT   (9U)
 
#define AIPS_PACRE_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
 
#define AIPS_PACRE_SP5_MASK   (0x400U)
 
#define AIPS_PACRE_SP5_SHIFT   (10U)
 
#define AIPS_PACRE_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
 
#define AIPS_PACRE_TP4_MASK   (0x1000U)
 
#define AIPS_PACRE_TP4_SHIFT   (12U)
 
#define AIPS_PACRE_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
 
#define AIPS_PACRE_WP4_MASK   (0x2000U)
 
#define AIPS_PACRE_WP4_SHIFT   (13U)
 
#define AIPS_PACRE_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
 
#define AIPS_PACRE_SP4_MASK   (0x4000U)
 
#define AIPS_PACRE_SP4_SHIFT   (14U)
 
#define AIPS_PACRE_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
 
#define AIPS_PACRE_TP3_MASK   (0x10000U)
 
#define AIPS_PACRE_TP3_SHIFT   (16U)
 
#define AIPS_PACRE_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
 
#define AIPS_PACRE_WP3_MASK   (0x20000U)
 
#define AIPS_PACRE_WP3_SHIFT   (17U)
 
#define AIPS_PACRE_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
 
#define AIPS_PACRE_SP3_MASK   (0x40000U)
 
#define AIPS_PACRE_SP3_SHIFT   (18U)
 
#define AIPS_PACRE_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
 
#define AIPS_PACRE_TP2_MASK   (0x100000U)
 
#define AIPS_PACRE_TP2_SHIFT   (20U)
 
#define AIPS_PACRE_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
 
#define AIPS_PACRE_WP2_MASK   (0x200000U)
 
#define AIPS_PACRE_WP2_SHIFT   (21U)
 
#define AIPS_PACRE_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
 
#define AIPS_PACRE_SP2_MASK   (0x400000U)
 
#define AIPS_PACRE_SP2_SHIFT   (22U)
 
#define AIPS_PACRE_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
 
#define AIPS_PACRE_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRE_TP1_SHIFT   (24U)
 
#define AIPS_PACRE_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
 
#define AIPS_PACRE_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRE_WP1_SHIFT   (25U)
 
#define AIPS_PACRE_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
 
#define AIPS_PACRE_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRE_SP1_SHIFT   (26U)
 
#define AIPS_PACRE_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
 
#define AIPS_PACRE_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRE_TP0_SHIFT   (28U)
 
#define AIPS_PACRE_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
 
#define AIPS_PACRE_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRE_WP0_SHIFT   (29U)
 
#define AIPS_PACRE_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
 
#define AIPS_PACRE_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRE_SP0_SHIFT   (30U)
 
#define AIPS_PACRE_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
 
#define AIPS_PACRE_TP7_MASK   (0x1U)
 
#define AIPS_PACRE_TP7_SHIFT   (0U)
 
#define AIPS_PACRE_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
 
#define AIPS_PACRE_WP7_MASK   (0x2U)
 
#define AIPS_PACRE_WP7_SHIFT   (1U)
 
#define AIPS_PACRE_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
 
#define AIPS_PACRE_SP7_MASK   (0x4U)
 
#define AIPS_PACRE_SP7_SHIFT   (2U)
 
#define AIPS_PACRE_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
 
#define AIPS_PACRE_TP6_MASK   (0x10U)
 
#define AIPS_PACRE_TP6_SHIFT   (4U)
 
#define AIPS_PACRE_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
 
#define AIPS_PACRE_WP6_MASK   (0x20U)
 
#define AIPS_PACRE_WP6_SHIFT   (5U)
 
#define AIPS_PACRE_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
 
#define AIPS_PACRE_SP6_MASK   (0x40U)
 
#define AIPS_PACRE_SP6_SHIFT   (6U)
 
#define AIPS_PACRE_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
 
#define AIPS_PACRE_TP5_MASK   (0x100U)
 
#define AIPS_PACRE_TP5_SHIFT   (8U)
 
#define AIPS_PACRE_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
 
#define AIPS_PACRE_WP5_MASK   (0x200U)
 
#define AIPS_PACRE_WP5_SHIFT   (9U)
 
#define AIPS_PACRE_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
 
#define AIPS_PACRE_SP5_MASK   (0x400U)
 
#define AIPS_PACRE_SP5_SHIFT   (10U)
 
#define AIPS_PACRE_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
 
#define AIPS_PACRE_TP4_MASK   (0x1000U)
 
#define AIPS_PACRE_TP4_SHIFT   (12U)
 
#define AIPS_PACRE_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
 
#define AIPS_PACRE_WP4_MASK   (0x2000U)
 
#define AIPS_PACRE_WP4_SHIFT   (13U)
 
#define AIPS_PACRE_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
 
#define AIPS_PACRE_SP4_MASK   (0x4000U)
 
#define AIPS_PACRE_SP4_SHIFT   (14U)
 
#define AIPS_PACRE_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
 
#define AIPS_PACRE_TP3_MASK   (0x10000U)
 
#define AIPS_PACRE_TP3_SHIFT   (16U)
 
#define AIPS_PACRE_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
 
#define AIPS_PACRE_WP3_MASK   (0x20000U)
 
#define AIPS_PACRE_WP3_SHIFT   (17U)
 
#define AIPS_PACRE_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
 
#define AIPS_PACRE_SP3_MASK   (0x40000U)
 
#define AIPS_PACRE_SP3_SHIFT   (18U)
 
#define AIPS_PACRE_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
 
#define AIPS_PACRE_TP2_MASK   (0x100000U)
 
#define AIPS_PACRE_TP2_SHIFT   (20U)
 
#define AIPS_PACRE_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
 
#define AIPS_PACRE_WP2_MASK   (0x200000U)
 
#define AIPS_PACRE_WP2_SHIFT   (21U)
 
#define AIPS_PACRE_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
 
#define AIPS_PACRE_SP2_MASK   (0x400000U)
 
#define AIPS_PACRE_SP2_SHIFT   (22U)
 
#define AIPS_PACRE_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
 
#define AIPS_PACRE_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRE_TP1_SHIFT   (24U)
 
#define AIPS_PACRE_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
 
#define AIPS_PACRE_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRE_WP1_SHIFT   (25U)
 
#define AIPS_PACRE_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
 
#define AIPS_PACRE_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRE_SP1_SHIFT   (26U)
 
#define AIPS_PACRE_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
 
#define AIPS_PACRE_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRE_TP0_SHIFT   (28U)
 
#define AIPS_PACRE_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
 
#define AIPS_PACRE_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRE_WP0_SHIFT   (29U)
 
#define AIPS_PACRE_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
 
#define AIPS_PACRE_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRE_SP0_SHIFT   (30U)
 
#define AIPS_PACRE_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
 
#define AIPS_PACRE_TP7_MASK   (0x1U)
 
#define AIPS_PACRE_TP7_SHIFT   (0U)
 
#define AIPS_PACRE_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
 
#define AIPS_PACRE_WP7_MASK   (0x2U)
 
#define AIPS_PACRE_WP7_SHIFT   (1U)
 
#define AIPS_PACRE_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
 
#define AIPS_PACRE_SP7_MASK   (0x4U)
 
#define AIPS_PACRE_SP7_SHIFT   (2U)
 
#define AIPS_PACRE_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
 
#define AIPS_PACRE_TP6_MASK   (0x10U)
 
#define AIPS_PACRE_TP6_SHIFT   (4U)
 
#define AIPS_PACRE_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
 
#define AIPS_PACRE_WP6_MASK   (0x20U)
 
#define AIPS_PACRE_WP6_SHIFT   (5U)
 
#define AIPS_PACRE_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
 
#define AIPS_PACRE_SP6_MASK   (0x40U)
 
#define AIPS_PACRE_SP6_SHIFT   (6U)
 
#define AIPS_PACRE_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
 
#define AIPS_PACRE_TP5_MASK   (0x100U)
 
#define AIPS_PACRE_TP5_SHIFT   (8U)
 
#define AIPS_PACRE_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
 
#define AIPS_PACRE_WP5_MASK   (0x200U)
 
#define AIPS_PACRE_WP5_SHIFT   (9U)
 
#define AIPS_PACRE_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
 
#define AIPS_PACRE_SP5_MASK   (0x400U)
 
#define AIPS_PACRE_SP5_SHIFT   (10U)
 
#define AIPS_PACRE_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
 
#define AIPS_PACRE_TP4_MASK   (0x1000U)
 
#define AIPS_PACRE_TP4_SHIFT   (12U)
 
#define AIPS_PACRE_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
 
#define AIPS_PACRE_WP4_MASK   (0x2000U)
 
#define AIPS_PACRE_WP4_SHIFT   (13U)
 
#define AIPS_PACRE_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
 
#define AIPS_PACRE_SP4_MASK   (0x4000U)
 
#define AIPS_PACRE_SP4_SHIFT   (14U)
 
#define AIPS_PACRE_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
 
#define AIPS_PACRE_TP3_MASK   (0x10000U)
 
#define AIPS_PACRE_TP3_SHIFT   (16U)
 
#define AIPS_PACRE_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
 
#define AIPS_PACRE_WP3_MASK   (0x20000U)
 
#define AIPS_PACRE_WP3_SHIFT   (17U)
 
#define AIPS_PACRE_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
 
#define AIPS_PACRE_SP3_MASK   (0x40000U)
 
#define AIPS_PACRE_SP3_SHIFT   (18U)
 
#define AIPS_PACRE_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
 
#define AIPS_PACRE_TP2_MASK   (0x100000U)
 
#define AIPS_PACRE_TP2_SHIFT   (20U)
 
#define AIPS_PACRE_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
 
#define AIPS_PACRE_WP2_MASK   (0x200000U)
 
#define AIPS_PACRE_WP2_SHIFT   (21U)
 
#define AIPS_PACRE_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
 
#define AIPS_PACRE_SP2_MASK   (0x400000U)
 
#define AIPS_PACRE_SP2_SHIFT   (22U)
 
#define AIPS_PACRE_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
 
#define AIPS_PACRE_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRE_TP1_SHIFT   (24U)
 
#define AIPS_PACRE_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
 
#define AIPS_PACRE_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRE_WP1_SHIFT   (25U)
 
#define AIPS_PACRE_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
 
#define AIPS_PACRE_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRE_SP1_SHIFT   (26U)
 
#define AIPS_PACRE_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
 
#define AIPS_PACRE_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRE_TP0_SHIFT   (28U)
 
#define AIPS_PACRE_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
 
#define AIPS_PACRE_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRE_WP0_SHIFT   (29U)
 
#define AIPS_PACRE_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
 
#define AIPS_PACRE_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRE_SP0_SHIFT   (30U)
 
#define AIPS_PACRE_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
 

PACRF - Peripheral Access Control Register

#define AIPS_PACRF_TP7_MASK   (0x1U)
 
#define AIPS_PACRF_TP7_SHIFT   (0U)
 
#define AIPS_PACRF_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
 
#define AIPS_PACRF_WP7_MASK   (0x2U)
 
#define AIPS_PACRF_WP7_SHIFT   (1U)
 
#define AIPS_PACRF_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
 
#define AIPS_PACRF_SP7_MASK   (0x4U)
 
#define AIPS_PACRF_SP7_SHIFT   (2U)
 
#define AIPS_PACRF_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
 
#define AIPS_PACRF_TP6_MASK   (0x10U)
 
#define AIPS_PACRF_TP6_SHIFT   (4U)
 
#define AIPS_PACRF_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
 
#define AIPS_PACRF_WP6_MASK   (0x20U)
 
#define AIPS_PACRF_WP6_SHIFT   (5U)
 
#define AIPS_PACRF_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
 
#define AIPS_PACRF_SP6_MASK   (0x40U)
 
#define AIPS_PACRF_SP6_SHIFT   (6U)
 
#define AIPS_PACRF_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
 
#define AIPS_PACRF_TP5_MASK   (0x100U)
 
#define AIPS_PACRF_TP5_SHIFT   (8U)
 
#define AIPS_PACRF_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
 
#define AIPS_PACRF_WP5_MASK   (0x200U)
 
#define AIPS_PACRF_WP5_SHIFT   (9U)
 
#define AIPS_PACRF_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
 
#define AIPS_PACRF_SP5_MASK   (0x400U)
 
#define AIPS_PACRF_SP5_SHIFT   (10U)
 
#define AIPS_PACRF_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
 
#define AIPS_PACRF_TP4_MASK   (0x1000U)
 
#define AIPS_PACRF_TP4_SHIFT   (12U)
 
#define AIPS_PACRF_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
 
#define AIPS_PACRF_WP4_MASK   (0x2000U)
 
#define AIPS_PACRF_WP4_SHIFT   (13U)
 
#define AIPS_PACRF_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
 
#define AIPS_PACRF_SP4_MASK   (0x4000U)
 
#define AIPS_PACRF_SP4_SHIFT   (14U)
 
#define AIPS_PACRF_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
 
#define AIPS_PACRF_TP3_MASK   (0x10000U)
 
#define AIPS_PACRF_TP3_SHIFT   (16U)
 
#define AIPS_PACRF_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
 
#define AIPS_PACRF_WP3_MASK   (0x20000U)
 
#define AIPS_PACRF_WP3_SHIFT   (17U)
 
#define AIPS_PACRF_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
 
#define AIPS_PACRF_SP3_MASK   (0x40000U)
 
#define AIPS_PACRF_SP3_SHIFT   (18U)
 
#define AIPS_PACRF_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
 
#define AIPS_PACRF_TP2_MASK   (0x100000U)
 
#define AIPS_PACRF_TP2_SHIFT   (20U)
 
#define AIPS_PACRF_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
 
#define AIPS_PACRF_WP2_MASK   (0x200000U)
 
#define AIPS_PACRF_WP2_SHIFT   (21U)
 
#define AIPS_PACRF_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
 
#define AIPS_PACRF_SP2_MASK   (0x400000U)
 
#define AIPS_PACRF_SP2_SHIFT   (22U)
 
#define AIPS_PACRF_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
 
#define AIPS_PACRF_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRF_TP1_SHIFT   (24U)
 
#define AIPS_PACRF_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
 
#define AIPS_PACRF_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRF_WP1_SHIFT   (25U)
 
#define AIPS_PACRF_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
 
#define AIPS_PACRF_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRF_SP1_SHIFT   (26U)
 
#define AIPS_PACRF_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
 
#define AIPS_PACRF_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRF_TP0_SHIFT   (28U)
 
#define AIPS_PACRF_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
 
#define AIPS_PACRF_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRF_WP0_SHIFT   (29U)
 
#define AIPS_PACRF_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
 
#define AIPS_PACRF_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRF_SP0_SHIFT   (30U)
 
#define AIPS_PACRF_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
 
#define AIPS_PACRF_TP7_MASK   0x1u
 
#define AIPS_PACRF_TP7_SHIFT   0
 
#define AIPS_PACRF_WP7_MASK   0x2u
 
#define AIPS_PACRF_WP7_SHIFT   1
 
#define AIPS_PACRF_SP7_MASK   0x4u
 
#define AIPS_PACRF_SP7_SHIFT   2
 
#define AIPS_PACRF_TP6_MASK   0x10u
 
#define AIPS_PACRF_TP6_SHIFT   4
 
#define AIPS_PACRF_WP6_MASK   0x20u
 
#define AIPS_PACRF_WP6_SHIFT   5
 
#define AIPS_PACRF_SP6_MASK   0x40u
 
#define AIPS_PACRF_SP6_SHIFT   6
 
#define AIPS_PACRF_TP5_MASK   0x100u
 
#define AIPS_PACRF_TP5_SHIFT   8
 
#define AIPS_PACRF_WP5_MASK   0x200u
 
#define AIPS_PACRF_WP5_SHIFT   9
 
#define AIPS_PACRF_SP5_MASK   0x400u
 
#define AIPS_PACRF_SP5_SHIFT   10
 
#define AIPS_PACRF_TP4_MASK   0x1000u
 
#define AIPS_PACRF_TP4_SHIFT   12
 
#define AIPS_PACRF_WP4_MASK   0x2000u
 
#define AIPS_PACRF_WP4_SHIFT   13
 
#define AIPS_PACRF_SP4_MASK   0x4000u
 
#define AIPS_PACRF_SP4_SHIFT   14
 
#define AIPS_PACRF_TP3_MASK   0x10000u
 
#define AIPS_PACRF_TP3_SHIFT   16
 
#define AIPS_PACRF_WP3_MASK   0x20000u
 
#define AIPS_PACRF_WP3_SHIFT   17
 
#define AIPS_PACRF_SP3_MASK   0x40000u
 
#define AIPS_PACRF_SP3_SHIFT   18
 
#define AIPS_PACRF_TP2_MASK   0x100000u
 
#define AIPS_PACRF_TP2_SHIFT   20
 
#define AIPS_PACRF_WP2_MASK   0x200000u
 
#define AIPS_PACRF_WP2_SHIFT   21
 
#define AIPS_PACRF_SP2_MASK   0x400000u
 
#define AIPS_PACRF_SP2_SHIFT   22
 
#define AIPS_PACRF_TP1_MASK   0x1000000u
 
#define AIPS_PACRF_TP1_SHIFT   24
 
#define AIPS_PACRF_WP1_MASK   0x2000000u
 
#define AIPS_PACRF_WP1_SHIFT   25
 
#define AIPS_PACRF_SP1_MASK   0x4000000u
 
#define AIPS_PACRF_SP1_SHIFT   26
 
#define AIPS_PACRF_TP0_MASK   0x10000000u
 
#define AIPS_PACRF_TP0_SHIFT   28
 
#define AIPS_PACRF_WP0_MASK   0x20000000u
 
#define AIPS_PACRF_WP0_SHIFT   29
 
#define AIPS_PACRF_SP0_MASK   0x40000000u
 
#define AIPS_PACRF_SP0_SHIFT   30
 
#define AIPS_PACRF_TP7_MASK   (0x1U)
 
#define AIPS_PACRF_TP7_SHIFT   (0U)
 
#define AIPS_PACRF_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
 
#define AIPS_PACRF_WP7_MASK   (0x2U)
 
#define AIPS_PACRF_WP7_SHIFT   (1U)
 
#define AIPS_PACRF_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
 
#define AIPS_PACRF_SP7_MASK   (0x4U)
 
#define AIPS_PACRF_SP7_SHIFT   (2U)
 
#define AIPS_PACRF_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
 
#define AIPS_PACRF_TP6_MASK   (0x10U)
 
#define AIPS_PACRF_TP6_SHIFT   (4U)
 
#define AIPS_PACRF_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
 
#define AIPS_PACRF_WP6_MASK   (0x20U)
 
#define AIPS_PACRF_WP6_SHIFT   (5U)
 
#define AIPS_PACRF_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
 
#define AIPS_PACRF_SP6_MASK   (0x40U)
 
#define AIPS_PACRF_SP6_SHIFT   (6U)
 
#define AIPS_PACRF_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
 
#define AIPS_PACRF_TP5_MASK   (0x100U)
 
#define AIPS_PACRF_TP5_SHIFT   (8U)
 
#define AIPS_PACRF_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
 
#define AIPS_PACRF_WP5_MASK   (0x200U)
 
#define AIPS_PACRF_WP5_SHIFT   (9U)
 
#define AIPS_PACRF_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
 
#define AIPS_PACRF_SP5_MASK   (0x400U)
 
#define AIPS_PACRF_SP5_SHIFT   (10U)
 
#define AIPS_PACRF_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
 
#define AIPS_PACRF_TP4_MASK   (0x1000U)
 
#define AIPS_PACRF_TP4_SHIFT   (12U)
 
#define AIPS_PACRF_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
 
#define AIPS_PACRF_WP4_MASK   (0x2000U)
 
#define AIPS_PACRF_WP4_SHIFT   (13U)
 
#define AIPS_PACRF_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
 
#define AIPS_PACRF_SP4_MASK   (0x4000U)
 
#define AIPS_PACRF_SP4_SHIFT   (14U)
 
#define AIPS_PACRF_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
 
#define AIPS_PACRF_TP3_MASK   (0x10000U)
 
#define AIPS_PACRF_TP3_SHIFT   (16U)
 
#define AIPS_PACRF_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
 
#define AIPS_PACRF_WP3_MASK   (0x20000U)
 
#define AIPS_PACRF_WP3_SHIFT   (17U)
 
#define AIPS_PACRF_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
 
#define AIPS_PACRF_SP3_MASK   (0x40000U)
 
#define AIPS_PACRF_SP3_SHIFT   (18U)
 
#define AIPS_PACRF_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
 
#define AIPS_PACRF_TP2_MASK   (0x100000U)
 
#define AIPS_PACRF_TP2_SHIFT   (20U)
 
#define AIPS_PACRF_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
 
#define AIPS_PACRF_WP2_MASK   (0x200000U)
 
#define AIPS_PACRF_WP2_SHIFT   (21U)
 
#define AIPS_PACRF_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
 
#define AIPS_PACRF_SP2_MASK   (0x400000U)
 
#define AIPS_PACRF_SP2_SHIFT   (22U)
 
#define AIPS_PACRF_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
 
#define AIPS_PACRF_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRF_TP1_SHIFT   (24U)
 
#define AIPS_PACRF_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
 
#define AIPS_PACRF_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRF_WP1_SHIFT   (25U)
 
#define AIPS_PACRF_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
 
#define AIPS_PACRF_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRF_SP1_SHIFT   (26U)
 
#define AIPS_PACRF_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
 
#define AIPS_PACRF_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRF_TP0_SHIFT   (28U)
 
#define AIPS_PACRF_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
 
#define AIPS_PACRF_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRF_WP0_SHIFT   (29U)
 
#define AIPS_PACRF_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
 
#define AIPS_PACRF_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRF_SP0_SHIFT   (30U)
 
#define AIPS_PACRF_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
 
#define AIPS_PACRF_TP7_MASK   (0x1U)
 
#define AIPS_PACRF_TP7_SHIFT   (0U)
 
#define AIPS_PACRF_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
 
#define AIPS_PACRF_WP7_MASK   (0x2U)
 
#define AIPS_PACRF_WP7_SHIFT   (1U)
 
#define AIPS_PACRF_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
 
#define AIPS_PACRF_SP7_MASK   (0x4U)
 
#define AIPS_PACRF_SP7_SHIFT   (2U)
 
#define AIPS_PACRF_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
 
#define AIPS_PACRF_TP6_MASK   (0x10U)
 
#define AIPS_PACRF_TP6_SHIFT   (4U)
 
#define AIPS_PACRF_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
 
#define AIPS_PACRF_WP6_MASK   (0x20U)
 
#define AIPS_PACRF_WP6_SHIFT   (5U)
 
#define AIPS_PACRF_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
 
#define AIPS_PACRF_SP6_MASK   (0x40U)
 
#define AIPS_PACRF_SP6_SHIFT   (6U)
 
#define AIPS_PACRF_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
 
#define AIPS_PACRF_TP5_MASK   (0x100U)
 
#define AIPS_PACRF_TP5_SHIFT   (8U)
 
#define AIPS_PACRF_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
 
#define AIPS_PACRF_WP5_MASK   (0x200U)
 
#define AIPS_PACRF_WP5_SHIFT   (9U)
 
#define AIPS_PACRF_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
 
#define AIPS_PACRF_SP5_MASK   (0x400U)
 
#define AIPS_PACRF_SP5_SHIFT   (10U)
 
#define AIPS_PACRF_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
 
#define AIPS_PACRF_TP4_MASK   (0x1000U)
 
#define AIPS_PACRF_TP4_SHIFT   (12U)
 
#define AIPS_PACRF_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
 
#define AIPS_PACRF_WP4_MASK   (0x2000U)
 
#define AIPS_PACRF_WP4_SHIFT   (13U)
 
#define AIPS_PACRF_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
 
#define AIPS_PACRF_SP4_MASK   (0x4000U)
 
#define AIPS_PACRF_SP4_SHIFT   (14U)
 
#define AIPS_PACRF_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
 
#define AIPS_PACRF_TP3_MASK   (0x10000U)
 
#define AIPS_PACRF_TP3_SHIFT   (16U)
 
#define AIPS_PACRF_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
 
#define AIPS_PACRF_WP3_MASK   (0x20000U)
 
#define AIPS_PACRF_WP3_SHIFT   (17U)
 
#define AIPS_PACRF_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
 
#define AIPS_PACRF_SP3_MASK   (0x40000U)
 
#define AIPS_PACRF_SP3_SHIFT   (18U)
 
#define AIPS_PACRF_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
 
#define AIPS_PACRF_TP2_MASK   (0x100000U)
 
#define AIPS_PACRF_TP2_SHIFT   (20U)
 
#define AIPS_PACRF_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
 
#define AIPS_PACRF_WP2_MASK   (0x200000U)
 
#define AIPS_PACRF_WP2_SHIFT   (21U)
 
#define AIPS_PACRF_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
 
#define AIPS_PACRF_SP2_MASK   (0x400000U)
 
#define AIPS_PACRF_SP2_SHIFT   (22U)
 
#define AIPS_PACRF_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
 
#define AIPS_PACRF_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRF_TP1_SHIFT   (24U)
 
#define AIPS_PACRF_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
 
#define AIPS_PACRF_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRF_WP1_SHIFT   (25U)
 
#define AIPS_PACRF_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
 
#define AIPS_PACRF_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRF_SP1_SHIFT   (26U)
 
#define AIPS_PACRF_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
 
#define AIPS_PACRF_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRF_TP0_SHIFT   (28U)
 
#define AIPS_PACRF_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
 
#define AIPS_PACRF_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRF_WP0_SHIFT   (29U)
 
#define AIPS_PACRF_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
 
#define AIPS_PACRF_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRF_SP0_SHIFT   (30U)
 
#define AIPS_PACRF_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
 
#define AIPS_PACRF_TP7_MASK   (0x1U)
 
#define AIPS_PACRF_TP7_SHIFT   (0U)
 
#define AIPS_PACRF_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
 
#define AIPS_PACRF_WP7_MASK   (0x2U)
 
#define AIPS_PACRF_WP7_SHIFT   (1U)
 
#define AIPS_PACRF_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
 
#define AIPS_PACRF_SP7_MASK   (0x4U)
 
#define AIPS_PACRF_SP7_SHIFT   (2U)
 
#define AIPS_PACRF_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
 
#define AIPS_PACRF_TP6_MASK   (0x10U)
 
#define AIPS_PACRF_TP6_SHIFT   (4U)
 
#define AIPS_PACRF_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
 
#define AIPS_PACRF_WP6_MASK   (0x20U)
 
#define AIPS_PACRF_WP6_SHIFT   (5U)
 
#define AIPS_PACRF_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
 
#define AIPS_PACRF_SP6_MASK   (0x40U)
 
#define AIPS_PACRF_SP6_SHIFT   (6U)
 
#define AIPS_PACRF_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
 
#define AIPS_PACRF_TP5_MASK   (0x100U)
 
#define AIPS_PACRF_TP5_SHIFT   (8U)
 
#define AIPS_PACRF_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
 
#define AIPS_PACRF_WP5_MASK   (0x200U)
 
#define AIPS_PACRF_WP5_SHIFT   (9U)
 
#define AIPS_PACRF_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
 
#define AIPS_PACRF_SP5_MASK   (0x400U)
 
#define AIPS_PACRF_SP5_SHIFT   (10U)
 
#define AIPS_PACRF_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
 
#define AIPS_PACRF_TP4_MASK   (0x1000U)
 
#define AIPS_PACRF_TP4_SHIFT   (12U)
 
#define AIPS_PACRF_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
 
#define AIPS_PACRF_WP4_MASK   (0x2000U)
 
#define AIPS_PACRF_WP4_SHIFT   (13U)
 
#define AIPS_PACRF_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
 
#define AIPS_PACRF_SP4_MASK   (0x4000U)
 
#define AIPS_PACRF_SP4_SHIFT   (14U)
 
#define AIPS_PACRF_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
 
#define AIPS_PACRF_TP3_MASK   (0x10000U)
 
#define AIPS_PACRF_TP3_SHIFT   (16U)
 
#define AIPS_PACRF_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
 
#define AIPS_PACRF_WP3_MASK   (0x20000U)
 
#define AIPS_PACRF_WP3_SHIFT   (17U)
 
#define AIPS_PACRF_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
 
#define AIPS_PACRF_SP3_MASK   (0x40000U)
 
#define AIPS_PACRF_SP3_SHIFT   (18U)
 
#define AIPS_PACRF_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
 
#define AIPS_PACRF_TP2_MASK   (0x100000U)
 
#define AIPS_PACRF_TP2_SHIFT   (20U)
 
#define AIPS_PACRF_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
 
#define AIPS_PACRF_WP2_MASK   (0x200000U)
 
#define AIPS_PACRF_WP2_SHIFT   (21U)
 
#define AIPS_PACRF_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
 
#define AIPS_PACRF_SP2_MASK   (0x400000U)
 
#define AIPS_PACRF_SP2_SHIFT   (22U)
 
#define AIPS_PACRF_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
 
#define AIPS_PACRF_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRF_TP1_SHIFT   (24U)
 
#define AIPS_PACRF_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
 
#define AIPS_PACRF_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRF_WP1_SHIFT   (25U)
 
#define AIPS_PACRF_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
 
#define AIPS_PACRF_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRF_SP1_SHIFT   (26U)
 
#define AIPS_PACRF_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
 
#define AIPS_PACRF_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRF_TP0_SHIFT   (28U)
 
#define AIPS_PACRF_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
 
#define AIPS_PACRF_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRF_WP0_SHIFT   (29U)
 
#define AIPS_PACRF_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
 
#define AIPS_PACRF_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRF_SP0_SHIFT   (30U)
 
#define AIPS_PACRF_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
 
#define AIPS_PACRF_TP7_MASK   (0x1U)
 
#define AIPS_PACRF_TP7_SHIFT   (0U)
 
#define AIPS_PACRF_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
 
#define AIPS_PACRF_WP7_MASK   (0x2U)
 
#define AIPS_PACRF_WP7_SHIFT   (1U)
 
#define AIPS_PACRF_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
 
#define AIPS_PACRF_SP7_MASK   (0x4U)
 
#define AIPS_PACRF_SP7_SHIFT   (2U)
 
#define AIPS_PACRF_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
 
#define AIPS_PACRF_TP6_MASK   (0x10U)
 
#define AIPS_PACRF_TP6_SHIFT   (4U)
 
#define AIPS_PACRF_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
 
#define AIPS_PACRF_WP6_MASK   (0x20U)
 
#define AIPS_PACRF_WP6_SHIFT   (5U)
 
#define AIPS_PACRF_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
 
#define AIPS_PACRF_SP6_MASK   (0x40U)
 
#define AIPS_PACRF_SP6_SHIFT   (6U)
 
#define AIPS_PACRF_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
 
#define AIPS_PACRF_TP5_MASK   (0x100U)
 
#define AIPS_PACRF_TP5_SHIFT   (8U)
 
#define AIPS_PACRF_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
 
#define AIPS_PACRF_WP5_MASK   (0x200U)
 
#define AIPS_PACRF_WP5_SHIFT   (9U)
 
#define AIPS_PACRF_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
 
#define AIPS_PACRF_SP5_MASK   (0x400U)
 
#define AIPS_PACRF_SP5_SHIFT   (10U)
 
#define AIPS_PACRF_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
 
#define AIPS_PACRF_TP4_MASK   (0x1000U)
 
#define AIPS_PACRF_TP4_SHIFT   (12U)
 
#define AIPS_PACRF_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
 
#define AIPS_PACRF_WP4_MASK   (0x2000U)
 
#define AIPS_PACRF_WP4_SHIFT   (13U)
 
#define AIPS_PACRF_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
 
#define AIPS_PACRF_SP4_MASK   (0x4000U)
 
#define AIPS_PACRF_SP4_SHIFT   (14U)
 
#define AIPS_PACRF_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
 
#define AIPS_PACRF_TP3_MASK   (0x10000U)
 
#define AIPS_PACRF_TP3_SHIFT   (16U)
 
#define AIPS_PACRF_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
 
#define AIPS_PACRF_WP3_MASK   (0x20000U)
 
#define AIPS_PACRF_WP3_SHIFT   (17U)
 
#define AIPS_PACRF_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
 
#define AIPS_PACRF_SP3_MASK   (0x40000U)
 
#define AIPS_PACRF_SP3_SHIFT   (18U)
 
#define AIPS_PACRF_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
 
#define AIPS_PACRF_TP2_MASK   (0x100000U)
 
#define AIPS_PACRF_TP2_SHIFT   (20U)
 
#define AIPS_PACRF_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
 
#define AIPS_PACRF_WP2_MASK   (0x200000U)
 
#define AIPS_PACRF_WP2_SHIFT   (21U)
 
#define AIPS_PACRF_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
 
#define AIPS_PACRF_SP2_MASK   (0x400000U)
 
#define AIPS_PACRF_SP2_SHIFT   (22U)
 
#define AIPS_PACRF_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
 
#define AIPS_PACRF_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRF_TP1_SHIFT   (24U)
 
#define AIPS_PACRF_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
 
#define AIPS_PACRF_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRF_WP1_SHIFT   (25U)
 
#define AIPS_PACRF_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
 
#define AIPS_PACRF_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRF_SP1_SHIFT   (26U)
 
#define AIPS_PACRF_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
 
#define AIPS_PACRF_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRF_TP0_SHIFT   (28U)
 
#define AIPS_PACRF_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
 
#define AIPS_PACRF_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRF_WP0_SHIFT   (29U)
 
#define AIPS_PACRF_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
 
#define AIPS_PACRF_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRF_SP0_SHIFT   (30U)
 
#define AIPS_PACRF_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
 

PACRG - Peripheral Access Control Register

#define AIPS_PACRG_TP7_MASK   (0x1U)
 
#define AIPS_PACRG_TP7_SHIFT   (0U)
 
#define AIPS_PACRG_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
 
#define AIPS_PACRG_WP7_MASK   (0x2U)
 
#define AIPS_PACRG_WP7_SHIFT   (1U)
 
#define AIPS_PACRG_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
 
#define AIPS_PACRG_SP7_MASK   (0x4U)
 
#define AIPS_PACRG_SP7_SHIFT   (2U)
 
#define AIPS_PACRG_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
 
#define AIPS_PACRG_TP6_MASK   (0x10U)
 
#define AIPS_PACRG_TP6_SHIFT   (4U)
 
#define AIPS_PACRG_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
 
#define AIPS_PACRG_WP6_MASK   (0x20U)
 
#define AIPS_PACRG_WP6_SHIFT   (5U)
 
#define AIPS_PACRG_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
 
#define AIPS_PACRG_SP6_MASK   (0x40U)
 
#define AIPS_PACRG_SP6_SHIFT   (6U)
 
#define AIPS_PACRG_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
 
#define AIPS_PACRG_TP5_MASK   (0x100U)
 
#define AIPS_PACRG_TP5_SHIFT   (8U)
 
#define AIPS_PACRG_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
 
#define AIPS_PACRG_WP5_MASK   (0x200U)
 
#define AIPS_PACRG_WP5_SHIFT   (9U)
 
#define AIPS_PACRG_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
 
#define AIPS_PACRG_SP5_MASK   (0x400U)
 
#define AIPS_PACRG_SP5_SHIFT   (10U)
 
#define AIPS_PACRG_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
 
#define AIPS_PACRG_TP4_MASK   (0x1000U)
 
#define AIPS_PACRG_TP4_SHIFT   (12U)
 
#define AIPS_PACRG_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
 
#define AIPS_PACRG_WP4_MASK   (0x2000U)
 
#define AIPS_PACRG_WP4_SHIFT   (13U)
 
#define AIPS_PACRG_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
 
#define AIPS_PACRG_SP4_MASK   (0x4000U)
 
#define AIPS_PACRG_SP4_SHIFT   (14U)
 
#define AIPS_PACRG_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
 
#define AIPS_PACRG_TP3_MASK   (0x10000U)
 
#define AIPS_PACRG_TP3_SHIFT   (16U)
 
#define AIPS_PACRG_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
 
#define AIPS_PACRG_WP3_MASK   (0x20000U)
 
#define AIPS_PACRG_WP3_SHIFT   (17U)
 
#define AIPS_PACRG_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
 
#define AIPS_PACRG_SP3_MASK   (0x40000U)
 
#define AIPS_PACRG_SP3_SHIFT   (18U)
 
#define AIPS_PACRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
 
#define AIPS_PACRG_TP2_MASK   (0x100000U)
 
#define AIPS_PACRG_TP2_SHIFT   (20U)
 
#define AIPS_PACRG_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
 
#define AIPS_PACRG_WP2_MASK   (0x200000U)
 
#define AIPS_PACRG_WP2_SHIFT   (21U)
 
#define AIPS_PACRG_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
 
#define AIPS_PACRG_SP2_MASK   (0x400000U)
 
#define AIPS_PACRG_SP2_SHIFT   (22U)
 
#define AIPS_PACRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
 
#define AIPS_PACRG_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRG_TP1_SHIFT   (24U)
 
#define AIPS_PACRG_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
 
#define AIPS_PACRG_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRG_WP1_SHIFT   (25U)
 
#define AIPS_PACRG_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
 
#define AIPS_PACRG_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRG_SP1_SHIFT   (26U)
 
#define AIPS_PACRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
 
#define AIPS_PACRG_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRG_TP0_SHIFT   (28U)
 
#define AIPS_PACRG_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
 
#define AIPS_PACRG_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRG_WP0_SHIFT   (29U)
 
#define AIPS_PACRG_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
 
#define AIPS_PACRG_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRG_SP0_SHIFT   (30U)
 
#define AIPS_PACRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
 
#define AIPS_PACRG_TP7_MASK   0x1u
 
#define AIPS_PACRG_TP7_SHIFT   0
 
#define AIPS_PACRG_WP7_MASK   0x2u
 
#define AIPS_PACRG_WP7_SHIFT   1
 
#define AIPS_PACRG_SP7_MASK   0x4u
 
#define AIPS_PACRG_SP7_SHIFT   2
 
#define AIPS_PACRG_TP6_MASK   0x10u
 
#define AIPS_PACRG_TP6_SHIFT   4
 
#define AIPS_PACRG_WP6_MASK   0x20u
 
#define AIPS_PACRG_WP6_SHIFT   5
 
#define AIPS_PACRG_SP6_MASK   0x40u
 
#define AIPS_PACRG_SP6_SHIFT   6
 
#define AIPS_PACRG_TP5_MASK   0x100u
 
#define AIPS_PACRG_TP5_SHIFT   8
 
#define AIPS_PACRG_WP5_MASK   0x200u
 
#define AIPS_PACRG_WP5_SHIFT   9
 
#define AIPS_PACRG_SP5_MASK   0x400u
 
#define AIPS_PACRG_SP5_SHIFT   10
 
#define AIPS_PACRG_TP4_MASK   0x1000u
 
#define AIPS_PACRG_TP4_SHIFT   12
 
#define AIPS_PACRG_WP4_MASK   0x2000u
 
#define AIPS_PACRG_WP4_SHIFT   13
 
#define AIPS_PACRG_SP4_MASK   0x4000u
 
#define AIPS_PACRG_SP4_SHIFT   14
 
#define AIPS_PACRG_TP3_MASK   0x10000u
 
#define AIPS_PACRG_TP3_SHIFT   16
 
#define AIPS_PACRG_WP3_MASK   0x20000u
 
#define AIPS_PACRG_WP3_SHIFT   17
 
#define AIPS_PACRG_SP3_MASK   0x40000u
 
#define AIPS_PACRG_SP3_SHIFT   18
 
#define AIPS_PACRG_TP2_MASK   0x100000u
 
#define AIPS_PACRG_TP2_SHIFT   20
 
#define AIPS_PACRG_WP2_MASK   0x200000u
 
#define AIPS_PACRG_WP2_SHIFT   21
 
#define AIPS_PACRG_SP2_MASK   0x400000u
 
#define AIPS_PACRG_SP2_SHIFT   22
 
#define AIPS_PACRG_TP1_MASK   0x1000000u
 
#define AIPS_PACRG_TP1_SHIFT   24
 
#define AIPS_PACRG_WP1_MASK   0x2000000u
 
#define AIPS_PACRG_WP1_SHIFT   25
 
#define AIPS_PACRG_SP1_MASK   0x4000000u
 
#define AIPS_PACRG_SP1_SHIFT   26
 
#define AIPS_PACRG_TP0_MASK   0x10000000u
 
#define AIPS_PACRG_TP0_SHIFT   28
 
#define AIPS_PACRG_WP0_MASK   0x20000000u
 
#define AIPS_PACRG_WP0_SHIFT   29
 
#define AIPS_PACRG_SP0_MASK   0x40000000u
 
#define AIPS_PACRG_SP0_SHIFT   30
 
#define AIPS_PACRG_TP7_MASK   (0x1U)
 
#define AIPS_PACRG_TP7_SHIFT   (0U)
 
#define AIPS_PACRG_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
 
#define AIPS_PACRG_WP7_MASK   (0x2U)
 
#define AIPS_PACRG_WP7_SHIFT   (1U)
 
#define AIPS_PACRG_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
 
#define AIPS_PACRG_SP7_MASK   (0x4U)
 
#define AIPS_PACRG_SP7_SHIFT   (2U)
 
#define AIPS_PACRG_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
 
#define AIPS_PACRG_TP6_MASK   (0x10U)
 
#define AIPS_PACRG_TP6_SHIFT   (4U)
 
#define AIPS_PACRG_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
 
#define AIPS_PACRG_WP6_MASK   (0x20U)
 
#define AIPS_PACRG_WP6_SHIFT   (5U)
 
#define AIPS_PACRG_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
 
#define AIPS_PACRG_SP6_MASK   (0x40U)
 
#define AIPS_PACRG_SP6_SHIFT   (6U)
 
#define AIPS_PACRG_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
 
#define AIPS_PACRG_TP5_MASK   (0x100U)
 
#define AIPS_PACRG_TP5_SHIFT   (8U)
 
#define AIPS_PACRG_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
 
#define AIPS_PACRG_WP5_MASK   (0x200U)
 
#define AIPS_PACRG_WP5_SHIFT   (9U)
 
#define AIPS_PACRG_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
 
#define AIPS_PACRG_SP5_MASK   (0x400U)
 
#define AIPS_PACRG_SP5_SHIFT   (10U)
 
#define AIPS_PACRG_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
 
#define AIPS_PACRG_TP4_MASK   (0x1000U)
 
#define AIPS_PACRG_TP4_SHIFT   (12U)
 
#define AIPS_PACRG_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
 
#define AIPS_PACRG_WP4_MASK   (0x2000U)
 
#define AIPS_PACRG_WP4_SHIFT   (13U)
 
#define AIPS_PACRG_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
 
#define AIPS_PACRG_SP4_MASK   (0x4000U)
 
#define AIPS_PACRG_SP4_SHIFT   (14U)
 
#define AIPS_PACRG_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
 
#define AIPS_PACRG_TP3_MASK   (0x10000U)
 
#define AIPS_PACRG_TP3_SHIFT   (16U)
 
#define AIPS_PACRG_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
 
#define AIPS_PACRG_WP3_MASK   (0x20000U)
 
#define AIPS_PACRG_WP3_SHIFT   (17U)
 
#define AIPS_PACRG_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
 
#define AIPS_PACRG_SP3_MASK   (0x40000U)
 
#define AIPS_PACRG_SP3_SHIFT   (18U)
 
#define AIPS_PACRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
 
#define AIPS_PACRG_TP2_MASK   (0x100000U)
 
#define AIPS_PACRG_TP2_SHIFT   (20U)
 
#define AIPS_PACRG_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
 
#define AIPS_PACRG_WP2_MASK   (0x200000U)
 
#define AIPS_PACRG_WP2_SHIFT   (21U)
 
#define AIPS_PACRG_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
 
#define AIPS_PACRG_SP2_MASK   (0x400000U)
 
#define AIPS_PACRG_SP2_SHIFT   (22U)
 
#define AIPS_PACRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
 
#define AIPS_PACRG_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRG_TP1_SHIFT   (24U)
 
#define AIPS_PACRG_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
 
#define AIPS_PACRG_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRG_WP1_SHIFT   (25U)
 
#define AIPS_PACRG_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
 
#define AIPS_PACRG_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRG_SP1_SHIFT   (26U)
 
#define AIPS_PACRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
 
#define AIPS_PACRG_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRG_TP0_SHIFT   (28U)
 
#define AIPS_PACRG_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
 
#define AIPS_PACRG_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRG_WP0_SHIFT   (29U)
 
#define AIPS_PACRG_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
 
#define AIPS_PACRG_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRG_SP0_SHIFT   (30U)
 
#define AIPS_PACRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
 
#define AIPS_PACRG_TP7_MASK   (0x1U)
 
#define AIPS_PACRG_TP7_SHIFT   (0U)
 
#define AIPS_PACRG_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
 
#define AIPS_PACRG_WP7_MASK   (0x2U)
 
#define AIPS_PACRG_WP7_SHIFT   (1U)
 
#define AIPS_PACRG_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
 
#define AIPS_PACRG_SP7_MASK   (0x4U)
 
#define AIPS_PACRG_SP7_SHIFT   (2U)
 
#define AIPS_PACRG_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
 
#define AIPS_PACRG_TP6_MASK   (0x10U)
 
#define AIPS_PACRG_TP6_SHIFT   (4U)
 
#define AIPS_PACRG_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
 
#define AIPS_PACRG_WP6_MASK   (0x20U)
 
#define AIPS_PACRG_WP6_SHIFT   (5U)
 
#define AIPS_PACRG_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
 
#define AIPS_PACRG_SP6_MASK   (0x40U)
 
#define AIPS_PACRG_SP6_SHIFT   (6U)
 
#define AIPS_PACRG_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
 
#define AIPS_PACRG_TP5_MASK   (0x100U)
 
#define AIPS_PACRG_TP5_SHIFT   (8U)
 
#define AIPS_PACRG_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
 
#define AIPS_PACRG_WP5_MASK   (0x200U)
 
#define AIPS_PACRG_WP5_SHIFT   (9U)
 
#define AIPS_PACRG_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
 
#define AIPS_PACRG_SP5_MASK   (0x400U)
 
#define AIPS_PACRG_SP5_SHIFT   (10U)
 
#define AIPS_PACRG_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
 
#define AIPS_PACRG_TP4_MASK   (0x1000U)
 
#define AIPS_PACRG_TP4_SHIFT   (12U)
 
#define AIPS_PACRG_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
 
#define AIPS_PACRG_WP4_MASK   (0x2000U)
 
#define AIPS_PACRG_WP4_SHIFT   (13U)
 
#define AIPS_PACRG_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
 
#define AIPS_PACRG_SP4_MASK   (0x4000U)
 
#define AIPS_PACRG_SP4_SHIFT   (14U)
 
#define AIPS_PACRG_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
 
#define AIPS_PACRG_TP3_MASK   (0x10000U)
 
#define AIPS_PACRG_TP3_SHIFT   (16U)
 
#define AIPS_PACRG_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
 
#define AIPS_PACRG_WP3_MASK   (0x20000U)
 
#define AIPS_PACRG_WP3_SHIFT   (17U)
 
#define AIPS_PACRG_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
 
#define AIPS_PACRG_SP3_MASK   (0x40000U)
 
#define AIPS_PACRG_SP3_SHIFT   (18U)
 
#define AIPS_PACRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
 
#define AIPS_PACRG_TP2_MASK   (0x100000U)
 
#define AIPS_PACRG_TP2_SHIFT   (20U)
 
#define AIPS_PACRG_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
 
#define AIPS_PACRG_WP2_MASK   (0x200000U)
 
#define AIPS_PACRG_WP2_SHIFT   (21U)
 
#define AIPS_PACRG_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
 
#define AIPS_PACRG_SP2_MASK   (0x400000U)
 
#define AIPS_PACRG_SP2_SHIFT   (22U)
 
#define AIPS_PACRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
 
#define AIPS_PACRG_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRG_TP1_SHIFT   (24U)
 
#define AIPS_PACRG_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
 
#define AIPS_PACRG_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRG_WP1_SHIFT   (25U)
 
#define AIPS_PACRG_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
 
#define AIPS_PACRG_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRG_SP1_SHIFT   (26U)
 
#define AIPS_PACRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
 
#define AIPS_PACRG_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRG_TP0_SHIFT   (28U)
 
#define AIPS_PACRG_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
 
#define AIPS_PACRG_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRG_WP0_SHIFT   (29U)
 
#define AIPS_PACRG_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
 
#define AIPS_PACRG_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRG_SP0_SHIFT   (30U)
 
#define AIPS_PACRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
 
#define AIPS_PACRG_TP7_MASK   (0x1U)
 
#define AIPS_PACRG_TP7_SHIFT   (0U)
 
#define AIPS_PACRG_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
 
#define AIPS_PACRG_WP7_MASK   (0x2U)
 
#define AIPS_PACRG_WP7_SHIFT   (1U)
 
#define AIPS_PACRG_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
 
#define AIPS_PACRG_SP7_MASK   (0x4U)
 
#define AIPS_PACRG_SP7_SHIFT   (2U)
 
#define AIPS_PACRG_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
 
#define AIPS_PACRG_TP6_MASK   (0x10U)
 
#define AIPS_PACRG_TP6_SHIFT   (4U)
 
#define AIPS_PACRG_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
 
#define AIPS_PACRG_WP6_MASK   (0x20U)
 
#define AIPS_PACRG_WP6_SHIFT   (5U)
 
#define AIPS_PACRG_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
 
#define AIPS_PACRG_SP6_MASK   (0x40U)
 
#define AIPS_PACRG_SP6_SHIFT   (6U)
 
#define AIPS_PACRG_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
 
#define AIPS_PACRG_TP5_MASK   (0x100U)
 
#define AIPS_PACRG_TP5_SHIFT   (8U)
 
#define AIPS_PACRG_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
 
#define AIPS_PACRG_WP5_MASK   (0x200U)
 
#define AIPS_PACRG_WP5_SHIFT   (9U)
 
#define AIPS_PACRG_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
 
#define AIPS_PACRG_SP5_MASK   (0x400U)
 
#define AIPS_PACRG_SP5_SHIFT   (10U)
 
#define AIPS_PACRG_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
 
#define AIPS_PACRG_TP4_MASK   (0x1000U)
 
#define AIPS_PACRG_TP4_SHIFT   (12U)
 
#define AIPS_PACRG_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
 
#define AIPS_PACRG_WP4_MASK   (0x2000U)
 
#define AIPS_PACRG_WP4_SHIFT   (13U)
 
#define AIPS_PACRG_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
 
#define AIPS_PACRG_SP4_MASK   (0x4000U)
 
#define AIPS_PACRG_SP4_SHIFT   (14U)
 
#define AIPS_PACRG_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
 
#define AIPS_PACRG_TP3_MASK   (0x10000U)
 
#define AIPS_PACRG_TP3_SHIFT   (16U)
 
#define AIPS_PACRG_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
 
#define AIPS_PACRG_WP3_MASK   (0x20000U)
 
#define AIPS_PACRG_WP3_SHIFT   (17U)
 
#define AIPS_PACRG_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
 
#define AIPS_PACRG_SP3_MASK   (0x40000U)
 
#define AIPS_PACRG_SP3_SHIFT   (18U)
 
#define AIPS_PACRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
 
#define AIPS_PACRG_TP2_MASK   (0x100000U)
 
#define AIPS_PACRG_TP2_SHIFT   (20U)
 
#define AIPS_PACRG_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
 
#define AIPS_PACRG_WP2_MASK   (0x200000U)
 
#define AIPS_PACRG_WP2_SHIFT   (21U)
 
#define AIPS_PACRG_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
 
#define AIPS_PACRG_SP2_MASK   (0x400000U)
 
#define AIPS_PACRG_SP2_SHIFT   (22U)
 
#define AIPS_PACRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
 
#define AIPS_PACRG_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRG_TP1_SHIFT   (24U)
 
#define AIPS_PACRG_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
 
#define AIPS_PACRG_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRG_WP1_SHIFT   (25U)
 
#define AIPS_PACRG_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
 
#define AIPS_PACRG_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRG_SP1_SHIFT   (26U)
 
#define AIPS_PACRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
 
#define AIPS_PACRG_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRG_TP0_SHIFT   (28U)
 
#define AIPS_PACRG_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
 
#define AIPS_PACRG_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRG_WP0_SHIFT   (29U)
 
#define AIPS_PACRG_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
 
#define AIPS_PACRG_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRG_SP0_SHIFT   (30U)
 
#define AIPS_PACRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
 
#define AIPS_PACRG_TP7_MASK   (0x1U)
 
#define AIPS_PACRG_TP7_SHIFT   (0U)
 
#define AIPS_PACRG_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
 
#define AIPS_PACRG_WP7_MASK   (0x2U)
 
#define AIPS_PACRG_WP7_SHIFT   (1U)
 
#define AIPS_PACRG_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
 
#define AIPS_PACRG_SP7_MASK   (0x4U)
 
#define AIPS_PACRG_SP7_SHIFT   (2U)
 
#define AIPS_PACRG_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
 
#define AIPS_PACRG_TP6_MASK   (0x10U)
 
#define AIPS_PACRG_TP6_SHIFT   (4U)
 
#define AIPS_PACRG_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
 
#define AIPS_PACRG_WP6_MASK   (0x20U)
 
#define AIPS_PACRG_WP6_SHIFT   (5U)
 
#define AIPS_PACRG_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
 
#define AIPS_PACRG_SP6_MASK   (0x40U)
 
#define AIPS_PACRG_SP6_SHIFT   (6U)
 
#define AIPS_PACRG_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
 
#define AIPS_PACRG_TP5_MASK   (0x100U)
 
#define AIPS_PACRG_TP5_SHIFT   (8U)
 
#define AIPS_PACRG_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
 
#define AIPS_PACRG_WP5_MASK   (0x200U)
 
#define AIPS_PACRG_WP5_SHIFT   (9U)
 
#define AIPS_PACRG_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
 
#define AIPS_PACRG_SP5_MASK   (0x400U)
 
#define AIPS_PACRG_SP5_SHIFT   (10U)
 
#define AIPS_PACRG_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
 
#define AIPS_PACRG_TP4_MASK   (0x1000U)
 
#define AIPS_PACRG_TP4_SHIFT   (12U)
 
#define AIPS_PACRG_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
 
#define AIPS_PACRG_WP4_MASK   (0x2000U)
 
#define AIPS_PACRG_WP4_SHIFT   (13U)
 
#define AIPS_PACRG_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
 
#define AIPS_PACRG_SP4_MASK   (0x4000U)
 
#define AIPS_PACRG_SP4_SHIFT   (14U)
 
#define AIPS_PACRG_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
 
#define AIPS_PACRG_TP3_MASK   (0x10000U)
 
#define AIPS_PACRG_TP3_SHIFT   (16U)
 
#define AIPS_PACRG_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
 
#define AIPS_PACRG_WP3_MASK   (0x20000U)
 
#define AIPS_PACRG_WP3_SHIFT   (17U)
 
#define AIPS_PACRG_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
 
#define AIPS_PACRG_SP3_MASK   (0x40000U)
 
#define AIPS_PACRG_SP3_SHIFT   (18U)
 
#define AIPS_PACRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
 
#define AIPS_PACRG_TP2_MASK   (0x100000U)
 
#define AIPS_PACRG_TP2_SHIFT   (20U)
 
#define AIPS_PACRG_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
 
#define AIPS_PACRG_WP2_MASK   (0x200000U)
 
#define AIPS_PACRG_WP2_SHIFT   (21U)
 
#define AIPS_PACRG_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
 
#define AIPS_PACRG_SP2_MASK   (0x400000U)
 
#define AIPS_PACRG_SP2_SHIFT   (22U)
 
#define AIPS_PACRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
 
#define AIPS_PACRG_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRG_TP1_SHIFT   (24U)
 
#define AIPS_PACRG_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
 
#define AIPS_PACRG_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRG_WP1_SHIFT   (25U)
 
#define AIPS_PACRG_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
 
#define AIPS_PACRG_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRG_SP1_SHIFT   (26U)
 
#define AIPS_PACRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
 
#define AIPS_PACRG_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRG_TP0_SHIFT   (28U)
 
#define AIPS_PACRG_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
 
#define AIPS_PACRG_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRG_WP0_SHIFT   (29U)
 
#define AIPS_PACRG_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
 
#define AIPS_PACRG_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRG_SP0_SHIFT   (30U)
 
#define AIPS_PACRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
 

PACRH - Peripheral Access Control Register

#define AIPS_PACRH_TP7_MASK   (0x1U)
 
#define AIPS_PACRH_TP7_SHIFT   (0U)
 
#define AIPS_PACRH_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
 
#define AIPS_PACRH_WP7_MASK   (0x2U)
 
#define AIPS_PACRH_WP7_SHIFT   (1U)
 
#define AIPS_PACRH_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
 
#define AIPS_PACRH_SP7_MASK   (0x4U)
 
#define AIPS_PACRH_SP7_SHIFT   (2U)
 
#define AIPS_PACRH_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
 
#define AIPS_PACRH_TP6_MASK   (0x10U)
 
#define AIPS_PACRH_TP6_SHIFT   (4U)
 
#define AIPS_PACRH_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
 
#define AIPS_PACRH_WP6_MASK   (0x20U)
 
#define AIPS_PACRH_WP6_SHIFT   (5U)
 
#define AIPS_PACRH_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
 
#define AIPS_PACRH_SP6_MASK   (0x40U)
 
#define AIPS_PACRH_SP6_SHIFT   (6U)
 
#define AIPS_PACRH_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
 
#define AIPS_PACRH_TP5_MASK   (0x100U)
 
#define AIPS_PACRH_TP5_SHIFT   (8U)
 
#define AIPS_PACRH_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
 
#define AIPS_PACRH_WP5_MASK   (0x200U)
 
#define AIPS_PACRH_WP5_SHIFT   (9U)
 
#define AIPS_PACRH_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
 
#define AIPS_PACRH_SP5_MASK   (0x400U)
 
#define AIPS_PACRH_SP5_SHIFT   (10U)
 
#define AIPS_PACRH_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
 
#define AIPS_PACRH_TP4_MASK   (0x1000U)
 
#define AIPS_PACRH_TP4_SHIFT   (12U)
 
#define AIPS_PACRH_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
 
#define AIPS_PACRH_WP4_MASK   (0x2000U)
 
#define AIPS_PACRH_WP4_SHIFT   (13U)
 
#define AIPS_PACRH_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
 
#define AIPS_PACRH_SP4_MASK   (0x4000U)
 
#define AIPS_PACRH_SP4_SHIFT   (14U)
 
#define AIPS_PACRH_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
 
#define AIPS_PACRH_TP3_MASK   (0x10000U)
 
#define AIPS_PACRH_TP3_SHIFT   (16U)
 
#define AIPS_PACRH_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
 
#define AIPS_PACRH_WP3_MASK   (0x20000U)
 
#define AIPS_PACRH_WP3_SHIFT   (17U)
 
#define AIPS_PACRH_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
 
#define AIPS_PACRH_SP3_MASK   (0x40000U)
 
#define AIPS_PACRH_SP3_SHIFT   (18U)
 
#define AIPS_PACRH_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
 
#define AIPS_PACRH_TP2_MASK   (0x100000U)
 
#define AIPS_PACRH_TP2_SHIFT   (20U)
 
#define AIPS_PACRH_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
 
#define AIPS_PACRH_WP2_MASK   (0x200000U)
 
#define AIPS_PACRH_WP2_SHIFT   (21U)
 
#define AIPS_PACRH_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
 
#define AIPS_PACRH_SP2_MASK   (0x400000U)
 
#define AIPS_PACRH_SP2_SHIFT   (22U)
 
#define AIPS_PACRH_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
 
#define AIPS_PACRH_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRH_TP1_SHIFT   (24U)
 
#define AIPS_PACRH_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
 
#define AIPS_PACRH_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRH_WP1_SHIFT   (25U)
 
#define AIPS_PACRH_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
 
#define AIPS_PACRH_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRH_SP1_SHIFT   (26U)
 
#define AIPS_PACRH_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
 
#define AIPS_PACRH_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRH_TP0_SHIFT   (28U)
 
#define AIPS_PACRH_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
 
#define AIPS_PACRH_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRH_WP0_SHIFT   (29U)
 
#define AIPS_PACRH_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
 
#define AIPS_PACRH_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRH_SP0_SHIFT   (30U)
 
#define AIPS_PACRH_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
 
#define AIPS_PACRH_TP7_MASK   0x1u
 
#define AIPS_PACRH_TP7_SHIFT   0
 
#define AIPS_PACRH_WP7_MASK   0x2u
 
#define AIPS_PACRH_WP7_SHIFT   1
 
#define AIPS_PACRH_SP7_MASK   0x4u
 
#define AIPS_PACRH_SP7_SHIFT   2
 
#define AIPS_PACRH_TP6_MASK   0x10u
 
#define AIPS_PACRH_TP6_SHIFT   4
 
#define AIPS_PACRH_WP6_MASK   0x20u
 
#define AIPS_PACRH_WP6_SHIFT   5
 
#define AIPS_PACRH_SP6_MASK   0x40u
 
#define AIPS_PACRH_SP6_SHIFT   6
 
#define AIPS_PACRH_TP5_MASK   0x100u
 
#define AIPS_PACRH_TP5_SHIFT   8
 
#define AIPS_PACRH_WP5_MASK   0x200u
 
#define AIPS_PACRH_WP5_SHIFT   9
 
#define AIPS_PACRH_SP5_MASK   0x400u
 
#define AIPS_PACRH_SP5_SHIFT   10
 
#define AIPS_PACRH_TP4_MASK   0x1000u
 
#define AIPS_PACRH_TP4_SHIFT   12
 
#define AIPS_PACRH_WP4_MASK   0x2000u
 
#define AIPS_PACRH_WP4_SHIFT   13
 
#define AIPS_PACRH_SP4_MASK   0x4000u
 
#define AIPS_PACRH_SP4_SHIFT   14
 
#define AIPS_PACRH_TP3_MASK   0x10000u
 
#define AIPS_PACRH_TP3_SHIFT   16
 
#define AIPS_PACRH_WP3_MASK   0x20000u
 
#define AIPS_PACRH_WP3_SHIFT   17
 
#define AIPS_PACRH_SP3_MASK   0x40000u
 
#define AIPS_PACRH_SP3_SHIFT   18
 
#define AIPS_PACRH_TP2_MASK   0x100000u
 
#define AIPS_PACRH_TP2_SHIFT   20
 
#define AIPS_PACRH_WP2_MASK   0x200000u
 
#define AIPS_PACRH_WP2_SHIFT   21
 
#define AIPS_PACRH_SP2_MASK   0x400000u
 
#define AIPS_PACRH_SP2_SHIFT   22
 
#define AIPS_PACRH_TP1_MASK   0x1000000u
 
#define AIPS_PACRH_TP1_SHIFT   24
 
#define AIPS_PACRH_WP1_MASK   0x2000000u
 
#define AIPS_PACRH_WP1_SHIFT   25
 
#define AIPS_PACRH_SP1_MASK   0x4000000u
 
#define AIPS_PACRH_SP1_SHIFT   26
 
#define AIPS_PACRH_TP0_MASK   0x10000000u
 
#define AIPS_PACRH_TP0_SHIFT   28
 
#define AIPS_PACRH_WP0_MASK   0x20000000u
 
#define AIPS_PACRH_WP0_SHIFT   29
 
#define AIPS_PACRH_SP0_MASK   0x40000000u
 
#define AIPS_PACRH_SP0_SHIFT   30
 
#define AIPS_PACRH_TP7_MASK   (0x1U)
 
#define AIPS_PACRH_TP7_SHIFT   (0U)
 
#define AIPS_PACRH_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
 
#define AIPS_PACRH_WP7_MASK   (0x2U)
 
#define AIPS_PACRH_WP7_SHIFT   (1U)
 
#define AIPS_PACRH_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
 
#define AIPS_PACRH_SP7_MASK   (0x4U)
 
#define AIPS_PACRH_SP7_SHIFT   (2U)
 
#define AIPS_PACRH_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
 
#define AIPS_PACRH_TP6_MASK   (0x10U)
 
#define AIPS_PACRH_TP6_SHIFT   (4U)
 
#define AIPS_PACRH_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
 
#define AIPS_PACRH_WP6_MASK   (0x20U)
 
#define AIPS_PACRH_WP6_SHIFT   (5U)
 
#define AIPS_PACRH_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
 
#define AIPS_PACRH_SP6_MASK   (0x40U)
 
#define AIPS_PACRH_SP6_SHIFT   (6U)
 
#define AIPS_PACRH_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
 
#define AIPS_PACRH_TP5_MASK   (0x100U)
 
#define AIPS_PACRH_TP5_SHIFT   (8U)
 
#define AIPS_PACRH_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
 
#define AIPS_PACRH_WP5_MASK   (0x200U)
 
#define AIPS_PACRH_WP5_SHIFT   (9U)
 
#define AIPS_PACRH_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
 
#define AIPS_PACRH_SP5_MASK   (0x400U)
 
#define AIPS_PACRH_SP5_SHIFT   (10U)
 
#define AIPS_PACRH_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
 
#define AIPS_PACRH_TP4_MASK   (0x1000U)
 
#define AIPS_PACRH_TP4_SHIFT   (12U)
 
#define AIPS_PACRH_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
 
#define AIPS_PACRH_WP4_MASK   (0x2000U)
 
#define AIPS_PACRH_WP4_SHIFT   (13U)
 
#define AIPS_PACRH_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
 
#define AIPS_PACRH_SP4_MASK   (0x4000U)
 
#define AIPS_PACRH_SP4_SHIFT   (14U)
 
#define AIPS_PACRH_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
 
#define AIPS_PACRH_TP3_MASK   (0x10000U)
 
#define AIPS_PACRH_TP3_SHIFT   (16U)
 
#define AIPS_PACRH_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
 
#define AIPS_PACRH_WP3_MASK   (0x20000U)
 
#define AIPS_PACRH_WP3_SHIFT   (17U)
 
#define AIPS_PACRH_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
 
#define AIPS_PACRH_SP3_MASK   (0x40000U)
 
#define AIPS_PACRH_SP3_SHIFT   (18U)
 
#define AIPS_PACRH_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
 
#define AIPS_PACRH_TP2_MASK   (0x100000U)
 
#define AIPS_PACRH_TP2_SHIFT   (20U)
 
#define AIPS_PACRH_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
 
#define AIPS_PACRH_WP2_MASK   (0x200000U)
 
#define AIPS_PACRH_WP2_SHIFT   (21U)
 
#define AIPS_PACRH_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
 
#define AIPS_PACRH_SP2_MASK   (0x400000U)
 
#define AIPS_PACRH_SP2_SHIFT   (22U)
 
#define AIPS_PACRH_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
 
#define AIPS_PACRH_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRH_TP1_SHIFT   (24U)
 
#define AIPS_PACRH_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
 
#define AIPS_PACRH_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRH_WP1_SHIFT   (25U)
 
#define AIPS_PACRH_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
 
#define AIPS_PACRH_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRH_SP1_SHIFT   (26U)
 
#define AIPS_PACRH_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
 
#define AIPS_PACRH_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRH_TP0_SHIFT   (28U)
 
#define AIPS_PACRH_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
 
#define AIPS_PACRH_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRH_WP0_SHIFT   (29U)
 
#define AIPS_PACRH_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
 
#define AIPS_PACRH_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRH_SP0_SHIFT   (30U)
 
#define AIPS_PACRH_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
 
#define AIPS_PACRH_TP7_MASK   (0x1U)
 
#define AIPS_PACRH_TP7_SHIFT   (0U)
 
#define AIPS_PACRH_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
 
#define AIPS_PACRH_WP7_MASK   (0x2U)
 
#define AIPS_PACRH_WP7_SHIFT   (1U)
 
#define AIPS_PACRH_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
 
#define AIPS_PACRH_SP7_MASK   (0x4U)
 
#define AIPS_PACRH_SP7_SHIFT   (2U)
 
#define AIPS_PACRH_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
 
#define AIPS_PACRH_TP6_MASK   (0x10U)
 
#define AIPS_PACRH_TP6_SHIFT   (4U)
 
#define AIPS_PACRH_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
 
#define AIPS_PACRH_WP6_MASK   (0x20U)
 
#define AIPS_PACRH_WP6_SHIFT   (5U)
 
#define AIPS_PACRH_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
 
#define AIPS_PACRH_SP6_MASK   (0x40U)
 
#define AIPS_PACRH_SP6_SHIFT   (6U)
 
#define AIPS_PACRH_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
 
#define AIPS_PACRH_TP5_MASK   (0x100U)
 
#define AIPS_PACRH_TP5_SHIFT   (8U)
 
#define AIPS_PACRH_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
 
#define AIPS_PACRH_WP5_MASK   (0x200U)
 
#define AIPS_PACRH_WP5_SHIFT   (9U)
 
#define AIPS_PACRH_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
 
#define AIPS_PACRH_SP5_MASK   (0x400U)
 
#define AIPS_PACRH_SP5_SHIFT   (10U)
 
#define AIPS_PACRH_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
 
#define AIPS_PACRH_TP4_MASK   (0x1000U)
 
#define AIPS_PACRH_TP4_SHIFT   (12U)
 
#define AIPS_PACRH_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
 
#define AIPS_PACRH_WP4_MASK   (0x2000U)
 
#define AIPS_PACRH_WP4_SHIFT   (13U)
 
#define AIPS_PACRH_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
 
#define AIPS_PACRH_SP4_MASK   (0x4000U)
 
#define AIPS_PACRH_SP4_SHIFT   (14U)
 
#define AIPS_PACRH_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
 
#define AIPS_PACRH_TP3_MASK   (0x10000U)
 
#define AIPS_PACRH_TP3_SHIFT   (16U)
 
#define AIPS_PACRH_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
 
#define AIPS_PACRH_WP3_MASK   (0x20000U)
 
#define AIPS_PACRH_WP3_SHIFT   (17U)
 
#define AIPS_PACRH_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
 
#define AIPS_PACRH_SP3_MASK   (0x40000U)
 
#define AIPS_PACRH_SP3_SHIFT   (18U)
 
#define AIPS_PACRH_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
 
#define AIPS_PACRH_TP2_MASK   (0x100000U)
 
#define AIPS_PACRH_TP2_SHIFT   (20U)
 
#define AIPS_PACRH_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
 
#define AIPS_PACRH_WP2_MASK   (0x200000U)
 
#define AIPS_PACRH_WP2_SHIFT   (21U)
 
#define AIPS_PACRH_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
 
#define AIPS_PACRH_SP2_MASK   (0x400000U)
 
#define AIPS_PACRH_SP2_SHIFT   (22U)
 
#define AIPS_PACRH_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
 
#define AIPS_PACRH_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRH_TP1_SHIFT   (24U)
 
#define AIPS_PACRH_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
 
#define AIPS_PACRH_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRH_WP1_SHIFT   (25U)
 
#define AIPS_PACRH_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
 
#define AIPS_PACRH_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRH_SP1_SHIFT   (26U)
 
#define AIPS_PACRH_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
 
#define AIPS_PACRH_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRH_TP0_SHIFT   (28U)
 
#define AIPS_PACRH_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
 
#define AIPS_PACRH_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRH_WP0_SHIFT   (29U)
 
#define AIPS_PACRH_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
 
#define AIPS_PACRH_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRH_SP0_SHIFT   (30U)
 
#define AIPS_PACRH_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
 
#define AIPS_PACRH_TP7_MASK   (0x1U)
 
#define AIPS_PACRH_TP7_SHIFT   (0U)
 
#define AIPS_PACRH_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
 
#define AIPS_PACRH_WP7_MASK   (0x2U)
 
#define AIPS_PACRH_WP7_SHIFT   (1U)
 
#define AIPS_PACRH_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
 
#define AIPS_PACRH_SP7_MASK   (0x4U)
 
#define AIPS_PACRH_SP7_SHIFT   (2U)
 
#define AIPS_PACRH_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
 
#define AIPS_PACRH_TP6_MASK   (0x10U)
 
#define AIPS_PACRH_TP6_SHIFT   (4U)
 
#define AIPS_PACRH_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
 
#define AIPS_PACRH_WP6_MASK   (0x20U)
 
#define AIPS_PACRH_WP6_SHIFT   (5U)
 
#define AIPS_PACRH_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
 
#define AIPS_PACRH_SP6_MASK   (0x40U)
 
#define AIPS_PACRH_SP6_SHIFT   (6U)
 
#define AIPS_PACRH_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
 
#define AIPS_PACRH_TP5_MASK   (0x100U)
 
#define AIPS_PACRH_TP5_SHIFT   (8U)
 
#define AIPS_PACRH_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
 
#define AIPS_PACRH_WP5_MASK   (0x200U)
 
#define AIPS_PACRH_WP5_SHIFT   (9U)
 
#define AIPS_PACRH_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
 
#define AIPS_PACRH_SP5_MASK   (0x400U)
 
#define AIPS_PACRH_SP5_SHIFT   (10U)
 
#define AIPS_PACRH_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
 
#define AIPS_PACRH_TP4_MASK   (0x1000U)
 
#define AIPS_PACRH_TP4_SHIFT   (12U)
 
#define AIPS_PACRH_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
 
#define AIPS_PACRH_WP4_MASK   (0x2000U)
 
#define AIPS_PACRH_WP4_SHIFT   (13U)
 
#define AIPS_PACRH_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
 
#define AIPS_PACRH_SP4_MASK   (0x4000U)
 
#define AIPS_PACRH_SP4_SHIFT   (14U)
 
#define AIPS_PACRH_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
 
#define AIPS_PACRH_TP3_MASK   (0x10000U)
 
#define AIPS_PACRH_TP3_SHIFT   (16U)
 
#define AIPS_PACRH_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
 
#define AIPS_PACRH_WP3_MASK   (0x20000U)
 
#define AIPS_PACRH_WP3_SHIFT   (17U)
 
#define AIPS_PACRH_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
 
#define AIPS_PACRH_SP3_MASK   (0x40000U)
 
#define AIPS_PACRH_SP3_SHIFT   (18U)
 
#define AIPS_PACRH_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
 
#define AIPS_PACRH_TP2_MASK   (0x100000U)
 
#define AIPS_PACRH_TP2_SHIFT   (20U)
 
#define AIPS_PACRH_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
 
#define AIPS_PACRH_WP2_MASK   (0x200000U)
 
#define AIPS_PACRH_WP2_SHIFT   (21U)
 
#define AIPS_PACRH_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
 
#define AIPS_PACRH_SP2_MASK   (0x400000U)
 
#define AIPS_PACRH_SP2_SHIFT   (22U)
 
#define AIPS_PACRH_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
 
#define AIPS_PACRH_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRH_TP1_SHIFT   (24U)
 
#define AIPS_PACRH_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
 
#define AIPS_PACRH_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRH_WP1_SHIFT   (25U)
 
#define AIPS_PACRH_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
 
#define AIPS_PACRH_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRH_SP1_SHIFT   (26U)
 
#define AIPS_PACRH_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
 
#define AIPS_PACRH_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRH_TP0_SHIFT   (28U)
 
#define AIPS_PACRH_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
 
#define AIPS_PACRH_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRH_WP0_SHIFT   (29U)
 
#define AIPS_PACRH_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
 
#define AIPS_PACRH_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRH_SP0_SHIFT   (30U)
 
#define AIPS_PACRH_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
 
#define AIPS_PACRH_TP7_MASK   (0x1U)
 
#define AIPS_PACRH_TP7_SHIFT   (0U)
 
#define AIPS_PACRH_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
 
#define AIPS_PACRH_WP7_MASK   (0x2U)
 
#define AIPS_PACRH_WP7_SHIFT   (1U)
 
#define AIPS_PACRH_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
 
#define AIPS_PACRH_SP7_MASK   (0x4U)
 
#define AIPS_PACRH_SP7_SHIFT   (2U)
 
#define AIPS_PACRH_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
 
#define AIPS_PACRH_TP6_MASK   (0x10U)
 
#define AIPS_PACRH_TP6_SHIFT   (4U)
 
#define AIPS_PACRH_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
 
#define AIPS_PACRH_WP6_MASK   (0x20U)
 
#define AIPS_PACRH_WP6_SHIFT   (5U)
 
#define AIPS_PACRH_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
 
#define AIPS_PACRH_SP6_MASK   (0x40U)
 
#define AIPS_PACRH_SP6_SHIFT   (6U)
 
#define AIPS_PACRH_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
 
#define AIPS_PACRH_TP5_MASK   (0x100U)
 
#define AIPS_PACRH_TP5_SHIFT   (8U)
 
#define AIPS_PACRH_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
 
#define AIPS_PACRH_WP5_MASK   (0x200U)
 
#define AIPS_PACRH_WP5_SHIFT   (9U)
 
#define AIPS_PACRH_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
 
#define AIPS_PACRH_SP5_MASK   (0x400U)
 
#define AIPS_PACRH_SP5_SHIFT   (10U)
 
#define AIPS_PACRH_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
 
#define AIPS_PACRH_TP4_MASK   (0x1000U)
 
#define AIPS_PACRH_TP4_SHIFT   (12U)
 
#define AIPS_PACRH_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
 
#define AIPS_PACRH_WP4_MASK   (0x2000U)
 
#define AIPS_PACRH_WP4_SHIFT   (13U)
 
#define AIPS_PACRH_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
 
#define AIPS_PACRH_SP4_MASK   (0x4000U)
 
#define AIPS_PACRH_SP4_SHIFT   (14U)
 
#define AIPS_PACRH_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
 
#define AIPS_PACRH_TP3_MASK   (0x10000U)
 
#define AIPS_PACRH_TP3_SHIFT   (16U)
 
#define AIPS_PACRH_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
 
#define AIPS_PACRH_WP3_MASK   (0x20000U)
 
#define AIPS_PACRH_WP3_SHIFT   (17U)
 
#define AIPS_PACRH_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
 
#define AIPS_PACRH_SP3_MASK   (0x40000U)
 
#define AIPS_PACRH_SP3_SHIFT   (18U)
 
#define AIPS_PACRH_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
 
#define AIPS_PACRH_TP2_MASK   (0x100000U)
 
#define AIPS_PACRH_TP2_SHIFT   (20U)
 
#define AIPS_PACRH_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
 
#define AIPS_PACRH_WP2_MASK   (0x200000U)
 
#define AIPS_PACRH_WP2_SHIFT   (21U)
 
#define AIPS_PACRH_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
 
#define AIPS_PACRH_SP2_MASK   (0x400000U)
 
#define AIPS_PACRH_SP2_SHIFT   (22U)
 
#define AIPS_PACRH_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
 
#define AIPS_PACRH_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRH_TP1_SHIFT   (24U)
 
#define AIPS_PACRH_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
 
#define AIPS_PACRH_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRH_WP1_SHIFT   (25U)
 
#define AIPS_PACRH_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
 
#define AIPS_PACRH_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRH_SP1_SHIFT   (26U)
 
#define AIPS_PACRH_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
 
#define AIPS_PACRH_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRH_TP0_SHIFT   (28U)
 
#define AIPS_PACRH_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
 
#define AIPS_PACRH_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRH_WP0_SHIFT   (29U)
 
#define AIPS_PACRH_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
 
#define AIPS_PACRH_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRH_SP0_SHIFT   (30U)
 
#define AIPS_PACRH_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
 

PACRI - Peripheral Access Control Register

#define AIPS_PACRI_TP7_MASK   (0x1U)
 
#define AIPS_PACRI_TP7_SHIFT   (0U)
 
#define AIPS_PACRI_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
 
#define AIPS_PACRI_WP7_MASK   (0x2U)
 
#define AIPS_PACRI_WP7_SHIFT   (1U)
 
#define AIPS_PACRI_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
 
#define AIPS_PACRI_SP7_MASK   (0x4U)
 
#define AIPS_PACRI_SP7_SHIFT   (2U)
 
#define AIPS_PACRI_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
 
#define AIPS_PACRI_TP6_MASK   (0x10U)
 
#define AIPS_PACRI_TP6_SHIFT   (4U)
 
#define AIPS_PACRI_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
 
#define AIPS_PACRI_WP6_MASK   (0x20U)
 
#define AIPS_PACRI_WP6_SHIFT   (5U)
 
#define AIPS_PACRI_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
 
#define AIPS_PACRI_SP6_MASK   (0x40U)
 
#define AIPS_PACRI_SP6_SHIFT   (6U)
 
#define AIPS_PACRI_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
 
#define AIPS_PACRI_TP5_MASK   (0x100U)
 
#define AIPS_PACRI_TP5_SHIFT   (8U)
 
#define AIPS_PACRI_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
 
#define AIPS_PACRI_WP5_MASK   (0x200U)
 
#define AIPS_PACRI_WP5_SHIFT   (9U)
 
#define AIPS_PACRI_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
 
#define AIPS_PACRI_SP5_MASK   (0x400U)
 
#define AIPS_PACRI_SP5_SHIFT   (10U)
 
#define AIPS_PACRI_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
 
#define AIPS_PACRI_TP4_MASK   (0x1000U)
 
#define AIPS_PACRI_TP4_SHIFT   (12U)
 
#define AIPS_PACRI_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
 
#define AIPS_PACRI_WP4_MASK   (0x2000U)
 
#define AIPS_PACRI_WP4_SHIFT   (13U)
 
#define AIPS_PACRI_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
 
#define AIPS_PACRI_SP4_MASK   (0x4000U)
 
#define AIPS_PACRI_SP4_SHIFT   (14U)
 
#define AIPS_PACRI_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
 
#define AIPS_PACRI_TP3_MASK   (0x10000U)
 
#define AIPS_PACRI_TP3_SHIFT   (16U)
 
#define AIPS_PACRI_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
 
#define AIPS_PACRI_WP3_MASK   (0x20000U)
 
#define AIPS_PACRI_WP3_SHIFT   (17U)
 
#define AIPS_PACRI_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
 
#define AIPS_PACRI_SP3_MASK   (0x40000U)
 
#define AIPS_PACRI_SP3_SHIFT   (18U)
 
#define AIPS_PACRI_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
 
#define AIPS_PACRI_TP2_MASK   (0x100000U)
 
#define AIPS_PACRI_TP2_SHIFT   (20U)
 
#define AIPS_PACRI_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
 
#define AIPS_PACRI_WP2_MASK   (0x200000U)
 
#define AIPS_PACRI_WP2_SHIFT   (21U)
 
#define AIPS_PACRI_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
 
#define AIPS_PACRI_SP2_MASK   (0x400000U)
 
#define AIPS_PACRI_SP2_SHIFT   (22U)
 
#define AIPS_PACRI_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
 
#define AIPS_PACRI_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRI_TP1_SHIFT   (24U)
 
#define AIPS_PACRI_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
 
#define AIPS_PACRI_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRI_WP1_SHIFT   (25U)
 
#define AIPS_PACRI_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
 
#define AIPS_PACRI_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRI_SP1_SHIFT   (26U)
 
#define AIPS_PACRI_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
 
#define AIPS_PACRI_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRI_TP0_SHIFT   (28U)
 
#define AIPS_PACRI_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
 
#define AIPS_PACRI_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRI_WP0_SHIFT   (29U)
 
#define AIPS_PACRI_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
 
#define AIPS_PACRI_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRI_SP0_SHIFT   (30U)
 
#define AIPS_PACRI_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
 
#define AIPS_PACRI_TP7_MASK   0x1u
 
#define AIPS_PACRI_TP7_SHIFT   0
 
#define AIPS_PACRI_WP7_MASK   0x2u
 
#define AIPS_PACRI_WP7_SHIFT   1
 
#define AIPS_PACRI_SP7_MASK   0x4u
 
#define AIPS_PACRI_SP7_SHIFT   2
 
#define AIPS_PACRI_TP6_MASK   0x10u
 
#define AIPS_PACRI_TP6_SHIFT   4
 
#define AIPS_PACRI_WP6_MASK   0x20u
 
#define AIPS_PACRI_WP6_SHIFT   5
 
#define AIPS_PACRI_SP6_MASK   0x40u
 
#define AIPS_PACRI_SP6_SHIFT   6
 
#define AIPS_PACRI_TP5_MASK   0x100u
 
#define AIPS_PACRI_TP5_SHIFT   8
 
#define AIPS_PACRI_WP5_MASK   0x200u
 
#define AIPS_PACRI_WP5_SHIFT   9
 
#define AIPS_PACRI_SP5_MASK   0x400u
 
#define AIPS_PACRI_SP5_SHIFT   10
 
#define AIPS_PACRI_TP4_MASK   0x1000u
 
#define AIPS_PACRI_TP4_SHIFT   12
 
#define AIPS_PACRI_WP4_MASK   0x2000u
 
#define AIPS_PACRI_WP4_SHIFT   13
 
#define AIPS_PACRI_SP4_MASK   0x4000u
 
#define AIPS_PACRI_SP4_SHIFT   14
 
#define AIPS_PACRI_TP3_MASK   0x10000u
 
#define AIPS_PACRI_TP3_SHIFT   16
 
#define AIPS_PACRI_WP3_MASK   0x20000u
 
#define AIPS_PACRI_WP3_SHIFT   17
 
#define AIPS_PACRI_SP3_MASK   0x40000u
 
#define AIPS_PACRI_SP3_SHIFT   18
 
#define AIPS_PACRI_TP2_MASK   0x100000u
 
#define AIPS_PACRI_TP2_SHIFT   20
 
#define AIPS_PACRI_WP2_MASK   0x200000u
 
#define AIPS_PACRI_WP2_SHIFT   21
 
#define AIPS_PACRI_SP2_MASK   0x400000u
 
#define AIPS_PACRI_SP2_SHIFT   22
 
#define AIPS_PACRI_TP1_MASK   0x1000000u
 
#define AIPS_PACRI_TP1_SHIFT   24
 
#define AIPS_PACRI_WP1_MASK   0x2000000u
 
#define AIPS_PACRI_WP1_SHIFT   25
 
#define AIPS_PACRI_SP1_MASK   0x4000000u
 
#define AIPS_PACRI_SP1_SHIFT   26
 
#define AIPS_PACRI_TP0_MASK   0x10000000u
 
#define AIPS_PACRI_TP0_SHIFT   28
 
#define AIPS_PACRI_WP0_MASK   0x20000000u
 
#define AIPS_PACRI_WP0_SHIFT   29
 
#define AIPS_PACRI_SP0_MASK   0x40000000u
 
#define AIPS_PACRI_SP0_SHIFT   30
 
#define AIPS_PACRI_TP7_MASK   (0x1U)
 
#define AIPS_PACRI_TP7_SHIFT   (0U)
 
#define AIPS_PACRI_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
 
#define AIPS_PACRI_WP7_MASK   (0x2U)
 
#define AIPS_PACRI_WP7_SHIFT   (1U)
 
#define AIPS_PACRI_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
 
#define AIPS_PACRI_SP7_MASK   (0x4U)
 
#define AIPS_PACRI_SP7_SHIFT   (2U)
 
#define AIPS_PACRI_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
 
#define AIPS_PACRI_TP6_MASK   (0x10U)
 
#define AIPS_PACRI_TP6_SHIFT   (4U)
 
#define AIPS_PACRI_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
 
#define AIPS_PACRI_WP6_MASK   (0x20U)
 
#define AIPS_PACRI_WP6_SHIFT   (5U)
 
#define AIPS_PACRI_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
 
#define AIPS_PACRI_SP6_MASK   (0x40U)
 
#define AIPS_PACRI_SP6_SHIFT   (6U)
 
#define AIPS_PACRI_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
 
#define AIPS_PACRI_TP5_MASK   (0x100U)
 
#define AIPS_PACRI_TP5_SHIFT   (8U)
 
#define AIPS_PACRI_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
 
#define AIPS_PACRI_WP5_MASK   (0x200U)
 
#define AIPS_PACRI_WP5_SHIFT   (9U)
 
#define AIPS_PACRI_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
 
#define AIPS_PACRI_SP5_MASK   (0x400U)
 
#define AIPS_PACRI_SP5_SHIFT   (10U)
 
#define AIPS_PACRI_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
 
#define AIPS_PACRI_TP4_MASK   (0x1000U)
 
#define AIPS_PACRI_TP4_SHIFT   (12U)
 
#define AIPS_PACRI_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
 
#define AIPS_PACRI_WP4_MASK   (0x2000U)
 
#define AIPS_PACRI_WP4_SHIFT   (13U)
 
#define AIPS_PACRI_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
 
#define AIPS_PACRI_SP4_MASK   (0x4000U)
 
#define AIPS_PACRI_SP4_SHIFT   (14U)
 
#define AIPS_PACRI_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
 
#define AIPS_PACRI_TP3_MASK   (0x10000U)
 
#define AIPS_PACRI_TP3_SHIFT   (16U)
 
#define AIPS_PACRI_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
 
#define AIPS_PACRI_WP3_MASK   (0x20000U)
 
#define AIPS_PACRI_WP3_SHIFT   (17U)
 
#define AIPS_PACRI_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
 
#define AIPS_PACRI_SP3_MASK   (0x40000U)
 
#define AIPS_PACRI_SP3_SHIFT   (18U)
 
#define AIPS_PACRI_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
 
#define AIPS_PACRI_TP2_MASK   (0x100000U)
 
#define AIPS_PACRI_TP2_SHIFT   (20U)
 
#define AIPS_PACRI_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
 
#define AIPS_PACRI_WP2_MASK   (0x200000U)
 
#define AIPS_PACRI_WP2_SHIFT   (21U)
 
#define AIPS_PACRI_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
 
#define AIPS_PACRI_SP2_MASK   (0x400000U)
 
#define AIPS_PACRI_SP2_SHIFT   (22U)
 
#define AIPS_PACRI_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
 
#define AIPS_PACRI_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRI_TP1_SHIFT   (24U)
 
#define AIPS_PACRI_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
 
#define AIPS_PACRI_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRI_WP1_SHIFT   (25U)
 
#define AIPS_PACRI_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
 
#define AIPS_PACRI_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRI_SP1_SHIFT   (26U)
 
#define AIPS_PACRI_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
 
#define AIPS_PACRI_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRI_TP0_SHIFT   (28U)
 
#define AIPS_PACRI_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
 
#define AIPS_PACRI_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRI_WP0_SHIFT   (29U)
 
#define AIPS_PACRI_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
 
#define AIPS_PACRI_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRI_SP0_SHIFT   (30U)
 
#define AIPS_PACRI_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
 
#define AIPS_PACRI_TP7_MASK   (0x1U)
 
#define AIPS_PACRI_TP7_SHIFT   (0U)
 
#define AIPS_PACRI_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
 
#define AIPS_PACRI_WP7_MASK   (0x2U)
 
#define AIPS_PACRI_WP7_SHIFT   (1U)
 
#define AIPS_PACRI_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
 
#define AIPS_PACRI_SP7_MASK   (0x4U)
 
#define AIPS_PACRI_SP7_SHIFT   (2U)
 
#define AIPS_PACRI_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
 
#define AIPS_PACRI_TP6_MASK   (0x10U)
 
#define AIPS_PACRI_TP6_SHIFT   (4U)
 
#define AIPS_PACRI_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
 
#define AIPS_PACRI_WP6_MASK   (0x20U)
 
#define AIPS_PACRI_WP6_SHIFT   (5U)
 
#define AIPS_PACRI_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
 
#define AIPS_PACRI_SP6_MASK   (0x40U)
 
#define AIPS_PACRI_SP6_SHIFT   (6U)
 
#define AIPS_PACRI_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
 
#define AIPS_PACRI_TP5_MASK   (0x100U)
 
#define AIPS_PACRI_TP5_SHIFT   (8U)
 
#define AIPS_PACRI_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
 
#define AIPS_PACRI_WP5_MASK   (0x200U)
 
#define AIPS_PACRI_WP5_SHIFT   (9U)
 
#define AIPS_PACRI_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
 
#define AIPS_PACRI_SP5_MASK   (0x400U)
 
#define AIPS_PACRI_SP5_SHIFT   (10U)
 
#define AIPS_PACRI_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
 
#define AIPS_PACRI_TP4_MASK   (0x1000U)
 
#define AIPS_PACRI_TP4_SHIFT   (12U)
 
#define AIPS_PACRI_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
 
#define AIPS_PACRI_WP4_MASK   (0x2000U)
 
#define AIPS_PACRI_WP4_SHIFT   (13U)
 
#define AIPS_PACRI_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
 
#define AIPS_PACRI_SP4_MASK   (0x4000U)
 
#define AIPS_PACRI_SP4_SHIFT   (14U)
 
#define AIPS_PACRI_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
 
#define AIPS_PACRI_TP3_MASK   (0x10000U)
 
#define AIPS_PACRI_TP3_SHIFT   (16U)
 
#define AIPS_PACRI_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
 
#define AIPS_PACRI_WP3_MASK   (0x20000U)
 
#define AIPS_PACRI_WP3_SHIFT   (17U)
 
#define AIPS_PACRI_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
 
#define AIPS_PACRI_SP3_MASK   (0x40000U)
 
#define AIPS_PACRI_SP3_SHIFT   (18U)
 
#define AIPS_PACRI_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
 
#define AIPS_PACRI_TP2_MASK   (0x100000U)
 
#define AIPS_PACRI_TP2_SHIFT   (20U)
 
#define AIPS_PACRI_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
 
#define AIPS_PACRI_WP2_MASK   (0x200000U)
 
#define AIPS_PACRI_WP2_SHIFT   (21U)
 
#define AIPS_PACRI_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
 
#define AIPS_PACRI_SP2_MASK   (0x400000U)
 
#define AIPS_PACRI_SP2_SHIFT   (22U)
 
#define AIPS_PACRI_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
 
#define AIPS_PACRI_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRI_TP1_SHIFT   (24U)
 
#define AIPS_PACRI_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
 
#define AIPS_PACRI_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRI_WP1_SHIFT   (25U)
 
#define AIPS_PACRI_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
 
#define AIPS_PACRI_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRI_SP1_SHIFT   (26U)
 
#define AIPS_PACRI_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
 
#define AIPS_PACRI_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRI_TP0_SHIFT   (28U)
 
#define AIPS_PACRI_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
 
#define AIPS_PACRI_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRI_WP0_SHIFT   (29U)
 
#define AIPS_PACRI_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
 
#define AIPS_PACRI_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRI_SP0_SHIFT   (30U)
 
#define AIPS_PACRI_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
 
#define AIPS_PACRI_TP7_MASK   (0x1U)
 
#define AIPS_PACRI_TP7_SHIFT   (0U)
 
#define AIPS_PACRI_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
 
#define AIPS_PACRI_WP7_MASK   (0x2U)
 
#define AIPS_PACRI_WP7_SHIFT   (1U)
 
#define AIPS_PACRI_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
 
#define AIPS_PACRI_SP7_MASK   (0x4U)
 
#define AIPS_PACRI_SP7_SHIFT   (2U)
 
#define AIPS_PACRI_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
 
#define AIPS_PACRI_TP6_MASK   (0x10U)
 
#define AIPS_PACRI_TP6_SHIFT   (4U)
 
#define AIPS_PACRI_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
 
#define AIPS_PACRI_WP6_MASK   (0x20U)
 
#define AIPS_PACRI_WP6_SHIFT   (5U)
 
#define AIPS_PACRI_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
 
#define AIPS_PACRI_SP6_MASK   (0x40U)
 
#define AIPS_PACRI_SP6_SHIFT   (6U)
 
#define AIPS_PACRI_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
 
#define AIPS_PACRI_TP5_MASK   (0x100U)
 
#define AIPS_PACRI_TP5_SHIFT   (8U)
 
#define AIPS_PACRI_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
 
#define AIPS_PACRI_WP5_MASK   (0x200U)
 
#define AIPS_PACRI_WP5_SHIFT   (9U)
 
#define AIPS_PACRI_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
 
#define AIPS_PACRI_SP5_MASK   (0x400U)
 
#define AIPS_PACRI_SP5_SHIFT   (10U)
 
#define AIPS_PACRI_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
 
#define AIPS_PACRI_TP4_MASK   (0x1000U)
 
#define AIPS_PACRI_TP4_SHIFT   (12U)
 
#define AIPS_PACRI_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
 
#define AIPS_PACRI_WP4_MASK   (0x2000U)
 
#define AIPS_PACRI_WP4_SHIFT   (13U)
 
#define AIPS_PACRI_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
 
#define AIPS_PACRI_SP4_MASK   (0x4000U)
 
#define AIPS_PACRI_SP4_SHIFT   (14U)
 
#define AIPS_PACRI_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
 
#define AIPS_PACRI_TP3_MASK   (0x10000U)
 
#define AIPS_PACRI_TP3_SHIFT   (16U)
 
#define AIPS_PACRI_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
 
#define AIPS_PACRI_WP3_MASK   (0x20000U)
 
#define AIPS_PACRI_WP3_SHIFT   (17U)
 
#define AIPS_PACRI_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
 
#define AIPS_PACRI_SP3_MASK   (0x40000U)
 
#define AIPS_PACRI_SP3_SHIFT   (18U)
 
#define AIPS_PACRI_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
 
#define AIPS_PACRI_TP2_MASK   (0x100000U)
 
#define AIPS_PACRI_TP2_SHIFT   (20U)
 
#define AIPS_PACRI_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
 
#define AIPS_PACRI_WP2_MASK   (0x200000U)
 
#define AIPS_PACRI_WP2_SHIFT   (21U)
 
#define AIPS_PACRI_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
 
#define AIPS_PACRI_SP2_MASK   (0x400000U)
 
#define AIPS_PACRI_SP2_SHIFT   (22U)
 
#define AIPS_PACRI_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
 
#define AIPS_PACRI_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRI_TP1_SHIFT   (24U)
 
#define AIPS_PACRI_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
 
#define AIPS_PACRI_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRI_WP1_SHIFT   (25U)
 
#define AIPS_PACRI_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
 
#define AIPS_PACRI_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRI_SP1_SHIFT   (26U)
 
#define AIPS_PACRI_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
 
#define AIPS_PACRI_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRI_TP0_SHIFT   (28U)
 
#define AIPS_PACRI_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
 
#define AIPS_PACRI_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRI_WP0_SHIFT   (29U)
 
#define AIPS_PACRI_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
 
#define AIPS_PACRI_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRI_SP0_SHIFT   (30U)
 
#define AIPS_PACRI_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
 
#define AIPS_PACRI_TP7_MASK   (0x1U)
 
#define AIPS_PACRI_TP7_SHIFT   (0U)
 
#define AIPS_PACRI_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
 
#define AIPS_PACRI_WP7_MASK   (0x2U)
 
#define AIPS_PACRI_WP7_SHIFT   (1U)
 
#define AIPS_PACRI_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
 
#define AIPS_PACRI_SP7_MASK   (0x4U)
 
#define AIPS_PACRI_SP7_SHIFT   (2U)
 
#define AIPS_PACRI_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
 
#define AIPS_PACRI_TP6_MASK   (0x10U)
 
#define AIPS_PACRI_TP6_SHIFT   (4U)
 
#define AIPS_PACRI_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
 
#define AIPS_PACRI_WP6_MASK   (0x20U)
 
#define AIPS_PACRI_WP6_SHIFT   (5U)
 
#define AIPS_PACRI_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
 
#define AIPS_PACRI_SP6_MASK   (0x40U)
 
#define AIPS_PACRI_SP6_SHIFT   (6U)
 
#define AIPS_PACRI_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
 
#define AIPS_PACRI_TP5_MASK   (0x100U)
 
#define AIPS_PACRI_TP5_SHIFT   (8U)
 
#define AIPS_PACRI_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
 
#define AIPS_PACRI_WP5_MASK   (0x200U)
 
#define AIPS_PACRI_WP5_SHIFT   (9U)
 
#define AIPS_PACRI_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
 
#define AIPS_PACRI_SP5_MASK   (0x400U)
 
#define AIPS_PACRI_SP5_SHIFT   (10U)
 
#define AIPS_PACRI_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
 
#define AIPS_PACRI_TP4_MASK   (0x1000U)
 
#define AIPS_PACRI_TP4_SHIFT   (12U)
 
#define AIPS_PACRI_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
 
#define AIPS_PACRI_WP4_MASK   (0x2000U)
 
#define AIPS_PACRI_WP4_SHIFT   (13U)
 
#define AIPS_PACRI_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
 
#define AIPS_PACRI_SP4_MASK   (0x4000U)
 
#define AIPS_PACRI_SP4_SHIFT   (14U)
 
#define AIPS_PACRI_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
 
#define AIPS_PACRI_TP3_MASK   (0x10000U)
 
#define AIPS_PACRI_TP3_SHIFT   (16U)
 
#define AIPS_PACRI_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
 
#define AIPS_PACRI_WP3_MASK   (0x20000U)
 
#define AIPS_PACRI_WP3_SHIFT   (17U)
 
#define AIPS_PACRI_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
 
#define AIPS_PACRI_SP3_MASK   (0x40000U)
 
#define AIPS_PACRI_SP3_SHIFT   (18U)
 
#define AIPS_PACRI_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
 
#define AIPS_PACRI_TP2_MASK   (0x100000U)
 
#define AIPS_PACRI_TP2_SHIFT   (20U)
 
#define AIPS_PACRI_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
 
#define AIPS_PACRI_WP2_MASK   (0x200000U)
 
#define AIPS_PACRI_WP2_SHIFT   (21U)
 
#define AIPS_PACRI_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
 
#define AIPS_PACRI_SP2_MASK   (0x400000U)
 
#define AIPS_PACRI_SP2_SHIFT   (22U)
 
#define AIPS_PACRI_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
 
#define AIPS_PACRI_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRI_TP1_SHIFT   (24U)
 
#define AIPS_PACRI_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
 
#define AIPS_PACRI_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRI_WP1_SHIFT   (25U)
 
#define AIPS_PACRI_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
 
#define AIPS_PACRI_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRI_SP1_SHIFT   (26U)
 
#define AIPS_PACRI_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
 
#define AIPS_PACRI_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRI_TP0_SHIFT   (28U)
 
#define AIPS_PACRI_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
 
#define AIPS_PACRI_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRI_WP0_SHIFT   (29U)
 
#define AIPS_PACRI_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
 
#define AIPS_PACRI_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRI_SP0_SHIFT   (30U)
 
#define AIPS_PACRI_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
 

PACRJ - Peripheral Access Control Register

#define AIPS_PACRJ_TP7_MASK   (0x1U)
 
#define AIPS_PACRJ_TP7_SHIFT   (0U)
 
#define AIPS_PACRJ_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
 
#define AIPS_PACRJ_WP7_MASK   (0x2U)
 
#define AIPS_PACRJ_WP7_SHIFT   (1U)
 
#define AIPS_PACRJ_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
 
#define AIPS_PACRJ_SP7_MASK   (0x4U)
 
#define AIPS_PACRJ_SP7_SHIFT   (2U)
 
#define AIPS_PACRJ_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
 
#define AIPS_PACRJ_TP6_MASK   (0x10U)
 
#define AIPS_PACRJ_TP6_SHIFT   (4U)
 
#define AIPS_PACRJ_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
 
#define AIPS_PACRJ_WP6_MASK   (0x20U)
 
#define AIPS_PACRJ_WP6_SHIFT   (5U)
 
#define AIPS_PACRJ_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
 
#define AIPS_PACRJ_SP6_MASK   (0x40U)
 
#define AIPS_PACRJ_SP6_SHIFT   (6U)
 
#define AIPS_PACRJ_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
 
#define AIPS_PACRJ_TP5_MASK   (0x100U)
 
#define AIPS_PACRJ_TP5_SHIFT   (8U)
 
#define AIPS_PACRJ_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
 
#define AIPS_PACRJ_WP5_MASK   (0x200U)
 
#define AIPS_PACRJ_WP5_SHIFT   (9U)
 
#define AIPS_PACRJ_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
 
#define AIPS_PACRJ_SP5_MASK   (0x400U)
 
#define AIPS_PACRJ_SP5_SHIFT   (10U)
 
#define AIPS_PACRJ_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
 
#define AIPS_PACRJ_TP4_MASK   (0x1000U)
 
#define AIPS_PACRJ_TP4_SHIFT   (12U)
 
#define AIPS_PACRJ_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
 
#define AIPS_PACRJ_WP4_MASK   (0x2000U)
 
#define AIPS_PACRJ_WP4_SHIFT   (13U)
 
#define AIPS_PACRJ_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
 
#define AIPS_PACRJ_SP4_MASK   (0x4000U)
 
#define AIPS_PACRJ_SP4_SHIFT   (14U)
 
#define AIPS_PACRJ_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
 
#define AIPS_PACRJ_TP3_MASK   (0x10000U)
 
#define AIPS_PACRJ_TP3_SHIFT   (16U)
 
#define AIPS_PACRJ_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
 
#define AIPS_PACRJ_WP3_MASK   (0x20000U)
 
#define AIPS_PACRJ_WP3_SHIFT   (17U)
 
#define AIPS_PACRJ_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
 
#define AIPS_PACRJ_SP3_MASK   (0x40000U)
 
#define AIPS_PACRJ_SP3_SHIFT   (18U)
 
#define AIPS_PACRJ_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
 
#define AIPS_PACRJ_TP2_MASK   (0x100000U)
 
#define AIPS_PACRJ_TP2_SHIFT   (20U)
 
#define AIPS_PACRJ_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
 
#define AIPS_PACRJ_WP2_MASK   (0x200000U)
 
#define AIPS_PACRJ_WP2_SHIFT   (21U)
 
#define AIPS_PACRJ_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
 
#define AIPS_PACRJ_SP2_MASK   (0x400000U)
 
#define AIPS_PACRJ_SP2_SHIFT   (22U)
 
#define AIPS_PACRJ_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
 
#define AIPS_PACRJ_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRJ_TP1_SHIFT   (24U)
 
#define AIPS_PACRJ_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
 
#define AIPS_PACRJ_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRJ_WP1_SHIFT   (25U)
 
#define AIPS_PACRJ_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
 
#define AIPS_PACRJ_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRJ_SP1_SHIFT   (26U)
 
#define AIPS_PACRJ_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
 
#define AIPS_PACRJ_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRJ_TP0_SHIFT   (28U)
 
#define AIPS_PACRJ_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
 
#define AIPS_PACRJ_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRJ_WP0_SHIFT   (29U)
 
#define AIPS_PACRJ_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
 
#define AIPS_PACRJ_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRJ_SP0_SHIFT   (30U)
 
#define AIPS_PACRJ_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
 
#define AIPS_PACRJ_TP7_MASK   0x1u
 
#define AIPS_PACRJ_TP7_SHIFT   0
 
#define AIPS_PACRJ_WP7_MASK   0x2u
 
#define AIPS_PACRJ_WP7_SHIFT   1
 
#define AIPS_PACRJ_SP7_MASK   0x4u
 
#define AIPS_PACRJ_SP7_SHIFT   2
 
#define AIPS_PACRJ_TP6_MASK   0x10u
 
#define AIPS_PACRJ_TP6_SHIFT   4
 
#define AIPS_PACRJ_WP6_MASK   0x20u
 
#define AIPS_PACRJ_WP6_SHIFT   5
 
#define AIPS_PACRJ_SP6_MASK   0x40u
 
#define AIPS_PACRJ_SP6_SHIFT   6
 
#define AIPS_PACRJ_TP5_MASK   0x100u
 
#define AIPS_PACRJ_TP5_SHIFT   8
 
#define AIPS_PACRJ_WP5_MASK   0x200u
 
#define AIPS_PACRJ_WP5_SHIFT   9
 
#define AIPS_PACRJ_SP5_MASK   0x400u
 
#define AIPS_PACRJ_SP5_SHIFT   10
 
#define AIPS_PACRJ_TP4_MASK   0x1000u
 
#define AIPS_PACRJ_TP4_SHIFT   12
 
#define AIPS_PACRJ_WP4_MASK   0x2000u
 
#define AIPS_PACRJ_WP4_SHIFT   13
 
#define AIPS_PACRJ_SP4_MASK   0x4000u
 
#define AIPS_PACRJ_SP4_SHIFT   14
 
#define AIPS_PACRJ_TP3_MASK   0x10000u
 
#define AIPS_PACRJ_TP3_SHIFT   16
 
#define AIPS_PACRJ_WP3_MASK   0x20000u
 
#define AIPS_PACRJ_WP3_SHIFT   17
 
#define AIPS_PACRJ_SP3_MASK   0x40000u
 
#define AIPS_PACRJ_SP3_SHIFT   18
 
#define AIPS_PACRJ_TP2_MASK   0x100000u
 
#define AIPS_PACRJ_TP2_SHIFT   20
 
#define AIPS_PACRJ_WP2_MASK   0x200000u
 
#define AIPS_PACRJ_WP2_SHIFT   21
 
#define AIPS_PACRJ_SP2_MASK   0x400000u
 
#define AIPS_PACRJ_SP2_SHIFT   22
 
#define AIPS_PACRJ_TP1_MASK   0x1000000u
 
#define AIPS_PACRJ_TP1_SHIFT   24
 
#define AIPS_PACRJ_WP1_MASK   0x2000000u
 
#define AIPS_PACRJ_WP1_SHIFT   25
 
#define AIPS_PACRJ_SP1_MASK   0x4000000u
 
#define AIPS_PACRJ_SP1_SHIFT   26
 
#define AIPS_PACRJ_TP0_MASK   0x10000000u
 
#define AIPS_PACRJ_TP0_SHIFT   28
 
#define AIPS_PACRJ_WP0_MASK   0x20000000u
 
#define AIPS_PACRJ_WP0_SHIFT   29
 
#define AIPS_PACRJ_SP0_MASK   0x40000000u
 
#define AIPS_PACRJ_SP0_SHIFT   30
 
#define AIPS_PACRJ_TP7_MASK   (0x1U)
 
#define AIPS_PACRJ_TP7_SHIFT   (0U)
 
#define AIPS_PACRJ_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
 
#define AIPS_PACRJ_WP7_MASK   (0x2U)
 
#define AIPS_PACRJ_WP7_SHIFT   (1U)
 
#define AIPS_PACRJ_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
 
#define AIPS_PACRJ_SP7_MASK   (0x4U)
 
#define AIPS_PACRJ_SP7_SHIFT   (2U)
 
#define AIPS_PACRJ_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
 
#define AIPS_PACRJ_TP6_MASK   (0x10U)
 
#define AIPS_PACRJ_TP6_SHIFT   (4U)
 
#define AIPS_PACRJ_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
 
#define AIPS_PACRJ_WP6_MASK   (0x20U)
 
#define AIPS_PACRJ_WP6_SHIFT   (5U)
 
#define AIPS_PACRJ_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
 
#define AIPS_PACRJ_SP6_MASK   (0x40U)
 
#define AIPS_PACRJ_SP6_SHIFT   (6U)
 
#define AIPS_PACRJ_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
 
#define AIPS_PACRJ_TP5_MASK   (0x100U)
 
#define AIPS_PACRJ_TP5_SHIFT   (8U)
 
#define AIPS_PACRJ_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
 
#define AIPS_PACRJ_WP5_MASK   (0x200U)
 
#define AIPS_PACRJ_WP5_SHIFT   (9U)
 
#define AIPS_PACRJ_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
 
#define AIPS_PACRJ_SP5_MASK   (0x400U)
 
#define AIPS_PACRJ_SP5_SHIFT   (10U)
 
#define AIPS_PACRJ_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
 
#define AIPS_PACRJ_TP4_MASK   (0x1000U)
 
#define AIPS_PACRJ_TP4_SHIFT   (12U)
 
#define AIPS_PACRJ_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
 
#define AIPS_PACRJ_WP4_MASK   (0x2000U)
 
#define AIPS_PACRJ_WP4_SHIFT   (13U)
 
#define AIPS_PACRJ_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
 
#define AIPS_PACRJ_SP4_MASK   (0x4000U)
 
#define AIPS_PACRJ_SP4_SHIFT   (14U)
 
#define AIPS_PACRJ_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
 
#define AIPS_PACRJ_TP3_MASK   (0x10000U)
 
#define AIPS_PACRJ_TP3_SHIFT   (16U)
 
#define AIPS_PACRJ_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
 
#define AIPS_PACRJ_WP3_MASK   (0x20000U)
 
#define AIPS_PACRJ_WP3_SHIFT   (17U)
 
#define AIPS_PACRJ_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
 
#define AIPS_PACRJ_SP3_MASK   (0x40000U)
 
#define AIPS_PACRJ_SP3_SHIFT   (18U)
 
#define AIPS_PACRJ_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
 
#define AIPS_PACRJ_TP2_MASK   (0x100000U)
 
#define AIPS_PACRJ_TP2_SHIFT   (20U)
 
#define AIPS_PACRJ_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
 
#define AIPS_PACRJ_WP2_MASK   (0x200000U)
 
#define AIPS_PACRJ_WP2_SHIFT   (21U)
 
#define AIPS_PACRJ_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
 
#define AIPS_PACRJ_SP2_MASK   (0x400000U)
 
#define AIPS_PACRJ_SP2_SHIFT   (22U)
 
#define AIPS_PACRJ_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
 
#define AIPS_PACRJ_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRJ_TP1_SHIFT   (24U)
 
#define AIPS_PACRJ_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
 
#define AIPS_PACRJ_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRJ_WP1_SHIFT   (25U)
 
#define AIPS_PACRJ_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
 
#define AIPS_PACRJ_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRJ_SP1_SHIFT   (26U)
 
#define AIPS_PACRJ_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
 
#define AIPS_PACRJ_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRJ_TP0_SHIFT   (28U)
 
#define AIPS_PACRJ_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
 
#define AIPS_PACRJ_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRJ_WP0_SHIFT   (29U)
 
#define AIPS_PACRJ_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
 
#define AIPS_PACRJ_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRJ_SP0_SHIFT   (30U)
 
#define AIPS_PACRJ_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
 
#define AIPS_PACRJ_TP7_MASK   (0x1U)
 
#define AIPS_PACRJ_TP7_SHIFT   (0U)
 
#define AIPS_PACRJ_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
 
#define AIPS_PACRJ_WP7_MASK   (0x2U)
 
#define AIPS_PACRJ_WP7_SHIFT   (1U)
 
#define AIPS_PACRJ_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
 
#define AIPS_PACRJ_SP7_MASK   (0x4U)
 
#define AIPS_PACRJ_SP7_SHIFT   (2U)
 
#define AIPS_PACRJ_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
 
#define AIPS_PACRJ_TP6_MASK   (0x10U)
 
#define AIPS_PACRJ_TP6_SHIFT   (4U)
 
#define AIPS_PACRJ_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
 
#define AIPS_PACRJ_WP6_MASK   (0x20U)
 
#define AIPS_PACRJ_WP6_SHIFT   (5U)
 
#define AIPS_PACRJ_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
 
#define AIPS_PACRJ_SP6_MASK   (0x40U)
 
#define AIPS_PACRJ_SP6_SHIFT   (6U)
 
#define AIPS_PACRJ_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
 
#define AIPS_PACRJ_TP5_MASK   (0x100U)
 
#define AIPS_PACRJ_TP5_SHIFT   (8U)
 
#define AIPS_PACRJ_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
 
#define AIPS_PACRJ_WP5_MASK   (0x200U)
 
#define AIPS_PACRJ_WP5_SHIFT   (9U)
 
#define AIPS_PACRJ_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
 
#define AIPS_PACRJ_SP5_MASK   (0x400U)
 
#define AIPS_PACRJ_SP5_SHIFT   (10U)
 
#define AIPS_PACRJ_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
 
#define AIPS_PACRJ_TP4_MASK   (0x1000U)
 
#define AIPS_PACRJ_TP4_SHIFT   (12U)
 
#define AIPS_PACRJ_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
 
#define AIPS_PACRJ_WP4_MASK   (0x2000U)
 
#define AIPS_PACRJ_WP4_SHIFT   (13U)
 
#define AIPS_PACRJ_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
 
#define AIPS_PACRJ_SP4_MASK   (0x4000U)
 
#define AIPS_PACRJ_SP4_SHIFT   (14U)
 
#define AIPS_PACRJ_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
 
#define AIPS_PACRJ_TP3_MASK   (0x10000U)
 
#define AIPS_PACRJ_TP3_SHIFT   (16U)
 
#define AIPS_PACRJ_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
 
#define AIPS_PACRJ_WP3_MASK   (0x20000U)
 
#define AIPS_PACRJ_WP3_SHIFT   (17U)
 
#define AIPS_PACRJ_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
 
#define AIPS_PACRJ_SP3_MASK   (0x40000U)
 
#define AIPS_PACRJ_SP3_SHIFT   (18U)
 
#define AIPS_PACRJ_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
 
#define AIPS_PACRJ_TP2_MASK   (0x100000U)
 
#define AIPS_PACRJ_TP2_SHIFT   (20U)
 
#define AIPS_PACRJ_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
 
#define AIPS_PACRJ_WP2_MASK   (0x200000U)
 
#define AIPS_PACRJ_WP2_SHIFT   (21U)
 
#define AIPS_PACRJ_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
 
#define AIPS_PACRJ_SP2_MASK   (0x400000U)
 
#define AIPS_PACRJ_SP2_SHIFT   (22U)
 
#define AIPS_PACRJ_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
 
#define AIPS_PACRJ_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRJ_TP1_SHIFT   (24U)
 
#define AIPS_PACRJ_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
 
#define AIPS_PACRJ_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRJ_WP1_SHIFT   (25U)
 
#define AIPS_PACRJ_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
 
#define AIPS_PACRJ_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRJ_SP1_SHIFT   (26U)
 
#define AIPS_PACRJ_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
 
#define AIPS_PACRJ_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRJ_TP0_SHIFT   (28U)
 
#define AIPS_PACRJ_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
 
#define AIPS_PACRJ_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRJ_WP0_SHIFT   (29U)
 
#define AIPS_PACRJ_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
 
#define AIPS_PACRJ_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRJ_SP0_SHIFT   (30U)
 
#define AIPS_PACRJ_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
 
#define AIPS_PACRJ_TP7_MASK   (0x1U)
 
#define AIPS_PACRJ_TP7_SHIFT   (0U)
 
#define AIPS_PACRJ_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
 
#define AIPS_PACRJ_WP7_MASK   (0x2U)
 
#define AIPS_PACRJ_WP7_SHIFT   (1U)
 
#define AIPS_PACRJ_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
 
#define AIPS_PACRJ_SP7_MASK   (0x4U)
 
#define AIPS_PACRJ_SP7_SHIFT   (2U)
 
#define AIPS_PACRJ_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
 
#define AIPS_PACRJ_TP6_MASK   (0x10U)
 
#define AIPS_PACRJ_TP6_SHIFT   (4U)
 
#define AIPS_PACRJ_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
 
#define AIPS_PACRJ_WP6_MASK   (0x20U)
 
#define AIPS_PACRJ_WP6_SHIFT   (5U)
 
#define AIPS_PACRJ_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
 
#define AIPS_PACRJ_SP6_MASK   (0x40U)
 
#define AIPS_PACRJ_SP6_SHIFT   (6U)
 
#define AIPS_PACRJ_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
 
#define AIPS_PACRJ_TP5_MASK   (0x100U)
 
#define AIPS_PACRJ_TP5_SHIFT   (8U)
 
#define AIPS_PACRJ_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
 
#define AIPS_PACRJ_WP5_MASK   (0x200U)
 
#define AIPS_PACRJ_WP5_SHIFT   (9U)
 
#define AIPS_PACRJ_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
 
#define AIPS_PACRJ_SP5_MASK   (0x400U)
 
#define AIPS_PACRJ_SP5_SHIFT   (10U)
 
#define AIPS_PACRJ_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
 
#define AIPS_PACRJ_TP4_MASK   (0x1000U)
 
#define AIPS_PACRJ_TP4_SHIFT   (12U)
 
#define AIPS_PACRJ_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
 
#define AIPS_PACRJ_WP4_MASK   (0x2000U)
 
#define AIPS_PACRJ_WP4_SHIFT   (13U)
 
#define AIPS_PACRJ_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
 
#define AIPS_PACRJ_SP4_MASK   (0x4000U)
 
#define AIPS_PACRJ_SP4_SHIFT   (14U)
 
#define AIPS_PACRJ_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
 
#define AIPS_PACRJ_TP3_MASK   (0x10000U)
 
#define AIPS_PACRJ_TP3_SHIFT   (16U)
 
#define AIPS_PACRJ_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
 
#define AIPS_PACRJ_WP3_MASK   (0x20000U)
 
#define AIPS_PACRJ_WP3_SHIFT   (17U)
 
#define AIPS_PACRJ_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
 
#define AIPS_PACRJ_SP3_MASK   (0x40000U)
 
#define AIPS_PACRJ_SP3_SHIFT   (18U)
 
#define AIPS_PACRJ_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
 
#define AIPS_PACRJ_TP2_MASK   (0x100000U)
 
#define AIPS_PACRJ_TP2_SHIFT   (20U)
 
#define AIPS_PACRJ_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
 
#define AIPS_PACRJ_WP2_MASK   (0x200000U)
 
#define AIPS_PACRJ_WP2_SHIFT   (21U)
 
#define AIPS_PACRJ_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
 
#define AIPS_PACRJ_SP2_MASK   (0x400000U)
 
#define AIPS_PACRJ_SP2_SHIFT   (22U)
 
#define AIPS_PACRJ_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
 
#define AIPS_PACRJ_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRJ_TP1_SHIFT   (24U)
 
#define AIPS_PACRJ_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
 
#define AIPS_PACRJ_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRJ_WP1_SHIFT   (25U)
 
#define AIPS_PACRJ_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
 
#define AIPS_PACRJ_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRJ_SP1_SHIFT   (26U)
 
#define AIPS_PACRJ_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
 
#define AIPS_PACRJ_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRJ_TP0_SHIFT   (28U)
 
#define AIPS_PACRJ_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
 
#define AIPS_PACRJ_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRJ_WP0_SHIFT   (29U)
 
#define AIPS_PACRJ_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
 
#define AIPS_PACRJ_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRJ_SP0_SHIFT   (30U)
 
#define AIPS_PACRJ_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
 
#define AIPS_PACRJ_TP7_MASK   (0x1U)
 
#define AIPS_PACRJ_TP7_SHIFT   (0U)
 
#define AIPS_PACRJ_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
 
#define AIPS_PACRJ_WP7_MASK   (0x2U)
 
#define AIPS_PACRJ_WP7_SHIFT   (1U)
 
#define AIPS_PACRJ_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
 
#define AIPS_PACRJ_SP7_MASK   (0x4U)
 
#define AIPS_PACRJ_SP7_SHIFT   (2U)
 
#define AIPS_PACRJ_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
 
#define AIPS_PACRJ_TP6_MASK   (0x10U)
 
#define AIPS_PACRJ_TP6_SHIFT   (4U)
 
#define AIPS_PACRJ_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
 
#define AIPS_PACRJ_WP6_MASK   (0x20U)
 
#define AIPS_PACRJ_WP6_SHIFT   (5U)
 
#define AIPS_PACRJ_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
 
#define AIPS_PACRJ_SP6_MASK   (0x40U)
 
#define AIPS_PACRJ_SP6_SHIFT   (6U)
 
#define AIPS_PACRJ_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
 
#define AIPS_PACRJ_TP5_MASK   (0x100U)
 
#define AIPS_PACRJ_TP5_SHIFT   (8U)
 
#define AIPS_PACRJ_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
 
#define AIPS_PACRJ_WP5_MASK   (0x200U)
 
#define AIPS_PACRJ_WP5_SHIFT   (9U)
 
#define AIPS_PACRJ_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
 
#define AIPS_PACRJ_SP5_MASK   (0x400U)
 
#define AIPS_PACRJ_SP5_SHIFT   (10U)
 
#define AIPS_PACRJ_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
 
#define AIPS_PACRJ_TP4_MASK   (0x1000U)
 
#define AIPS_PACRJ_TP4_SHIFT   (12U)
 
#define AIPS_PACRJ_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
 
#define AIPS_PACRJ_WP4_MASK   (0x2000U)
 
#define AIPS_PACRJ_WP4_SHIFT   (13U)
 
#define AIPS_PACRJ_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
 
#define AIPS_PACRJ_SP4_MASK   (0x4000U)
 
#define AIPS_PACRJ_SP4_SHIFT   (14U)
 
#define AIPS_PACRJ_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
 
#define AIPS_PACRJ_TP3_MASK   (0x10000U)
 
#define AIPS_PACRJ_TP3_SHIFT   (16U)
 
#define AIPS_PACRJ_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
 
#define AIPS_PACRJ_WP3_MASK   (0x20000U)
 
#define AIPS_PACRJ_WP3_SHIFT   (17U)
 
#define AIPS_PACRJ_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
 
#define AIPS_PACRJ_SP3_MASK   (0x40000U)
 
#define AIPS_PACRJ_SP3_SHIFT   (18U)
 
#define AIPS_PACRJ_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
 
#define AIPS_PACRJ_TP2_MASK   (0x100000U)
 
#define AIPS_PACRJ_TP2_SHIFT   (20U)
 
#define AIPS_PACRJ_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
 
#define AIPS_PACRJ_WP2_MASK   (0x200000U)
 
#define AIPS_PACRJ_WP2_SHIFT   (21U)
 
#define AIPS_PACRJ_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
 
#define AIPS_PACRJ_SP2_MASK   (0x400000U)
 
#define AIPS_PACRJ_SP2_SHIFT   (22U)
 
#define AIPS_PACRJ_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
 
#define AIPS_PACRJ_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRJ_TP1_SHIFT   (24U)
 
#define AIPS_PACRJ_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
 
#define AIPS_PACRJ_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRJ_WP1_SHIFT   (25U)
 
#define AIPS_PACRJ_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
 
#define AIPS_PACRJ_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRJ_SP1_SHIFT   (26U)
 
#define AIPS_PACRJ_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
 
#define AIPS_PACRJ_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRJ_TP0_SHIFT   (28U)
 
#define AIPS_PACRJ_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
 
#define AIPS_PACRJ_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRJ_WP0_SHIFT   (29U)
 
#define AIPS_PACRJ_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
 
#define AIPS_PACRJ_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRJ_SP0_SHIFT   (30U)
 
#define AIPS_PACRJ_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
 

PACRK - Peripheral Access Control Register

#define AIPS_PACRK_TP7_MASK   (0x1U)
 
#define AIPS_PACRK_TP7_SHIFT   (0U)
 
#define AIPS_PACRK_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
 
#define AIPS_PACRK_WP7_MASK   (0x2U)
 
#define AIPS_PACRK_WP7_SHIFT   (1U)
 
#define AIPS_PACRK_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
 
#define AIPS_PACRK_SP7_MASK   (0x4U)
 
#define AIPS_PACRK_SP7_SHIFT   (2U)
 
#define AIPS_PACRK_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
 
#define AIPS_PACRK_TP6_MASK   (0x10U)
 
#define AIPS_PACRK_TP6_SHIFT   (4U)
 
#define AIPS_PACRK_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
 
#define AIPS_PACRK_WP6_MASK   (0x20U)
 
#define AIPS_PACRK_WP6_SHIFT   (5U)
 
#define AIPS_PACRK_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
 
#define AIPS_PACRK_SP6_MASK   (0x40U)
 
#define AIPS_PACRK_SP6_SHIFT   (6U)
 
#define AIPS_PACRK_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
 
#define AIPS_PACRK_TP5_MASK   (0x100U)
 
#define AIPS_PACRK_TP5_SHIFT   (8U)
 
#define AIPS_PACRK_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
 
#define AIPS_PACRK_WP5_MASK   (0x200U)
 
#define AIPS_PACRK_WP5_SHIFT   (9U)
 
#define AIPS_PACRK_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
 
#define AIPS_PACRK_SP5_MASK   (0x400U)
 
#define AIPS_PACRK_SP5_SHIFT   (10U)
 
#define AIPS_PACRK_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
 
#define AIPS_PACRK_TP4_MASK   (0x1000U)
 
#define AIPS_PACRK_TP4_SHIFT   (12U)
 
#define AIPS_PACRK_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
 
#define AIPS_PACRK_WP4_MASK   (0x2000U)
 
#define AIPS_PACRK_WP4_SHIFT   (13U)
 
#define AIPS_PACRK_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
 
#define AIPS_PACRK_SP4_MASK   (0x4000U)
 
#define AIPS_PACRK_SP4_SHIFT   (14U)
 
#define AIPS_PACRK_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
 
#define AIPS_PACRK_TP3_MASK   (0x10000U)
 
#define AIPS_PACRK_TP3_SHIFT   (16U)
 
#define AIPS_PACRK_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
 
#define AIPS_PACRK_WP3_MASK   (0x20000U)
 
#define AIPS_PACRK_WP3_SHIFT   (17U)
 
#define AIPS_PACRK_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
 
#define AIPS_PACRK_SP3_MASK   (0x40000U)
 
#define AIPS_PACRK_SP3_SHIFT   (18U)
 
#define AIPS_PACRK_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
 
#define AIPS_PACRK_TP2_MASK   (0x100000U)
 
#define AIPS_PACRK_TP2_SHIFT   (20U)
 
#define AIPS_PACRK_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
 
#define AIPS_PACRK_WP2_MASK   (0x200000U)
 
#define AIPS_PACRK_WP2_SHIFT   (21U)
 
#define AIPS_PACRK_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
 
#define AIPS_PACRK_SP2_MASK   (0x400000U)
 
#define AIPS_PACRK_SP2_SHIFT   (22U)
 
#define AIPS_PACRK_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
 
#define AIPS_PACRK_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRK_TP1_SHIFT   (24U)
 
#define AIPS_PACRK_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
 
#define AIPS_PACRK_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRK_WP1_SHIFT   (25U)
 
#define AIPS_PACRK_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
 
#define AIPS_PACRK_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRK_SP1_SHIFT   (26U)
 
#define AIPS_PACRK_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
 
#define AIPS_PACRK_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRK_TP0_SHIFT   (28U)
 
#define AIPS_PACRK_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
 
#define AIPS_PACRK_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRK_WP0_SHIFT   (29U)
 
#define AIPS_PACRK_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
 
#define AIPS_PACRK_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRK_SP0_SHIFT   (30U)
 
#define AIPS_PACRK_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
 
#define AIPS_PACRK_TP7_MASK   0x1u
 
#define AIPS_PACRK_TP7_SHIFT   0
 
#define AIPS_PACRK_WP7_MASK   0x2u
 
#define AIPS_PACRK_WP7_SHIFT   1
 
#define AIPS_PACRK_SP7_MASK   0x4u
 
#define AIPS_PACRK_SP7_SHIFT   2
 
#define AIPS_PACRK_TP6_MASK   0x10u
 
#define AIPS_PACRK_TP6_SHIFT   4
 
#define AIPS_PACRK_WP6_MASK   0x20u
 
#define AIPS_PACRK_WP6_SHIFT   5
 
#define AIPS_PACRK_SP6_MASK   0x40u
 
#define AIPS_PACRK_SP6_SHIFT   6
 
#define AIPS_PACRK_TP5_MASK   0x100u
 
#define AIPS_PACRK_TP5_SHIFT   8
 
#define AIPS_PACRK_WP5_MASK   0x200u
 
#define AIPS_PACRK_WP5_SHIFT   9
 
#define AIPS_PACRK_SP5_MASK   0x400u
 
#define AIPS_PACRK_SP5_SHIFT   10
 
#define AIPS_PACRK_TP4_MASK   0x1000u
 
#define AIPS_PACRK_TP4_SHIFT   12
 
#define AIPS_PACRK_WP4_MASK   0x2000u
 
#define AIPS_PACRK_WP4_SHIFT   13
 
#define AIPS_PACRK_SP4_MASK   0x4000u
 
#define AIPS_PACRK_SP4_SHIFT   14
 
#define AIPS_PACRK_TP3_MASK   0x10000u
 
#define AIPS_PACRK_TP3_SHIFT   16
 
#define AIPS_PACRK_WP3_MASK   0x20000u
 
#define AIPS_PACRK_WP3_SHIFT   17
 
#define AIPS_PACRK_SP3_MASK   0x40000u
 
#define AIPS_PACRK_SP3_SHIFT   18
 
#define AIPS_PACRK_TP2_MASK   0x100000u
 
#define AIPS_PACRK_TP2_SHIFT   20
 
#define AIPS_PACRK_WP2_MASK   0x200000u
 
#define AIPS_PACRK_WP2_SHIFT   21
 
#define AIPS_PACRK_SP2_MASK   0x400000u
 
#define AIPS_PACRK_SP2_SHIFT   22
 
#define AIPS_PACRK_TP1_MASK   0x1000000u
 
#define AIPS_PACRK_TP1_SHIFT   24
 
#define AIPS_PACRK_WP1_MASK   0x2000000u
 
#define AIPS_PACRK_WP1_SHIFT   25
 
#define AIPS_PACRK_SP1_MASK   0x4000000u
 
#define AIPS_PACRK_SP1_SHIFT   26
 
#define AIPS_PACRK_TP0_MASK   0x10000000u
 
#define AIPS_PACRK_TP0_SHIFT   28
 
#define AIPS_PACRK_WP0_MASK   0x20000000u
 
#define AIPS_PACRK_WP0_SHIFT   29
 
#define AIPS_PACRK_SP0_MASK   0x40000000u
 
#define AIPS_PACRK_SP0_SHIFT   30
 
#define AIPS_PACRK_TP7_MASK   (0x1U)
 
#define AIPS_PACRK_TP7_SHIFT   (0U)
 
#define AIPS_PACRK_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
 
#define AIPS_PACRK_WP7_MASK   (0x2U)
 
#define AIPS_PACRK_WP7_SHIFT   (1U)
 
#define AIPS_PACRK_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
 
#define AIPS_PACRK_SP7_MASK   (0x4U)
 
#define AIPS_PACRK_SP7_SHIFT   (2U)
 
#define AIPS_PACRK_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
 
#define AIPS_PACRK_TP6_MASK   (0x10U)
 
#define AIPS_PACRK_TP6_SHIFT   (4U)
 
#define AIPS_PACRK_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
 
#define AIPS_PACRK_WP6_MASK   (0x20U)
 
#define AIPS_PACRK_WP6_SHIFT   (5U)
 
#define AIPS_PACRK_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
 
#define AIPS_PACRK_SP6_MASK   (0x40U)
 
#define AIPS_PACRK_SP6_SHIFT   (6U)
 
#define AIPS_PACRK_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
 
#define AIPS_PACRK_TP5_MASK   (0x100U)
 
#define AIPS_PACRK_TP5_SHIFT   (8U)
 
#define AIPS_PACRK_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
 
#define AIPS_PACRK_WP5_MASK   (0x200U)
 
#define AIPS_PACRK_WP5_SHIFT   (9U)
 
#define AIPS_PACRK_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
 
#define AIPS_PACRK_SP5_MASK   (0x400U)
 
#define AIPS_PACRK_SP5_SHIFT   (10U)
 
#define AIPS_PACRK_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
 
#define AIPS_PACRK_TP4_MASK   (0x1000U)
 
#define AIPS_PACRK_TP4_SHIFT   (12U)
 
#define AIPS_PACRK_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
 
#define AIPS_PACRK_WP4_MASK   (0x2000U)
 
#define AIPS_PACRK_WP4_SHIFT   (13U)
 
#define AIPS_PACRK_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
 
#define AIPS_PACRK_SP4_MASK   (0x4000U)
 
#define AIPS_PACRK_SP4_SHIFT   (14U)
 
#define AIPS_PACRK_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
 
#define AIPS_PACRK_TP3_MASK   (0x10000U)
 
#define AIPS_PACRK_TP3_SHIFT   (16U)
 
#define AIPS_PACRK_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
 
#define AIPS_PACRK_WP3_MASK   (0x20000U)
 
#define AIPS_PACRK_WP3_SHIFT   (17U)
 
#define AIPS_PACRK_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
 
#define AIPS_PACRK_SP3_MASK   (0x40000U)
 
#define AIPS_PACRK_SP3_SHIFT   (18U)
 
#define AIPS_PACRK_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
 
#define AIPS_PACRK_TP2_MASK   (0x100000U)
 
#define AIPS_PACRK_TP2_SHIFT   (20U)
 
#define AIPS_PACRK_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
 
#define AIPS_PACRK_WP2_MASK   (0x200000U)
 
#define AIPS_PACRK_WP2_SHIFT   (21U)
 
#define AIPS_PACRK_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
 
#define AIPS_PACRK_SP2_MASK   (0x400000U)
 
#define AIPS_PACRK_SP2_SHIFT   (22U)
 
#define AIPS_PACRK_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
 
#define AIPS_PACRK_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRK_TP1_SHIFT   (24U)
 
#define AIPS_PACRK_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
 
#define AIPS_PACRK_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRK_WP1_SHIFT   (25U)
 
#define AIPS_PACRK_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
 
#define AIPS_PACRK_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRK_SP1_SHIFT   (26U)
 
#define AIPS_PACRK_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
 
#define AIPS_PACRK_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRK_TP0_SHIFT   (28U)
 
#define AIPS_PACRK_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
 
#define AIPS_PACRK_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRK_WP0_SHIFT   (29U)
 
#define AIPS_PACRK_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
 
#define AIPS_PACRK_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRK_SP0_SHIFT   (30U)
 
#define AIPS_PACRK_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
 
#define AIPS_PACRK_TP7_MASK   (0x1U)
 
#define AIPS_PACRK_TP7_SHIFT   (0U)
 
#define AIPS_PACRK_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
 
#define AIPS_PACRK_WP7_MASK   (0x2U)
 
#define AIPS_PACRK_WP7_SHIFT   (1U)
 
#define AIPS_PACRK_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
 
#define AIPS_PACRK_SP7_MASK   (0x4U)
 
#define AIPS_PACRK_SP7_SHIFT   (2U)
 
#define AIPS_PACRK_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
 
#define AIPS_PACRK_TP6_MASK   (0x10U)
 
#define AIPS_PACRK_TP6_SHIFT   (4U)
 
#define AIPS_PACRK_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
 
#define AIPS_PACRK_WP6_MASK   (0x20U)
 
#define AIPS_PACRK_WP6_SHIFT   (5U)
 
#define AIPS_PACRK_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
 
#define AIPS_PACRK_SP6_MASK   (0x40U)
 
#define AIPS_PACRK_SP6_SHIFT   (6U)
 
#define AIPS_PACRK_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
 
#define AIPS_PACRK_TP5_MASK   (0x100U)
 
#define AIPS_PACRK_TP5_SHIFT   (8U)
 
#define AIPS_PACRK_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
 
#define AIPS_PACRK_WP5_MASK   (0x200U)
 
#define AIPS_PACRK_WP5_SHIFT   (9U)
 
#define AIPS_PACRK_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
 
#define AIPS_PACRK_SP5_MASK   (0x400U)
 
#define AIPS_PACRK_SP5_SHIFT   (10U)
 
#define AIPS_PACRK_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
 
#define AIPS_PACRK_TP4_MASK   (0x1000U)
 
#define AIPS_PACRK_TP4_SHIFT   (12U)
 
#define AIPS_PACRK_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
 
#define AIPS_PACRK_WP4_MASK   (0x2000U)
 
#define AIPS_PACRK_WP4_SHIFT   (13U)
 
#define AIPS_PACRK_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
 
#define AIPS_PACRK_SP4_MASK   (0x4000U)
 
#define AIPS_PACRK_SP4_SHIFT   (14U)
 
#define AIPS_PACRK_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
 
#define AIPS_PACRK_TP3_MASK   (0x10000U)
 
#define AIPS_PACRK_TP3_SHIFT   (16U)
 
#define AIPS_PACRK_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
 
#define AIPS_PACRK_WP3_MASK   (0x20000U)
 
#define AIPS_PACRK_WP3_SHIFT   (17U)
 
#define AIPS_PACRK_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
 
#define AIPS_PACRK_SP3_MASK   (0x40000U)
 
#define AIPS_PACRK_SP3_SHIFT   (18U)
 
#define AIPS_PACRK_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
 
#define AIPS_PACRK_TP2_MASK   (0x100000U)
 
#define AIPS_PACRK_TP2_SHIFT   (20U)
 
#define AIPS_PACRK_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
 
#define AIPS_PACRK_WP2_MASK   (0x200000U)
 
#define AIPS_PACRK_WP2_SHIFT   (21U)
 
#define AIPS_PACRK_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
 
#define AIPS_PACRK_SP2_MASK   (0x400000U)
 
#define AIPS_PACRK_SP2_SHIFT   (22U)
 
#define AIPS_PACRK_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
 
#define AIPS_PACRK_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRK_TP1_SHIFT   (24U)
 
#define AIPS_PACRK_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
 
#define AIPS_PACRK_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRK_WP1_SHIFT   (25U)
 
#define AIPS_PACRK_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
 
#define AIPS_PACRK_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRK_SP1_SHIFT   (26U)
 
#define AIPS_PACRK_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
 
#define AIPS_PACRK_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRK_TP0_SHIFT   (28U)
 
#define AIPS_PACRK_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
 
#define AIPS_PACRK_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRK_WP0_SHIFT   (29U)
 
#define AIPS_PACRK_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
 
#define AIPS_PACRK_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRK_SP0_SHIFT   (30U)
 
#define AIPS_PACRK_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
 
#define AIPS_PACRK_TP7_MASK   (0x1U)
 
#define AIPS_PACRK_TP7_SHIFT   (0U)
 
#define AIPS_PACRK_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
 
#define AIPS_PACRK_WP7_MASK   (0x2U)
 
#define AIPS_PACRK_WP7_SHIFT   (1U)
 
#define AIPS_PACRK_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
 
#define AIPS_PACRK_SP7_MASK   (0x4U)
 
#define AIPS_PACRK_SP7_SHIFT   (2U)
 
#define AIPS_PACRK_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
 
#define AIPS_PACRK_TP6_MASK   (0x10U)
 
#define AIPS_PACRK_TP6_SHIFT   (4U)
 
#define AIPS_PACRK_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
 
#define AIPS_PACRK_WP6_MASK   (0x20U)
 
#define AIPS_PACRK_WP6_SHIFT   (5U)
 
#define AIPS_PACRK_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
 
#define AIPS_PACRK_SP6_MASK   (0x40U)
 
#define AIPS_PACRK_SP6_SHIFT   (6U)
 
#define AIPS_PACRK_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
 
#define AIPS_PACRK_TP5_MASK   (0x100U)
 
#define AIPS_PACRK_TP5_SHIFT   (8U)
 
#define AIPS_PACRK_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
 
#define AIPS_PACRK_WP5_MASK   (0x200U)
 
#define AIPS_PACRK_WP5_SHIFT   (9U)
 
#define AIPS_PACRK_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
 
#define AIPS_PACRK_SP5_MASK   (0x400U)
 
#define AIPS_PACRK_SP5_SHIFT   (10U)
 
#define AIPS_PACRK_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
 
#define AIPS_PACRK_TP4_MASK   (0x1000U)
 
#define AIPS_PACRK_TP4_SHIFT   (12U)
 
#define AIPS_PACRK_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
 
#define AIPS_PACRK_WP4_MASK   (0x2000U)
 
#define AIPS_PACRK_WP4_SHIFT   (13U)
 
#define AIPS_PACRK_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
 
#define AIPS_PACRK_SP4_MASK   (0x4000U)
 
#define AIPS_PACRK_SP4_SHIFT   (14U)
 
#define AIPS_PACRK_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
 
#define AIPS_PACRK_TP3_MASK   (0x10000U)
 
#define AIPS_PACRK_TP3_SHIFT   (16U)
 
#define AIPS_PACRK_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
 
#define AIPS_PACRK_WP3_MASK   (0x20000U)
 
#define AIPS_PACRK_WP3_SHIFT   (17U)
 
#define AIPS_PACRK_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
 
#define AIPS_PACRK_SP3_MASK   (0x40000U)
 
#define AIPS_PACRK_SP3_SHIFT   (18U)
 
#define AIPS_PACRK_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
 
#define AIPS_PACRK_TP2_MASK   (0x100000U)
 
#define AIPS_PACRK_TP2_SHIFT   (20U)
 
#define AIPS_PACRK_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
 
#define AIPS_PACRK_WP2_MASK   (0x200000U)
 
#define AIPS_PACRK_WP2_SHIFT   (21U)
 
#define AIPS_PACRK_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
 
#define AIPS_PACRK_SP2_MASK   (0x400000U)
 
#define AIPS_PACRK_SP2_SHIFT   (22U)
 
#define AIPS_PACRK_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
 
#define AIPS_PACRK_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRK_TP1_SHIFT   (24U)
 
#define AIPS_PACRK_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
 
#define AIPS_PACRK_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRK_WP1_SHIFT   (25U)
 
#define AIPS_PACRK_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
 
#define AIPS_PACRK_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRK_SP1_SHIFT   (26U)
 
#define AIPS_PACRK_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
 
#define AIPS_PACRK_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRK_TP0_SHIFT   (28U)
 
#define AIPS_PACRK_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
 
#define AIPS_PACRK_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRK_WP0_SHIFT   (29U)
 
#define AIPS_PACRK_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
 
#define AIPS_PACRK_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRK_SP0_SHIFT   (30U)
 
#define AIPS_PACRK_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
 
#define AIPS_PACRK_TP7_MASK   (0x1U)
 
#define AIPS_PACRK_TP7_SHIFT   (0U)
 
#define AIPS_PACRK_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
 
#define AIPS_PACRK_WP7_MASK   (0x2U)
 
#define AIPS_PACRK_WP7_SHIFT   (1U)
 
#define AIPS_PACRK_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
 
#define AIPS_PACRK_SP7_MASK   (0x4U)
 
#define AIPS_PACRK_SP7_SHIFT   (2U)
 
#define AIPS_PACRK_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
 
#define AIPS_PACRK_TP6_MASK   (0x10U)
 
#define AIPS_PACRK_TP6_SHIFT   (4U)
 
#define AIPS_PACRK_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
 
#define AIPS_PACRK_WP6_MASK   (0x20U)
 
#define AIPS_PACRK_WP6_SHIFT   (5U)
 
#define AIPS_PACRK_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
 
#define AIPS_PACRK_SP6_MASK   (0x40U)
 
#define AIPS_PACRK_SP6_SHIFT   (6U)
 
#define AIPS_PACRK_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
 
#define AIPS_PACRK_TP5_MASK   (0x100U)
 
#define AIPS_PACRK_TP5_SHIFT   (8U)
 
#define AIPS_PACRK_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
 
#define AIPS_PACRK_WP5_MASK   (0x200U)
 
#define AIPS_PACRK_WP5_SHIFT   (9U)
 
#define AIPS_PACRK_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
 
#define AIPS_PACRK_SP5_MASK   (0x400U)
 
#define AIPS_PACRK_SP5_SHIFT   (10U)
 
#define AIPS_PACRK_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
 
#define AIPS_PACRK_TP4_MASK   (0x1000U)
 
#define AIPS_PACRK_TP4_SHIFT   (12U)
 
#define AIPS_PACRK_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
 
#define AIPS_PACRK_WP4_MASK   (0x2000U)
 
#define AIPS_PACRK_WP4_SHIFT   (13U)
 
#define AIPS_PACRK_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
 
#define AIPS_PACRK_SP4_MASK   (0x4000U)
 
#define AIPS_PACRK_SP4_SHIFT   (14U)
 
#define AIPS_PACRK_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
 
#define AIPS_PACRK_TP3_MASK   (0x10000U)
 
#define AIPS_PACRK_TP3_SHIFT   (16U)
 
#define AIPS_PACRK_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
 
#define AIPS_PACRK_WP3_MASK   (0x20000U)
 
#define AIPS_PACRK_WP3_SHIFT   (17U)
 
#define AIPS_PACRK_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
 
#define AIPS_PACRK_SP3_MASK   (0x40000U)
 
#define AIPS_PACRK_SP3_SHIFT   (18U)
 
#define AIPS_PACRK_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
 
#define AIPS_PACRK_TP2_MASK   (0x100000U)
 
#define AIPS_PACRK_TP2_SHIFT   (20U)
 
#define AIPS_PACRK_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
 
#define AIPS_PACRK_WP2_MASK   (0x200000U)
 
#define AIPS_PACRK_WP2_SHIFT   (21U)
 
#define AIPS_PACRK_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
 
#define AIPS_PACRK_SP2_MASK   (0x400000U)
 
#define AIPS_PACRK_SP2_SHIFT   (22U)
 
#define AIPS_PACRK_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
 
#define AIPS_PACRK_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRK_TP1_SHIFT   (24U)
 
#define AIPS_PACRK_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
 
#define AIPS_PACRK_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRK_WP1_SHIFT   (25U)
 
#define AIPS_PACRK_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
 
#define AIPS_PACRK_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRK_SP1_SHIFT   (26U)
 
#define AIPS_PACRK_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
 
#define AIPS_PACRK_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRK_TP0_SHIFT   (28U)
 
#define AIPS_PACRK_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
 
#define AIPS_PACRK_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRK_WP0_SHIFT   (29U)
 
#define AIPS_PACRK_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
 
#define AIPS_PACRK_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRK_SP0_SHIFT   (30U)
 
#define AIPS_PACRK_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
 

PACRL - Peripheral Access Control Register

#define AIPS_PACRL_TP7_MASK   (0x1U)
 
#define AIPS_PACRL_TP7_SHIFT   (0U)
 
#define AIPS_PACRL_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
 
#define AIPS_PACRL_WP7_MASK   (0x2U)
 
#define AIPS_PACRL_WP7_SHIFT   (1U)
 
#define AIPS_PACRL_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
 
#define AIPS_PACRL_SP7_MASK   (0x4U)
 
#define AIPS_PACRL_SP7_SHIFT   (2U)
 
#define AIPS_PACRL_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
 
#define AIPS_PACRL_TP6_MASK   (0x10U)
 
#define AIPS_PACRL_TP6_SHIFT   (4U)
 
#define AIPS_PACRL_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
 
#define AIPS_PACRL_WP6_MASK   (0x20U)
 
#define AIPS_PACRL_WP6_SHIFT   (5U)
 
#define AIPS_PACRL_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
 
#define AIPS_PACRL_SP6_MASK   (0x40U)
 
#define AIPS_PACRL_SP6_SHIFT   (6U)
 
#define AIPS_PACRL_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
 
#define AIPS_PACRL_TP5_MASK   (0x100U)
 
#define AIPS_PACRL_TP5_SHIFT   (8U)
 
#define AIPS_PACRL_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
 
#define AIPS_PACRL_WP5_MASK   (0x200U)
 
#define AIPS_PACRL_WP5_SHIFT   (9U)
 
#define AIPS_PACRL_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
 
#define AIPS_PACRL_SP5_MASK   (0x400U)
 
#define AIPS_PACRL_SP5_SHIFT   (10U)
 
#define AIPS_PACRL_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
 
#define AIPS_PACRL_TP4_MASK   (0x1000U)
 
#define AIPS_PACRL_TP4_SHIFT   (12U)
 
#define AIPS_PACRL_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
 
#define AIPS_PACRL_WP4_MASK   (0x2000U)
 
#define AIPS_PACRL_WP4_SHIFT   (13U)
 
#define AIPS_PACRL_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
 
#define AIPS_PACRL_SP4_MASK   (0x4000U)
 
#define AIPS_PACRL_SP4_SHIFT   (14U)
 
#define AIPS_PACRL_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
 
#define AIPS_PACRL_TP3_MASK   (0x10000U)
 
#define AIPS_PACRL_TP3_SHIFT   (16U)
 
#define AIPS_PACRL_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
 
#define AIPS_PACRL_WP3_MASK   (0x20000U)
 
#define AIPS_PACRL_WP3_SHIFT   (17U)
 
#define AIPS_PACRL_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
 
#define AIPS_PACRL_SP3_MASK   (0x40000U)
 
#define AIPS_PACRL_SP3_SHIFT   (18U)
 
#define AIPS_PACRL_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
 
#define AIPS_PACRL_TP2_MASK   (0x100000U)
 
#define AIPS_PACRL_TP2_SHIFT   (20U)
 
#define AIPS_PACRL_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
 
#define AIPS_PACRL_WP2_MASK   (0x200000U)
 
#define AIPS_PACRL_WP2_SHIFT   (21U)
 
#define AIPS_PACRL_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
 
#define AIPS_PACRL_SP2_MASK   (0x400000U)
 
#define AIPS_PACRL_SP2_SHIFT   (22U)
 
#define AIPS_PACRL_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
 
#define AIPS_PACRL_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRL_TP1_SHIFT   (24U)
 
#define AIPS_PACRL_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
 
#define AIPS_PACRL_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRL_WP1_SHIFT   (25U)
 
#define AIPS_PACRL_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
 
#define AIPS_PACRL_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRL_SP1_SHIFT   (26U)
 
#define AIPS_PACRL_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
 
#define AIPS_PACRL_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRL_TP0_SHIFT   (28U)
 
#define AIPS_PACRL_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
 
#define AIPS_PACRL_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRL_WP0_SHIFT   (29U)
 
#define AIPS_PACRL_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
 
#define AIPS_PACRL_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRL_SP0_SHIFT   (30U)
 
#define AIPS_PACRL_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
 
#define AIPS_PACRL_TP7_MASK   0x1u
 
#define AIPS_PACRL_TP7_SHIFT   0
 
#define AIPS_PACRL_WP7_MASK   0x2u
 
#define AIPS_PACRL_WP7_SHIFT   1
 
#define AIPS_PACRL_SP7_MASK   0x4u
 
#define AIPS_PACRL_SP7_SHIFT   2
 
#define AIPS_PACRL_TP6_MASK   0x10u
 
#define AIPS_PACRL_TP6_SHIFT   4
 
#define AIPS_PACRL_WP6_MASK   0x20u
 
#define AIPS_PACRL_WP6_SHIFT   5
 
#define AIPS_PACRL_SP6_MASK   0x40u
 
#define AIPS_PACRL_SP6_SHIFT   6
 
#define AIPS_PACRL_TP5_MASK   0x100u
 
#define AIPS_PACRL_TP5_SHIFT   8
 
#define AIPS_PACRL_WP5_MASK   0x200u
 
#define AIPS_PACRL_WP5_SHIFT   9
 
#define AIPS_PACRL_SP5_MASK   0x400u
 
#define AIPS_PACRL_SP5_SHIFT   10
 
#define AIPS_PACRL_TP4_MASK   0x1000u
 
#define AIPS_PACRL_TP4_SHIFT   12
 
#define AIPS_PACRL_WP4_MASK   0x2000u
 
#define AIPS_PACRL_WP4_SHIFT   13
 
#define AIPS_PACRL_SP4_MASK   0x4000u
 
#define AIPS_PACRL_SP4_SHIFT   14
 
#define AIPS_PACRL_TP3_MASK   0x10000u
 
#define AIPS_PACRL_TP3_SHIFT   16
 
#define AIPS_PACRL_WP3_MASK   0x20000u
 
#define AIPS_PACRL_WP3_SHIFT   17
 
#define AIPS_PACRL_SP3_MASK   0x40000u
 
#define AIPS_PACRL_SP3_SHIFT   18
 
#define AIPS_PACRL_TP2_MASK   0x100000u
 
#define AIPS_PACRL_TP2_SHIFT   20
 
#define AIPS_PACRL_WP2_MASK   0x200000u
 
#define AIPS_PACRL_WP2_SHIFT   21
 
#define AIPS_PACRL_SP2_MASK   0x400000u
 
#define AIPS_PACRL_SP2_SHIFT   22
 
#define AIPS_PACRL_TP1_MASK   0x1000000u
 
#define AIPS_PACRL_TP1_SHIFT   24
 
#define AIPS_PACRL_WP1_MASK   0x2000000u
 
#define AIPS_PACRL_WP1_SHIFT   25
 
#define AIPS_PACRL_SP1_MASK   0x4000000u
 
#define AIPS_PACRL_SP1_SHIFT   26
 
#define AIPS_PACRL_TP0_MASK   0x10000000u
 
#define AIPS_PACRL_TP0_SHIFT   28
 
#define AIPS_PACRL_WP0_MASK   0x20000000u
 
#define AIPS_PACRL_WP0_SHIFT   29
 
#define AIPS_PACRL_SP0_MASK   0x40000000u
 
#define AIPS_PACRL_SP0_SHIFT   30
 
#define AIPS_PACRL_TP7_MASK   (0x1U)
 
#define AIPS_PACRL_TP7_SHIFT   (0U)
 
#define AIPS_PACRL_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
 
#define AIPS_PACRL_WP7_MASK   (0x2U)
 
#define AIPS_PACRL_WP7_SHIFT   (1U)
 
#define AIPS_PACRL_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
 
#define AIPS_PACRL_SP7_MASK   (0x4U)
 
#define AIPS_PACRL_SP7_SHIFT   (2U)
 
#define AIPS_PACRL_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
 
#define AIPS_PACRL_TP6_MASK   (0x10U)
 
#define AIPS_PACRL_TP6_SHIFT   (4U)
 
#define AIPS_PACRL_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
 
#define AIPS_PACRL_WP6_MASK   (0x20U)
 
#define AIPS_PACRL_WP6_SHIFT   (5U)
 
#define AIPS_PACRL_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
 
#define AIPS_PACRL_SP6_MASK   (0x40U)
 
#define AIPS_PACRL_SP6_SHIFT   (6U)
 
#define AIPS_PACRL_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
 
#define AIPS_PACRL_TP5_MASK   (0x100U)
 
#define AIPS_PACRL_TP5_SHIFT   (8U)
 
#define AIPS_PACRL_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
 
#define AIPS_PACRL_WP5_MASK   (0x200U)
 
#define AIPS_PACRL_WP5_SHIFT   (9U)
 
#define AIPS_PACRL_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
 
#define AIPS_PACRL_SP5_MASK   (0x400U)
 
#define AIPS_PACRL_SP5_SHIFT   (10U)
 
#define AIPS_PACRL_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
 
#define AIPS_PACRL_TP4_MASK   (0x1000U)
 
#define AIPS_PACRL_TP4_SHIFT   (12U)
 
#define AIPS_PACRL_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
 
#define AIPS_PACRL_WP4_MASK   (0x2000U)
 
#define AIPS_PACRL_WP4_SHIFT   (13U)
 
#define AIPS_PACRL_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
 
#define AIPS_PACRL_SP4_MASK   (0x4000U)
 
#define AIPS_PACRL_SP4_SHIFT   (14U)
 
#define AIPS_PACRL_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
 
#define AIPS_PACRL_TP3_MASK   (0x10000U)
 
#define AIPS_PACRL_TP3_SHIFT   (16U)
 
#define AIPS_PACRL_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
 
#define AIPS_PACRL_WP3_MASK   (0x20000U)
 
#define AIPS_PACRL_WP3_SHIFT   (17U)
 
#define AIPS_PACRL_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
 
#define AIPS_PACRL_SP3_MASK   (0x40000U)
 
#define AIPS_PACRL_SP3_SHIFT   (18U)
 
#define AIPS_PACRL_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
 
#define AIPS_PACRL_TP2_MASK   (0x100000U)
 
#define AIPS_PACRL_TP2_SHIFT   (20U)
 
#define AIPS_PACRL_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
 
#define AIPS_PACRL_WP2_MASK   (0x200000U)
 
#define AIPS_PACRL_WP2_SHIFT   (21U)
 
#define AIPS_PACRL_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
 
#define AIPS_PACRL_SP2_MASK   (0x400000U)
 
#define AIPS_PACRL_SP2_SHIFT   (22U)
 
#define AIPS_PACRL_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
 
#define AIPS_PACRL_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRL_TP1_SHIFT   (24U)
 
#define AIPS_PACRL_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
 
#define AIPS_PACRL_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRL_WP1_SHIFT   (25U)
 
#define AIPS_PACRL_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
 
#define AIPS_PACRL_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRL_SP1_SHIFT   (26U)
 
#define AIPS_PACRL_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
 
#define AIPS_PACRL_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRL_TP0_SHIFT   (28U)
 
#define AIPS_PACRL_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
 
#define AIPS_PACRL_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRL_WP0_SHIFT   (29U)
 
#define AIPS_PACRL_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
 
#define AIPS_PACRL_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRL_SP0_SHIFT   (30U)
 
#define AIPS_PACRL_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
 
#define AIPS_PACRL_TP7_MASK   (0x1U)
 
#define AIPS_PACRL_TP7_SHIFT   (0U)
 
#define AIPS_PACRL_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
 
#define AIPS_PACRL_WP7_MASK   (0x2U)
 
#define AIPS_PACRL_WP7_SHIFT   (1U)
 
#define AIPS_PACRL_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
 
#define AIPS_PACRL_SP7_MASK   (0x4U)
 
#define AIPS_PACRL_SP7_SHIFT   (2U)
 
#define AIPS_PACRL_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
 
#define AIPS_PACRL_TP6_MASK   (0x10U)
 
#define AIPS_PACRL_TP6_SHIFT   (4U)
 
#define AIPS_PACRL_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
 
#define AIPS_PACRL_WP6_MASK   (0x20U)
 
#define AIPS_PACRL_WP6_SHIFT   (5U)
 
#define AIPS_PACRL_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
 
#define AIPS_PACRL_SP6_MASK   (0x40U)
 
#define AIPS_PACRL_SP6_SHIFT   (6U)
 
#define AIPS_PACRL_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
 
#define AIPS_PACRL_TP5_MASK   (0x100U)
 
#define AIPS_PACRL_TP5_SHIFT   (8U)
 
#define AIPS_PACRL_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
 
#define AIPS_PACRL_WP5_MASK   (0x200U)
 
#define AIPS_PACRL_WP5_SHIFT   (9U)
 
#define AIPS_PACRL_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
 
#define AIPS_PACRL_SP5_MASK   (0x400U)
 
#define AIPS_PACRL_SP5_SHIFT   (10U)
 
#define AIPS_PACRL_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
 
#define AIPS_PACRL_TP4_MASK   (0x1000U)
 
#define AIPS_PACRL_TP4_SHIFT   (12U)
 
#define AIPS_PACRL_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
 
#define AIPS_PACRL_WP4_MASK   (0x2000U)
 
#define AIPS_PACRL_WP4_SHIFT   (13U)
 
#define AIPS_PACRL_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
 
#define AIPS_PACRL_SP4_MASK   (0x4000U)
 
#define AIPS_PACRL_SP4_SHIFT   (14U)
 
#define AIPS_PACRL_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
 
#define AIPS_PACRL_TP3_MASK   (0x10000U)
 
#define AIPS_PACRL_TP3_SHIFT   (16U)
 
#define AIPS_PACRL_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
 
#define AIPS_PACRL_WP3_MASK   (0x20000U)
 
#define AIPS_PACRL_WP3_SHIFT   (17U)
 
#define AIPS_PACRL_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
 
#define AIPS_PACRL_SP3_MASK   (0x40000U)
 
#define AIPS_PACRL_SP3_SHIFT   (18U)
 
#define AIPS_PACRL_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
 
#define AIPS_PACRL_TP2_MASK   (0x100000U)
 
#define AIPS_PACRL_TP2_SHIFT   (20U)
 
#define AIPS_PACRL_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
 
#define AIPS_PACRL_WP2_MASK   (0x200000U)
 
#define AIPS_PACRL_WP2_SHIFT   (21U)
 
#define AIPS_PACRL_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
 
#define AIPS_PACRL_SP2_MASK   (0x400000U)
 
#define AIPS_PACRL_SP2_SHIFT   (22U)
 
#define AIPS_PACRL_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
 
#define AIPS_PACRL_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRL_TP1_SHIFT   (24U)
 
#define AIPS_PACRL_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
 
#define AIPS_PACRL_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRL_WP1_SHIFT   (25U)
 
#define AIPS_PACRL_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
 
#define AIPS_PACRL_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRL_SP1_SHIFT   (26U)
 
#define AIPS_PACRL_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
 
#define AIPS_PACRL_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRL_TP0_SHIFT   (28U)
 
#define AIPS_PACRL_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
 
#define AIPS_PACRL_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRL_WP0_SHIFT   (29U)
 
#define AIPS_PACRL_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
 
#define AIPS_PACRL_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRL_SP0_SHIFT   (30U)
 
#define AIPS_PACRL_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
 
#define AIPS_PACRL_TP7_MASK   (0x1U)
 
#define AIPS_PACRL_TP7_SHIFT   (0U)
 
#define AIPS_PACRL_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
 
#define AIPS_PACRL_WP7_MASK   (0x2U)
 
#define AIPS_PACRL_WP7_SHIFT   (1U)
 
#define AIPS_PACRL_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
 
#define AIPS_PACRL_SP7_MASK   (0x4U)
 
#define AIPS_PACRL_SP7_SHIFT   (2U)
 
#define AIPS_PACRL_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
 
#define AIPS_PACRL_TP6_MASK   (0x10U)
 
#define AIPS_PACRL_TP6_SHIFT   (4U)
 
#define AIPS_PACRL_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
 
#define AIPS_PACRL_WP6_MASK   (0x20U)
 
#define AIPS_PACRL_WP6_SHIFT   (5U)
 
#define AIPS_PACRL_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
 
#define AIPS_PACRL_SP6_MASK   (0x40U)
 
#define AIPS_PACRL_SP6_SHIFT   (6U)
 
#define AIPS_PACRL_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
 
#define AIPS_PACRL_TP5_MASK   (0x100U)
 
#define AIPS_PACRL_TP5_SHIFT   (8U)
 
#define AIPS_PACRL_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
 
#define AIPS_PACRL_WP5_MASK   (0x200U)
 
#define AIPS_PACRL_WP5_SHIFT   (9U)
 
#define AIPS_PACRL_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
 
#define AIPS_PACRL_SP5_MASK   (0x400U)
 
#define AIPS_PACRL_SP5_SHIFT   (10U)
 
#define AIPS_PACRL_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
 
#define AIPS_PACRL_TP4_MASK   (0x1000U)
 
#define AIPS_PACRL_TP4_SHIFT   (12U)
 
#define AIPS_PACRL_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
 
#define AIPS_PACRL_WP4_MASK   (0x2000U)
 
#define AIPS_PACRL_WP4_SHIFT   (13U)
 
#define AIPS_PACRL_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
 
#define AIPS_PACRL_SP4_MASK   (0x4000U)
 
#define AIPS_PACRL_SP4_SHIFT   (14U)
 
#define AIPS_PACRL_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
 
#define AIPS_PACRL_TP3_MASK   (0x10000U)
 
#define AIPS_PACRL_TP3_SHIFT   (16U)
 
#define AIPS_PACRL_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
 
#define AIPS_PACRL_WP3_MASK   (0x20000U)
 
#define AIPS_PACRL_WP3_SHIFT   (17U)
 
#define AIPS_PACRL_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
 
#define AIPS_PACRL_SP3_MASK   (0x40000U)
 
#define AIPS_PACRL_SP3_SHIFT   (18U)
 
#define AIPS_PACRL_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
 
#define AIPS_PACRL_TP2_MASK   (0x100000U)
 
#define AIPS_PACRL_TP2_SHIFT   (20U)
 
#define AIPS_PACRL_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
 
#define AIPS_PACRL_WP2_MASK   (0x200000U)
 
#define AIPS_PACRL_WP2_SHIFT   (21U)
 
#define AIPS_PACRL_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
 
#define AIPS_PACRL_SP2_MASK   (0x400000U)
 
#define AIPS_PACRL_SP2_SHIFT   (22U)
 
#define AIPS_PACRL_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
 
#define AIPS_PACRL_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRL_TP1_SHIFT   (24U)
 
#define AIPS_PACRL_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
 
#define AIPS_PACRL_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRL_WP1_SHIFT   (25U)
 
#define AIPS_PACRL_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
 
#define AIPS_PACRL_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRL_SP1_SHIFT   (26U)
 
#define AIPS_PACRL_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
 
#define AIPS_PACRL_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRL_TP0_SHIFT   (28U)
 
#define AIPS_PACRL_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
 
#define AIPS_PACRL_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRL_WP0_SHIFT   (29U)
 
#define AIPS_PACRL_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
 
#define AIPS_PACRL_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRL_SP0_SHIFT   (30U)
 
#define AIPS_PACRL_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
 
#define AIPS_PACRL_TP7_MASK   (0x1U)
 
#define AIPS_PACRL_TP7_SHIFT   (0U)
 
#define AIPS_PACRL_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
 
#define AIPS_PACRL_WP7_MASK   (0x2U)
 
#define AIPS_PACRL_WP7_SHIFT   (1U)
 
#define AIPS_PACRL_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
 
#define AIPS_PACRL_SP7_MASK   (0x4U)
 
#define AIPS_PACRL_SP7_SHIFT   (2U)
 
#define AIPS_PACRL_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
 
#define AIPS_PACRL_TP6_MASK   (0x10U)
 
#define AIPS_PACRL_TP6_SHIFT   (4U)
 
#define AIPS_PACRL_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
 
#define AIPS_PACRL_WP6_MASK   (0x20U)
 
#define AIPS_PACRL_WP6_SHIFT   (5U)
 
#define AIPS_PACRL_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
 
#define AIPS_PACRL_SP6_MASK   (0x40U)
 
#define AIPS_PACRL_SP6_SHIFT   (6U)
 
#define AIPS_PACRL_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
 
#define AIPS_PACRL_TP5_MASK   (0x100U)
 
#define AIPS_PACRL_TP5_SHIFT   (8U)
 
#define AIPS_PACRL_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
 
#define AIPS_PACRL_WP5_MASK   (0x200U)
 
#define AIPS_PACRL_WP5_SHIFT   (9U)
 
#define AIPS_PACRL_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
 
#define AIPS_PACRL_SP5_MASK   (0x400U)
 
#define AIPS_PACRL_SP5_SHIFT   (10U)
 
#define AIPS_PACRL_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
 
#define AIPS_PACRL_TP4_MASK   (0x1000U)
 
#define AIPS_PACRL_TP4_SHIFT   (12U)
 
#define AIPS_PACRL_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
 
#define AIPS_PACRL_WP4_MASK   (0x2000U)
 
#define AIPS_PACRL_WP4_SHIFT   (13U)
 
#define AIPS_PACRL_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
 
#define AIPS_PACRL_SP4_MASK   (0x4000U)
 
#define AIPS_PACRL_SP4_SHIFT   (14U)
 
#define AIPS_PACRL_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
 
#define AIPS_PACRL_TP3_MASK   (0x10000U)
 
#define AIPS_PACRL_TP3_SHIFT   (16U)
 
#define AIPS_PACRL_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
 
#define AIPS_PACRL_WP3_MASK   (0x20000U)
 
#define AIPS_PACRL_WP3_SHIFT   (17U)
 
#define AIPS_PACRL_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
 
#define AIPS_PACRL_SP3_MASK   (0x40000U)
 
#define AIPS_PACRL_SP3_SHIFT   (18U)
 
#define AIPS_PACRL_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
 
#define AIPS_PACRL_TP2_MASK   (0x100000U)
 
#define AIPS_PACRL_TP2_SHIFT   (20U)
 
#define AIPS_PACRL_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
 
#define AIPS_PACRL_WP2_MASK   (0x200000U)
 
#define AIPS_PACRL_WP2_SHIFT   (21U)
 
#define AIPS_PACRL_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
 
#define AIPS_PACRL_SP2_MASK   (0x400000U)
 
#define AIPS_PACRL_SP2_SHIFT   (22U)
 
#define AIPS_PACRL_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
 
#define AIPS_PACRL_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRL_TP1_SHIFT   (24U)
 
#define AIPS_PACRL_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
 
#define AIPS_PACRL_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRL_WP1_SHIFT   (25U)
 
#define AIPS_PACRL_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
 
#define AIPS_PACRL_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRL_SP1_SHIFT   (26U)
 
#define AIPS_PACRL_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
 
#define AIPS_PACRL_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRL_TP0_SHIFT   (28U)
 
#define AIPS_PACRL_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
 
#define AIPS_PACRL_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRL_WP0_SHIFT   (29U)
 
#define AIPS_PACRL_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
 
#define AIPS_PACRL_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRL_SP0_SHIFT   (30U)
 
#define AIPS_PACRL_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
 

PACRM - Peripheral Access Control Register

#define AIPS_PACRM_TP7_MASK   (0x1U)
 
#define AIPS_PACRM_TP7_SHIFT   (0U)
 
#define AIPS_PACRM_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
 
#define AIPS_PACRM_WP7_MASK   (0x2U)
 
#define AIPS_PACRM_WP7_SHIFT   (1U)
 
#define AIPS_PACRM_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
 
#define AIPS_PACRM_SP7_MASK   (0x4U)
 
#define AIPS_PACRM_SP7_SHIFT   (2U)
 
#define AIPS_PACRM_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
 
#define AIPS_PACRM_TP6_MASK   (0x10U)
 
#define AIPS_PACRM_TP6_SHIFT   (4U)
 
#define AIPS_PACRM_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
 
#define AIPS_PACRM_WP6_MASK   (0x20U)
 
#define AIPS_PACRM_WP6_SHIFT   (5U)
 
#define AIPS_PACRM_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
 
#define AIPS_PACRM_SP6_MASK   (0x40U)
 
#define AIPS_PACRM_SP6_SHIFT   (6U)
 
#define AIPS_PACRM_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
 
#define AIPS_PACRM_TP5_MASK   (0x100U)
 
#define AIPS_PACRM_TP5_SHIFT   (8U)
 
#define AIPS_PACRM_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
 
#define AIPS_PACRM_WP5_MASK   (0x200U)
 
#define AIPS_PACRM_WP5_SHIFT   (9U)
 
#define AIPS_PACRM_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
 
#define AIPS_PACRM_SP5_MASK   (0x400U)
 
#define AIPS_PACRM_SP5_SHIFT   (10U)
 
#define AIPS_PACRM_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
 
#define AIPS_PACRM_TP4_MASK   (0x1000U)
 
#define AIPS_PACRM_TP4_SHIFT   (12U)
 
#define AIPS_PACRM_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
 
#define AIPS_PACRM_WP4_MASK   (0x2000U)
 
#define AIPS_PACRM_WP4_SHIFT   (13U)
 
#define AIPS_PACRM_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
 
#define AIPS_PACRM_SP4_MASK   (0x4000U)
 
#define AIPS_PACRM_SP4_SHIFT   (14U)
 
#define AIPS_PACRM_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
 
#define AIPS_PACRM_TP3_MASK   (0x10000U)
 
#define AIPS_PACRM_TP3_SHIFT   (16U)
 
#define AIPS_PACRM_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
 
#define AIPS_PACRM_WP3_MASK   (0x20000U)
 
#define AIPS_PACRM_WP3_SHIFT   (17U)
 
#define AIPS_PACRM_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
 
#define AIPS_PACRM_SP3_MASK   (0x40000U)
 
#define AIPS_PACRM_SP3_SHIFT   (18U)
 
#define AIPS_PACRM_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
 
#define AIPS_PACRM_TP2_MASK   (0x100000U)
 
#define AIPS_PACRM_TP2_SHIFT   (20U)
 
#define AIPS_PACRM_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
 
#define AIPS_PACRM_WP2_MASK   (0x200000U)
 
#define AIPS_PACRM_WP2_SHIFT   (21U)
 
#define AIPS_PACRM_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
 
#define AIPS_PACRM_SP2_MASK   (0x400000U)
 
#define AIPS_PACRM_SP2_SHIFT   (22U)
 
#define AIPS_PACRM_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
 
#define AIPS_PACRM_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRM_TP1_SHIFT   (24U)
 
#define AIPS_PACRM_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
 
#define AIPS_PACRM_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRM_WP1_SHIFT   (25U)
 
#define AIPS_PACRM_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
 
#define AIPS_PACRM_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRM_SP1_SHIFT   (26U)
 
#define AIPS_PACRM_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
 
#define AIPS_PACRM_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRM_TP0_SHIFT   (28U)
 
#define AIPS_PACRM_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
 
#define AIPS_PACRM_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRM_WP0_SHIFT   (29U)
 
#define AIPS_PACRM_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
 
#define AIPS_PACRM_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRM_SP0_SHIFT   (30U)
 
#define AIPS_PACRM_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
 
#define AIPS_PACRM_TP7_MASK   0x1u
 
#define AIPS_PACRM_TP7_SHIFT   0
 
#define AIPS_PACRM_WP7_MASK   0x2u
 
#define AIPS_PACRM_WP7_SHIFT   1
 
#define AIPS_PACRM_SP7_MASK   0x4u
 
#define AIPS_PACRM_SP7_SHIFT   2
 
#define AIPS_PACRM_TP6_MASK   0x10u
 
#define AIPS_PACRM_TP6_SHIFT   4
 
#define AIPS_PACRM_WP6_MASK   0x20u
 
#define AIPS_PACRM_WP6_SHIFT   5
 
#define AIPS_PACRM_SP6_MASK   0x40u
 
#define AIPS_PACRM_SP6_SHIFT   6
 
#define AIPS_PACRM_TP5_MASK   0x100u
 
#define AIPS_PACRM_TP5_SHIFT   8
 
#define AIPS_PACRM_WP5_MASK   0x200u
 
#define AIPS_PACRM_WP5_SHIFT   9
 
#define AIPS_PACRM_SP5_MASK   0x400u
 
#define AIPS_PACRM_SP5_SHIFT   10
 
#define AIPS_PACRM_TP4_MASK   0x1000u
 
#define AIPS_PACRM_TP4_SHIFT   12
 
#define AIPS_PACRM_WP4_MASK   0x2000u
 
#define AIPS_PACRM_WP4_SHIFT   13
 
#define AIPS_PACRM_SP4_MASK   0x4000u
 
#define AIPS_PACRM_SP4_SHIFT   14
 
#define AIPS_PACRM_TP3_MASK   0x10000u
 
#define AIPS_PACRM_TP3_SHIFT   16
 
#define AIPS_PACRM_WP3_MASK   0x20000u
 
#define AIPS_PACRM_WP3_SHIFT   17
 
#define AIPS_PACRM_SP3_MASK   0x40000u
 
#define AIPS_PACRM_SP3_SHIFT   18
 
#define AIPS_PACRM_TP2_MASK   0x100000u
 
#define AIPS_PACRM_TP2_SHIFT   20
 
#define AIPS_PACRM_WP2_MASK   0x200000u
 
#define AIPS_PACRM_WP2_SHIFT   21
 
#define AIPS_PACRM_SP2_MASK   0x400000u
 
#define AIPS_PACRM_SP2_SHIFT   22
 
#define AIPS_PACRM_TP1_MASK   0x1000000u
 
#define AIPS_PACRM_TP1_SHIFT   24
 
#define AIPS_PACRM_WP1_MASK   0x2000000u
 
#define AIPS_PACRM_WP1_SHIFT   25
 
#define AIPS_PACRM_SP1_MASK   0x4000000u
 
#define AIPS_PACRM_SP1_SHIFT   26
 
#define AIPS_PACRM_TP0_MASK   0x10000000u
 
#define AIPS_PACRM_TP0_SHIFT   28
 
#define AIPS_PACRM_WP0_MASK   0x20000000u
 
#define AIPS_PACRM_WP0_SHIFT   29
 
#define AIPS_PACRM_SP0_MASK   0x40000000u
 
#define AIPS_PACRM_SP0_SHIFT   30
 
#define AIPS_PACRM_TP7_MASK   (0x1U)
 
#define AIPS_PACRM_TP7_SHIFT   (0U)
 
#define AIPS_PACRM_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
 
#define AIPS_PACRM_WP7_MASK   (0x2U)
 
#define AIPS_PACRM_WP7_SHIFT   (1U)
 
#define AIPS_PACRM_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
 
#define AIPS_PACRM_SP7_MASK   (0x4U)
 
#define AIPS_PACRM_SP7_SHIFT   (2U)
 
#define AIPS_PACRM_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
 
#define AIPS_PACRM_TP6_MASK   (0x10U)
 
#define AIPS_PACRM_TP6_SHIFT   (4U)
 
#define AIPS_PACRM_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
 
#define AIPS_PACRM_WP6_MASK   (0x20U)
 
#define AIPS_PACRM_WP6_SHIFT   (5U)
 
#define AIPS_PACRM_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
 
#define AIPS_PACRM_SP6_MASK   (0x40U)
 
#define AIPS_PACRM_SP6_SHIFT   (6U)
 
#define AIPS_PACRM_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
 
#define AIPS_PACRM_TP5_MASK   (0x100U)
 
#define AIPS_PACRM_TP5_SHIFT   (8U)
 
#define AIPS_PACRM_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
 
#define AIPS_PACRM_WP5_MASK   (0x200U)
 
#define AIPS_PACRM_WP5_SHIFT   (9U)
 
#define AIPS_PACRM_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
 
#define AIPS_PACRM_SP5_MASK   (0x400U)
 
#define AIPS_PACRM_SP5_SHIFT   (10U)
 
#define AIPS_PACRM_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
 
#define AIPS_PACRM_TP4_MASK   (0x1000U)
 
#define AIPS_PACRM_TP4_SHIFT   (12U)
 
#define AIPS_PACRM_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
 
#define AIPS_PACRM_WP4_MASK   (0x2000U)
 
#define AIPS_PACRM_WP4_SHIFT   (13U)
 
#define AIPS_PACRM_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
 
#define AIPS_PACRM_SP4_MASK   (0x4000U)
 
#define AIPS_PACRM_SP4_SHIFT   (14U)
 
#define AIPS_PACRM_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
 
#define AIPS_PACRM_TP3_MASK   (0x10000U)
 
#define AIPS_PACRM_TP3_SHIFT   (16U)
 
#define AIPS_PACRM_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
 
#define AIPS_PACRM_WP3_MASK   (0x20000U)
 
#define AIPS_PACRM_WP3_SHIFT   (17U)
 
#define AIPS_PACRM_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
 
#define AIPS_PACRM_SP3_MASK   (0x40000U)
 
#define AIPS_PACRM_SP3_SHIFT   (18U)
 
#define AIPS_PACRM_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
 
#define AIPS_PACRM_TP2_MASK   (0x100000U)
 
#define AIPS_PACRM_TP2_SHIFT   (20U)
 
#define AIPS_PACRM_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
 
#define AIPS_PACRM_WP2_MASK   (0x200000U)
 
#define AIPS_PACRM_WP2_SHIFT   (21U)
 
#define AIPS_PACRM_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
 
#define AIPS_PACRM_SP2_MASK   (0x400000U)
 
#define AIPS_PACRM_SP2_SHIFT   (22U)
 
#define AIPS_PACRM_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
 
#define AIPS_PACRM_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRM_TP1_SHIFT   (24U)
 
#define AIPS_PACRM_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
 
#define AIPS_PACRM_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRM_WP1_SHIFT   (25U)
 
#define AIPS_PACRM_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
 
#define AIPS_PACRM_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRM_SP1_SHIFT   (26U)
 
#define AIPS_PACRM_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
 
#define AIPS_PACRM_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRM_TP0_SHIFT   (28U)
 
#define AIPS_PACRM_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
 
#define AIPS_PACRM_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRM_WP0_SHIFT   (29U)
 
#define AIPS_PACRM_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
 
#define AIPS_PACRM_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRM_SP0_SHIFT   (30U)
 
#define AIPS_PACRM_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
 
#define AIPS_PACRM_TP7_MASK   (0x1U)
 
#define AIPS_PACRM_TP7_SHIFT   (0U)
 
#define AIPS_PACRM_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
 
#define AIPS_PACRM_WP7_MASK   (0x2U)
 
#define AIPS_PACRM_WP7_SHIFT   (1U)
 
#define AIPS_PACRM_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
 
#define AIPS_PACRM_SP7_MASK   (0x4U)
 
#define AIPS_PACRM_SP7_SHIFT   (2U)
 
#define AIPS_PACRM_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
 
#define AIPS_PACRM_TP6_MASK   (0x10U)
 
#define AIPS_PACRM_TP6_SHIFT   (4U)
 
#define AIPS_PACRM_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
 
#define AIPS_PACRM_WP6_MASK   (0x20U)
 
#define AIPS_PACRM_WP6_SHIFT   (5U)
 
#define AIPS_PACRM_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
 
#define AIPS_PACRM_SP6_MASK   (0x40U)
 
#define AIPS_PACRM_SP6_SHIFT   (6U)
 
#define AIPS_PACRM_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
 
#define AIPS_PACRM_TP5_MASK   (0x100U)
 
#define AIPS_PACRM_TP5_SHIFT   (8U)
 
#define AIPS_PACRM_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
 
#define AIPS_PACRM_WP5_MASK   (0x200U)
 
#define AIPS_PACRM_WP5_SHIFT   (9U)
 
#define AIPS_PACRM_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
 
#define AIPS_PACRM_SP5_MASK   (0x400U)
 
#define AIPS_PACRM_SP5_SHIFT   (10U)
 
#define AIPS_PACRM_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
 
#define AIPS_PACRM_TP4_MASK   (0x1000U)
 
#define AIPS_PACRM_TP4_SHIFT   (12U)
 
#define AIPS_PACRM_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
 
#define AIPS_PACRM_WP4_MASK   (0x2000U)
 
#define AIPS_PACRM_WP4_SHIFT   (13U)
 
#define AIPS_PACRM_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
 
#define AIPS_PACRM_SP4_MASK   (0x4000U)
 
#define AIPS_PACRM_SP4_SHIFT   (14U)
 
#define AIPS_PACRM_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
 
#define AIPS_PACRM_TP3_MASK   (0x10000U)
 
#define AIPS_PACRM_TP3_SHIFT   (16U)
 
#define AIPS_PACRM_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
 
#define AIPS_PACRM_WP3_MASK   (0x20000U)
 
#define AIPS_PACRM_WP3_SHIFT   (17U)
 
#define AIPS_PACRM_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
 
#define AIPS_PACRM_SP3_MASK   (0x40000U)
 
#define AIPS_PACRM_SP3_SHIFT   (18U)
 
#define AIPS_PACRM_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
 
#define AIPS_PACRM_TP2_MASK   (0x100000U)
 
#define AIPS_PACRM_TP2_SHIFT   (20U)
 
#define AIPS_PACRM_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
 
#define AIPS_PACRM_WP2_MASK   (0x200000U)
 
#define AIPS_PACRM_WP2_SHIFT   (21U)
 
#define AIPS_PACRM_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
 
#define AIPS_PACRM_SP2_MASK   (0x400000U)
 
#define AIPS_PACRM_SP2_SHIFT   (22U)
 
#define AIPS_PACRM_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
 
#define AIPS_PACRM_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRM_TP1_SHIFT   (24U)
 
#define AIPS_PACRM_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
 
#define AIPS_PACRM_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRM_WP1_SHIFT   (25U)
 
#define AIPS_PACRM_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
 
#define AIPS_PACRM_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRM_SP1_SHIFT   (26U)
 
#define AIPS_PACRM_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
 
#define AIPS_PACRM_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRM_TP0_SHIFT   (28U)
 
#define AIPS_PACRM_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
 
#define AIPS_PACRM_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRM_WP0_SHIFT   (29U)
 
#define AIPS_PACRM_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
 
#define AIPS_PACRM_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRM_SP0_SHIFT   (30U)
 
#define AIPS_PACRM_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
 
#define AIPS_PACRM_TP7_MASK   (0x1U)
 
#define AIPS_PACRM_TP7_SHIFT   (0U)
 
#define AIPS_PACRM_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
 
#define AIPS_PACRM_WP7_MASK   (0x2U)
 
#define AIPS_PACRM_WP7_SHIFT   (1U)
 
#define AIPS_PACRM_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
 
#define AIPS_PACRM_SP7_MASK   (0x4U)
 
#define AIPS_PACRM_SP7_SHIFT   (2U)
 
#define AIPS_PACRM_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
 
#define AIPS_PACRM_TP6_MASK   (0x10U)
 
#define AIPS_PACRM_TP6_SHIFT   (4U)
 
#define AIPS_PACRM_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
 
#define AIPS_PACRM_WP6_MASK   (0x20U)
 
#define AIPS_PACRM_WP6_SHIFT   (5U)
 
#define AIPS_PACRM_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
 
#define AIPS_PACRM_SP6_MASK   (0x40U)
 
#define AIPS_PACRM_SP6_SHIFT   (6U)
 
#define AIPS_PACRM_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
 
#define AIPS_PACRM_TP5_MASK   (0x100U)
 
#define AIPS_PACRM_TP5_SHIFT   (8U)
 
#define AIPS_PACRM_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
 
#define AIPS_PACRM_WP5_MASK   (0x200U)
 
#define AIPS_PACRM_WP5_SHIFT   (9U)
 
#define AIPS_PACRM_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
 
#define AIPS_PACRM_SP5_MASK   (0x400U)
 
#define AIPS_PACRM_SP5_SHIFT   (10U)
 
#define AIPS_PACRM_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
 
#define AIPS_PACRM_TP4_MASK   (0x1000U)
 
#define AIPS_PACRM_TP4_SHIFT   (12U)
 
#define AIPS_PACRM_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
 
#define AIPS_PACRM_WP4_MASK   (0x2000U)
 
#define AIPS_PACRM_WP4_SHIFT   (13U)
 
#define AIPS_PACRM_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
 
#define AIPS_PACRM_SP4_MASK   (0x4000U)
 
#define AIPS_PACRM_SP4_SHIFT   (14U)
 
#define AIPS_PACRM_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
 
#define AIPS_PACRM_TP3_MASK   (0x10000U)
 
#define AIPS_PACRM_TP3_SHIFT   (16U)
 
#define AIPS_PACRM_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
 
#define AIPS_PACRM_WP3_MASK   (0x20000U)
 
#define AIPS_PACRM_WP3_SHIFT   (17U)
 
#define AIPS_PACRM_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
 
#define AIPS_PACRM_SP3_MASK   (0x40000U)
 
#define AIPS_PACRM_SP3_SHIFT   (18U)
 
#define AIPS_PACRM_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
 
#define AIPS_PACRM_TP2_MASK   (0x100000U)
 
#define AIPS_PACRM_TP2_SHIFT   (20U)
 
#define AIPS_PACRM_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
 
#define AIPS_PACRM_WP2_MASK   (0x200000U)
 
#define AIPS_PACRM_WP2_SHIFT   (21U)
 
#define AIPS_PACRM_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
 
#define AIPS_PACRM_SP2_MASK   (0x400000U)
 
#define AIPS_PACRM_SP2_SHIFT   (22U)
 
#define AIPS_PACRM_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
 
#define AIPS_PACRM_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRM_TP1_SHIFT   (24U)
 
#define AIPS_PACRM_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
 
#define AIPS_PACRM_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRM_WP1_SHIFT   (25U)
 
#define AIPS_PACRM_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
 
#define AIPS_PACRM_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRM_SP1_SHIFT   (26U)
 
#define AIPS_PACRM_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
 
#define AIPS_PACRM_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRM_TP0_SHIFT   (28U)
 
#define AIPS_PACRM_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
 
#define AIPS_PACRM_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRM_WP0_SHIFT   (29U)
 
#define AIPS_PACRM_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
 
#define AIPS_PACRM_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRM_SP0_SHIFT   (30U)
 
#define AIPS_PACRM_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
 
#define AIPS_PACRM_TP7_MASK   (0x1U)
 
#define AIPS_PACRM_TP7_SHIFT   (0U)
 
#define AIPS_PACRM_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
 
#define AIPS_PACRM_WP7_MASK   (0x2U)
 
#define AIPS_PACRM_WP7_SHIFT   (1U)
 
#define AIPS_PACRM_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
 
#define AIPS_PACRM_SP7_MASK   (0x4U)
 
#define AIPS_PACRM_SP7_SHIFT   (2U)
 
#define AIPS_PACRM_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
 
#define AIPS_PACRM_TP6_MASK   (0x10U)
 
#define AIPS_PACRM_TP6_SHIFT   (4U)
 
#define AIPS_PACRM_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
 
#define AIPS_PACRM_WP6_MASK   (0x20U)
 
#define AIPS_PACRM_WP6_SHIFT   (5U)
 
#define AIPS_PACRM_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
 
#define AIPS_PACRM_SP6_MASK   (0x40U)
 
#define AIPS_PACRM_SP6_SHIFT   (6U)
 
#define AIPS_PACRM_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
 
#define AIPS_PACRM_TP5_MASK   (0x100U)
 
#define AIPS_PACRM_TP5_SHIFT   (8U)
 
#define AIPS_PACRM_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
 
#define AIPS_PACRM_WP5_MASK   (0x200U)
 
#define AIPS_PACRM_WP5_SHIFT   (9U)
 
#define AIPS_PACRM_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
 
#define AIPS_PACRM_SP5_MASK   (0x400U)
 
#define AIPS_PACRM_SP5_SHIFT   (10U)
 
#define AIPS_PACRM_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
 
#define AIPS_PACRM_TP4_MASK   (0x1000U)
 
#define AIPS_PACRM_TP4_SHIFT   (12U)
 
#define AIPS_PACRM_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
 
#define AIPS_PACRM_WP4_MASK   (0x2000U)
 
#define AIPS_PACRM_WP4_SHIFT   (13U)
 
#define AIPS_PACRM_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
 
#define AIPS_PACRM_SP4_MASK   (0x4000U)
 
#define AIPS_PACRM_SP4_SHIFT   (14U)
 
#define AIPS_PACRM_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
 
#define AIPS_PACRM_TP3_MASK   (0x10000U)
 
#define AIPS_PACRM_TP3_SHIFT   (16U)
 
#define AIPS_PACRM_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
 
#define AIPS_PACRM_WP3_MASK   (0x20000U)
 
#define AIPS_PACRM_WP3_SHIFT   (17U)
 
#define AIPS_PACRM_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
 
#define AIPS_PACRM_SP3_MASK   (0x40000U)
 
#define AIPS_PACRM_SP3_SHIFT   (18U)
 
#define AIPS_PACRM_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
 
#define AIPS_PACRM_TP2_MASK   (0x100000U)
 
#define AIPS_PACRM_TP2_SHIFT   (20U)
 
#define AIPS_PACRM_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
 
#define AIPS_PACRM_WP2_MASK   (0x200000U)
 
#define AIPS_PACRM_WP2_SHIFT   (21U)
 
#define AIPS_PACRM_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
 
#define AIPS_PACRM_SP2_MASK   (0x400000U)
 
#define AIPS_PACRM_SP2_SHIFT   (22U)
 
#define AIPS_PACRM_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
 
#define AIPS_PACRM_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRM_TP1_SHIFT   (24U)
 
#define AIPS_PACRM_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
 
#define AIPS_PACRM_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRM_WP1_SHIFT   (25U)
 
#define AIPS_PACRM_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
 
#define AIPS_PACRM_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRM_SP1_SHIFT   (26U)
 
#define AIPS_PACRM_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
 
#define AIPS_PACRM_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRM_TP0_SHIFT   (28U)
 
#define AIPS_PACRM_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
 
#define AIPS_PACRM_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRM_WP0_SHIFT   (29U)
 
#define AIPS_PACRM_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
 
#define AIPS_PACRM_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRM_SP0_SHIFT   (30U)
 
#define AIPS_PACRM_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
 

PACRN - Peripheral Access Control Register

#define AIPS_PACRN_TP7_MASK   (0x1U)
 
#define AIPS_PACRN_TP7_SHIFT   (0U)
 
#define AIPS_PACRN_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
 
#define AIPS_PACRN_WP7_MASK   (0x2U)
 
#define AIPS_PACRN_WP7_SHIFT   (1U)
 
#define AIPS_PACRN_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
 
#define AIPS_PACRN_SP7_MASK   (0x4U)
 
#define AIPS_PACRN_SP7_SHIFT   (2U)
 
#define AIPS_PACRN_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
 
#define AIPS_PACRN_TP6_MASK   (0x10U)
 
#define AIPS_PACRN_TP6_SHIFT   (4U)
 
#define AIPS_PACRN_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
 
#define AIPS_PACRN_WP6_MASK   (0x20U)
 
#define AIPS_PACRN_WP6_SHIFT   (5U)
 
#define AIPS_PACRN_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
 
#define AIPS_PACRN_SP6_MASK   (0x40U)
 
#define AIPS_PACRN_SP6_SHIFT   (6U)
 
#define AIPS_PACRN_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
 
#define AIPS_PACRN_TP5_MASK   (0x100U)
 
#define AIPS_PACRN_TP5_SHIFT   (8U)
 
#define AIPS_PACRN_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
 
#define AIPS_PACRN_WP5_MASK   (0x200U)
 
#define AIPS_PACRN_WP5_SHIFT   (9U)
 
#define AIPS_PACRN_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
 
#define AIPS_PACRN_SP5_MASK   (0x400U)
 
#define AIPS_PACRN_SP5_SHIFT   (10U)
 
#define AIPS_PACRN_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
 
#define AIPS_PACRN_TP4_MASK   (0x1000U)
 
#define AIPS_PACRN_TP4_SHIFT   (12U)
 
#define AIPS_PACRN_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
 
#define AIPS_PACRN_WP4_MASK   (0x2000U)
 
#define AIPS_PACRN_WP4_SHIFT   (13U)
 
#define AIPS_PACRN_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
 
#define AIPS_PACRN_SP4_MASK   (0x4000U)
 
#define AIPS_PACRN_SP4_SHIFT   (14U)
 
#define AIPS_PACRN_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
 
#define AIPS_PACRN_TP3_MASK   (0x10000U)
 
#define AIPS_PACRN_TP3_SHIFT   (16U)
 
#define AIPS_PACRN_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
 
#define AIPS_PACRN_WP3_MASK   (0x20000U)
 
#define AIPS_PACRN_WP3_SHIFT   (17U)
 
#define AIPS_PACRN_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
 
#define AIPS_PACRN_SP3_MASK   (0x40000U)
 
#define AIPS_PACRN_SP3_SHIFT   (18U)
 
#define AIPS_PACRN_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
 
#define AIPS_PACRN_TP2_MASK   (0x100000U)
 
#define AIPS_PACRN_TP2_SHIFT   (20U)
 
#define AIPS_PACRN_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
 
#define AIPS_PACRN_WP2_MASK   (0x200000U)
 
#define AIPS_PACRN_WP2_SHIFT   (21U)
 
#define AIPS_PACRN_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
 
#define AIPS_PACRN_SP2_MASK   (0x400000U)
 
#define AIPS_PACRN_SP2_SHIFT   (22U)
 
#define AIPS_PACRN_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
 
#define AIPS_PACRN_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRN_TP1_SHIFT   (24U)
 
#define AIPS_PACRN_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
 
#define AIPS_PACRN_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRN_WP1_SHIFT   (25U)
 
#define AIPS_PACRN_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
 
#define AIPS_PACRN_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRN_SP1_SHIFT   (26U)
 
#define AIPS_PACRN_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
 
#define AIPS_PACRN_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRN_TP0_SHIFT   (28U)
 
#define AIPS_PACRN_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
 
#define AIPS_PACRN_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRN_WP0_SHIFT   (29U)
 
#define AIPS_PACRN_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
 
#define AIPS_PACRN_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRN_SP0_SHIFT   (30U)
 
#define AIPS_PACRN_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
 
#define AIPS_PACRN_TP7_MASK   0x1u
 
#define AIPS_PACRN_TP7_SHIFT   0
 
#define AIPS_PACRN_WP7_MASK   0x2u
 
#define AIPS_PACRN_WP7_SHIFT   1
 
#define AIPS_PACRN_SP7_MASK   0x4u
 
#define AIPS_PACRN_SP7_SHIFT   2
 
#define AIPS_PACRN_TP6_MASK   0x10u
 
#define AIPS_PACRN_TP6_SHIFT   4
 
#define AIPS_PACRN_WP6_MASK   0x20u
 
#define AIPS_PACRN_WP6_SHIFT   5
 
#define AIPS_PACRN_SP6_MASK   0x40u
 
#define AIPS_PACRN_SP6_SHIFT   6
 
#define AIPS_PACRN_TP5_MASK   0x100u
 
#define AIPS_PACRN_TP5_SHIFT   8
 
#define AIPS_PACRN_WP5_MASK   0x200u
 
#define AIPS_PACRN_WP5_SHIFT   9
 
#define AIPS_PACRN_SP5_MASK   0x400u
 
#define AIPS_PACRN_SP5_SHIFT   10
 
#define AIPS_PACRN_TP4_MASK   0x1000u
 
#define AIPS_PACRN_TP4_SHIFT   12
 
#define AIPS_PACRN_WP4_MASK   0x2000u
 
#define AIPS_PACRN_WP4_SHIFT   13
 
#define AIPS_PACRN_SP4_MASK   0x4000u
 
#define AIPS_PACRN_SP4_SHIFT   14
 
#define AIPS_PACRN_TP3_MASK   0x10000u
 
#define AIPS_PACRN_TP3_SHIFT   16
 
#define AIPS_PACRN_WP3_MASK   0x20000u
 
#define AIPS_PACRN_WP3_SHIFT   17
 
#define AIPS_PACRN_SP3_MASK   0x40000u
 
#define AIPS_PACRN_SP3_SHIFT   18
 
#define AIPS_PACRN_TP2_MASK   0x100000u
 
#define AIPS_PACRN_TP2_SHIFT   20
 
#define AIPS_PACRN_WP2_MASK   0x200000u
 
#define AIPS_PACRN_WP2_SHIFT   21
 
#define AIPS_PACRN_SP2_MASK   0x400000u
 
#define AIPS_PACRN_SP2_SHIFT   22
 
#define AIPS_PACRN_TP1_MASK   0x1000000u
 
#define AIPS_PACRN_TP1_SHIFT   24
 
#define AIPS_PACRN_WP1_MASK   0x2000000u
 
#define AIPS_PACRN_WP1_SHIFT   25
 
#define AIPS_PACRN_SP1_MASK   0x4000000u
 
#define AIPS_PACRN_SP1_SHIFT   26
 
#define AIPS_PACRN_TP0_MASK   0x10000000u
 
#define AIPS_PACRN_TP0_SHIFT   28
 
#define AIPS_PACRN_WP0_MASK   0x20000000u
 
#define AIPS_PACRN_WP0_SHIFT   29
 
#define AIPS_PACRN_SP0_MASK   0x40000000u
 
#define AIPS_PACRN_SP0_SHIFT   30
 
#define AIPS_PACRN_TP7_MASK   (0x1U)
 
#define AIPS_PACRN_TP7_SHIFT   (0U)
 
#define AIPS_PACRN_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
 
#define AIPS_PACRN_WP7_MASK   (0x2U)
 
#define AIPS_PACRN_WP7_SHIFT   (1U)
 
#define AIPS_PACRN_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
 
#define AIPS_PACRN_SP7_MASK   (0x4U)
 
#define AIPS_PACRN_SP7_SHIFT   (2U)
 
#define AIPS_PACRN_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
 
#define AIPS_PACRN_TP6_MASK   (0x10U)
 
#define AIPS_PACRN_TP6_SHIFT   (4U)
 
#define AIPS_PACRN_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
 
#define AIPS_PACRN_WP6_MASK   (0x20U)
 
#define AIPS_PACRN_WP6_SHIFT   (5U)
 
#define AIPS_PACRN_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
 
#define AIPS_PACRN_SP6_MASK   (0x40U)
 
#define AIPS_PACRN_SP6_SHIFT   (6U)
 
#define AIPS_PACRN_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
 
#define AIPS_PACRN_TP5_MASK   (0x100U)
 
#define AIPS_PACRN_TP5_SHIFT   (8U)
 
#define AIPS_PACRN_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
 
#define AIPS_PACRN_WP5_MASK   (0x200U)
 
#define AIPS_PACRN_WP5_SHIFT   (9U)
 
#define AIPS_PACRN_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
 
#define AIPS_PACRN_SP5_MASK   (0x400U)
 
#define AIPS_PACRN_SP5_SHIFT   (10U)
 
#define AIPS_PACRN_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
 
#define AIPS_PACRN_TP4_MASK   (0x1000U)
 
#define AIPS_PACRN_TP4_SHIFT   (12U)
 
#define AIPS_PACRN_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
 
#define AIPS_PACRN_WP4_MASK   (0x2000U)
 
#define AIPS_PACRN_WP4_SHIFT   (13U)
 
#define AIPS_PACRN_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
 
#define AIPS_PACRN_SP4_MASK   (0x4000U)
 
#define AIPS_PACRN_SP4_SHIFT   (14U)
 
#define AIPS_PACRN_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
 
#define AIPS_PACRN_TP3_MASK   (0x10000U)
 
#define AIPS_PACRN_TP3_SHIFT   (16U)
 
#define AIPS_PACRN_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
 
#define AIPS_PACRN_WP3_MASK   (0x20000U)
 
#define AIPS_PACRN_WP3_SHIFT   (17U)
 
#define AIPS_PACRN_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
 
#define AIPS_PACRN_SP3_MASK   (0x40000U)
 
#define AIPS_PACRN_SP3_SHIFT   (18U)
 
#define AIPS_PACRN_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
 
#define AIPS_PACRN_TP2_MASK   (0x100000U)
 
#define AIPS_PACRN_TP2_SHIFT   (20U)
 
#define AIPS_PACRN_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
 
#define AIPS_PACRN_WP2_MASK   (0x200000U)
 
#define AIPS_PACRN_WP2_SHIFT   (21U)
 
#define AIPS_PACRN_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
 
#define AIPS_PACRN_SP2_MASK   (0x400000U)
 
#define AIPS_PACRN_SP2_SHIFT   (22U)
 
#define AIPS_PACRN_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
 
#define AIPS_PACRN_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRN_TP1_SHIFT   (24U)
 
#define AIPS_PACRN_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
 
#define AIPS_PACRN_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRN_WP1_SHIFT   (25U)
 
#define AIPS_PACRN_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
 
#define AIPS_PACRN_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRN_SP1_SHIFT   (26U)
 
#define AIPS_PACRN_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
 
#define AIPS_PACRN_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRN_TP0_SHIFT   (28U)
 
#define AIPS_PACRN_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
 
#define AIPS_PACRN_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRN_WP0_SHIFT   (29U)
 
#define AIPS_PACRN_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
 
#define AIPS_PACRN_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRN_SP0_SHIFT   (30U)
 
#define AIPS_PACRN_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
 
#define AIPS_PACRN_TP7_MASK   (0x1U)
 
#define AIPS_PACRN_TP7_SHIFT   (0U)
 
#define AIPS_PACRN_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
 
#define AIPS_PACRN_WP7_MASK   (0x2U)
 
#define AIPS_PACRN_WP7_SHIFT   (1U)
 
#define AIPS_PACRN_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
 
#define AIPS_PACRN_SP7_MASK   (0x4U)
 
#define AIPS_PACRN_SP7_SHIFT   (2U)
 
#define AIPS_PACRN_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
 
#define AIPS_PACRN_TP6_MASK   (0x10U)
 
#define AIPS_PACRN_TP6_SHIFT   (4U)
 
#define AIPS_PACRN_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
 
#define AIPS_PACRN_WP6_MASK   (0x20U)
 
#define AIPS_PACRN_WP6_SHIFT   (5U)
 
#define AIPS_PACRN_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
 
#define AIPS_PACRN_SP6_MASK   (0x40U)
 
#define AIPS_PACRN_SP6_SHIFT   (6U)
 
#define AIPS_PACRN_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
 
#define AIPS_PACRN_TP5_MASK   (0x100U)
 
#define AIPS_PACRN_TP5_SHIFT   (8U)
 
#define AIPS_PACRN_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
 
#define AIPS_PACRN_WP5_MASK   (0x200U)
 
#define AIPS_PACRN_WP5_SHIFT   (9U)
 
#define AIPS_PACRN_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
 
#define AIPS_PACRN_SP5_MASK   (0x400U)
 
#define AIPS_PACRN_SP5_SHIFT   (10U)
 
#define AIPS_PACRN_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
 
#define AIPS_PACRN_TP4_MASK   (0x1000U)
 
#define AIPS_PACRN_TP4_SHIFT   (12U)
 
#define AIPS_PACRN_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
 
#define AIPS_PACRN_WP4_MASK   (0x2000U)
 
#define AIPS_PACRN_WP4_SHIFT   (13U)
 
#define AIPS_PACRN_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
 
#define AIPS_PACRN_SP4_MASK   (0x4000U)
 
#define AIPS_PACRN_SP4_SHIFT   (14U)
 
#define AIPS_PACRN_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
 
#define AIPS_PACRN_TP3_MASK   (0x10000U)
 
#define AIPS_PACRN_TP3_SHIFT   (16U)
 
#define AIPS_PACRN_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
 
#define AIPS_PACRN_WP3_MASK   (0x20000U)
 
#define AIPS_PACRN_WP3_SHIFT   (17U)
 
#define AIPS_PACRN_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
 
#define AIPS_PACRN_SP3_MASK   (0x40000U)
 
#define AIPS_PACRN_SP3_SHIFT   (18U)
 
#define AIPS_PACRN_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
 
#define AIPS_PACRN_TP2_MASK   (0x100000U)
 
#define AIPS_PACRN_TP2_SHIFT   (20U)
 
#define AIPS_PACRN_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
 
#define AIPS_PACRN_WP2_MASK   (0x200000U)
 
#define AIPS_PACRN_WP2_SHIFT   (21U)
 
#define AIPS_PACRN_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
 
#define AIPS_PACRN_SP2_MASK   (0x400000U)
 
#define AIPS_PACRN_SP2_SHIFT   (22U)
 
#define AIPS_PACRN_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
 
#define AIPS_PACRN_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRN_TP1_SHIFT   (24U)
 
#define AIPS_PACRN_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
 
#define AIPS_PACRN_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRN_WP1_SHIFT   (25U)
 
#define AIPS_PACRN_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
 
#define AIPS_PACRN_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRN_SP1_SHIFT   (26U)
 
#define AIPS_PACRN_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
 
#define AIPS_PACRN_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRN_TP0_SHIFT   (28U)
 
#define AIPS_PACRN_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
 
#define AIPS_PACRN_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRN_WP0_SHIFT   (29U)
 
#define AIPS_PACRN_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
 
#define AIPS_PACRN_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRN_SP0_SHIFT   (30U)
 
#define AIPS_PACRN_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
 
#define AIPS_PACRN_TP7_MASK   (0x1U)
 
#define AIPS_PACRN_TP7_SHIFT   (0U)
 
#define AIPS_PACRN_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
 
#define AIPS_PACRN_WP7_MASK   (0x2U)
 
#define AIPS_PACRN_WP7_SHIFT   (1U)
 
#define AIPS_PACRN_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
 
#define AIPS_PACRN_SP7_MASK   (0x4U)
 
#define AIPS_PACRN_SP7_SHIFT   (2U)
 
#define AIPS_PACRN_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
 
#define AIPS_PACRN_TP6_MASK   (0x10U)
 
#define AIPS_PACRN_TP6_SHIFT   (4U)
 
#define AIPS_PACRN_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
 
#define AIPS_PACRN_WP6_MASK   (0x20U)
 
#define AIPS_PACRN_WP6_SHIFT   (5U)
 
#define AIPS_PACRN_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
 
#define AIPS_PACRN_SP6_MASK   (0x40U)
 
#define AIPS_PACRN_SP6_SHIFT   (6U)
 
#define AIPS_PACRN_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
 
#define AIPS_PACRN_TP5_MASK   (0x100U)
 
#define AIPS_PACRN_TP5_SHIFT   (8U)
 
#define AIPS_PACRN_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
 
#define AIPS_PACRN_WP5_MASK   (0x200U)
 
#define AIPS_PACRN_WP5_SHIFT   (9U)
 
#define AIPS_PACRN_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
 
#define AIPS_PACRN_SP5_MASK   (0x400U)
 
#define AIPS_PACRN_SP5_SHIFT   (10U)
 
#define AIPS_PACRN_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
 
#define AIPS_PACRN_TP4_MASK   (0x1000U)
 
#define AIPS_PACRN_TP4_SHIFT   (12U)
 
#define AIPS_PACRN_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
 
#define AIPS_PACRN_WP4_MASK   (0x2000U)
 
#define AIPS_PACRN_WP4_SHIFT   (13U)
 
#define AIPS_PACRN_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
 
#define AIPS_PACRN_SP4_MASK   (0x4000U)
 
#define AIPS_PACRN_SP4_SHIFT   (14U)
 
#define AIPS_PACRN_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
 
#define AIPS_PACRN_TP3_MASK   (0x10000U)
 
#define AIPS_PACRN_TP3_SHIFT   (16U)
 
#define AIPS_PACRN_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
 
#define AIPS_PACRN_WP3_MASK   (0x20000U)
 
#define AIPS_PACRN_WP3_SHIFT   (17U)
 
#define AIPS_PACRN_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
 
#define AIPS_PACRN_SP3_MASK   (0x40000U)
 
#define AIPS_PACRN_SP3_SHIFT   (18U)
 
#define AIPS_PACRN_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
 
#define AIPS_PACRN_TP2_MASK   (0x100000U)
 
#define AIPS_PACRN_TP2_SHIFT   (20U)
 
#define AIPS_PACRN_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
 
#define AIPS_PACRN_WP2_MASK   (0x200000U)
 
#define AIPS_PACRN_WP2_SHIFT   (21U)
 
#define AIPS_PACRN_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
 
#define AIPS_PACRN_SP2_MASK   (0x400000U)
 
#define AIPS_PACRN_SP2_SHIFT   (22U)
 
#define AIPS_PACRN_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
 
#define AIPS_PACRN_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRN_TP1_SHIFT   (24U)
 
#define AIPS_PACRN_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
 
#define AIPS_PACRN_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRN_WP1_SHIFT   (25U)
 
#define AIPS_PACRN_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
 
#define AIPS_PACRN_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRN_SP1_SHIFT   (26U)
 
#define AIPS_PACRN_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
 
#define AIPS_PACRN_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRN_TP0_SHIFT   (28U)
 
#define AIPS_PACRN_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
 
#define AIPS_PACRN_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRN_WP0_SHIFT   (29U)
 
#define AIPS_PACRN_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
 
#define AIPS_PACRN_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRN_SP0_SHIFT   (30U)
 
#define AIPS_PACRN_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
 
#define AIPS_PACRN_TP7_MASK   (0x1U)
 
#define AIPS_PACRN_TP7_SHIFT   (0U)
 
#define AIPS_PACRN_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
 
#define AIPS_PACRN_WP7_MASK   (0x2U)
 
#define AIPS_PACRN_WP7_SHIFT   (1U)
 
#define AIPS_PACRN_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
 
#define AIPS_PACRN_SP7_MASK   (0x4U)
 
#define AIPS_PACRN_SP7_SHIFT   (2U)
 
#define AIPS_PACRN_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
 
#define AIPS_PACRN_TP6_MASK   (0x10U)
 
#define AIPS_PACRN_TP6_SHIFT   (4U)
 
#define AIPS_PACRN_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
 
#define AIPS_PACRN_WP6_MASK   (0x20U)
 
#define AIPS_PACRN_WP6_SHIFT   (5U)
 
#define AIPS_PACRN_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
 
#define AIPS_PACRN_SP6_MASK   (0x40U)
 
#define AIPS_PACRN_SP6_SHIFT   (6U)
 
#define AIPS_PACRN_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
 
#define AIPS_PACRN_TP5_MASK   (0x100U)
 
#define AIPS_PACRN_TP5_SHIFT   (8U)
 
#define AIPS_PACRN_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
 
#define AIPS_PACRN_WP5_MASK   (0x200U)
 
#define AIPS_PACRN_WP5_SHIFT   (9U)
 
#define AIPS_PACRN_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
 
#define AIPS_PACRN_SP5_MASK   (0x400U)
 
#define AIPS_PACRN_SP5_SHIFT   (10U)
 
#define AIPS_PACRN_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
 
#define AIPS_PACRN_TP4_MASK   (0x1000U)
 
#define AIPS_PACRN_TP4_SHIFT   (12U)
 
#define AIPS_PACRN_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
 
#define AIPS_PACRN_WP4_MASK   (0x2000U)
 
#define AIPS_PACRN_WP4_SHIFT   (13U)
 
#define AIPS_PACRN_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
 
#define AIPS_PACRN_SP4_MASK   (0x4000U)
 
#define AIPS_PACRN_SP4_SHIFT   (14U)
 
#define AIPS_PACRN_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
 
#define AIPS_PACRN_TP3_MASK   (0x10000U)
 
#define AIPS_PACRN_TP3_SHIFT   (16U)
 
#define AIPS_PACRN_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
 
#define AIPS_PACRN_WP3_MASK   (0x20000U)
 
#define AIPS_PACRN_WP3_SHIFT   (17U)
 
#define AIPS_PACRN_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
 
#define AIPS_PACRN_SP3_MASK   (0x40000U)
 
#define AIPS_PACRN_SP3_SHIFT   (18U)
 
#define AIPS_PACRN_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
 
#define AIPS_PACRN_TP2_MASK   (0x100000U)
 
#define AIPS_PACRN_TP2_SHIFT   (20U)
 
#define AIPS_PACRN_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
 
#define AIPS_PACRN_WP2_MASK   (0x200000U)
 
#define AIPS_PACRN_WP2_SHIFT   (21U)
 
#define AIPS_PACRN_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
 
#define AIPS_PACRN_SP2_MASK   (0x400000U)
 
#define AIPS_PACRN_SP2_SHIFT   (22U)
 
#define AIPS_PACRN_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
 
#define AIPS_PACRN_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRN_TP1_SHIFT   (24U)
 
#define AIPS_PACRN_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
 
#define AIPS_PACRN_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRN_WP1_SHIFT   (25U)
 
#define AIPS_PACRN_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
 
#define AIPS_PACRN_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRN_SP1_SHIFT   (26U)
 
#define AIPS_PACRN_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
 
#define AIPS_PACRN_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRN_TP0_SHIFT   (28U)
 
#define AIPS_PACRN_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
 
#define AIPS_PACRN_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRN_WP0_SHIFT   (29U)
 
#define AIPS_PACRN_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
 
#define AIPS_PACRN_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRN_SP0_SHIFT   (30U)
 
#define AIPS_PACRN_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
 

PACRO - Peripheral Access Control Register

#define AIPS_PACRO_TP7_MASK   (0x1U)
 
#define AIPS_PACRO_TP7_SHIFT   (0U)
 
#define AIPS_PACRO_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
 
#define AIPS_PACRO_WP7_MASK   (0x2U)
 
#define AIPS_PACRO_WP7_SHIFT   (1U)
 
#define AIPS_PACRO_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
 
#define AIPS_PACRO_SP7_MASK   (0x4U)
 
#define AIPS_PACRO_SP7_SHIFT   (2U)
 
#define AIPS_PACRO_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
 
#define AIPS_PACRO_TP6_MASK   (0x10U)
 
#define AIPS_PACRO_TP6_SHIFT   (4U)
 
#define AIPS_PACRO_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
 
#define AIPS_PACRO_WP6_MASK   (0x20U)
 
#define AIPS_PACRO_WP6_SHIFT   (5U)
 
#define AIPS_PACRO_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
 
#define AIPS_PACRO_SP6_MASK   (0x40U)
 
#define AIPS_PACRO_SP6_SHIFT   (6U)
 
#define AIPS_PACRO_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
 
#define AIPS_PACRO_TP5_MASK   (0x100U)
 
#define AIPS_PACRO_TP5_SHIFT   (8U)
 
#define AIPS_PACRO_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
 
#define AIPS_PACRO_WP5_MASK   (0x200U)
 
#define AIPS_PACRO_WP5_SHIFT   (9U)
 
#define AIPS_PACRO_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
 
#define AIPS_PACRO_SP5_MASK   (0x400U)
 
#define AIPS_PACRO_SP5_SHIFT   (10U)
 
#define AIPS_PACRO_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
 
#define AIPS_PACRO_TP4_MASK   (0x1000U)
 
#define AIPS_PACRO_TP4_SHIFT   (12U)
 
#define AIPS_PACRO_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
 
#define AIPS_PACRO_WP4_MASK   (0x2000U)
 
#define AIPS_PACRO_WP4_SHIFT   (13U)
 
#define AIPS_PACRO_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
 
#define AIPS_PACRO_SP4_MASK   (0x4000U)
 
#define AIPS_PACRO_SP4_SHIFT   (14U)
 
#define AIPS_PACRO_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
 
#define AIPS_PACRO_TP3_MASK   (0x10000U)
 
#define AIPS_PACRO_TP3_SHIFT   (16U)
 
#define AIPS_PACRO_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
 
#define AIPS_PACRO_WP3_MASK   (0x20000U)
 
#define AIPS_PACRO_WP3_SHIFT   (17U)
 
#define AIPS_PACRO_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
 
#define AIPS_PACRO_SP3_MASK   (0x40000U)
 
#define AIPS_PACRO_SP3_SHIFT   (18U)
 
#define AIPS_PACRO_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
 
#define AIPS_PACRO_TP2_MASK   (0x100000U)
 
#define AIPS_PACRO_TP2_SHIFT   (20U)
 
#define AIPS_PACRO_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
 
#define AIPS_PACRO_WP2_MASK   (0x200000U)
 
#define AIPS_PACRO_WP2_SHIFT   (21U)
 
#define AIPS_PACRO_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
 
#define AIPS_PACRO_SP2_MASK   (0x400000U)
 
#define AIPS_PACRO_SP2_SHIFT   (22U)
 
#define AIPS_PACRO_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
 
#define AIPS_PACRO_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRO_TP1_SHIFT   (24U)
 
#define AIPS_PACRO_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
 
#define AIPS_PACRO_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRO_WP1_SHIFT   (25U)
 
#define AIPS_PACRO_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
 
#define AIPS_PACRO_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRO_SP1_SHIFT   (26U)
 
#define AIPS_PACRO_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
 
#define AIPS_PACRO_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRO_TP0_SHIFT   (28U)
 
#define AIPS_PACRO_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
 
#define AIPS_PACRO_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRO_WP0_SHIFT   (29U)
 
#define AIPS_PACRO_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
 
#define AIPS_PACRO_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRO_SP0_SHIFT   (30U)
 
#define AIPS_PACRO_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
 
#define AIPS_PACRO_TP7_MASK   0x1u
 
#define AIPS_PACRO_TP7_SHIFT   0
 
#define AIPS_PACRO_WP7_MASK   0x2u
 
#define AIPS_PACRO_WP7_SHIFT   1
 
#define AIPS_PACRO_SP7_MASK   0x4u
 
#define AIPS_PACRO_SP7_SHIFT   2
 
#define AIPS_PACRO_TP6_MASK   0x10u
 
#define AIPS_PACRO_TP6_SHIFT   4
 
#define AIPS_PACRO_WP6_MASK   0x20u
 
#define AIPS_PACRO_WP6_SHIFT   5
 
#define AIPS_PACRO_SP6_MASK   0x40u
 
#define AIPS_PACRO_SP6_SHIFT   6
 
#define AIPS_PACRO_TP5_MASK   0x100u
 
#define AIPS_PACRO_TP5_SHIFT   8
 
#define AIPS_PACRO_WP5_MASK   0x200u
 
#define AIPS_PACRO_WP5_SHIFT   9
 
#define AIPS_PACRO_SP5_MASK   0x400u
 
#define AIPS_PACRO_SP5_SHIFT   10
 
#define AIPS_PACRO_TP4_MASK   0x1000u
 
#define AIPS_PACRO_TP4_SHIFT   12
 
#define AIPS_PACRO_WP4_MASK   0x2000u
 
#define AIPS_PACRO_WP4_SHIFT   13
 
#define AIPS_PACRO_SP4_MASK   0x4000u
 
#define AIPS_PACRO_SP4_SHIFT   14
 
#define AIPS_PACRO_TP3_MASK   0x10000u
 
#define AIPS_PACRO_TP3_SHIFT   16
 
#define AIPS_PACRO_WP3_MASK   0x20000u
 
#define AIPS_PACRO_WP3_SHIFT   17
 
#define AIPS_PACRO_SP3_MASK   0x40000u
 
#define AIPS_PACRO_SP3_SHIFT   18
 
#define AIPS_PACRO_TP2_MASK   0x100000u
 
#define AIPS_PACRO_TP2_SHIFT   20
 
#define AIPS_PACRO_WP2_MASK   0x200000u
 
#define AIPS_PACRO_WP2_SHIFT   21
 
#define AIPS_PACRO_SP2_MASK   0x400000u
 
#define AIPS_PACRO_SP2_SHIFT   22
 
#define AIPS_PACRO_TP1_MASK   0x1000000u
 
#define AIPS_PACRO_TP1_SHIFT   24
 
#define AIPS_PACRO_WP1_MASK   0x2000000u
 
#define AIPS_PACRO_WP1_SHIFT   25
 
#define AIPS_PACRO_SP1_MASK   0x4000000u
 
#define AIPS_PACRO_SP1_SHIFT   26
 
#define AIPS_PACRO_TP0_MASK   0x10000000u
 
#define AIPS_PACRO_TP0_SHIFT   28
 
#define AIPS_PACRO_WP0_MASK   0x20000000u
 
#define AIPS_PACRO_WP0_SHIFT   29
 
#define AIPS_PACRO_SP0_MASK   0x40000000u
 
#define AIPS_PACRO_SP0_SHIFT   30
 
#define AIPS_PACRO_TP7_MASK   (0x1U)
 
#define AIPS_PACRO_TP7_SHIFT   (0U)
 
#define AIPS_PACRO_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
 
#define AIPS_PACRO_WP7_MASK   (0x2U)
 
#define AIPS_PACRO_WP7_SHIFT   (1U)
 
#define AIPS_PACRO_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
 
#define AIPS_PACRO_SP7_MASK   (0x4U)
 
#define AIPS_PACRO_SP7_SHIFT   (2U)
 
#define AIPS_PACRO_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
 
#define AIPS_PACRO_TP6_MASK   (0x10U)
 
#define AIPS_PACRO_TP6_SHIFT   (4U)
 
#define AIPS_PACRO_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
 
#define AIPS_PACRO_WP6_MASK   (0x20U)
 
#define AIPS_PACRO_WP6_SHIFT   (5U)
 
#define AIPS_PACRO_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
 
#define AIPS_PACRO_SP6_MASK   (0x40U)
 
#define AIPS_PACRO_SP6_SHIFT   (6U)
 
#define AIPS_PACRO_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
 
#define AIPS_PACRO_TP5_MASK   (0x100U)
 
#define AIPS_PACRO_TP5_SHIFT   (8U)
 
#define AIPS_PACRO_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
 
#define AIPS_PACRO_WP5_MASK   (0x200U)
 
#define AIPS_PACRO_WP5_SHIFT   (9U)
 
#define AIPS_PACRO_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
 
#define AIPS_PACRO_SP5_MASK   (0x400U)
 
#define AIPS_PACRO_SP5_SHIFT   (10U)
 
#define AIPS_PACRO_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
 
#define AIPS_PACRO_TP4_MASK   (0x1000U)
 
#define AIPS_PACRO_TP4_SHIFT   (12U)
 
#define AIPS_PACRO_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
 
#define AIPS_PACRO_WP4_MASK   (0x2000U)
 
#define AIPS_PACRO_WP4_SHIFT   (13U)
 
#define AIPS_PACRO_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
 
#define AIPS_PACRO_SP4_MASK   (0x4000U)
 
#define AIPS_PACRO_SP4_SHIFT   (14U)
 
#define AIPS_PACRO_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
 
#define AIPS_PACRO_TP3_MASK   (0x10000U)
 
#define AIPS_PACRO_TP3_SHIFT   (16U)
 
#define AIPS_PACRO_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
 
#define AIPS_PACRO_WP3_MASK   (0x20000U)
 
#define AIPS_PACRO_WP3_SHIFT   (17U)
 
#define AIPS_PACRO_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
 
#define AIPS_PACRO_SP3_MASK   (0x40000U)
 
#define AIPS_PACRO_SP3_SHIFT   (18U)
 
#define AIPS_PACRO_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
 
#define AIPS_PACRO_TP2_MASK   (0x100000U)
 
#define AIPS_PACRO_TP2_SHIFT   (20U)
 
#define AIPS_PACRO_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
 
#define AIPS_PACRO_WP2_MASK   (0x200000U)
 
#define AIPS_PACRO_WP2_SHIFT   (21U)
 
#define AIPS_PACRO_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
 
#define AIPS_PACRO_SP2_MASK   (0x400000U)
 
#define AIPS_PACRO_SP2_SHIFT   (22U)
 
#define AIPS_PACRO_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
 
#define AIPS_PACRO_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRO_TP1_SHIFT   (24U)
 
#define AIPS_PACRO_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
 
#define AIPS_PACRO_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRO_WP1_SHIFT   (25U)
 
#define AIPS_PACRO_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
 
#define AIPS_PACRO_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRO_SP1_SHIFT   (26U)
 
#define AIPS_PACRO_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
 
#define AIPS_PACRO_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRO_TP0_SHIFT   (28U)
 
#define AIPS_PACRO_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
 
#define AIPS_PACRO_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRO_WP0_SHIFT   (29U)
 
#define AIPS_PACRO_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
 
#define AIPS_PACRO_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRO_SP0_SHIFT   (30U)
 
#define AIPS_PACRO_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
 
#define AIPS_PACRO_TP7_MASK   (0x1U)
 
#define AIPS_PACRO_TP7_SHIFT   (0U)
 
#define AIPS_PACRO_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
 
#define AIPS_PACRO_WP7_MASK   (0x2U)
 
#define AIPS_PACRO_WP7_SHIFT   (1U)
 
#define AIPS_PACRO_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
 
#define AIPS_PACRO_SP7_MASK   (0x4U)
 
#define AIPS_PACRO_SP7_SHIFT   (2U)
 
#define AIPS_PACRO_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
 
#define AIPS_PACRO_TP6_MASK   (0x10U)
 
#define AIPS_PACRO_TP6_SHIFT   (4U)
 
#define AIPS_PACRO_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
 
#define AIPS_PACRO_WP6_MASK   (0x20U)
 
#define AIPS_PACRO_WP6_SHIFT   (5U)
 
#define AIPS_PACRO_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
 
#define AIPS_PACRO_SP6_MASK   (0x40U)
 
#define AIPS_PACRO_SP6_SHIFT   (6U)
 
#define AIPS_PACRO_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
 
#define AIPS_PACRO_TP5_MASK   (0x100U)
 
#define AIPS_PACRO_TP5_SHIFT   (8U)
 
#define AIPS_PACRO_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
 
#define AIPS_PACRO_WP5_MASK   (0x200U)
 
#define AIPS_PACRO_WP5_SHIFT   (9U)
 
#define AIPS_PACRO_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
 
#define AIPS_PACRO_SP5_MASK   (0x400U)
 
#define AIPS_PACRO_SP5_SHIFT   (10U)
 
#define AIPS_PACRO_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
 
#define AIPS_PACRO_TP4_MASK   (0x1000U)
 
#define AIPS_PACRO_TP4_SHIFT   (12U)
 
#define AIPS_PACRO_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
 
#define AIPS_PACRO_WP4_MASK   (0x2000U)
 
#define AIPS_PACRO_WP4_SHIFT   (13U)
 
#define AIPS_PACRO_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
 
#define AIPS_PACRO_SP4_MASK   (0x4000U)
 
#define AIPS_PACRO_SP4_SHIFT   (14U)
 
#define AIPS_PACRO_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
 
#define AIPS_PACRO_TP3_MASK   (0x10000U)
 
#define AIPS_PACRO_TP3_SHIFT   (16U)
 
#define AIPS_PACRO_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
 
#define AIPS_PACRO_WP3_MASK   (0x20000U)
 
#define AIPS_PACRO_WP3_SHIFT   (17U)
 
#define AIPS_PACRO_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
 
#define AIPS_PACRO_SP3_MASK   (0x40000U)
 
#define AIPS_PACRO_SP3_SHIFT   (18U)
 
#define AIPS_PACRO_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
 
#define AIPS_PACRO_TP2_MASK   (0x100000U)
 
#define AIPS_PACRO_TP2_SHIFT   (20U)
 
#define AIPS_PACRO_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
 
#define AIPS_PACRO_WP2_MASK   (0x200000U)
 
#define AIPS_PACRO_WP2_SHIFT   (21U)
 
#define AIPS_PACRO_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
 
#define AIPS_PACRO_SP2_MASK   (0x400000U)
 
#define AIPS_PACRO_SP2_SHIFT   (22U)
 
#define AIPS_PACRO_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
 
#define AIPS_PACRO_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRO_TP1_SHIFT   (24U)
 
#define AIPS_PACRO_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
 
#define AIPS_PACRO_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRO_WP1_SHIFT   (25U)
 
#define AIPS_PACRO_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
 
#define AIPS_PACRO_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRO_SP1_SHIFT   (26U)
 
#define AIPS_PACRO_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
 
#define AIPS_PACRO_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRO_TP0_SHIFT   (28U)
 
#define AIPS_PACRO_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
 
#define AIPS_PACRO_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRO_WP0_SHIFT   (29U)
 
#define AIPS_PACRO_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
 
#define AIPS_PACRO_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRO_SP0_SHIFT   (30U)
 
#define AIPS_PACRO_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
 
#define AIPS_PACRO_TP7_MASK   (0x1U)
 
#define AIPS_PACRO_TP7_SHIFT   (0U)
 
#define AIPS_PACRO_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
 
#define AIPS_PACRO_WP7_MASK   (0x2U)
 
#define AIPS_PACRO_WP7_SHIFT   (1U)
 
#define AIPS_PACRO_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
 
#define AIPS_PACRO_SP7_MASK   (0x4U)
 
#define AIPS_PACRO_SP7_SHIFT   (2U)
 
#define AIPS_PACRO_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
 
#define AIPS_PACRO_TP6_MASK   (0x10U)
 
#define AIPS_PACRO_TP6_SHIFT   (4U)
 
#define AIPS_PACRO_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
 
#define AIPS_PACRO_WP6_MASK   (0x20U)
 
#define AIPS_PACRO_WP6_SHIFT   (5U)
 
#define AIPS_PACRO_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
 
#define AIPS_PACRO_SP6_MASK   (0x40U)
 
#define AIPS_PACRO_SP6_SHIFT   (6U)
 
#define AIPS_PACRO_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
 
#define AIPS_PACRO_TP5_MASK   (0x100U)
 
#define AIPS_PACRO_TP5_SHIFT   (8U)
 
#define AIPS_PACRO_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
 
#define AIPS_PACRO_WP5_MASK   (0x200U)
 
#define AIPS_PACRO_WP5_SHIFT   (9U)
 
#define AIPS_PACRO_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
 
#define AIPS_PACRO_SP5_MASK   (0x400U)
 
#define AIPS_PACRO_SP5_SHIFT   (10U)
 
#define AIPS_PACRO_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
 
#define AIPS_PACRO_TP4_MASK   (0x1000U)
 
#define AIPS_PACRO_TP4_SHIFT   (12U)
 
#define AIPS_PACRO_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
 
#define AIPS_PACRO_WP4_MASK   (0x2000U)
 
#define AIPS_PACRO_WP4_SHIFT   (13U)
 
#define AIPS_PACRO_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
 
#define AIPS_PACRO_SP4_MASK   (0x4000U)
 
#define AIPS_PACRO_SP4_SHIFT   (14U)
 
#define AIPS_PACRO_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
 
#define AIPS_PACRO_TP3_MASK   (0x10000U)
 
#define AIPS_PACRO_TP3_SHIFT   (16U)
 
#define AIPS_PACRO_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
 
#define AIPS_PACRO_WP3_MASK   (0x20000U)
 
#define AIPS_PACRO_WP3_SHIFT   (17U)
 
#define AIPS_PACRO_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
 
#define AIPS_PACRO_SP3_MASK   (0x40000U)
 
#define AIPS_PACRO_SP3_SHIFT   (18U)
 
#define AIPS_PACRO_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
 
#define AIPS_PACRO_TP2_MASK   (0x100000U)
 
#define AIPS_PACRO_TP2_SHIFT   (20U)
 
#define AIPS_PACRO_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
 
#define AIPS_PACRO_WP2_MASK   (0x200000U)
 
#define AIPS_PACRO_WP2_SHIFT   (21U)
 
#define AIPS_PACRO_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
 
#define AIPS_PACRO_SP2_MASK   (0x400000U)
 
#define AIPS_PACRO_SP2_SHIFT   (22U)
 
#define AIPS_PACRO_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
 
#define AIPS_PACRO_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRO_TP1_SHIFT   (24U)
 
#define AIPS_PACRO_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
 
#define AIPS_PACRO_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRO_WP1_SHIFT   (25U)
 
#define AIPS_PACRO_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
 
#define AIPS_PACRO_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRO_SP1_SHIFT   (26U)
 
#define AIPS_PACRO_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
 
#define AIPS_PACRO_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRO_TP0_SHIFT   (28U)
 
#define AIPS_PACRO_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
 
#define AIPS_PACRO_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRO_WP0_SHIFT   (29U)
 
#define AIPS_PACRO_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
 
#define AIPS_PACRO_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRO_SP0_SHIFT   (30U)
 
#define AIPS_PACRO_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
 
#define AIPS_PACRO_TP7_MASK   (0x1U)
 
#define AIPS_PACRO_TP7_SHIFT   (0U)
 
#define AIPS_PACRO_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
 
#define AIPS_PACRO_WP7_MASK   (0x2U)
 
#define AIPS_PACRO_WP7_SHIFT   (1U)
 
#define AIPS_PACRO_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
 
#define AIPS_PACRO_SP7_MASK   (0x4U)
 
#define AIPS_PACRO_SP7_SHIFT   (2U)
 
#define AIPS_PACRO_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
 
#define AIPS_PACRO_TP6_MASK   (0x10U)
 
#define AIPS_PACRO_TP6_SHIFT   (4U)
 
#define AIPS_PACRO_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
 
#define AIPS_PACRO_WP6_MASK   (0x20U)
 
#define AIPS_PACRO_WP6_SHIFT   (5U)
 
#define AIPS_PACRO_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
 
#define AIPS_PACRO_SP6_MASK   (0x40U)
 
#define AIPS_PACRO_SP6_SHIFT   (6U)
 
#define AIPS_PACRO_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
 
#define AIPS_PACRO_TP5_MASK   (0x100U)
 
#define AIPS_PACRO_TP5_SHIFT   (8U)
 
#define AIPS_PACRO_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
 
#define AIPS_PACRO_WP5_MASK   (0x200U)
 
#define AIPS_PACRO_WP5_SHIFT   (9U)
 
#define AIPS_PACRO_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
 
#define AIPS_PACRO_SP5_MASK   (0x400U)
 
#define AIPS_PACRO_SP5_SHIFT   (10U)
 
#define AIPS_PACRO_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
 
#define AIPS_PACRO_TP4_MASK   (0x1000U)
 
#define AIPS_PACRO_TP4_SHIFT   (12U)
 
#define AIPS_PACRO_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
 
#define AIPS_PACRO_WP4_MASK   (0x2000U)
 
#define AIPS_PACRO_WP4_SHIFT   (13U)
 
#define AIPS_PACRO_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
 
#define AIPS_PACRO_SP4_MASK   (0x4000U)
 
#define AIPS_PACRO_SP4_SHIFT   (14U)
 
#define AIPS_PACRO_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
 
#define AIPS_PACRO_TP3_MASK   (0x10000U)
 
#define AIPS_PACRO_TP3_SHIFT   (16U)
 
#define AIPS_PACRO_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
 
#define AIPS_PACRO_WP3_MASK   (0x20000U)
 
#define AIPS_PACRO_WP3_SHIFT   (17U)
 
#define AIPS_PACRO_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
 
#define AIPS_PACRO_SP3_MASK   (0x40000U)
 
#define AIPS_PACRO_SP3_SHIFT   (18U)
 
#define AIPS_PACRO_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
 
#define AIPS_PACRO_TP2_MASK   (0x100000U)
 
#define AIPS_PACRO_TP2_SHIFT   (20U)
 
#define AIPS_PACRO_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
 
#define AIPS_PACRO_WP2_MASK   (0x200000U)
 
#define AIPS_PACRO_WP2_SHIFT   (21U)
 
#define AIPS_PACRO_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
 
#define AIPS_PACRO_SP2_MASK   (0x400000U)
 
#define AIPS_PACRO_SP2_SHIFT   (22U)
 
#define AIPS_PACRO_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
 
#define AIPS_PACRO_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRO_TP1_SHIFT   (24U)
 
#define AIPS_PACRO_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
 
#define AIPS_PACRO_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRO_WP1_SHIFT   (25U)
 
#define AIPS_PACRO_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
 
#define AIPS_PACRO_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRO_SP1_SHIFT   (26U)
 
#define AIPS_PACRO_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
 
#define AIPS_PACRO_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRO_TP0_SHIFT   (28U)
 
#define AIPS_PACRO_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
 
#define AIPS_PACRO_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRO_WP0_SHIFT   (29U)
 
#define AIPS_PACRO_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
 
#define AIPS_PACRO_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRO_SP0_SHIFT   (30U)
 
#define AIPS_PACRO_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
 

PACRP - Peripheral Access Control Register

#define AIPS_PACRP_TP7_MASK   (0x1U)
 
#define AIPS_PACRP_TP7_SHIFT   (0U)
 
#define AIPS_PACRP_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
 
#define AIPS_PACRP_WP7_MASK   (0x2U)
 
#define AIPS_PACRP_WP7_SHIFT   (1U)
 
#define AIPS_PACRP_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
 
#define AIPS_PACRP_SP7_MASK   (0x4U)
 
#define AIPS_PACRP_SP7_SHIFT   (2U)
 
#define AIPS_PACRP_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
 
#define AIPS_PACRP_TP6_MASK   (0x10U)
 
#define AIPS_PACRP_TP6_SHIFT   (4U)
 
#define AIPS_PACRP_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
 
#define AIPS_PACRP_WP6_MASK   (0x20U)
 
#define AIPS_PACRP_WP6_SHIFT   (5U)
 
#define AIPS_PACRP_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
 
#define AIPS_PACRP_SP6_MASK   (0x40U)
 
#define AIPS_PACRP_SP6_SHIFT   (6U)
 
#define AIPS_PACRP_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
 
#define AIPS_PACRP_TP5_MASK   (0x100U)
 
#define AIPS_PACRP_TP5_SHIFT   (8U)
 
#define AIPS_PACRP_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
 
#define AIPS_PACRP_WP5_MASK   (0x200U)
 
#define AIPS_PACRP_WP5_SHIFT   (9U)
 
#define AIPS_PACRP_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
 
#define AIPS_PACRP_SP5_MASK   (0x400U)
 
#define AIPS_PACRP_SP5_SHIFT   (10U)
 
#define AIPS_PACRP_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
 
#define AIPS_PACRP_TP4_MASK   (0x1000U)
 
#define AIPS_PACRP_TP4_SHIFT   (12U)
 
#define AIPS_PACRP_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
 
#define AIPS_PACRP_WP4_MASK   (0x2000U)
 
#define AIPS_PACRP_WP4_SHIFT   (13U)
 
#define AIPS_PACRP_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
 
#define AIPS_PACRP_SP4_MASK   (0x4000U)
 
#define AIPS_PACRP_SP4_SHIFT   (14U)
 
#define AIPS_PACRP_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
 
#define AIPS_PACRP_TP3_MASK   (0x10000U)
 
#define AIPS_PACRP_TP3_SHIFT   (16U)
 
#define AIPS_PACRP_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
 
#define AIPS_PACRP_WP3_MASK   (0x20000U)
 
#define AIPS_PACRP_WP3_SHIFT   (17U)
 
#define AIPS_PACRP_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
 
#define AIPS_PACRP_SP3_MASK   (0x40000U)
 
#define AIPS_PACRP_SP3_SHIFT   (18U)
 
#define AIPS_PACRP_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
 
#define AIPS_PACRP_TP2_MASK   (0x100000U)
 
#define AIPS_PACRP_TP2_SHIFT   (20U)
 
#define AIPS_PACRP_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
 
#define AIPS_PACRP_WP2_MASK   (0x200000U)
 
#define AIPS_PACRP_WP2_SHIFT   (21U)
 
#define AIPS_PACRP_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
 
#define AIPS_PACRP_SP2_MASK   (0x400000U)
 
#define AIPS_PACRP_SP2_SHIFT   (22U)
 
#define AIPS_PACRP_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
 
#define AIPS_PACRP_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRP_TP1_SHIFT   (24U)
 
#define AIPS_PACRP_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
 
#define AIPS_PACRP_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRP_WP1_SHIFT   (25U)
 
#define AIPS_PACRP_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
 
#define AIPS_PACRP_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRP_SP1_SHIFT   (26U)
 
#define AIPS_PACRP_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
 
#define AIPS_PACRP_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRP_TP0_SHIFT   (28U)
 
#define AIPS_PACRP_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
 
#define AIPS_PACRP_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRP_WP0_SHIFT   (29U)
 
#define AIPS_PACRP_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
 
#define AIPS_PACRP_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRP_SP0_SHIFT   (30U)
 
#define AIPS_PACRP_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
 
#define AIPS_PACRP_TP7_MASK   0x1u
 
#define AIPS_PACRP_TP7_SHIFT   0
 
#define AIPS_PACRP_WP7_MASK   0x2u
 
#define AIPS_PACRP_WP7_SHIFT   1
 
#define AIPS_PACRP_SP7_MASK   0x4u
 
#define AIPS_PACRP_SP7_SHIFT   2
 
#define AIPS_PACRP_TP6_MASK   0x10u
 
#define AIPS_PACRP_TP6_SHIFT   4
 
#define AIPS_PACRP_WP6_MASK   0x20u
 
#define AIPS_PACRP_WP6_SHIFT   5
 
#define AIPS_PACRP_SP6_MASK   0x40u
 
#define AIPS_PACRP_SP6_SHIFT   6
 
#define AIPS_PACRP_TP5_MASK   0x100u
 
#define AIPS_PACRP_TP5_SHIFT   8
 
#define AIPS_PACRP_WP5_MASK   0x200u
 
#define AIPS_PACRP_WP5_SHIFT   9
 
#define AIPS_PACRP_SP5_MASK   0x400u
 
#define AIPS_PACRP_SP5_SHIFT   10
 
#define AIPS_PACRP_TP4_MASK   0x1000u
 
#define AIPS_PACRP_TP4_SHIFT   12
 
#define AIPS_PACRP_WP4_MASK   0x2000u
 
#define AIPS_PACRP_WP4_SHIFT   13
 
#define AIPS_PACRP_SP4_MASK   0x4000u
 
#define AIPS_PACRP_SP4_SHIFT   14
 
#define AIPS_PACRP_TP3_MASK   0x10000u
 
#define AIPS_PACRP_TP3_SHIFT   16
 
#define AIPS_PACRP_WP3_MASK   0x20000u
 
#define AIPS_PACRP_WP3_SHIFT   17
 
#define AIPS_PACRP_SP3_MASK   0x40000u
 
#define AIPS_PACRP_SP3_SHIFT   18
 
#define AIPS_PACRP_TP2_MASK   0x100000u
 
#define AIPS_PACRP_TP2_SHIFT   20
 
#define AIPS_PACRP_WP2_MASK   0x200000u
 
#define AIPS_PACRP_WP2_SHIFT   21
 
#define AIPS_PACRP_SP2_MASK   0x400000u
 
#define AIPS_PACRP_SP2_SHIFT   22
 
#define AIPS_PACRP_TP1_MASK   0x1000000u
 
#define AIPS_PACRP_TP1_SHIFT   24
 
#define AIPS_PACRP_WP1_MASK   0x2000000u
 
#define AIPS_PACRP_WP1_SHIFT   25
 
#define AIPS_PACRP_SP1_MASK   0x4000000u
 
#define AIPS_PACRP_SP1_SHIFT   26
 
#define AIPS_PACRP_TP0_MASK   0x10000000u
 
#define AIPS_PACRP_TP0_SHIFT   28
 
#define AIPS_PACRP_WP0_MASK   0x20000000u
 
#define AIPS_PACRP_WP0_SHIFT   29
 
#define AIPS_PACRP_SP0_MASK   0x40000000u
 
#define AIPS_PACRP_SP0_SHIFT   30
 
#define AIPS_PACRP_TP7_MASK   (0x1U)
 
#define AIPS_PACRP_TP7_SHIFT   (0U)
 
#define AIPS_PACRP_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
 
#define AIPS_PACRP_WP7_MASK   (0x2U)
 
#define AIPS_PACRP_WP7_SHIFT   (1U)
 
#define AIPS_PACRP_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
 
#define AIPS_PACRP_SP7_MASK   (0x4U)
 
#define AIPS_PACRP_SP7_SHIFT   (2U)
 
#define AIPS_PACRP_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
 
#define AIPS_PACRP_TP6_MASK   (0x10U)
 
#define AIPS_PACRP_TP6_SHIFT   (4U)
 
#define AIPS_PACRP_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
 
#define AIPS_PACRP_WP6_MASK   (0x20U)
 
#define AIPS_PACRP_WP6_SHIFT   (5U)
 
#define AIPS_PACRP_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
 
#define AIPS_PACRP_SP6_MASK   (0x40U)
 
#define AIPS_PACRP_SP6_SHIFT   (6U)
 
#define AIPS_PACRP_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
 
#define AIPS_PACRP_TP5_MASK   (0x100U)
 
#define AIPS_PACRP_TP5_SHIFT   (8U)
 
#define AIPS_PACRP_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
 
#define AIPS_PACRP_WP5_MASK   (0x200U)
 
#define AIPS_PACRP_WP5_SHIFT   (9U)
 
#define AIPS_PACRP_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
 
#define AIPS_PACRP_SP5_MASK   (0x400U)
 
#define AIPS_PACRP_SP5_SHIFT   (10U)
 
#define AIPS_PACRP_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
 
#define AIPS_PACRP_TP4_MASK   (0x1000U)
 
#define AIPS_PACRP_TP4_SHIFT   (12U)
 
#define AIPS_PACRP_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
 
#define AIPS_PACRP_WP4_MASK   (0x2000U)
 
#define AIPS_PACRP_WP4_SHIFT   (13U)
 
#define AIPS_PACRP_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
 
#define AIPS_PACRP_SP4_MASK   (0x4000U)
 
#define AIPS_PACRP_SP4_SHIFT   (14U)
 
#define AIPS_PACRP_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
 
#define AIPS_PACRP_TP3_MASK   (0x10000U)
 
#define AIPS_PACRP_TP3_SHIFT   (16U)
 
#define AIPS_PACRP_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
 
#define AIPS_PACRP_WP3_MASK   (0x20000U)
 
#define AIPS_PACRP_WP3_SHIFT   (17U)
 
#define AIPS_PACRP_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
 
#define AIPS_PACRP_SP3_MASK   (0x40000U)
 
#define AIPS_PACRP_SP3_SHIFT   (18U)
 
#define AIPS_PACRP_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
 
#define AIPS_PACRP_TP2_MASK   (0x100000U)
 
#define AIPS_PACRP_TP2_SHIFT   (20U)
 
#define AIPS_PACRP_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
 
#define AIPS_PACRP_WP2_MASK   (0x200000U)
 
#define AIPS_PACRP_WP2_SHIFT   (21U)
 
#define AIPS_PACRP_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
 
#define AIPS_PACRP_SP2_MASK   (0x400000U)
 
#define AIPS_PACRP_SP2_SHIFT   (22U)
 
#define AIPS_PACRP_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
 
#define AIPS_PACRP_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRP_TP1_SHIFT   (24U)
 
#define AIPS_PACRP_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
 
#define AIPS_PACRP_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRP_WP1_SHIFT   (25U)
 
#define AIPS_PACRP_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
 
#define AIPS_PACRP_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRP_SP1_SHIFT   (26U)
 
#define AIPS_PACRP_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
 
#define AIPS_PACRP_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRP_TP0_SHIFT   (28U)
 
#define AIPS_PACRP_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
 
#define AIPS_PACRP_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRP_WP0_SHIFT   (29U)
 
#define AIPS_PACRP_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
 
#define AIPS_PACRP_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRP_SP0_SHIFT   (30U)
 
#define AIPS_PACRP_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
 
#define AIPS_PACRP_TP7_MASK   (0x1U)
 
#define AIPS_PACRP_TP7_SHIFT   (0U)
 
#define AIPS_PACRP_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
 
#define AIPS_PACRP_WP7_MASK   (0x2U)
 
#define AIPS_PACRP_WP7_SHIFT   (1U)
 
#define AIPS_PACRP_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
 
#define AIPS_PACRP_SP7_MASK   (0x4U)
 
#define AIPS_PACRP_SP7_SHIFT   (2U)
 
#define AIPS_PACRP_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
 
#define AIPS_PACRP_TP6_MASK   (0x10U)
 
#define AIPS_PACRP_TP6_SHIFT   (4U)
 
#define AIPS_PACRP_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
 
#define AIPS_PACRP_WP6_MASK   (0x20U)
 
#define AIPS_PACRP_WP6_SHIFT   (5U)
 
#define AIPS_PACRP_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
 
#define AIPS_PACRP_SP6_MASK   (0x40U)
 
#define AIPS_PACRP_SP6_SHIFT   (6U)
 
#define AIPS_PACRP_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
 
#define AIPS_PACRP_TP5_MASK   (0x100U)
 
#define AIPS_PACRP_TP5_SHIFT   (8U)
 
#define AIPS_PACRP_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
 
#define AIPS_PACRP_WP5_MASK   (0x200U)
 
#define AIPS_PACRP_WP5_SHIFT   (9U)
 
#define AIPS_PACRP_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
 
#define AIPS_PACRP_SP5_MASK   (0x400U)
 
#define AIPS_PACRP_SP5_SHIFT   (10U)
 
#define AIPS_PACRP_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
 
#define AIPS_PACRP_TP4_MASK   (0x1000U)
 
#define AIPS_PACRP_TP4_SHIFT   (12U)
 
#define AIPS_PACRP_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
 
#define AIPS_PACRP_WP4_MASK   (0x2000U)
 
#define AIPS_PACRP_WP4_SHIFT   (13U)
 
#define AIPS_PACRP_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
 
#define AIPS_PACRP_SP4_MASK   (0x4000U)
 
#define AIPS_PACRP_SP4_SHIFT   (14U)
 
#define AIPS_PACRP_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
 
#define AIPS_PACRP_TP3_MASK   (0x10000U)
 
#define AIPS_PACRP_TP3_SHIFT   (16U)
 
#define AIPS_PACRP_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
 
#define AIPS_PACRP_WP3_MASK   (0x20000U)
 
#define AIPS_PACRP_WP3_SHIFT   (17U)
 
#define AIPS_PACRP_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
 
#define AIPS_PACRP_SP3_MASK   (0x40000U)
 
#define AIPS_PACRP_SP3_SHIFT   (18U)
 
#define AIPS_PACRP_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
 
#define AIPS_PACRP_TP2_MASK   (0x100000U)
 
#define AIPS_PACRP_TP2_SHIFT   (20U)
 
#define AIPS_PACRP_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
 
#define AIPS_PACRP_WP2_MASK   (0x200000U)
 
#define AIPS_PACRP_WP2_SHIFT   (21U)
 
#define AIPS_PACRP_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
 
#define AIPS_PACRP_SP2_MASK   (0x400000U)
 
#define AIPS_PACRP_SP2_SHIFT   (22U)
 
#define AIPS_PACRP_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
 
#define AIPS_PACRP_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRP_TP1_SHIFT   (24U)
 
#define AIPS_PACRP_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
 
#define AIPS_PACRP_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRP_WP1_SHIFT   (25U)
 
#define AIPS_PACRP_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
 
#define AIPS_PACRP_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRP_SP1_SHIFT   (26U)
 
#define AIPS_PACRP_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
 
#define AIPS_PACRP_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRP_TP0_SHIFT   (28U)
 
#define AIPS_PACRP_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
 
#define AIPS_PACRP_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRP_WP0_SHIFT   (29U)
 
#define AIPS_PACRP_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
 
#define AIPS_PACRP_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRP_SP0_SHIFT   (30U)
 
#define AIPS_PACRP_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
 
#define AIPS_PACRP_TP7_MASK   (0x1U)
 
#define AIPS_PACRP_TP7_SHIFT   (0U)
 
#define AIPS_PACRP_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
 
#define AIPS_PACRP_WP7_MASK   (0x2U)
 
#define AIPS_PACRP_WP7_SHIFT   (1U)
 
#define AIPS_PACRP_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
 
#define AIPS_PACRP_SP7_MASK   (0x4U)
 
#define AIPS_PACRP_SP7_SHIFT   (2U)
 
#define AIPS_PACRP_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
 
#define AIPS_PACRP_TP6_MASK   (0x10U)
 
#define AIPS_PACRP_TP6_SHIFT   (4U)
 
#define AIPS_PACRP_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
 
#define AIPS_PACRP_WP6_MASK   (0x20U)
 
#define AIPS_PACRP_WP6_SHIFT   (5U)
 
#define AIPS_PACRP_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
 
#define AIPS_PACRP_SP6_MASK   (0x40U)
 
#define AIPS_PACRP_SP6_SHIFT   (6U)
 
#define AIPS_PACRP_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
 
#define AIPS_PACRP_TP5_MASK   (0x100U)
 
#define AIPS_PACRP_TP5_SHIFT   (8U)
 
#define AIPS_PACRP_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
 
#define AIPS_PACRP_WP5_MASK   (0x200U)
 
#define AIPS_PACRP_WP5_SHIFT   (9U)
 
#define AIPS_PACRP_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
 
#define AIPS_PACRP_SP5_MASK   (0x400U)
 
#define AIPS_PACRP_SP5_SHIFT   (10U)
 
#define AIPS_PACRP_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
 
#define AIPS_PACRP_TP4_MASK   (0x1000U)
 
#define AIPS_PACRP_TP4_SHIFT   (12U)
 
#define AIPS_PACRP_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
 
#define AIPS_PACRP_WP4_MASK   (0x2000U)
 
#define AIPS_PACRP_WP4_SHIFT   (13U)
 
#define AIPS_PACRP_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
 
#define AIPS_PACRP_SP4_MASK   (0x4000U)
 
#define AIPS_PACRP_SP4_SHIFT   (14U)
 
#define AIPS_PACRP_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
 
#define AIPS_PACRP_TP3_MASK   (0x10000U)
 
#define AIPS_PACRP_TP3_SHIFT   (16U)
 
#define AIPS_PACRP_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
 
#define AIPS_PACRP_WP3_MASK   (0x20000U)
 
#define AIPS_PACRP_WP3_SHIFT   (17U)
 
#define AIPS_PACRP_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
 
#define AIPS_PACRP_SP3_MASK   (0x40000U)
 
#define AIPS_PACRP_SP3_SHIFT   (18U)
 
#define AIPS_PACRP_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
 
#define AIPS_PACRP_TP2_MASK   (0x100000U)
 
#define AIPS_PACRP_TP2_SHIFT   (20U)
 
#define AIPS_PACRP_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
 
#define AIPS_PACRP_WP2_MASK   (0x200000U)
 
#define AIPS_PACRP_WP2_SHIFT   (21U)
 
#define AIPS_PACRP_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
 
#define AIPS_PACRP_SP2_MASK   (0x400000U)
 
#define AIPS_PACRP_SP2_SHIFT   (22U)
 
#define AIPS_PACRP_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
 
#define AIPS_PACRP_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRP_TP1_SHIFT   (24U)
 
#define AIPS_PACRP_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
 
#define AIPS_PACRP_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRP_WP1_SHIFT   (25U)
 
#define AIPS_PACRP_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
 
#define AIPS_PACRP_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRP_SP1_SHIFT   (26U)
 
#define AIPS_PACRP_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
 
#define AIPS_PACRP_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRP_TP0_SHIFT   (28U)
 
#define AIPS_PACRP_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
 
#define AIPS_PACRP_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRP_WP0_SHIFT   (29U)
 
#define AIPS_PACRP_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
 
#define AIPS_PACRP_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRP_SP0_SHIFT   (30U)
 
#define AIPS_PACRP_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
 
#define AIPS_PACRP_TP7_MASK   (0x1U)
 
#define AIPS_PACRP_TP7_SHIFT   (0U)
 
#define AIPS_PACRP_TP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
 
#define AIPS_PACRP_WP7_MASK   (0x2U)
 
#define AIPS_PACRP_WP7_SHIFT   (1U)
 
#define AIPS_PACRP_WP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
 
#define AIPS_PACRP_SP7_MASK   (0x4U)
 
#define AIPS_PACRP_SP7_SHIFT   (2U)
 
#define AIPS_PACRP_SP7(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
 
#define AIPS_PACRP_TP6_MASK   (0x10U)
 
#define AIPS_PACRP_TP6_SHIFT   (4U)
 
#define AIPS_PACRP_TP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
 
#define AIPS_PACRP_WP6_MASK   (0x20U)
 
#define AIPS_PACRP_WP6_SHIFT   (5U)
 
#define AIPS_PACRP_WP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
 
#define AIPS_PACRP_SP6_MASK   (0x40U)
 
#define AIPS_PACRP_SP6_SHIFT   (6U)
 
#define AIPS_PACRP_SP6(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
 
#define AIPS_PACRP_TP5_MASK   (0x100U)
 
#define AIPS_PACRP_TP5_SHIFT   (8U)
 
#define AIPS_PACRP_TP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
 
#define AIPS_PACRP_WP5_MASK   (0x200U)
 
#define AIPS_PACRP_WP5_SHIFT   (9U)
 
#define AIPS_PACRP_WP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
 
#define AIPS_PACRP_SP5_MASK   (0x400U)
 
#define AIPS_PACRP_SP5_SHIFT   (10U)
 
#define AIPS_PACRP_SP5(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
 
#define AIPS_PACRP_TP4_MASK   (0x1000U)
 
#define AIPS_PACRP_TP4_SHIFT   (12U)
 
#define AIPS_PACRP_TP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
 
#define AIPS_PACRP_WP4_MASK   (0x2000U)
 
#define AIPS_PACRP_WP4_SHIFT   (13U)
 
#define AIPS_PACRP_WP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
 
#define AIPS_PACRP_SP4_MASK   (0x4000U)
 
#define AIPS_PACRP_SP4_SHIFT   (14U)
 
#define AIPS_PACRP_SP4(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
 
#define AIPS_PACRP_TP3_MASK   (0x10000U)
 
#define AIPS_PACRP_TP3_SHIFT   (16U)
 
#define AIPS_PACRP_TP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
 
#define AIPS_PACRP_WP3_MASK   (0x20000U)
 
#define AIPS_PACRP_WP3_SHIFT   (17U)
 
#define AIPS_PACRP_WP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
 
#define AIPS_PACRP_SP3_MASK   (0x40000U)
 
#define AIPS_PACRP_SP3_SHIFT   (18U)
 
#define AIPS_PACRP_SP3(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
 
#define AIPS_PACRP_TP2_MASK   (0x100000U)
 
#define AIPS_PACRP_TP2_SHIFT   (20U)
 
#define AIPS_PACRP_TP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
 
#define AIPS_PACRP_WP2_MASK   (0x200000U)
 
#define AIPS_PACRP_WP2_SHIFT   (21U)
 
#define AIPS_PACRP_WP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
 
#define AIPS_PACRP_SP2_MASK   (0x400000U)
 
#define AIPS_PACRP_SP2_SHIFT   (22U)
 
#define AIPS_PACRP_SP2(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
 
#define AIPS_PACRP_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRP_TP1_SHIFT   (24U)
 
#define AIPS_PACRP_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
 
#define AIPS_PACRP_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRP_WP1_SHIFT   (25U)
 
#define AIPS_PACRP_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
 
#define AIPS_PACRP_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRP_SP1_SHIFT   (26U)
 
#define AIPS_PACRP_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
 
#define AIPS_PACRP_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRP_TP0_SHIFT   (28U)
 
#define AIPS_PACRP_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
 
#define AIPS_PACRP_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRP_WP0_SHIFT   (29U)
 
#define AIPS_PACRP_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
 
#define AIPS_PACRP_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRP_SP0_SHIFT   (30U)
 
#define AIPS_PACRP_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
 

PACRU - Peripheral Access Control Register

#define AIPS_PACRU_TP1_MASK   (0x1000000U)
 
#define AIPS_PACRU_TP1_SHIFT   (24U)
 
#define AIPS_PACRU_TP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP1_SHIFT)) & AIPS_PACRU_TP1_MASK)
 
#define AIPS_PACRU_WP1_MASK   (0x2000000U)
 
#define AIPS_PACRU_WP1_SHIFT   (25U)
 
#define AIPS_PACRU_WP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP1_SHIFT)) & AIPS_PACRU_WP1_MASK)
 
#define AIPS_PACRU_SP1_MASK   (0x4000000U)
 
#define AIPS_PACRU_SP1_SHIFT   (26U)
 
#define AIPS_PACRU_SP1(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP1_SHIFT)) & AIPS_PACRU_SP1_MASK)
 
#define AIPS_PACRU_TP0_MASK   (0x10000000U)
 
#define AIPS_PACRU_TP0_SHIFT   (28U)
 
#define AIPS_PACRU_TP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP0_SHIFT)) & AIPS_PACRU_TP0_MASK)
 
#define AIPS_PACRU_WP0_MASK   (0x20000000U)
 
#define AIPS_PACRU_WP0_SHIFT   (29U)
 
#define AIPS_PACRU_WP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP0_SHIFT)) & AIPS_PACRU_WP0_MASK)
 
#define AIPS_PACRU_SP0_MASK   (0x40000000U)
 
#define AIPS_PACRU_SP0_SHIFT   (30U)
 
#define AIPS_PACRU_SP0(x)   (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP0_SHIFT)) & AIPS_PACRU_SP0_MASK)
 

Macro Definition Documentation

◆ AIPS0

#define AIPS0   ((AIPS_Type *)AIPS0_BASE)

Peripheral AIPS0 base pointer

◆ AIPS0_BASE

#define AIPS0_BASE   (0x40000000u)

Peripheral AIPS0 base address

◆ AIPS1

#define AIPS1   ((AIPS_Type *)AIPS1_BASE)

Peripheral AIPS1 base pointer

◆ AIPS1_BASE

#define AIPS1_BASE   (0x40080000u)

Peripheral AIPS1 base address

◆ AIPS_BASE_ADDRS

#define AIPS_BASE_ADDRS   { AIPS0_BASE, AIPS1_BASE }

Array initializer of AIPS peripheral base addresses

◆ AIPS_BASE_PTRS

#define AIPS_BASE_PTRS   { AIPS0, AIPS1 }

Array initializer of AIPS peripheral base pointers

◆ AIPS_MPRA_MPL0 [1/5]

#define AIPS_MPRA_MPL0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)

MPL0 - Master 0 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL0 [2/5]

#define AIPS_MPRA_MPL0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)

MPL0 - Master 0 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL0 [3/5]

#define AIPS_MPRA_MPL0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)

MPL0 - Master 0 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL0 [4/5]

#define AIPS_MPRA_MPL0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)

MPL0 - Master 0 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL0 [5/5]

#define AIPS_MPRA_MPL0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)

MPL0 - Master 0 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL1 [1/5]

#define AIPS_MPRA_MPL1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)

MPL1 - Master 1 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL1 [2/5]

#define AIPS_MPRA_MPL1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)

MPL1 - Master 1 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL1 [3/5]

#define AIPS_MPRA_MPL1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)

MPL1 - Master 1 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL1 [4/5]

#define AIPS_MPRA_MPL1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)

MPL1 - Master 1 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL1 [5/5]

#define AIPS_MPRA_MPL1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)

MPL1 - Master 1 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL2 [1/5]

#define AIPS_MPRA_MPL2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)

MPL2 - Master 2 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL2 [2/5]

#define AIPS_MPRA_MPL2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)

MPL2 - Master 2 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL2 [3/5]

#define AIPS_MPRA_MPL2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)

MPL2 - Master 2 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL2 [4/5]

#define AIPS_MPRA_MPL2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)

MPL2 - Master 2 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL2 [5/5]

#define AIPS_MPRA_MPL2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)

MPL2 - Master 2 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL3 [1/5]

#define AIPS_MPRA_MPL3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)

MPL3 - Master 3 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL3 [2/5]

#define AIPS_MPRA_MPL3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)

MPL3 - Master 3 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL3 [3/5]

#define AIPS_MPRA_MPL3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)

MPL3 - Master 3 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL3 [4/5]

#define AIPS_MPRA_MPL3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)

MPL3 - Master 3 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL3 [5/5]

#define AIPS_MPRA_MPL3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)

MPL3 - Master 3 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL4 [1/4]

#define AIPS_MPRA_MPL4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)

MPL4 - Master 4 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL4 [2/4]

#define AIPS_MPRA_MPL4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)

MPL4 - Master 4 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL4 [3/4]

#define AIPS_MPRA_MPL4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)

MPL4 - Master 4 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL4 [4/4]

#define AIPS_MPRA_MPL4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)

MPL4 - Master 4 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL5 [1/4]

#define AIPS_MPRA_MPL5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)

MPL5 - Master 5 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL5 [2/4]

#define AIPS_MPRA_MPL5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)

MPL5 - Master 5 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL5 [3/4]

#define AIPS_MPRA_MPL5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)

MPL5 - Master 5 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL5 [4/4]

#define AIPS_MPRA_MPL5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)

MPL5 - Master 5 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL6 [1/2]

#define AIPS_MPRA_MPL6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)

MPL6 - Master 6 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MPL6 [2/2]

#define AIPS_MPRA_MPL6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)

MPL6 - Master 6 Privilege Level 0b0..Accesses from this master are forced to user-mode. 0b1..Accesses from this master are not forced to user-mode.

◆ AIPS_MPRA_MTR0 [1/5]

#define AIPS_MPRA_MTR0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)

MTR0 - Master 0 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR0 [2/5]

#define AIPS_MPRA_MTR0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)

MTR0 - Master 0 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR0 [3/5]

#define AIPS_MPRA_MTR0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)

MTR0 - Master 0 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR0 [4/5]

#define AIPS_MPRA_MTR0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)

MTR0 - Master 0 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR0 [5/5]

#define AIPS_MPRA_MTR0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)

MTR0 - Master 0 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR1 [1/5]

#define AIPS_MPRA_MTR1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)

MTR1 - Master 1 Trusted for Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR1 [2/5]

#define AIPS_MPRA_MTR1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)

MTR1 - Master 1 Trusted for Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR1 [3/5]

#define AIPS_MPRA_MTR1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)

MTR1 - Master 1 Trusted for Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR1 [4/5]

#define AIPS_MPRA_MTR1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)

MTR1 - Master 1 Trusted for Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR1 [5/5]

#define AIPS_MPRA_MTR1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)

MTR1 - Master 1 Trusted for Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR2 [1/5]

#define AIPS_MPRA_MTR2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)

MTR2 - Master 2 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR2 [2/5]

#define AIPS_MPRA_MTR2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)

MTR2 - Master 2 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR2 [3/5]

#define AIPS_MPRA_MTR2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)

MTR2 - Master 2 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR2 [4/5]

#define AIPS_MPRA_MTR2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)

MTR2 - Master 2 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR2 [5/5]

#define AIPS_MPRA_MTR2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)

MTR2 - Master 2 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR3 [1/5]

#define AIPS_MPRA_MTR3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)

MTR3 - Master 3 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR3 [2/5]

#define AIPS_MPRA_MTR3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)

MTR3 - Master 3 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR3 [3/5]

#define AIPS_MPRA_MTR3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)

MTR3 - Master 3 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR3 [4/5]

#define AIPS_MPRA_MTR3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)

MTR3 - Master 3 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR3 [5/5]

#define AIPS_MPRA_MTR3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)

MTR3 - Master 3 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR4 [1/4]

#define AIPS_MPRA_MTR4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)

MTR4 - Master 4 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR4 [2/4]

#define AIPS_MPRA_MTR4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)

MTR4 - Master 4 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR4 [3/4]

#define AIPS_MPRA_MTR4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)

MTR4 - Master 4 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR4 [4/4]

#define AIPS_MPRA_MTR4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)

MTR4 - Master 4 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR5 [1/4]

#define AIPS_MPRA_MTR5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)

MTR5 - Master 5 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR5 [2/4]

#define AIPS_MPRA_MTR5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)

MTR5 - Master 5 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR5 [3/4]

#define AIPS_MPRA_MTR5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)

MTR5 - Master 5 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR5 [4/4]

#define AIPS_MPRA_MTR5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)

MTR5 - Master 5 Trusted For Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR6 [1/2]

#define AIPS_MPRA_MTR6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)

MTR6 - Master 6 Trusted for Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTR6 [2/2]

#define AIPS_MPRA_MTR6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)

MTR6 - Master 6 Trusted for Read 0b0..This master is not trusted for read accesses. 0b1..This master is trusted for read accesses.

◆ AIPS_MPRA_MTW0 [1/5]

#define AIPS_MPRA_MTW0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)

MTW0 - Master 0 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW0 [2/5]

#define AIPS_MPRA_MTW0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)

MTW0 - Master 0 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW0 [3/5]

#define AIPS_MPRA_MTW0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)

MTW0 - Master 0 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW0 [4/5]

#define AIPS_MPRA_MTW0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)

MTW0 - Master 0 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW0 [5/5]

#define AIPS_MPRA_MTW0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)

MTW0 - Master 0 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW1 [1/5]

#define AIPS_MPRA_MTW1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)

MTW1 - Master 1 Trusted for Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW1 [2/5]

#define AIPS_MPRA_MTW1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)

MTW1 - Master 1 Trusted for Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW1 [3/5]

#define AIPS_MPRA_MTW1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)

MTW1 - Master 1 Trusted for Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW1 [4/5]

#define AIPS_MPRA_MTW1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)

MTW1 - Master 1 Trusted for Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW1 [5/5]

#define AIPS_MPRA_MTW1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)

MTW1 - Master 1 Trusted for Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW2 [1/5]

#define AIPS_MPRA_MTW2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)

MTW2 - Master 2 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW2 [2/5]

#define AIPS_MPRA_MTW2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)

MTW2 - Master 2 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW2 [3/5]

#define AIPS_MPRA_MTW2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)

MTW2 - Master 2 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW2 [4/5]

#define AIPS_MPRA_MTW2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)

MTW2 - Master 2 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW2 [5/5]

#define AIPS_MPRA_MTW2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)

MTW2 - Master 2 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW3 [1/5]

#define AIPS_MPRA_MTW3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)

MTW3 - Master 3 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW3 [2/5]

#define AIPS_MPRA_MTW3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)

MTW3 - Master 3 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW3 [3/5]

#define AIPS_MPRA_MTW3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)

MTW3 - Master 3 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW3 [4/5]

#define AIPS_MPRA_MTW3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)

MTW3 - Master 3 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW3 [5/5]

#define AIPS_MPRA_MTW3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)

MTW3 - Master 3 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW4 [1/4]

#define AIPS_MPRA_MTW4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)

MTW4 - Master 4 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW4 [2/4]

#define AIPS_MPRA_MTW4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)

MTW4 - Master 4 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW4 [3/4]

#define AIPS_MPRA_MTW4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)

MTW4 - Master 4 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW4 [4/4]

#define AIPS_MPRA_MTW4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)

MTW4 - Master 4 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW5 [1/4]

#define AIPS_MPRA_MTW5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)

MTW5 - Master 5 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW5 [2/4]

#define AIPS_MPRA_MTW5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)

MTW5 - Master 5 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW5 [3/4]

#define AIPS_MPRA_MTW5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)

MTW5 - Master 5 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW5 [4/4]

#define AIPS_MPRA_MTW5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)

MTW5 - Master 5 Trusted For Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW6 [1/2]

#define AIPS_MPRA_MTW6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)

MTW6 - Master 6 Trusted for Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_MPRA_MTW6 [2/2]

#define AIPS_MPRA_MTW6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)

MTW6 - Master 6 Trusted for Writes 0b0..This master is not trusted for write accesses. 0b1..This master is trusted for write accesses.

◆ AIPS_PACRA_SP0 [1/5]

#define AIPS_PACRA_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP0 [2/5]

#define AIPS_PACRA_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP0 [3/5]

#define AIPS_PACRA_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP0 [4/5]

#define AIPS_PACRA_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP0 [5/5]

#define AIPS_PACRA_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP1 [1/5]

#define AIPS_PACRA_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP1 [2/5]

#define AIPS_PACRA_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP1 [3/5]

#define AIPS_PACRA_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP1 [4/5]

#define AIPS_PACRA_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP1 [5/5]

#define AIPS_PACRA_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP2 [1/5]

#define AIPS_PACRA_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP2 [2/5]

#define AIPS_PACRA_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP2 [3/5]

#define AIPS_PACRA_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP2 [4/5]

#define AIPS_PACRA_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP2 [5/5]

#define AIPS_PACRA_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP3 [1/5]

#define AIPS_PACRA_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP3 [2/5]

#define AIPS_PACRA_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP3 [3/5]

#define AIPS_PACRA_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP3 [4/5]

#define AIPS_PACRA_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP3 [5/5]

#define AIPS_PACRA_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP4 [1/5]

#define AIPS_PACRA_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP4 [2/5]

#define AIPS_PACRA_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP4 [3/5]

#define AIPS_PACRA_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP4 [4/5]

#define AIPS_PACRA_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP4 [5/5]

#define AIPS_PACRA_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP5 [1/5]

#define AIPS_PACRA_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP5 [2/5]

#define AIPS_PACRA_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP5 [3/5]

#define AIPS_PACRA_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP5 [4/5]

#define AIPS_PACRA_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP5 [5/5]

#define AIPS_PACRA_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP6 [1/5]

#define AIPS_PACRA_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP6 [2/5]

#define AIPS_PACRA_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP6 [3/5]

#define AIPS_PACRA_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP6 [4/5]

#define AIPS_PACRA_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP6 [5/5]

#define AIPS_PACRA_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP7 [1/5]

#define AIPS_PACRA_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP7 [2/5]

#define AIPS_PACRA_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP7 [3/5]

#define AIPS_PACRA_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP7 [4/5]

#define AIPS_PACRA_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_SP7 [5/5]

#define AIPS_PACRA_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRA_TP0 [1/5]

#define AIPS_PACRA_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP0 [2/5]

#define AIPS_PACRA_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP0 [3/5]

#define AIPS_PACRA_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP0 [4/5]

#define AIPS_PACRA_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP0 [5/5]

#define AIPS_PACRA_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP1 [1/5]

#define AIPS_PACRA_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP1 [2/5]

#define AIPS_PACRA_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP1 [3/5]

#define AIPS_PACRA_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP1 [4/5]

#define AIPS_PACRA_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP1 [5/5]

#define AIPS_PACRA_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP2 [1/5]

#define AIPS_PACRA_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP2 [2/5]

#define AIPS_PACRA_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP2 [3/5]

#define AIPS_PACRA_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP2 [4/5]

#define AIPS_PACRA_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP2 [5/5]

#define AIPS_PACRA_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP3 [1/5]

#define AIPS_PACRA_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP3 [2/5]

#define AIPS_PACRA_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP3 [3/5]

#define AIPS_PACRA_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP3 [4/5]

#define AIPS_PACRA_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP3 [5/5]

#define AIPS_PACRA_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP4 [1/5]

#define AIPS_PACRA_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP4 [2/5]

#define AIPS_PACRA_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP4 [3/5]

#define AIPS_PACRA_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP4 [4/5]

#define AIPS_PACRA_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP4 [5/5]

#define AIPS_PACRA_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP5 [1/5]

#define AIPS_PACRA_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP5 [2/5]

#define AIPS_PACRA_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP5 [3/5]

#define AIPS_PACRA_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP5 [4/5]

#define AIPS_PACRA_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP5 [5/5]

#define AIPS_PACRA_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP6 [1/5]

#define AIPS_PACRA_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP6 [2/5]

#define AIPS_PACRA_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP6 [3/5]

#define AIPS_PACRA_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP6 [4/5]

#define AIPS_PACRA_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP6 [5/5]

#define AIPS_PACRA_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP7 [1/5]

#define AIPS_PACRA_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP7 [2/5]

#define AIPS_PACRA_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP7 [3/5]

#define AIPS_PACRA_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP7 [4/5]

#define AIPS_PACRA_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_TP7 [5/5]

#define AIPS_PACRA_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRA_WP0 [1/5]

#define AIPS_PACRA_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP0 [2/5]

#define AIPS_PACRA_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP0 [3/5]

#define AIPS_PACRA_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP0 [4/5]

#define AIPS_PACRA_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP0 [5/5]

#define AIPS_PACRA_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP1 [1/5]

#define AIPS_PACRA_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP1 [2/5]

#define AIPS_PACRA_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP1 [3/5]

#define AIPS_PACRA_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP1 [4/5]

#define AIPS_PACRA_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP1 [5/5]

#define AIPS_PACRA_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP2 [1/5]

#define AIPS_PACRA_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP2 [2/5]

#define AIPS_PACRA_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP2 [3/5]

#define AIPS_PACRA_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP2 [4/5]

#define AIPS_PACRA_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP2 [5/5]

#define AIPS_PACRA_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP3 [1/5]

#define AIPS_PACRA_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP3 [2/5]

#define AIPS_PACRA_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP3 [3/5]

#define AIPS_PACRA_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP3 [4/5]

#define AIPS_PACRA_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP3 [5/5]

#define AIPS_PACRA_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP4 [1/5]

#define AIPS_PACRA_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP4 [2/5]

#define AIPS_PACRA_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP4 [3/5]

#define AIPS_PACRA_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP4 [4/5]

#define AIPS_PACRA_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP4 [5/5]

#define AIPS_PACRA_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP5 [1/5]

#define AIPS_PACRA_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP5 [2/5]

#define AIPS_PACRA_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP5 [3/5]

#define AIPS_PACRA_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP5 [4/5]

#define AIPS_PACRA_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP5 [5/5]

#define AIPS_PACRA_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP6 [1/5]

#define AIPS_PACRA_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP6 [2/5]

#define AIPS_PACRA_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP6 [3/5]

#define AIPS_PACRA_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP6 [4/5]

#define AIPS_PACRA_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP6 [5/5]

#define AIPS_PACRA_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP7 [1/5]

#define AIPS_PACRA_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP7 [2/5]

#define AIPS_PACRA_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP7 [3/5]

#define AIPS_PACRA_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP7 [4/5]

#define AIPS_PACRA_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRA_WP7 [5/5]

#define AIPS_PACRA_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_SP0 [1/5]

#define AIPS_PACRB_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP0 [2/5]

#define AIPS_PACRB_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP0 [3/5]

#define AIPS_PACRB_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP0 [4/5]

#define AIPS_PACRB_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP0 [5/5]

#define AIPS_PACRB_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP1 [1/5]

#define AIPS_PACRB_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP1 [2/5]

#define AIPS_PACRB_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP1 [3/5]

#define AIPS_PACRB_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP1 [4/5]

#define AIPS_PACRB_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP1 [5/5]

#define AIPS_PACRB_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP2 [1/5]

#define AIPS_PACRB_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP2 [2/5]

#define AIPS_PACRB_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP2 [3/5]

#define AIPS_PACRB_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP2 [4/5]

#define AIPS_PACRB_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP2 [5/5]

#define AIPS_PACRB_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP3 [1/5]

#define AIPS_PACRB_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP3 [2/5]

#define AIPS_PACRB_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP3 [3/5]

#define AIPS_PACRB_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP3 [4/5]

#define AIPS_PACRB_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP3 [5/5]

#define AIPS_PACRB_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP4 [1/5]

#define AIPS_PACRB_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP4 [2/5]

#define AIPS_PACRB_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP4 [3/5]

#define AIPS_PACRB_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP4 [4/5]

#define AIPS_PACRB_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP4 [5/5]

#define AIPS_PACRB_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP5 [1/5]

#define AIPS_PACRB_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP5 [2/5]

#define AIPS_PACRB_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP5 [3/5]

#define AIPS_PACRB_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP5 [4/5]

#define AIPS_PACRB_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP5 [5/5]

#define AIPS_PACRB_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP6 [1/5]

#define AIPS_PACRB_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP6 [2/5]

#define AIPS_PACRB_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP6 [3/5]

#define AIPS_PACRB_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP6 [4/5]

#define AIPS_PACRB_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP6 [5/5]

#define AIPS_PACRB_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP7 [1/5]

#define AIPS_PACRB_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP7 [2/5]

#define AIPS_PACRB_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP7 [3/5]

#define AIPS_PACRB_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP7 [4/5]

#define AIPS_PACRB_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_SP7 [5/5]

#define AIPS_PACRB_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRB_TP0 [1/5]

#define AIPS_PACRB_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP0 [2/5]

#define AIPS_PACRB_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP0 [3/5]

#define AIPS_PACRB_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP0 [4/5]

#define AIPS_PACRB_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP0 [5/5]

#define AIPS_PACRB_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP1 [1/5]

#define AIPS_PACRB_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP1 [2/5]

#define AIPS_PACRB_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP1 [3/5]

#define AIPS_PACRB_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP1 [4/5]

#define AIPS_PACRB_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP1 [5/5]

#define AIPS_PACRB_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP2 [1/5]

#define AIPS_PACRB_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP2 [2/5]

#define AIPS_PACRB_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP2 [3/5]

#define AIPS_PACRB_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP2 [4/5]

#define AIPS_PACRB_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP2 [5/5]

#define AIPS_PACRB_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP3 [1/5]

#define AIPS_PACRB_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP3 [2/5]

#define AIPS_PACRB_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP3 [3/5]

#define AIPS_PACRB_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP3 [4/5]

#define AIPS_PACRB_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP3 [5/5]

#define AIPS_PACRB_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP4 [1/5]

#define AIPS_PACRB_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP4 [2/5]

#define AIPS_PACRB_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP4 [3/5]

#define AIPS_PACRB_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP4 [4/5]

#define AIPS_PACRB_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP4 [5/5]

#define AIPS_PACRB_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP5 [1/5]

#define AIPS_PACRB_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP5 [2/5]

#define AIPS_PACRB_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP5 [3/5]

#define AIPS_PACRB_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP5 [4/5]

#define AIPS_PACRB_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP5 [5/5]

#define AIPS_PACRB_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP6 [1/5]

#define AIPS_PACRB_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP6 [2/5]

#define AIPS_PACRB_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP6 [3/5]

#define AIPS_PACRB_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP6 [4/5]

#define AIPS_PACRB_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP6 [5/5]

#define AIPS_PACRB_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP7 [1/5]

#define AIPS_PACRB_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP7 [2/5]

#define AIPS_PACRB_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP7 [3/5]

#define AIPS_PACRB_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP7 [4/5]

#define AIPS_PACRB_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_TP7 [5/5]

#define AIPS_PACRB_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRB_WP0 [1/5]

#define AIPS_PACRB_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP0 [2/5]

#define AIPS_PACRB_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP0 [3/5]

#define AIPS_PACRB_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP0 [4/5]

#define AIPS_PACRB_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP0 [5/5]

#define AIPS_PACRB_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP1 [1/5]

#define AIPS_PACRB_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP1 [2/5]

#define AIPS_PACRB_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP1 [3/5]

#define AIPS_PACRB_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP1 [4/5]

#define AIPS_PACRB_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP1 [5/5]

#define AIPS_PACRB_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP2 [1/5]

#define AIPS_PACRB_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP2 [2/5]

#define AIPS_PACRB_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP2 [3/5]

#define AIPS_PACRB_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP2 [4/5]

#define AIPS_PACRB_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP2 [5/5]

#define AIPS_PACRB_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP3 [1/5]

#define AIPS_PACRB_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP3 [2/5]

#define AIPS_PACRB_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP3 [3/5]

#define AIPS_PACRB_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP3 [4/5]

#define AIPS_PACRB_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP3 [5/5]

#define AIPS_PACRB_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP4 [1/5]

#define AIPS_PACRB_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP4 [2/5]

#define AIPS_PACRB_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP4 [3/5]

#define AIPS_PACRB_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP4 [4/5]

#define AIPS_PACRB_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP4 [5/5]

#define AIPS_PACRB_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP5 [1/5]

#define AIPS_PACRB_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP5 [2/5]

#define AIPS_PACRB_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP5 [3/5]

#define AIPS_PACRB_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP5 [4/5]

#define AIPS_PACRB_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP5 [5/5]

#define AIPS_PACRB_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP6 [1/5]

#define AIPS_PACRB_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP6 [2/5]

#define AIPS_PACRB_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP6 [3/5]

#define AIPS_PACRB_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP6 [4/5]

#define AIPS_PACRB_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP6 [5/5]

#define AIPS_PACRB_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP7 [1/5]

#define AIPS_PACRB_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP7 [2/5]

#define AIPS_PACRB_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP7 [3/5]

#define AIPS_PACRB_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP7 [4/5]

#define AIPS_PACRB_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRB_WP7 [5/5]

#define AIPS_PACRB_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_SP0 [1/5]

#define AIPS_PACRC_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP0 [2/5]

#define AIPS_PACRC_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP0 [3/5]

#define AIPS_PACRC_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP0 [4/5]

#define AIPS_PACRC_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP0 [5/5]

#define AIPS_PACRC_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP1 [1/5]

#define AIPS_PACRC_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP1 [2/5]

#define AIPS_PACRC_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP1 [3/5]

#define AIPS_PACRC_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP1 [4/5]

#define AIPS_PACRC_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP1 [5/5]

#define AIPS_PACRC_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP2 [1/5]

#define AIPS_PACRC_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP2 [2/5]

#define AIPS_PACRC_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP2 [3/5]

#define AIPS_PACRC_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP2 [4/5]

#define AIPS_PACRC_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP2 [5/5]

#define AIPS_PACRC_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP3 [1/5]

#define AIPS_PACRC_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP3 [2/5]

#define AIPS_PACRC_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP3 [3/5]

#define AIPS_PACRC_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP3 [4/5]

#define AIPS_PACRC_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP3 [5/5]

#define AIPS_PACRC_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP4 [1/5]

#define AIPS_PACRC_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP4 [2/5]

#define AIPS_PACRC_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP4 [3/5]

#define AIPS_PACRC_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP4 [4/5]

#define AIPS_PACRC_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP4 [5/5]

#define AIPS_PACRC_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP5 [1/5]

#define AIPS_PACRC_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP5 [2/5]

#define AIPS_PACRC_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP5 [3/5]

#define AIPS_PACRC_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP5 [4/5]

#define AIPS_PACRC_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP5 [5/5]

#define AIPS_PACRC_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP6 [1/5]

#define AIPS_PACRC_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP6 [2/5]

#define AIPS_PACRC_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP6 [3/5]

#define AIPS_PACRC_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP6 [4/5]

#define AIPS_PACRC_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP6 [5/5]

#define AIPS_PACRC_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP7 [1/5]

#define AIPS_PACRC_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP7 [2/5]

#define AIPS_PACRC_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP7 [3/5]

#define AIPS_PACRC_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP7 [4/5]

#define AIPS_PACRC_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_SP7 [5/5]

#define AIPS_PACRC_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRC_TP0 [1/5]

#define AIPS_PACRC_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP0 [2/5]

#define AIPS_PACRC_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP0 [3/5]

#define AIPS_PACRC_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP0 [4/5]

#define AIPS_PACRC_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP0 [5/5]

#define AIPS_PACRC_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP1 [1/5]

#define AIPS_PACRC_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP1 [2/5]

#define AIPS_PACRC_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP1 [3/5]

#define AIPS_PACRC_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP1 [4/5]

#define AIPS_PACRC_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP1 [5/5]

#define AIPS_PACRC_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP2 [1/5]

#define AIPS_PACRC_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP2 [2/5]

#define AIPS_PACRC_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP2 [3/5]

#define AIPS_PACRC_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP2 [4/5]

#define AIPS_PACRC_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP2 [5/5]

#define AIPS_PACRC_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP3 [1/5]

#define AIPS_PACRC_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP3 [2/5]

#define AIPS_PACRC_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP3 [3/5]

#define AIPS_PACRC_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP3 [4/5]

#define AIPS_PACRC_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP3 [5/5]

#define AIPS_PACRC_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP4 [1/5]

#define AIPS_PACRC_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP4 [2/5]

#define AIPS_PACRC_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP4 [3/5]

#define AIPS_PACRC_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP4 [4/5]

#define AIPS_PACRC_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP4 [5/5]

#define AIPS_PACRC_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP5 [1/5]

#define AIPS_PACRC_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP5 [2/5]

#define AIPS_PACRC_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP5 [3/5]

#define AIPS_PACRC_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP5 [4/5]

#define AIPS_PACRC_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP5 [5/5]

#define AIPS_PACRC_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP6 [1/5]

#define AIPS_PACRC_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP6 [2/5]

#define AIPS_PACRC_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP6 [3/5]

#define AIPS_PACRC_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP6 [4/5]

#define AIPS_PACRC_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP6 [5/5]

#define AIPS_PACRC_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP7 [1/5]

#define AIPS_PACRC_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP7 [2/5]

#define AIPS_PACRC_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP7 [3/5]

#define AIPS_PACRC_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP7 [4/5]

#define AIPS_PACRC_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_TP7 [5/5]

#define AIPS_PACRC_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRC_WP0 [1/5]

#define AIPS_PACRC_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP0 [2/5]

#define AIPS_PACRC_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP0 [3/5]

#define AIPS_PACRC_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP0 [4/5]

#define AIPS_PACRC_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP0 [5/5]

#define AIPS_PACRC_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP1 [1/5]

#define AIPS_PACRC_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP1 [2/5]

#define AIPS_PACRC_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP1 [3/5]

#define AIPS_PACRC_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP1 [4/5]

#define AIPS_PACRC_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP1 [5/5]

#define AIPS_PACRC_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP2 [1/5]

#define AIPS_PACRC_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP2 [2/5]

#define AIPS_PACRC_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP2 [3/5]

#define AIPS_PACRC_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP2 [4/5]

#define AIPS_PACRC_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP2 [5/5]

#define AIPS_PACRC_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP3 [1/5]

#define AIPS_PACRC_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP3 [2/5]

#define AIPS_PACRC_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP3 [3/5]

#define AIPS_PACRC_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP3 [4/5]

#define AIPS_PACRC_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP3 [5/5]

#define AIPS_PACRC_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP4 [1/5]

#define AIPS_PACRC_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP4 [2/5]

#define AIPS_PACRC_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP4 [3/5]

#define AIPS_PACRC_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP4 [4/5]

#define AIPS_PACRC_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP4 [5/5]

#define AIPS_PACRC_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP5 [1/5]

#define AIPS_PACRC_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP5 [2/5]

#define AIPS_PACRC_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP5 [3/5]

#define AIPS_PACRC_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP5 [4/5]

#define AIPS_PACRC_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP5 [5/5]

#define AIPS_PACRC_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP6 [1/5]

#define AIPS_PACRC_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP6 [2/5]

#define AIPS_PACRC_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP6 [3/5]

#define AIPS_PACRC_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP6 [4/5]

#define AIPS_PACRC_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP6 [5/5]

#define AIPS_PACRC_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP7 [1/5]

#define AIPS_PACRC_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP7 [2/5]

#define AIPS_PACRC_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP7 [3/5]

#define AIPS_PACRC_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP7 [4/5]

#define AIPS_PACRC_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRC_WP7 [5/5]

#define AIPS_PACRC_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_SP0 [1/5]

#define AIPS_PACRD_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP0 [2/5]

#define AIPS_PACRD_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP0 [3/5]

#define AIPS_PACRD_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP0 [4/5]

#define AIPS_PACRD_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP0 [5/5]

#define AIPS_PACRD_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP1 [1/5]

#define AIPS_PACRD_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP1 [2/5]

#define AIPS_PACRD_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP1 [3/5]

#define AIPS_PACRD_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP1 [4/5]

#define AIPS_PACRD_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP1 [5/5]

#define AIPS_PACRD_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP2 [1/5]

#define AIPS_PACRD_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP2 [2/5]

#define AIPS_PACRD_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP2 [3/5]

#define AIPS_PACRD_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP2 [4/5]

#define AIPS_PACRD_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP2 [5/5]

#define AIPS_PACRD_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP3 [1/5]

#define AIPS_PACRD_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP3 [2/5]

#define AIPS_PACRD_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP3 [3/5]

#define AIPS_PACRD_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP3 [4/5]

#define AIPS_PACRD_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP3 [5/5]

#define AIPS_PACRD_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP4 [1/5]

#define AIPS_PACRD_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP4 [2/5]

#define AIPS_PACRD_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP4 [3/5]

#define AIPS_PACRD_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP4 [4/5]

#define AIPS_PACRD_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP4 [5/5]

#define AIPS_PACRD_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP5 [1/5]

#define AIPS_PACRD_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP5 [2/5]

#define AIPS_PACRD_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP5 [3/5]

#define AIPS_PACRD_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP5 [4/5]

#define AIPS_PACRD_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP5 [5/5]

#define AIPS_PACRD_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP6 [1/5]

#define AIPS_PACRD_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP6 [2/5]

#define AIPS_PACRD_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP6 [3/5]

#define AIPS_PACRD_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP6 [4/5]

#define AIPS_PACRD_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP6 [5/5]

#define AIPS_PACRD_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP7 [1/5]

#define AIPS_PACRD_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP7 [2/5]

#define AIPS_PACRD_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP7 [3/5]

#define AIPS_PACRD_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP7 [4/5]

#define AIPS_PACRD_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_SP7 [5/5]

#define AIPS_PACRD_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRD_TP0 [1/5]

#define AIPS_PACRD_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP0 [2/5]

#define AIPS_PACRD_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP0 [3/5]

#define AIPS_PACRD_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP0 [4/5]

#define AIPS_PACRD_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP0 [5/5]

#define AIPS_PACRD_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP1 [1/5]

#define AIPS_PACRD_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP1 [2/5]

#define AIPS_PACRD_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP1 [3/5]

#define AIPS_PACRD_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP1 [4/5]

#define AIPS_PACRD_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP1 [5/5]

#define AIPS_PACRD_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP2 [1/5]

#define AIPS_PACRD_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP2 [2/5]

#define AIPS_PACRD_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP2 [3/5]

#define AIPS_PACRD_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP2 [4/5]

#define AIPS_PACRD_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP2 [5/5]

#define AIPS_PACRD_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP3 [1/5]

#define AIPS_PACRD_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP3 [2/5]

#define AIPS_PACRD_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP3 [3/5]

#define AIPS_PACRD_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP3 [4/5]

#define AIPS_PACRD_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP3 [5/5]

#define AIPS_PACRD_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP4 [1/5]

#define AIPS_PACRD_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP4 [2/5]

#define AIPS_PACRD_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP4 [3/5]

#define AIPS_PACRD_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP4 [4/5]

#define AIPS_PACRD_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP4 [5/5]

#define AIPS_PACRD_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP5 [1/5]

#define AIPS_PACRD_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP5 [2/5]

#define AIPS_PACRD_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP5 [3/5]

#define AIPS_PACRD_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP5 [4/5]

#define AIPS_PACRD_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP5 [5/5]

#define AIPS_PACRD_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP6 [1/5]

#define AIPS_PACRD_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP6 [2/5]

#define AIPS_PACRD_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP6 [3/5]

#define AIPS_PACRD_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP6 [4/5]

#define AIPS_PACRD_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP6 [5/5]

#define AIPS_PACRD_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP7 [1/5]

#define AIPS_PACRD_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP7 [2/5]

#define AIPS_PACRD_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP7 [3/5]

#define AIPS_PACRD_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP7 [4/5]

#define AIPS_PACRD_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_TP7 [5/5]

#define AIPS_PACRD_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRD_WP0 [1/5]

#define AIPS_PACRD_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP0 [2/5]

#define AIPS_PACRD_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP0 [3/5]

#define AIPS_PACRD_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP0 [4/5]

#define AIPS_PACRD_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP0 [5/5]

#define AIPS_PACRD_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP1 [1/5]

#define AIPS_PACRD_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP1 [2/5]

#define AIPS_PACRD_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP1 [3/5]

#define AIPS_PACRD_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP1 [4/5]

#define AIPS_PACRD_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP1 [5/5]

#define AIPS_PACRD_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP2 [1/5]

#define AIPS_PACRD_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP2 [2/5]

#define AIPS_PACRD_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP2 [3/5]

#define AIPS_PACRD_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP2 [4/5]

#define AIPS_PACRD_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP2 [5/5]

#define AIPS_PACRD_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP3 [1/5]

#define AIPS_PACRD_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP3 [2/5]

#define AIPS_PACRD_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP3 [3/5]

#define AIPS_PACRD_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP3 [4/5]

#define AIPS_PACRD_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP3 [5/5]

#define AIPS_PACRD_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP4 [1/5]

#define AIPS_PACRD_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP4 [2/5]

#define AIPS_PACRD_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP4 [3/5]

#define AIPS_PACRD_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP4 [4/5]

#define AIPS_PACRD_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP4 [5/5]

#define AIPS_PACRD_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP5 [1/5]

#define AIPS_PACRD_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP5 [2/5]

#define AIPS_PACRD_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP5 [3/5]

#define AIPS_PACRD_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP5 [4/5]

#define AIPS_PACRD_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP5 [5/5]

#define AIPS_PACRD_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP6 [1/5]

#define AIPS_PACRD_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP6 [2/5]

#define AIPS_PACRD_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP6 [3/5]

#define AIPS_PACRD_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP6 [4/5]

#define AIPS_PACRD_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP6 [5/5]

#define AIPS_PACRD_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP7 [1/5]

#define AIPS_PACRD_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP7 [2/5]

#define AIPS_PACRD_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP7 [3/5]

#define AIPS_PACRD_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP7 [4/5]

#define AIPS_PACRD_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRD_WP7 [5/5]

#define AIPS_PACRD_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_SP0 [1/5]

#define AIPS_PACRE_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP0 [2/5]

#define AIPS_PACRE_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP0 [3/5]

#define AIPS_PACRE_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP0 [4/5]

#define AIPS_PACRE_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP0 [5/5]

#define AIPS_PACRE_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP1 [1/5]

#define AIPS_PACRE_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP1 [2/5]

#define AIPS_PACRE_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP1 [3/5]

#define AIPS_PACRE_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP1 [4/5]

#define AIPS_PACRE_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP1 [5/5]

#define AIPS_PACRE_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP2 [1/5]

#define AIPS_PACRE_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP2 [2/5]

#define AIPS_PACRE_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP2 [3/5]

#define AIPS_PACRE_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP2 [4/5]

#define AIPS_PACRE_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP2 [5/5]

#define AIPS_PACRE_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP3 [1/5]

#define AIPS_PACRE_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP3 [2/5]

#define AIPS_PACRE_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP3 [3/5]

#define AIPS_PACRE_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP3 [4/5]

#define AIPS_PACRE_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP3 [5/5]

#define AIPS_PACRE_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP4 [1/5]

#define AIPS_PACRE_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP4 [2/5]

#define AIPS_PACRE_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP4 [3/5]

#define AIPS_PACRE_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP4 [4/5]

#define AIPS_PACRE_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP4 [5/5]

#define AIPS_PACRE_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP5 [1/5]

#define AIPS_PACRE_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP5 [2/5]

#define AIPS_PACRE_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP5 [3/5]

#define AIPS_PACRE_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP5 [4/5]

#define AIPS_PACRE_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP5 [5/5]

#define AIPS_PACRE_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP6 [1/5]

#define AIPS_PACRE_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP6 [2/5]

#define AIPS_PACRE_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP6 [3/5]

#define AIPS_PACRE_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP6 [4/5]

#define AIPS_PACRE_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP6 [5/5]

#define AIPS_PACRE_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP7 [1/5]

#define AIPS_PACRE_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP7 [2/5]

#define AIPS_PACRE_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP7 [3/5]

#define AIPS_PACRE_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP7 [4/5]

#define AIPS_PACRE_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_SP7 [5/5]

#define AIPS_PACRE_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRE_TP0 [1/5]

#define AIPS_PACRE_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP0 [2/5]

#define AIPS_PACRE_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP0 [3/5]

#define AIPS_PACRE_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP0 [4/5]

#define AIPS_PACRE_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP0 [5/5]

#define AIPS_PACRE_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP1 [1/5]

#define AIPS_PACRE_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP1 [2/5]

#define AIPS_PACRE_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP1 [3/5]

#define AIPS_PACRE_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP1 [4/5]

#define AIPS_PACRE_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP1 [5/5]

#define AIPS_PACRE_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP2 [1/5]

#define AIPS_PACRE_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP2 [2/5]

#define AIPS_PACRE_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP2 [3/5]

#define AIPS_PACRE_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP2 [4/5]

#define AIPS_PACRE_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP2 [5/5]

#define AIPS_PACRE_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP3 [1/5]

#define AIPS_PACRE_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP3 [2/5]

#define AIPS_PACRE_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP3 [3/5]

#define AIPS_PACRE_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP3 [4/5]

#define AIPS_PACRE_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP3 [5/5]

#define AIPS_PACRE_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP4 [1/5]

#define AIPS_PACRE_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP4 [2/5]

#define AIPS_PACRE_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP4 [3/5]

#define AIPS_PACRE_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP4 [4/5]

#define AIPS_PACRE_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP4 [5/5]

#define AIPS_PACRE_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP5 [1/5]

#define AIPS_PACRE_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP5 [2/5]

#define AIPS_PACRE_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP5 [3/5]

#define AIPS_PACRE_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP5 [4/5]

#define AIPS_PACRE_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP5 [5/5]

#define AIPS_PACRE_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP6 [1/5]

#define AIPS_PACRE_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP6 [2/5]

#define AIPS_PACRE_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP6 [3/5]

#define AIPS_PACRE_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP6 [4/5]

#define AIPS_PACRE_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP6 [5/5]

#define AIPS_PACRE_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP7 [1/5]

#define AIPS_PACRE_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP7 [2/5]

#define AIPS_PACRE_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP7 [3/5]

#define AIPS_PACRE_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP7 [4/5]

#define AIPS_PACRE_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_TP7 [5/5]

#define AIPS_PACRE_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRE_WP0 [1/5]

#define AIPS_PACRE_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP0 [2/5]

#define AIPS_PACRE_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP0 [3/5]

#define AIPS_PACRE_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP0 [4/5]

#define AIPS_PACRE_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP0 [5/5]

#define AIPS_PACRE_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP1 [1/5]

#define AIPS_PACRE_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP1 [2/5]

#define AIPS_PACRE_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP1 [3/5]

#define AIPS_PACRE_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP1 [4/5]

#define AIPS_PACRE_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP1 [5/5]

#define AIPS_PACRE_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP2 [1/5]

#define AIPS_PACRE_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP2 [2/5]

#define AIPS_PACRE_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP2 [3/5]

#define AIPS_PACRE_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP2 [4/5]

#define AIPS_PACRE_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP2 [5/5]

#define AIPS_PACRE_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP3 [1/5]

#define AIPS_PACRE_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP3 [2/5]

#define AIPS_PACRE_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP3 [3/5]

#define AIPS_PACRE_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP3 [4/5]

#define AIPS_PACRE_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP3 [5/5]

#define AIPS_PACRE_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP4 [1/5]

#define AIPS_PACRE_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP4 [2/5]

#define AIPS_PACRE_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP4 [3/5]

#define AIPS_PACRE_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP4 [4/5]

#define AIPS_PACRE_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP4 [5/5]

#define AIPS_PACRE_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP5 [1/5]

#define AIPS_PACRE_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP5 [2/5]

#define AIPS_PACRE_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP5 [3/5]

#define AIPS_PACRE_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP5 [4/5]

#define AIPS_PACRE_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP5 [5/5]

#define AIPS_PACRE_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP6 [1/5]

#define AIPS_PACRE_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP6 [2/5]

#define AIPS_PACRE_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP6 [3/5]

#define AIPS_PACRE_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP6 [4/5]

#define AIPS_PACRE_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP6 [5/5]

#define AIPS_PACRE_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP7 [1/5]

#define AIPS_PACRE_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP7 [2/5]

#define AIPS_PACRE_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP7 [3/5]

#define AIPS_PACRE_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP7 [4/5]

#define AIPS_PACRE_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRE_WP7 [5/5]

#define AIPS_PACRE_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_SP0 [1/5]

#define AIPS_PACRF_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP0 [2/5]

#define AIPS_PACRF_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP0 [3/5]

#define AIPS_PACRF_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP0 [4/5]

#define AIPS_PACRF_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP0 [5/5]

#define AIPS_PACRF_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP1 [1/5]

#define AIPS_PACRF_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP1 [2/5]

#define AIPS_PACRF_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP1 [3/5]

#define AIPS_PACRF_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP1 [4/5]

#define AIPS_PACRF_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP1 [5/5]

#define AIPS_PACRF_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP2 [1/5]

#define AIPS_PACRF_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP2 [2/5]

#define AIPS_PACRF_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP2 [3/5]

#define AIPS_PACRF_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP2 [4/5]

#define AIPS_PACRF_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP2 [5/5]

#define AIPS_PACRF_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP3 [1/5]

#define AIPS_PACRF_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP3 [2/5]

#define AIPS_PACRF_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP3 [3/5]

#define AIPS_PACRF_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP3 [4/5]

#define AIPS_PACRF_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP3 [5/5]

#define AIPS_PACRF_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP4 [1/5]

#define AIPS_PACRF_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP4 [2/5]

#define AIPS_PACRF_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP4 [3/5]

#define AIPS_PACRF_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP4 [4/5]

#define AIPS_PACRF_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP4 [5/5]

#define AIPS_PACRF_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP5 [1/5]

#define AIPS_PACRF_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP5 [2/5]

#define AIPS_PACRF_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP5 [3/5]

#define AIPS_PACRF_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP5 [4/5]

#define AIPS_PACRF_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP5 [5/5]

#define AIPS_PACRF_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP6 [1/5]

#define AIPS_PACRF_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP6 [2/5]

#define AIPS_PACRF_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP6 [3/5]

#define AIPS_PACRF_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP6 [4/5]

#define AIPS_PACRF_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP6 [5/5]

#define AIPS_PACRF_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP7 [1/5]

#define AIPS_PACRF_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP7 [2/5]

#define AIPS_PACRF_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP7 [3/5]

#define AIPS_PACRF_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP7 [4/5]

#define AIPS_PACRF_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_SP7 [5/5]

#define AIPS_PACRF_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRF_TP0 [1/5]

#define AIPS_PACRF_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP0 [2/5]

#define AIPS_PACRF_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP0 [3/5]

#define AIPS_PACRF_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP0 [4/5]

#define AIPS_PACRF_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP0 [5/5]

#define AIPS_PACRF_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP1 [1/5]

#define AIPS_PACRF_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP1 [2/5]

#define AIPS_PACRF_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP1 [3/5]

#define AIPS_PACRF_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP1 [4/5]

#define AIPS_PACRF_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP1 [5/5]

#define AIPS_PACRF_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP2 [1/5]

#define AIPS_PACRF_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP2 [2/5]

#define AIPS_PACRF_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP2 [3/5]

#define AIPS_PACRF_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP2 [4/5]

#define AIPS_PACRF_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP2 [5/5]

#define AIPS_PACRF_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP3 [1/5]

#define AIPS_PACRF_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP3 [2/5]

#define AIPS_PACRF_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP3 [3/5]

#define AIPS_PACRF_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP3 [4/5]

#define AIPS_PACRF_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP3 [5/5]

#define AIPS_PACRF_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP4 [1/5]

#define AIPS_PACRF_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP4 [2/5]

#define AIPS_PACRF_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP4 [3/5]

#define AIPS_PACRF_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP4 [4/5]

#define AIPS_PACRF_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP4 [5/5]

#define AIPS_PACRF_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP5 [1/5]

#define AIPS_PACRF_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP5 [2/5]

#define AIPS_PACRF_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP5 [3/5]

#define AIPS_PACRF_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP5 [4/5]

#define AIPS_PACRF_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP5 [5/5]

#define AIPS_PACRF_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP6 [1/5]

#define AIPS_PACRF_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP6 [2/5]

#define AIPS_PACRF_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP6 [3/5]

#define AIPS_PACRF_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP6 [4/5]

#define AIPS_PACRF_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP6 [5/5]

#define AIPS_PACRF_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP7 [1/5]

#define AIPS_PACRF_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP7 [2/5]

#define AIPS_PACRF_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP7 [3/5]

#define AIPS_PACRF_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP7 [4/5]

#define AIPS_PACRF_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_TP7 [5/5]

#define AIPS_PACRF_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRF_WP0 [1/5]

#define AIPS_PACRF_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP0 [2/5]

#define AIPS_PACRF_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP0 [3/5]

#define AIPS_PACRF_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP0 [4/5]

#define AIPS_PACRF_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP0 [5/5]

#define AIPS_PACRF_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP1 [1/5]

#define AIPS_PACRF_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP1 [2/5]

#define AIPS_PACRF_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP1 [3/5]

#define AIPS_PACRF_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP1 [4/5]

#define AIPS_PACRF_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP1 [5/5]

#define AIPS_PACRF_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP2 [1/5]

#define AIPS_PACRF_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP2 [2/5]

#define AIPS_PACRF_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP2 [3/5]

#define AIPS_PACRF_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP2 [4/5]

#define AIPS_PACRF_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP2 [5/5]

#define AIPS_PACRF_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP3 [1/5]

#define AIPS_PACRF_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP3 [2/5]

#define AIPS_PACRF_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP3 [3/5]

#define AIPS_PACRF_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP3 [4/5]

#define AIPS_PACRF_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP3 [5/5]

#define AIPS_PACRF_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP4 [1/5]

#define AIPS_PACRF_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP4 [2/5]

#define AIPS_PACRF_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP4 [3/5]

#define AIPS_PACRF_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP4 [4/5]

#define AIPS_PACRF_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP4 [5/5]

#define AIPS_PACRF_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP5 [1/5]

#define AIPS_PACRF_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP5 [2/5]

#define AIPS_PACRF_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP5 [3/5]

#define AIPS_PACRF_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP5 [4/5]

#define AIPS_PACRF_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP5 [5/5]

#define AIPS_PACRF_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP6 [1/5]

#define AIPS_PACRF_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP6 [2/5]

#define AIPS_PACRF_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP6 [3/5]

#define AIPS_PACRF_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP6 [4/5]

#define AIPS_PACRF_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP6 [5/5]

#define AIPS_PACRF_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP7 [1/5]

#define AIPS_PACRF_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP7 [2/5]

#define AIPS_PACRF_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP7 [3/5]

#define AIPS_PACRF_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP7 [4/5]

#define AIPS_PACRF_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRF_WP7 [5/5]

#define AIPS_PACRF_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_SP0 [1/5]

#define AIPS_PACRG_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP0 [2/5]

#define AIPS_PACRG_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP0 [3/5]

#define AIPS_PACRG_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP0 [4/5]

#define AIPS_PACRG_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP0 [5/5]

#define AIPS_PACRG_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP1 [1/5]

#define AIPS_PACRG_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP1 [2/5]

#define AIPS_PACRG_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP1 [3/5]

#define AIPS_PACRG_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP1 [4/5]

#define AIPS_PACRG_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP1 [5/5]

#define AIPS_PACRG_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP2 [1/5]

#define AIPS_PACRG_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP2 [2/5]

#define AIPS_PACRG_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP2 [3/5]

#define AIPS_PACRG_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP2 [4/5]

#define AIPS_PACRG_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP2 [5/5]

#define AIPS_PACRG_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP3 [1/5]

#define AIPS_PACRG_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP3 [2/5]

#define AIPS_PACRG_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP3 [3/5]

#define AIPS_PACRG_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP3 [4/5]

#define AIPS_PACRG_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP3 [5/5]

#define AIPS_PACRG_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP4 [1/5]

#define AIPS_PACRG_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP4 [2/5]

#define AIPS_PACRG_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP4 [3/5]

#define AIPS_PACRG_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP4 [4/5]

#define AIPS_PACRG_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP4 [5/5]

#define AIPS_PACRG_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP5 [1/5]

#define AIPS_PACRG_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP5 [2/5]

#define AIPS_PACRG_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP5 [3/5]

#define AIPS_PACRG_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP5 [4/5]

#define AIPS_PACRG_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP5 [5/5]

#define AIPS_PACRG_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP6 [1/5]

#define AIPS_PACRG_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP6 [2/5]

#define AIPS_PACRG_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP6 [3/5]

#define AIPS_PACRG_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP6 [4/5]

#define AIPS_PACRG_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP6 [5/5]

#define AIPS_PACRG_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP7 [1/5]

#define AIPS_PACRG_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP7 [2/5]

#define AIPS_PACRG_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP7 [3/5]

#define AIPS_PACRG_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP7 [4/5]

#define AIPS_PACRG_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_SP7 [5/5]

#define AIPS_PACRG_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRG_TP0 [1/5]

#define AIPS_PACRG_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP0 [2/5]

#define AIPS_PACRG_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP0 [3/5]

#define AIPS_PACRG_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP0 [4/5]

#define AIPS_PACRG_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP0 [5/5]

#define AIPS_PACRG_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP1 [1/5]

#define AIPS_PACRG_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP1 [2/5]

#define AIPS_PACRG_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP1 [3/5]

#define AIPS_PACRG_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP1 [4/5]

#define AIPS_PACRG_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP1 [5/5]

#define AIPS_PACRG_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP2 [1/5]

#define AIPS_PACRG_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP2 [2/5]

#define AIPS_PACRG_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP2 [3/5]

#define AIPS_PACRG_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP2 [4/5]

#define AIPS_PACRG_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP2 [5/5]

#define AIPS_PACRG_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP3 [1/5]

#define AIPS_PACRG_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP3 [2/5]

#define AIPS_PACRG_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP3 [3/5]

#define AIPS_PACRG_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP3 [4/5]

#define AIPS_PACRG_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP3 [5/5]

#define AIPS_PACRG_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP4 [1/5]

#define AIPS_PACRG_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP4 [2/5]

#define AIPS_PACRG_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP4 [3/5]

#define AIPS_PACRG_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP4 [4/5]

#define AIPS_PACRG_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP4 [5/5]

#define AIPS_PACRG_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP5 [1/5]

#define AIPS_PACRG_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP5 [2/5]

#define AIPS_PACRG_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP5 [3/5]

#define AIPS_PACRG_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP5 [4/5]

#define AIPS_PACRG_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP5 [5/5]

#define AIPS_PACRG_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP6 [1/5]

#define AIPS_PACRG_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP6 [2/5]

#define AIPS_PACRG_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP6 [3/5]

#define AIPS_PACRG_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP6 [4/5]

#define AIPS_PACRG_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP6 [5/5]

#define AIPS_PACRG_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP7 [1/5]

#define AIPS_PACRG_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP7 [2/5]

#define AIPS_PACRG_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP7 [3/5]

#define AIPS_PACRG_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP7 [4/5]

#define AIPS_PACRG_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_TP7 [5/5]

#define AIPS_PACRG_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRG_WP0 [1/5]

#define AIPS_PACRG_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP0 [2/5]

#define AIPS_PACRG_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP0 [3/5]

#define AIPS_PACRG_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP0 [4/5]

#define AIPS_PACRG_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP0 [5/5]

#define AIPS_PACRG_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP1 [1/5]

#define AIPS_PACRG_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP1 [2/5]

#define AIPS_PACRG_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP1 [3/5]

#define AIPS_PACRG_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP1 [4/5]

#define AIPS_PACRG_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP1 [5/5]

#define AIPS_PACRG_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP2 [1/5]

#define AIPS_PACRG_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP2 [2/5]

#define AIPS_PACRG_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP2 [3/5]

#define AIPS_PACRG_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP2 [4/5]

#define AIPS_PACRG_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP2 [5/5]

#define AIPS_PACRG_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP3 [1/5]

#define AIPS_PACRG_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP3 [2/5]

#define AIPS_PACRG_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP3 [3/5]

#define AIPS_PACRG_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP3 [4/5]

#define AIPS_PACRG_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP3 [5/5]

#define AIPS_PACRG_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP4 [1/5]

#define AIPS_PACRG_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP4 [2/5]

#define AIPS_PACRG_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP4 [3/5]

#define AIPS_PACRG_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP4 [4/5]

#define AIPS_PACRG_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP4 [5/5]

#define AIPS_PACRG_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP5 [1/5]

#define AIPS_PACRG_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP5 [2/5]

#define AIPS_PACRG_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP5 [3/5]

#define AIPS_PACRG_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP5 [4/5]

#define AIPS_PACRG_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP5 [5/5]

#define AIPS_PACRG_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP6 [1/5]

#define AIPS_PACRG_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP6 [2/5]

#define AIPS_PACRG_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP6 [3/5]

#define AIPS_PACRG_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP6 [4/5]

#define AIPS_PACRG_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP6 [5/5]

#define AIPS_PACRG_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP7 [1/5]

#define AIPS_PACRG_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP7 [2/5]

#define AIPS_PACRG_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP7 [3/5]

#define AIPS_PACRG_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP7 [4/5]

#define AIPS_PACRG_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRG_WP7 [5/5]

#define AIPS_PACRG_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_SP0 [1/5]

#define AIPS_PACRH_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP0 [2/5]

#define AIPS_PACRH_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP0 [3/5]

#define AIPS_PACRH_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP0 [4/5]

#define AIPS_PACRH_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP0 [5/5]

#define AIPS_PACRH_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP1 [1/5]

#define AIPS_PACRH_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP1 [2/5]

#define AIPS_PACRH_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP1 [3/5]

#define AIPS_PACRH_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP1 [4/5]

#define AIPS_PACRH_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP1 [5/5]

#define AIPS_PACRH_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP2 [1/5]

#define AIPS_PACRH_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP2 [2/5]

#define AIPS_PACRH_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP2 [3/5]

#define AIPS_PACRH_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP2 [4/5]

#define AIPS_PACRH_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP2 [5/5]

#define AIPS_PACRH_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP3 [1/5]

#define AIPS_PACRH_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP3 [2/5]

#define AIPS_PACRH_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP3 [3/5]

#define AIPS_PACRH_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP3 [4/5]

#define AIPS_PACRH_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP3 [5/5]

#define AIPS_PACRH_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP4 [1/5]

#define AIPS_PACRH_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP4 [2/5]

#define AIPS_PACRH_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP4 [3/5]

#define AIPS_PACRH_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP4 [4/5]

#define AIPS_PACRH_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP4 [5/5]

#define AIPS_PACRH_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP5 [1/5]

#define AIPS_PACRH_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP5 [2/5]

#define AIPS_PACRH_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP5 [3/5]

#define AIPS_PACRH_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP5 [4/5]

#define AIPS_PACRH_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP5 [5/5]

#define AIPS_PACRH_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP6 [1/5]

#define AIPS_PACRH_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP6 [2/5]

#define AIPS_PACRH_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP6 [3/5]

#define AIPS_PACRH_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP6 [4/5]

#define AIPS_PACRH_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP6 [5/5]

#define AIPS_PACRH_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP7 [1/5]

#define AIPS_PACRH_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP7 [2/5]

#define AIPS_PACRH_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP7 [3/5]

#define AIPS_PACRH_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP7 [4/5]

#define AIPS_PACRH_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_SP7 [5/5]

#define AIPS_PACRH_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRH_TP0 [1/5]

#define AIPS_PACRH_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP0 [2/5]

#define AIPS_PACRH_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP0 [3/5]

#define AIPS_PACRH_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP0 [4/5]

#define AIPS_PACRH_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP0 [5/5]

#define AIPS_PACRH_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP1 [1/5]

#define AIPS_PACRH_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP1 [2/5]

#define AIPS_PACRH_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP1 [3/5]

#define AIPS_PACRH_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP1 [4/5]

#define AIPS_PACRH_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP1 [5/5]

#define AIPS_PACRH_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP2 [1/5]

#define AIPS_PACRH_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP2 [2/5]

#define AIPS_PACRH_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP2 [3/5]

#define AIPS_PACRH_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP2 [4/5]

#define AIPS_PACRH_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP2 [5/5]

#define AIPS_PACRH_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP3 [1/5]

#define AIPS_PACRH_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP3 [2/5]

#define AIPS_PACRH_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP3 [3/5]

#define AIPS_PACRH_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP3 [4/5]

#define AIPS_PACRH_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP3 [5/5]

#define AIPS_PACRH_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP4 [1/5]

#define AIPS_PACRH_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP4 [2/5]

#define AIPS_PACRH_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP4 [3/5]

#define AIPS_PACRH_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP4 [4/5]

#define AIPS_PACRH_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP4 [5/5]

#define AIPS_PACRH_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP5 [1/5]

#define AIPS_PACRH_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP5 [2/5]

#define AIPS_PACRH_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP5 [3/5]

#define AIPS_PACRH_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP5 [4/5]

#define AIPS_PACRH_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP5 [5/5]

#define AIPS_PACRH_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP6 [1/5]

#define AIPS_PACRH_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP6 [2/5]

#define AIPS_PACRH_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP6 [3/5]

#define AIPS_PACRH_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP6 [4/5]

#define AIPS_PACRH_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP6 [5/5]

#define AIPS_PACRH_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP7 [1/5]

#define AIPS_PACRH_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP7 [2/5]

#define AIPS_PACRH_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP7 [3/5]

#define AIPS_PACRH_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP7 [4/5]

#define AIPS_PACRH_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_TP7 [5/5]

#define AIPS_PACRH_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRH_WP0 [1/5]

#define AIPS_PACRH_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP0 [2/5]

#define AIPS_PACRH_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP0 [3/5]

#define AIPS_PACRH_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP0 [4/5]

#define AIPS_PACRH_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP0 [5/5]

#define AIPS_PACRH_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP1 [1/5]

#define AIPS_PACRH_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP1 [2/5]

#define AIPS_PACRH_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP1 [3/5]

#define AIPS_PACRH_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP1 [4/5]

#define AIPS_PACRH_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP1 [5/5]

#define AIPS_PACRH_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP2 [1/5]

#define AIPS_PACRH_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP2 [2/5]

#define AIPS_PACRH_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP2 [3/5]

#define AIPS_PACRH_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP2 [4/5]

#define AIPS_PACRH_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP2 [5/5]

#define AIPS_PACRH_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP3 [1/5]

#define AIPS_PACRH_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP3 [2/5]

#define AIPS_PACRH_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP3 [3/5]

#define AIPS_PACRH_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP3 [4/5]

#define AIPS_PACRH_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP3 [5/5]

#define AIPS_PACRH_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP4 [1/5]

#define AIPS_PACRH_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP4 [2/5]

#define AIPS_PACRH_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP4 [3/5]

#define AIPS_PACRH_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP4 [4/5]

#define AIPS_PACRH_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP4 [5/5]

#define AIPS_PACRH_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP5 [1/5]

#define AIPS_PACRH_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP5 [2/5]

#define AIPS_PACRH_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP5 [3/5]

#define AIPS_PACRH_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP5 [4/5]

#define AIPS_PACRH_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP5 [5/5]

#define AIPS_PACRH_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP6 [1/5]

#define AIPS_PACRH_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP6 [2/5]

#define AIPS_PACRH_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP6 [3/5]

#define AIPS_PACRH_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP6 [4/5]

#define AIPS_PACRH_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP6 [5/5]

#define AIPS_PACRH_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP7 [1/5]

#define AIPS_PACRH_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP7 [2/5]

#define AIPS_PACRH_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP7 [3/5]

#define AIPS_PACRH_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP7 [4/5]

#define AIPS_PACRH_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRH_WP7 [5/5]

#define AIPS_PACRH_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_SP0 [1/5]

#define AIPS_PACRI_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP0 [2/5]

#define AIPS_PACRI_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP0 [3/5]

#define AIPS_PACRI_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP0 [4/5]

#define AIPS_PACRI_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP0 [5/5]

#define AIPS_PACRI_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP1 [1/5]

#define AIPS_PACRI_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP1 [2/5]

#define AIPS_PACRI_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP1 [3/5]

#define AIPS_PACRI_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP1 [4/5]

#define AIPS_PACRI_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP1 [5/5]

#define AIPS_PACRI_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP2 [1/5]

#define AIPS_PACRI_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP2 [2/5]

#define AIPS_PACRI_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP2 [3/5]

#define AIPS_PACRI_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP2 [4/5]

#define AIPS_PACRI_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP2 [5/5]

#define AIPS_PACRI_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP3 [1/5]

#define AIPS_PACRI_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP3 [2/5]

#define AIPS_PACRI_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP3 [3/5]

#define AIPS_PACRI_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP3 [4/5]

#define AIPS_PACRI_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP3 [5/5]

#define AIPS_PACRI_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP4 [1/5]

#define AIPS_PACRI_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP4 [2/5]

#define AIPS_PACRI_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP4 [3/5]

#define AIPS_PACRI_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP4 [4/5]

#define AIPS_PACRI_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP4 [5/5]

#define AIPS_PACRI_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP5 [1/5]

#define AIPS_PACRI_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP5 [2/5]

#define AIPS_PACRI_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP5 [3/5]

#define AIPS_PACRI_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP5 [4/5]

#define AIPS_PACRI_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP5 [5/5]

#define AIPS_PACRI_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP6 [1/5]

#define AIPS_PACRI_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP6 [2/5]

#define AIPS_PACRI_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP6 [3/5]

#define AIPS_PACRI_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP6 [4/5]

#define AIPS_PACRI_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP6 [5/5]

#define AIPS_PACRI_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP7 [1/5]

#define AIPS_PACRI_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP7 [2/5]

#define AIPS_PACRI_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP7 [3/5]

#define AIPS_PACRI_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP7 [4/5]

#define AIPS_PACRI_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_SP7 [5/5]

#define AIPS_PACRI_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRI_TP0 [1/5]

#define AIPS_PACRI_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP0 [2/5]

#define AIPS_PACRI_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP0 [3/5]

#define AIPS_PACRI_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP0 [4/5]

#define AIPS_PACRI_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP0 [5/5]

#define AIPS_PACRI_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP1 [1/5]

#define AIPS_PACRI_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP1 [2/5]

#define AIPS_PACRI_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP1 [3/5]

#define AIPS_PACRI_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP1 [4/5]

#define AIPS_PACRI_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP1 [5/5]

#define AIPS_PACRI_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP2 [1/5]

#define AIPS_PACRI_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP2 [2/5]

#define AIPS_PACRI_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP2 [3/5]

#define AIPS_PACRI_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP2 [4/5]

#define AIPS_PACRI_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP2 [5/5]

#define AIPS_PACRI_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP3 [1/5]

#define AIPS_PACRI_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP3 [2/5]

#define AIPS_PACRI_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP3 [3/5]

#define AIPS_PACRI_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP3 [4/5]

#define AIPS_PACRI_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP3 [5/5]

#define AIPS_PACRI_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP4 [1/5]

#define AIPS_PACRI_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP4 [2/5]

#define AIPS_PACRI_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP4 [3/5]

#define AIPS_PACRI_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP4 [4/5]

#define AIPS_PACRI_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP4 [5/5]

#define AIPS_PACRI_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP5 [1/5]

#define AIPS_PACRI_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP5 [2/5]

#define AIPS_PACRI_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP5 [3/5]

#define AIPS_PACRI_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP5 [4/5]

#define AIPS_PACRI_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP5 [5/5]

#define AIPS_PACRI_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP6 [1/5]

#define AIPS_PACRI_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP6 [2/5]

#define AIPS_PACRI_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP6 [3/5]

#define AIPS_PACRI_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP6 [4/5]

#define AIPS_PACRI_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP6 [5/5]

#define AIPS_PACRI_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP7 [1/5]

#define AIPS_PACRI_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP7 [2/5]

#define AIPS_PACRI_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP7 [3/5]

#define AIPS_PACRI_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP7 [4/5]

#define AIPS_PACRI_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_TP7 [5/5]

#define AIPS_PACRI_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRI_WP0 [1/5]

#define AIPS_PACRI_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP0 [2/5]

#define AIPS_PACRI_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP0 [3/5]

#define AIPS_PACRI_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP0 [4/5]

#define AIPS_PACRI_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP0 [5/5]

#define AIPS_PACRI_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP1 [1/5]

#define AIPS_PACRI_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP1 [2/5]

#define AIPS_PACRI_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP1 [3/5]

#define AIPS_PACRI_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP1 [4/5]

#define AIPS_PACRI_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP1 [5/5]

#define AIPS_PACRI_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP2 [1/5]

#define AIPS_PACRI_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP2 [2/5]

#define AIPS_PACRI_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP2 [3/5]

#define AIPS_PACRI_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP2 [4/5]

#define AIPS_PACRI_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP2 [5/5]

#define AIPS_PACRI_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP3 [1/5]

#define AIPS_PACRI_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP3 [2/5]

#define AIPS_PACRI_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP3 [3/5]

#define AIPS_PACRI_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP3 [4/5]

#define AIPS_PACRI_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP3 [5/5]

#define AIPS_PACRI_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP4 [1/5]

#define AIPS_PACRI_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP4 [2/5]

#define AIPS_PACRI_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP4 [3/5]

#define AIPS_PACRI_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP4 [4/5]

#define AIPS_PACRI_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP4 [5/5]

#define AIPS_PACRI_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP5 [1/5]

#define AIPS_PACRI_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP5 [2/5]

#define AIPS_PACRI_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP5 [3/5]

#define AIPS_PACRI_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP5 [4/5]

#define AIPS_PACRI_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP5 [5/5]

#define AIPS_PACRI_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP6 [1/5]

#define AIPS_PACRI_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP6 [2/5]

#define AIPS_PACRI_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP6 [3/5]

#define AIPS_PACRI_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP6 [4/5]

#define AIPS_PACRI_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP6 [5/5]

#define AIPS_PACRI_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP7 [1/5]

#define AIPS_PACRI_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP7 [2/5]

#define AIPS_PACRI_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP7 [3/5]

#define AIPS_PACRI_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP7 [4/5]

#define AIPS_PACRI_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRI_WP7 [5/5]

#define AIPS_PACRI_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_SP0 [1/5]

#define AIPS_PACRJ_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP0 [2/5]

#define AIPS_PACRJ_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP0 [3/5]

#define AIPS_PACRJ_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP0 [4/5]

#define AIPS_PACRJ_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP0 [5/5]

#define AIPS_PACRJ_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP1 [1/5]

#define AIPS_PACRJ_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP1 [2/5]

#define AIPS_PACRJ_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP1 [3/5]

#define AIPS_PACRJ_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP1 [4/5]

#define AIPS_PACRJ_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP1 [5/5]

#define AIPS_PACRJ_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP2 [1/5]

#define AIPS_PACRJ_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP2 [2/5]

#define AIPS_PACRJ_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP2 [3/5]

#define AIPS_PACRJ_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP2 [4/5]

#define AIPS_PACRJ_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP2 [5/5]

#define AIPS_PACRJ_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP3 [1/5]

#define AIPS_PACRJ_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP3 [2/5]

#define AIPS_PACRJ_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP3 [3/5]

#define AIPS_PACRJ_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP3 [4/5]

#define AIPS_PACRJ_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP3 [5/5]

#define AIPS_PACRJ_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP4 [1/5]

#define AIPS_PACRJ_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP4 [2/5]

#define AIPS_PACRJ_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP4 [3/5]

#define AIPS_PACRJ_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP4 [4/5]

#define AIPS_PACRJ_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP4 [5/5]

#define AIPS_PACRJ_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP5 [1/5]

#define AIPS_PACRJ_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP5 [2/5]

#define AIPS_PACRJ_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP5 [3/5]

#define AIPS_PACRJ_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP5 [4/5]

#define AIPS_PACRJ_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP5 [5/5]

#define AIPS_PACRJ_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP6 [1/5]

#define AIPS_PACRJ_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP6 [2/5]

#define AIPS_PACRJ_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP6 [3/5]

#define AIPS_PACRJ_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP6 [4/5]

#define AIPS_PACRJ_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP6 [5/5]

#define AIPS_PACRJ_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP7 [1/5]

#define AIPS_PACRJ_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP7 [2/5]

#define AIPS_PACRJ_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP7 [3/5]

#define AIPS_PACRJ_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP7 [4/5]

#define AIPS_PACRJ_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_SP7 [5/5]

#define AIPS_PACRJ_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRJ_TP0 [1/5]

#define AIPS_PACRJ_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP0 [2/5]

#define AIPS_PACRJ_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP0 [3/5]

#define AIPS_PACRJ_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP0 [4/5]

#define AIPS_PACRJ_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP0 [5/5]

#define AIPS_PACRJ_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP1 [1/5]

#define AIPS_PACRJ_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP1 [2/5]

#define AIPS_PACRJ_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP1 [3/5]

#define AIPS_PACRJ_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP1 [4/5]

#define AIPS_PACRJ_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP1 [5/5]

#define AIPS_PACRJ_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP2 [1/5]

#define AIPS_PACRJ_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP2 [2/5]

#define AIPS_PACRJ_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP2 [3/5]

#define AIPS_PACRJ_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP2 [4/5]

#define AIPS_PACRJ_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP2 [5/5]

#define AIPS_PACRJ_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP3 [1/5]

#define AIPS_PACRJ_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP3 [2/5]

#define AIPS_PACRJ_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP3 [3/5]

#define AIPS_PACRJ_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP3 [4/5]

#define AIPS_PACRJ_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP3 [5/5]

#define AIPS_PACRJ_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP4 [1/5]

#define AIPS_PACRJ_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP4 [2/5]

#define AIPS_PACRJ_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP4 [3/5]

#define AIPS_PACRJ_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP4 [4/5]

#define AIPS_PACRJ_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP4 [5/5]

#define AIPS_PACRJ_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP5 [1/5]

#define AIPS_PACRJ_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP5 [2/5]

#define AIPS_PACRJ_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP5 [3/5]

#define AIPS_PACRJ_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP5 [4/5]

#define AIPS_PACRJ_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP5 [5/5]

#define AIPS_PACRJ_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP6 [1/5]

#define AIPS_PACRJ_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP6 [2/5]

#define AIPS_PACRJ_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP6 [3/5]

#define AIPS_PACRJ_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP6 [4/5]

#define AIPS_PACRJ_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP6 [5/5]

#define AIPS_PACRJ_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP7 [1/5]

#define AIPS_PACRJ_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP7 [2/5]

#define AIPS_PACRJ_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP7 [3/5]

#define AIPS_PACRJ_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP7 [4/5]

#define AIPS_PACRJ_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_TP7 [5/5]

#define AIPS_PACRJ_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRJ_WP0 [1/5]

#define AIPS_PACRJ_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP0 [2/5]

#define AIPS_PACRJ_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP0 [3/5]

#define AIPS_PACRJ_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP0 [4/5]

#define AIPS_PACRJ_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP0 [5/5]

#define AIPS_PACRJ_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP1 [1/5]

#define AIPS_PACRJ_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP1 [2/5]

#define AIPS_PACRJ_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP1 [3/5]

#define AIPS_PACRJ_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP1 [4/5]

#define AIPS_PACRJ_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP1 [5/5]

#define AIPS_PACRJ_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP2 [1/5]

#define AIPS_PACRJ_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP2 [2/5]

#define AIPS_PACRJ_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP2 [3/5]

#define AIPS_PACRJ_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP2 [4/5]

#define AIPS_PACRJ_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP2 [5/5]

#define AIPS_PACRJ_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP3 [1/5]

#define AIPS_PACRJ_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP3 [2/5]

#define AIPS_PACRJ_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP3 [3/5]

#define AIPS_PACRJ_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP3 [4/5]

#define AIPS_PACRJ_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP3 [5/5]

#define AIPS_PACRJ_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP4 [1/5]

#define AIPS_PACRJ_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP4 [2/5]

#define AIPS_PACRJ_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP4 [3/5]

#define AIPS_PACRJ_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP4 [4/5]

#define AIPS_PACRJ_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP4 [5/5]

#define AIPS_PACRJ_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP5 [1/5]

#define AIPS_PACRJ_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP5 [2/5]

#define AIPS_PACRJ_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP5 [3/5]

#define AIPS_PACRJ_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP5 [4/5]

#define AIPS_PACRJ_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP5 [5/5]

#define AIPS_PACRJ_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP6 [1/5]

#define AIPS_PACRJ_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP6 [2/5]

#define AIPS_PACRJ_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP6 [3/5]

#define AIPS_PACRJ_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP6 [4/5]

#define AIPS_PACRJ_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP6 [5/5]

#define AIPS_PACRJ_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP7 [1/5]

#define AIPS_PACRJ_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP7 [2/5]

#define AIPS_PACRJ_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP7 [3/5]

#define AIPS_PACRJ_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP7 [4/5]

#define AIPS_PACRJ_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRJ_WP7 [5/5]

#define AIPS_PACRJ_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_SP0 [1/5]

#define AIPS_PACRK_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP0 [2/5]

#define AIPS_PACRK_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP0 [3/5]

#define AIPS_PACRK_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP0 [4/5]

#define AIPS_PACRK_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP0 [5/5]

#define AIPS_PACRK_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP1 [1/5]

#define AIPS_PACRK_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP1 [2/5]

#define AIPS_PACRK_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP1 [3/5]

#define AIPS_PACRK_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP1 [4/5]

#define AIPS_PACRK_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP1 [5/5]

#define AIPS_PACRK_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP2 [1/5]

#define AIPS_PACRK_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP2 [2/5]

#define AIPS_PACRK_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP2 [3/5]

#define AIPS_PACRK_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP2 [4/5]

#define AIPS_PACRK_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP2 [5/5]

#define AIPS_PACRK_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP3 [1/5]

#define AIPS_PACRK_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP3 [2/5]

#define AIPS_PACRK_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP3 [3/5]

#define AIPS_PACRK_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP3 [4/5]

#define AIPS_PACRK_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP3 [5/5]

#define AIPS_PACRK_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP4 [1/5]

#define AIPS_PACRK_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP4 [2/5]

#define AIPS_PACRK_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP4 [3/5]

#define AIPS_PACRK_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP4 [4/5]

#define AIPS_PACRK_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP4 [5/5]

#define AIPS_PACRK_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP5 [1/5]

#define AIPS_PACRK_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP5 [2/5]

#define AIPS_PACRK_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP5 [3/5]

#define AIPS_PACRK_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP5 [4/5]

#define AIPS_PACRK_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP5 [5/5]

#define AIPS_PACRK_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP6 [1/5]

#define AIPS_PACRK_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP6 [2/5]

#define AIPS_PACRK_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP6 [3/5]

#define AIPS_PACRK_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP6 [4/5]

#define AIPS_PACRK_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP6 [5/5]

#define AIPS_PACRK_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP7 [1/5]

#define AIPS_PACRK_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP7 [2/5]

#define AIPS_PACRK_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP7 [3/5]

#define AIPS_PACRK_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP7 [4/5]

#define AIPS_PACRK_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_SP7 [5/5]

#define AIPS_PACRK_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRK_TP0 [1/5]

#define AIPS_PACRK_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP0 [2/5]

#define AIPS_PACRK_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP0 [3/5]

#define AIPS_PACRK_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP0 [4/5]

#define AIPS_PACRK_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP0 [5/5]

#define AIPS_PACRK_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP1 [1/5]

#define AIPS_PACRK_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP1 [2/5]

#define AIPS_PACRK_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP1 [3/5]

#define AIPS_PACRK_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP1 [4/5]

#define AIPS_PACRK_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP1 [5/5]

#define AIPS_PACRK_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP2 [1/5]

#define AIPS_PACRK_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP2 [2/5]

#define AIPS_PACRK_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP2 [3/5]

#define AIPS_PACRK_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP2 [4/5]

#define AIPS_PACRK_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP2 [5/5]

#define AIPS_PACRK_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP3 [1/5]

#define AIPS_PACRK_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP3 [2/5]

#define AIPS_PACRK_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP3 [3/5]

#define AIPS_PACRK_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP3 [4/5]

#define AIPS_PACRK_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP3 [5/5]

#define AIPS_PACRK_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP4 [1/5]

#define AIPS_PACRK_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP4 [2/5]

#define AIPS_PACRK_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP4 [3/5]

#define AIPS_PACRK_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP4 [4/5]

#define AIPS_PACRK_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP4 [5/5]

#define AIPS_PACRK_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP5 [1/5]

#define AIPS_PACRK_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP5 [2/5]

#define AIPS_PACRK_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP5 [3/5]

#define AIPS_PACRK_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP5 [4/5]

#define AIPS_PACRK_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP5 [5/5]

#define AIPS_PACRK_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP6 [1/5]

#define AIPS_PACRK_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP6 [2/5]

#define AIPS_PACRK_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP6 [3/5]

#define AIPS_PACRK_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP6 [4/5]

#define AIPS_PACRK_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP6 [5/5]

#define AIPS_PACRK_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP7 [1/5]

#define AIPS_PACRK_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP7 [2/5]

#define AIPS_PACRK_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP7 [3/5]

#define AIPS_PACRK_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP7 [4/5]

#define AIPS_PACRK_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_TP7 [5/5]

#define AIPS_PACRK_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRK_WP0 [1/5]

#define AIPS_PACRK_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP0 [2/5]

#define AIPS_PACRK_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP0 [3/5]

#define AIPS_PACRK_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP0 [4/5]

#define AIPS_PACRK_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP0 [5/5]

#define AIPS_PACRK_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP1 [1/5]

#define AIPS_PACRK_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP1 [2/5]

#define AIPS_PACRK_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP1 [3/5]

#define AIPS_PACRK_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP1 [4/5]

#define AIPS_PACRK_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP1 [5/5]

#define AIPS_PACRK_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP2 [1/5]

#define AIPS_PACRK_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP2 [2/5]

#define AIPS_PACRK_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP2 [3/5]

#define AIPS_PACRK_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP2 [4/5]

#define AIPS_PACRK_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP2 [5/5]

#define AIPS_PACRK_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP3 [1/5]

#define AIPS_PACRK_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP3 [2/5]

#define AIPS_PACRK_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP3 [3/5]

#define AIPS_PACRK_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP3 [4/5]

#define AIPS_PACRK_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP3 [5/5]

#define AIPS_PACRK_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP4 [1/5]

#define AIPS_PACRK_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP4 [2/5]

#define AIPS_PACRK_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP4 [3/5]

#define AIPS_PACRK_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP4 [4/5]

#define AIPS_PACRK_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP4 [5/5]

#define AIPS_PACRK_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP5 [1/5]

#define AIPS_PACRK_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP5 [2/5]

#define AIPS_PACRK_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP5 [3/5]

#define AIPS_PACRK_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP5 [4/5]

#define AIPS_PACRK_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP5 [5/5]

#define AIPS_PACRK_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP6 [1/5]

#define AIPS_PACRK_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP6 [2/5]

#define AIPS_PACRK_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP6 [3/5]

#define AIPS_PACRK_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP6 [4/5]

#define AIPS_PACRK_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP6 [5/5]

#define AIPS_PACRK_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP7 [1/5]

#define AIPS_PACRK_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP7 [2/5]

#define AIPS_PACRK_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP7 [3/5]

#define AIPS_PACRK_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP7 [4/5]

#define AIPS_PACRK_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRK_WP7 [5/5]

#define AIPS_PACRK_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_SP0 [1/5]

#define AIPS_PACRL_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP0 [2/5]

#define AIPS_PACRL_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP0 [3/5]

#define AIPS_PACRL_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP0 [4/5]

#define AIPS_PACRL_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP0 [5/5]

#define AIPS_PACRL_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP1 [1/5]

#define AIPS_PACRL_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP1 [2/5]

#define AIPS_PACRL_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP1 [3/5]

#define AIPS_PACRL_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP1 [4/5]

#define AIPS_PACRL_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP1 [5/5]

#define AIPS_PACRL_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP2 [1/5]

#define AIPS_PACRL_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP2 [2/5]

#define AIPS_PACRL_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP2 [3/5]

#define AIPS_PACRL_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP2 [4/5]

#define AIPS_PACRL_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP2 [5/5]

#define AIPS_PACRL_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP3 [1/5]

#define AIPS_PACRL_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP3 [2/5]

#define AIPS_PACRL_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP3 [3/5]

#define AIPS_PACRL_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP3 [4/5]

#define AIPS_PACRL_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP3 [5/5]

#define AIPS_PACRL_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP4 [1/5]

#define AIPS_PACRL_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP4 [2/5]

#define AIPS_PACRL_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP4 [3/5]

#define AIPS_PACRL_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP4 [4/5]

#define AIPS_PACRL_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP4 [5/5]

#define AIPS_PACRL_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP5 [1/5]

#define AIPS_PACRL_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP5 [2/5]

#define AIPS_PACRL_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP5 [3/5]

#define AIPS_PACRL_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP5 [4/5]

#define AIPS_PACRL_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP5 [5/5]

#define AIPS_PACRL_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP6 [1/5]

#define AIPS_PACRL_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP6 [2/5]

#define AIPS_PACRL_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP6 [3/5]

#define AIPS_PACRL_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP6 [4/5]

#define AIPS_PACRL_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP6 [5/5]

#define AIPS_PACRL_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP7 [1/5]

#define AIPS_PACRL_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP7 [2/5]

#define AIPS_PACRL_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP7 [3/5]

#define AIPS_PACRL_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP7 [4/5]

#define AIPS_PACRL_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_SP7 [5/5]

#define AIPS_PACRL_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRL_TP0 [1/5]

#define AIPS_PACRL_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP0 [2/5]

#define AIPS_PACRL_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP0 [3/5]

#define AIPS_PACRL_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP0 [4/5]

#define AIPS_PACRL_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP0 [5/5]

#define AIPS_PACRL_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP1 [1/5]

#define AIPS_PACRL_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP1 [2/5]

#define AIPS_PACRL_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP1 [3/5]

#define AIPS_PACRL_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP1 [4/5]

#define AIPS_PACRL_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP1 [5/5]

#define AIPS_PACRL_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP2 [1/5]

#define AIPS_PACRL_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP2 [2/5]

#define AIPS_PACRL_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP2 [3/5]

#define AIPS_PACRL_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP2 [4/5]

#define AIPS_PACRL_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP2 [5/5]

#define AIPS_PACRL_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP3 [1/5]

#define AIPS_PACRL_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP3 [2/5]

#define AIPS_PACRL_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP3 [3/5]

#define AIPS_PACRL_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP3 [4/5]

#define AIPS_PACRL_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP3 [5/5]

#define AIPS_PACRL_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP4 [1/5]

#define AIPS_PACRL_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP4 [2/5]

#define AIPS_PACRL_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP4 [3/5]

#define AIPS_PACRL_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP4 [4/5]

#define AIPS_PACRL_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP4 [5/5]

#define AIPS_PACRL_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP5 [1/5]

#define AIPS_PACRL_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP5 [2/5]

#define AIPS_PACRL_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP5 [3/5]

#define AIPS_PACRL_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP5 [4/5]

#define AIPS_PACRL_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP5 [5/5]

#define AIPS_PACRL_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP6 [1/5]

#define AIPS_PACRL_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP6 [2/5]

#define AIPS_PACRL_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP6 [3/5]

#define AIPS_PACRL_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP6 [4/5]

#define AIPS_PACRL_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP6 [5/5]

#define AIPS_PACRL_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP7 [1/5]

#define AIPS_PACRL_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP7 [2/5]

#define AIPS_PACRL_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP7 [3/5]

#define AIPS_PACRL_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP7 [4/5]

#define AIPS_PACRL_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_TP7 [5/5]

#define AIPS_PACRL_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRL_WP0 [1/5]

#define AIPS_PACRL_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP0 [2/5]

#define AIPS_PACRL_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP0 [3/5]

#define AIPS_PACRL_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP0 [4/5]

#define AIPS_PACRL_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP0 [5/5]

#define AIPS_PACRL_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP1 [1/5]

#define AIPS_PACRL_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP1 [2/5]

#define AIPS_PACRL_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP1 [3/5]

#define AIPS_PACRL_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP1 [4/5]

#define AIPS_PACRL_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP1 [5/5]

#define AIPS_PACRL_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP2 [1/5]

#define AIPS_PACRL_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP2 [2/5]

#define AIPS_PACRL_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP2 [3/5]

#define AIPS_PACRL_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP2 [4/5]

#define AIPS_PACRL_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP2 [5/5]

#define AIPS_PACRL_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP3 [1/5]

#define AIPS_PACRL_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP3 [2/5]

#define AIPS_PACRL_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP3 [3/5]

#define AIPS_PACRL_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP3 [4/5]

#define AIPS_PACRL_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP3 [5/5]

#define AIPS_PACRL_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP4 [1/5]

#define AIPS_PACRL_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP4 [2/5]

#define AIPS_PACRL_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP4 [3/5]

#define AIPS_PACRL_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP4 [4/5]

#define AIPS_PACRL_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP4 [5/5]

#define AIPS_PACRL_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP5 [1/5]

#define AIPS_PACRL_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP5 [2/5]

#define AIPS_PACRL_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP5 [3/5]

#define AIPS_PACRL_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP5 [4/5]

#define AIPS_PACRL_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP5 [5/5]

#define AIPS_PACRL_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP6 [1/5]

#define AIPS_PACRL_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP6 [2/5]

#define AIPS_PACRL_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP6 [3/5]

#define AIPS_PACRL_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP6 [4/5]

#define AIPS_PACRL_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP6 [5/5]

#define AIPS_PACRL_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP7 [1/5]

#define AIPS_PACRL_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP7 [2/5]

#define AIPS_PACRL_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP7 [3/5]

#define AIPS_PACRL_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP7 [4/5]

#define AIPS_PACRL_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRL_WP7 [5/5]

#define AIPS_PACRL_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_SP0 [1/5]

#define AIPS_PACRM_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP0 [2/5]

#define AIPS_PACRM_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP0 [3/5]

#define AIPS_PACRM_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP0 [4/5]

#define AIPS_PACRM_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP0 [5/5]

#define AIPS_PACRM_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP1 [1/5]

#define AIPS_PACRM_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP1 [2/5]

#define AIPS_PACRM_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP1 [3/5]

#define AIPS_PACRM_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP1 [4/5]

#define AIPS_PACRM_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP1 [5/5]

#define AIPS_PACRM_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP2 [1/5]

#define AIPS_PACRM_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP2 [2/5]

#define AIPS_PACRM_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP2 [3/5]

#define AIPS_PACRM_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP2 [4/5]

#define AIPS_PACRM_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP2 [5/5]

#define AIPS_PACRM_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP3 [1/5]

#define AIPS_PACRM_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP3 [2/5]

#define AIPS_PACRM_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP3 [3/5]

#define AIPS_PACRM_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP3 [4/5]

#define AIPS_PACRM_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP3 [5/5]

#define AIPS_PACRM_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP4 [1/5]

#define AIPS_PACRM_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP4 [2/5]

#define AIPS_PACRM_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP4 [3/5]

#define AIPS_PACRM_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP4 [4/5]

#define AIPS_PACRM_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP4 [5/5]

#define AIPS_PACRM_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP5 [1/5]

#define AIPS_PACRM_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP5 [2/5]

#define AIPS_PACRM_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP5 [3/5]

#define AIPS_PACRM_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP5 [4/5]

#define AIPS_PACRM_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP5 [5/5]

#define AIPS_PACRM_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP6 [1/5]

#define AIPS_PACRM_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP6 [2/5]

#define AIPS_PACRM_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP6 [3/5]

#define AIPS_PACRM_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP6 [4/5]

#define AIPS_PACRM_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP6 [5/5]

#define AIPS_PACRM_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP7 [1/5]

#define AIPS_PACRM_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP7 [2/5]

#define AIPS_PACRM_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP7 [3/5]

#define AIPS_PACRM_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP7 [4/5]

#define AIPS_PACRM_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_SP7 [5/5]

#define AIPS_PACRM_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRM_TP0 [1/5]

#define AIPS_PACRM_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP0 [2/5]

#define AIPS_PACRM_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP0 [3/5]

#define AIPS_PACRM_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP0 [4/5]

#define AIPS_PACRM_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP0 [5/5]

#define AIPS_PACRM_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP1 [1/5]

#define AIPS_PACRM_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP1 [2/5]

#define AIPS_PACRM_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP1 [3/5]

#define AIPS_PACRM_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP1 [4/5]

#define AIPS_PACRM_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP1 [5/5]

#define AIPS_PACRM_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP2 [1/5]

#define AIPS_PACRM_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP2 [2/5]

#define AIPS_PACRM_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP2 [3/5]

#define AIPS_PACRM_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP2 [4/5]

#define AIPS_PACRM_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP2 [5/5]

#define AIPS_PACRM_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP3 [1/5]

#define AIPS_PACRM_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP3 [2/5]

#define AIPS_PACRM_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP3 [3/5]

#define AIPS_PACRM_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP3 [4/5]

#define AIPS_PACRM_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP3 [5/5]

#define AIPS_PACRM_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP4 [1/5]

#define AIPS_PACRM_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP4 [2/5]

#define AIPS_PACRM_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP4 [3/5]

#define AIPS_PACRM_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP4 [4/5]

#define AIPS_PACRM_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP4 [5/5]

#define AIPS_PACRM_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP5 [1/5]

#define AIPS_PACRM_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP5 [2/5]

#define AIPS_PACRM_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP5 [3/5]

#define AIPS_PACRM_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP5 [4/5]

#define AIPS_PACRM_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP5 [5/5]

#define AIPS_PACRM_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP6 [1/5]

#define AIPS_PACRM_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP6 [2/5]

#define AIPS_PACRM_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP6 [3/5]

#define AIPS_PACRM_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP6 [4/5]

#define AIPS_PACRM_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP6 [5/5]

#define AIPS_PACRM_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP7 [1/5]

#define AIPS_PACRM_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP7 [2/5]

#define AIPS_PACRM_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP7 [3/5]

#define AIPS_PACRM_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP7 [4/5]

#define AIPS_PACRM_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_TP7 [5/5]

#define AIPS_PACRM_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRM_WP0 [1/5]

#define AIPS_PACRM_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP0 [2/5]

#define AIPS_PACRM_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP0 [3/5]

#define AIPS_PACRM_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP0 [4/5]

#define AIPS_PACRM_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP0 [5/5]

#define AIPS_PACRM_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP1 [1/5]

#define AIPS_PACRM_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP1 [2/5]

#define AIPS_PACRM_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP1 [3/5]

#define AIPS_PACRM_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP1 [4/5]

#define AIPS_PACRM_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP1 [5/5]

#define AIPS_PACRM_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP2 [1/5]

#define AIPS_PACRM_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP2 [2/5]

#define AIPS_PACRM_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP2 [3/5]

#define AIPS_PACRM_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP2 [4/5]

#define AIPS_PACRM_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP2 [5/5]

#define AIPS_PACRM_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP3 [1/5]

#define AIPS_PACRM_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP3 [2/5]

#define AIPS_PACRM_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP3 [3/5]

#define AIPS_PACRM_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP3 [4/5]

#define AIPS_PACRM_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP3 [5/5]

#define AIPS_PACRM_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP4 [1/5]

#define AIPS_PACRM_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP4 [2/5]

#define AIPS_PACRM_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP4 [3/5]

#define AIPS_PACRM_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP4 [4/5]

#define AIPS_PACRM_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP4 [5/5]

#define AIPS_PACRM_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP5 [1/5]

#define AIPS_PACRM_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP5 [2/5]

#define AIPS_PACRM_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP5 [3/5]

#define AIPS_PACRM_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP5 [4/5]

#define AIPS_PACRM_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP5 [5/5]

#define AIPS_PACRM_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP6 [1/5]

#define AIPS_PACRM_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP6 [2/5]

#define AIPS_PACRM_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP6 [3/5]

#define AIPS_PACRM_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP6 [4/5]

#define AIPS_PACRM_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP6 [5/5]

#define AIPS_PACRM_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP7 [1/5]

#define AIPS_PACRM_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP7 [2/5]

#define AIPS_PACRM_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP7 [3/5]

#define AIPS_PACRM_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP7 [4/5]

#define AIPS_PACRM_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRM_WP7 [5/5]

#define AIPS_PACRM_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_SP0 [1/5]

#define AIPS_PACRN_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP0 [2/5]

#define AIPS_PACRN_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP0 [3/5]

#define AIPS_PACRN_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP0 [4/5]

#define AIPS_PACRN_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP0 [5/5]

#define AIPS_PACRN_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP1 [1/5]

#define AIPS_PACRN_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP1 [2/5]

#define AIPS_PACRN_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP1 [3/5]

#define AIPS_PACRN_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP1 [4/5]

#define AIPS_PACRN_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP1 [5/5]

#define AIPS_PACRN_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP2 [1/5]

#define AIPS_PACRN_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP2 [2/5]

#define AIPS_PACRN_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP2 [3/5]

#define AIPS_PACRN_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP2 [4/5]

#define AIPS_PACRN_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP2 [5/5]

#define AIPS_PACRN_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP3 [1/5]

#define AIPS_PACRN_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP3 [2/5]

#define AIPS_PACRN_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP3 [3/5]

#define AIPS_PACRN_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP3 [4/5]

#define AIPS_PACRN_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP3 [5/5]

#define AIPS_PACRN_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP4 [1/5]

#define AIPS_PACRN_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP4 [2/5]

#define AIPS_PACRN_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP4 [3/5]

#define AIPS_PACRN_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP4 [4/5]

#define AIPS_PACRN_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP4 [5/5]

#define AIPS_PACRN_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP5 [1/5]

#define AIPS_PACRN_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP5 [2/5]

#define AIPS_PACRN_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP5 [3/5]

#define AIPS_PACRN_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP5 [4/5]

#define AIPS_PACRN_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP5 [5/5]

#define AIPS_PACRN_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP6 [1/5]

#define AIPS_PACRN_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP6 [2/5]

#define AIPS_PACRN_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP6 [3/5]

#define AIPS_PACRN_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP6 [4/5]

#define AIPS_PACRN_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP6 [5/5]

#define AIPS_PACRN_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP7 [1/5]

#define AIPS_PACRN_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP7 [2/5]

#define AIPS_PACRN_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP7 [3/5]

#define AIPS_PACRN_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP7 [4/5]

#define AIPS_PACRN_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_SP7 [5/5]

#define AIPS_PACRN_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRN_TP0 [1/5]

#define AIPS_PACRN_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP0 [2/5]

#define AIPS_PACRN_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP0 [3/5]

#define AIPS_PACRN_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP0 [4/5]

#define AIPS_PACRN_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP0 [5/5]

#define AIPS_PACRN_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP1 [1/5]

#define AIPS_PACRN_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP1 [2/5]

#define AIPS_PACRN_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP1 [3/5]

#define AIPS_PACRN_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP1 [4/5]

#define AIPS_PACRN_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP1 [5/5]

#define AIPS_PACRN_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP2 [1/5]

#define AIPS_PACRN_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP2 [2/5]

#define AIPS_PACRN_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP2 [3/5]

#define AIPS_PACRN_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP2 [4/5]

#define AIPS_PACRN_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP2 [5/5]

#define AIPS_PACRN_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP3 [1/5]

#define AIPS_PACRN_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP3 [2/5]

#define AIPS_PACRN_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP3 [3/5]

#define AIPS_PACRN_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP3 [4/5]

#define AIPS_PACRN_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP3 [5/5]

#define AIPS_PACRN_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP4 [1/5]

#define AIPS_PACRN_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP4 [2/5]

#define AIPS_PACRN_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP4 [3/5]

#define AIPS_PACRN_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP4 [4/5]

#define AIPS_PACRN_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP4 [5/5]

#define AIPS_PACRN_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP5 [1/5]

#define AIPS_PACRN_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP5 [2/5]

#define AIPS_PACRN_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP5 [3/5]

#define AIPS_PACRN_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP5 [4/5]

#define AIPS_PACRN_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP5 [5/5]

#define AIPS_PACRN_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP6 [1/5]

#define AIPS_PACRN_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP6 [2/5]

#define AIPS_PACRN_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP6 [3/5]

#define AIPS_PACRN_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP6 [4/5]

#define AIPS_PACRN_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP6 [5/5]

#define AIPS_PACRN_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP7 [1/5]

#define AIPS_PACRN_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP7 [2/5]

#define AIPS_PACRN_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP7 [3/5]

#define AIPS_PACRN_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP7 [4/5]

#define AIPS_PACRN_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_TP7 [5/5]

#define AIPS_PACRN_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRN_WP0 [1/5]

#define AIPS_PACRN_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP0 [2/5]

#define AIPS_PACRN_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP0 [3/5]

#define AIPS_PACRN_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP0 [4/5]

#define AIPS_PACRN_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP0 [5/5]

#define AIPS_PACRN_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP1 [1/5]

#define AIPS_PACRN_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP1 [2/5]

#define AIPS_PACRN_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP1 [3/5]

#define AIPS_PACRN_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP1 [4/5]

#define AIPS_PACRN_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP1 [5/5]

#define AIPS_PACRN_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP2 [1/5]

#define AIPS_PACRN_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP2 [2/5]

#define AIPS_PACRN_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP2 [3/5]

#define AIPS_PACRN_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP2 [4/5]

#define AIPS_PACRN_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP2 [5/5]

#define AIPS_PACRN_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP3 [1/5]

#define AIPS_PACRN_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP3 [2/5]

#define AIPS_PACRN_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP3 [3/5]

#define AIPS_PACRN_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP3 [4/5]

#define AIPS_PACRN_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP3 [5/5]

#define AIPS_PACRN_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP4 [1/5]

#define AIPS_PACRN_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP4 [2/5]

#define AIPS_PACRN_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP4 [3/5]

#define AIPS_PACRN_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP4 [4/5]

#define AIPS_PACRN_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP4 [5/5]

#define AIPS_PACRN_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP5 [1/5]

#define AIPS_PACRN_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP5 [2/5]

#define AIPS_PACRN_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP5 [3/5]

#define AIPS_PACRN_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP5 [4/5]

#define AIPS_PACRN_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP5 [5/5]

#define AIPS_PACRN_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP6 [1/5]

#define AIPS_PACRN_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP6 [2/5]

#define AIPS_PACRN_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP6 [3/5]

#define AIPS_PACRN_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP6 [4/5]

#define AIPS_PACRN_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP6 [5/5]

#define AIPS_PACRN_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP7 [1/5]

#define AIPS_PACRN_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP7 [2/5]

#define AIPS_PACRN_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP7 [3/5]

#define AIPS_PACRN_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP7 [4/5]

#define AIPS_PACRN_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRN_WP7 [5/5]

#define AIPS_PACRN_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_SP0 [1/5]

#define AIPS_PACRO_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP0 [2/5]

#define AIPS_PACRO_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP0 [3/5]

#define AIPS_PACRO_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP0 [4/5]

#define AIPS_PACRO_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP0 [5/5]

#define AIPS_PACRO_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP1 [1/5]

#define AIPS_PACRO_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP1 [2/5]

#define AIPS_PACRO_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP1 [3/5]

#define AIPS_PACRO_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP1 [4/5]

#define AIPS_PACRO_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP1 [5/5]

#define AIPS_PACRO_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP2 [1/5]

#define AIPS_PACRO_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP2 [2/5]

#define AIPS_PACRO_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP2 [3/5]

#define AIPS_PACRO_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP2 [4/5]

#define AIPS_PACRO_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP2 [5/5]

#define AIPS_PACRO_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP3 [1/5]

#define AIPS_PACRO_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP3 [2/5]

#define AIPS_PACRO_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP3 [3/5]

#define AIPS_PACRO_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP3 [4/5]

#define AIPS_PACRO_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP3 [5/5]

#define AIPS_PACRO_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP4 [1/5]

#define AIPS_PACRO_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP4 [2/5]

#define AIPS_PACRO_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP4 [3/5]

#define AIPS_PACRO_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP4 [4/5]

#define AIPS_PACRO_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP4 [5/5]

#define AIPS_PACRO_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP5 [1/5]

#define AIPS_PACRO_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP5 [2/5]

#define AIPS_PACRO_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP5 [3/5]

#define AIPS_PACRO_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP5 [4/5]

#define AIPS_PACRO_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP5 [5/5]

#define AIPS_PACRO_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP6 [1/5]

#define AIPS_PACRO_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP6 [2/5]

#define AIPS_PACRO_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP6 [3/5]

#define AIPS_PACRO_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP6 [4/5]

#define AIPS_PACRO_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP6 [5/5]

#define AIPS_PACRO_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP7 [1/5]

#define AIPS_PACRO_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP7 [2/5]

#define AIPS_PACRO_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP7 [3/5]

#define AIPS_PACRO_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP7 [4/5]

#define AIPS_PACRO_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_SP7 [5/5]

#define AIPS_PACRO_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRO_TP0 [1/5]

#define AIPS_PACRO_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP0 [2/5]

#define AIPS_PACRO_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP0 [3/5]

#define AIPS_PACRO_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP0 [4/5]

#define AIPS_PACRO_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP0 [5/5]

#define AIPS_PACRO_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP1 [1/5]

#define AIPS_PACRO_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP1 [2/5]

#define AIPS_PACRO_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP1 [3/5]

#define AIPS_PACRO_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP1 [4/5]

#define AIPS_PACRO_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP1 [5/5]

#define AIPS_PACRO_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP2 [1/5]

#define AIPS_PACRO_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP2 [2/5]

#define AIPS_PACRO_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP2 [3/5]

#define AIPS_PACRO_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP2 [4/5]

#define AIPS_PACRO_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP2 [5/5]

#define AIPS_PACRO_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP3 [1/5]

#define AIPS_PACRO_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP3 [2/5]

#define AIPS_PACRO_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP3 [3/5]

#define AIPS_PACRO_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP3 [4/5]

#define AIPS_PACRO_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP3 [5/5]

#define AIPS_PACRO_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP4 [1/5]

#define AIPS_PACRO_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP4 [2/5]

#define AIPS_PACRO_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP4 [3/5]

#define AIPS_PACRO_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP4 [4/5]

#define AIPS_PACRO_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP4 [5/5]

#define AIPS_PACRO_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP5 [1/5]

#define AIPS_PACRO_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP5 [2/5]

#define AIPS_PACRO_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP5 [3/5]

#define AIPS_PACRO_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP5 [4/5]

#define AIPS_PACRO_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP5 [5/5]

#define AIPS_PACRO_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP6 [1/5]

#define AIPS_PACRO_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP6 [2/5]

#define AIPS_PACRO_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP6 [3/5]

#define AIPS_PACRO_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP6 [4/5]

#define AIPS_PACRO_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP6 [5/5]

#define AIPS_PACRO_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP7 [1/5]

#define AIPS_PACRO_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP7 [2/5]

#define AIPS_PACRO_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP7 [3/5]

#define AIPS_PACRO_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP7 [4/5]

#define AIPS_PACRO_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_TP7 [5/5]

#define AIPS_PACRO_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRO_WP0 [1/5]

#define AIPS_PACRO_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP0 [2/5]

#define AIPS_PACRO_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP0 [3/5]

#define AIPS_PACRO_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP0 [4/5]

#define AIPS_PACRO_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP0 [5/5]

#define AIPS_PACRO_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP1 [1/5]

#define AIPS_PACRO_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP1 [2/5]

#define AIPS_PACRO_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP1 [3/5]

#define AIPS_PACRO_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP1 [4/5]

#define AIPS_PACRO_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP1 [5/5]

#define AIPS_PACRO_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP2 [1/5]

#define AIPS_PACRO_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP2 [2/5]

#define AIPS_PACRO_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP2 [3/5]

#define AIPS_PACRO_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP2 [4/5]

#define AIPS_PACRO_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP2 [5/5]

#define AIPS_PACRO_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP3 [1/5]

#define AIPS_PACRO_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP3 [2/5]

#define AIPS_PACRO_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP3 [3/5]

#define AIPS_PACRO_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP3 [4/5]

#define AIPS_PACRO_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP3 [5/5]

#define AIPS_PACRO_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP4 [1/5]

#define AIPS_PACRO_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP4 [2/5]

#define AIPS_PACRO_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP4 [3/5]

#define AIPS_PACRO_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP4 [4/5]

#define AIPS_PACRO_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP4 [5/5]

#define AIPS_PACRO_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP5 [1/5]

#define AIPS_PACRO_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP5 [2/5]

#define AIPS_PACRO_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP5 [3/5]

#define AIPS_PACRO_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP5 [4/5]

#define AIPS_PACRO_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP5 [5/5]

#define AIPS_PACRO_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP6 [1/5]

#define AIPS_PACRO_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP6 [2/5]

#define AIPS_PACRO_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP6 [3/5]

#define AIPS_PACRO_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP6 [4/5]

#define AIPS_PACRO_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP6 [5/5]

#define AIPS_PACRO_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP7 [1/5]

#define AIPS_PACRO_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP7 [2/5]

#define AIPS_PACRO_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP7 [3/5]

#define AIPS_PACRO_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP7 [4/5]

#define AIPS_PACRO_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRO_WP7 [5/5]

#define AIPS_PACRO_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_SP0 [1/5]

#define AIPS_PACRP_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP0 [2/5]

#define AIPS_PACRP_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP0 [3/5]

#define AIPS_PACRP_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP0 [4/5]

#define AIPS_PACRP_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP0 [5/5]

#define AIPS_PACRP_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP1 [1/5]

#define AIPS_PACRP_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP1 [2/5]

#define AIPS_PACRP_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP1 [3/5]

#define AIPS_PACRP_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP1 [4/5]

#define AIPS_PACRP_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP1 [5/5]

#define AIPS_PACRP_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP2 [1/5]

#define AIPS_PACRP_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP2 [2/5]

#define AIPS_PACRP_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP2 [3/5]

#define AIPS_PACRP_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP2 [4/5]

#define AIPS_PACRP_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP2 [5/5]

#define AIPS_PACRP_SP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)

SP2 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP3 [1/5]

#define AIPS_PACRP_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP3 [2/5]

#define AIPS_PACRP_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP3 [3/5]

#define AIPS_PACRP_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP3 [4/5]

#define AIPS_PACRP_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP3 [5/5]

#define AIPS_PACRP_SP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)

SP3 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP4 [1/5]

#define AIPS_PACRP_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP4 [2/5]

#define AIPS_PACRP_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP4 [3/5]

#define AIPS_PACRP_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP4 [4/5]

#define AIPS_PACRP_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP4 [5/5]

#define AIPS_PACRP_SP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)

SP4 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP5 [1/5]

#define AIPS_PACRP_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP5 [2/5]

#define AIPS_PACRP_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP5 [3/5]

#define AIPS_PACRP_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP5 [4/5]

#define AIPS_PACRP_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP5 [5/5]

#define AIPS_PACRP_SP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)

SP5 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP6 [1/5]

#define AIPS_PACRP_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP6 [2/5]

#define AIPS_PACRP_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP6 [3/5]

#define AIPS_PACRP_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP6 [4/5]

#define AIPS_PACRP_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP6 [5/5]

#define AIPS_PACRP_SP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)

SP6 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP7 [1/5]

#define AIPS_PACRP_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP7 [2/5]

#define AIPS_PACRP_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP7 [3/5]

#define AIPS_PACRP_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP7 [4/5]

#define AIPS_PACRP_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_SP7 [5/5]

#define AIPS_PACRP_SP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)

SP7 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRP_TP0 [1/5]

#define AIPS_PACRP_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP0 [2/5]

#define AIPS_PACRP_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP0 [3/5]

#define AIPS_PACRP_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP0 [4/5]

#define AIPS_PACRP_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP0 [5/5]

#define AIPS_PACRP_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP1 [1/5]

#define AIPS_PACRP_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP1 [2/5]

#define AIPS_PACRP_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP1 [3/5]

#define AIPS_PACRP_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP1 [4/5]

#define AIPS_PACRP_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP1 [5/5]

#define AIPS_PACRP_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP2 [1/5]

#define AIPS_PACRP_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP2 [2/5]

#define AIPS_PACRP_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP2 [3/5]

#define AIPS_PACRP_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP2 [4/5]

#define AIPS_PACRP_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP2 [5/5]

#define AIPS_PACRP_TP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)

TP2 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP3 [1/5]

#define AIPS_PACRP_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP3 [2/5]

#define AIPS_PACRP_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP3 [3/5]

#define AIPS_PACRP_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP3 [4/5]

#define AIPS_PACRP_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP3 [5/5]

#define AIPS_PACRP_TP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)

TP3 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP4 [1/5]

#define AIPS_PACRP_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP4 [2/5]

#define AIPS_PACRP_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP4 [3/5]

#define AIPS_PACRP_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP4 [4/5]

#define AIPS_PACRP_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP4 [5/5]

#define AIPS_PACRP_TP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)

TP4 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP5 [1/5]

#define AIPS_PACRP_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP5 [2/5]

#define AIPS_PACRP_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP5 [3/5]

#define AIPS_PACRP_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP5 [4/5]

#define AIPS_PACRP_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP5 [5/5]

#define AIPS_PACRP_TP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)

TP5 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP6 [1/5]

#define AIPS_PACRP_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP6 [2/5]

#define AIPS_PACRP_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP6 [3/5]

#define AIPS_PACRP_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP6 [4/5]

#define AIPS_PACRP_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP6 [5/5]

#define AIPS_PACRP_TP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)

TP6 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP7 [1/5]

#define AIPS_PACRP_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP7 [2/5]

#define AIPS_PACRP_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP7 [3/5]

#define AIPS_PACRP_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP7 [4/5]

#define AIPS_PACRP_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_TP7 [5/5]

#define AIPS_PACRP_TP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)

TP7 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRP_WP0 [1/5]

#define AIPS_PACRP_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP0 [2/5]

#define AIPS_PACRP_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP0 [3/5]

#define AIPS_PACRP_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP0 [4/5]

#define AIPS_PACRP_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP0 [5/5]

#define AIPS_PACRP_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP1 [1/5]

#define AIPS_PACRP_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP1 [2/5]

#define AIPS_PACRP_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP1 [3/5]

#define AIPS_PACRP_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP1 [4/5]

#define AIPS_PACRP_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP1 [5/5]

#define AIPS_PACRP_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP2 [1/5]

#define AIPS_PACRP_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP2 [2/5]

#define AIPS_PACRP_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP2 [3/5]

#define AIPS_PACRP_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP2 [4/5]

#define AIPS_PACRP_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP2 [5/5]

#define AIPS_PACRP_WP2 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)

WP2 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP3 [1/5]

#define AIPS_PACRP_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP3 [2/5]

#define AIPS_PACRP_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP3 [3/5]

#define AIPS_PACRP_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP3 [4/5]

#define AIPS_PACRP_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP3 [5/5]

#define AIPS_PACRP_WP3 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)

WP3 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP4 [1/5]

#define AIPS_PACRP_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP4 [2/5]

#define AIPS_PACRP_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP4 [3/5]

#define AIPS_PACRP_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP4 [4/5]

#define AIPS_PACRP_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP4 [5/5]

#define AIPS_PACRP_WP4 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)

WP4 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP5 [1/5]

#define AIPS_PACRP_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP5 [2/5]

#define AIPS_PACRP_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP5 [3/5]

#define AIPS_PACRP_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP5 [4/5]

#define AIPS_PACRP_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP5 [5/5]

#define AIPS_PACRP_WP5 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)

WP5 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP6 [1/5]

#define AIPS_PACRP_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP6 [2/5]

#define AIPS_PACRP_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP6 [3/5]

#define AIPS_PACRP_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP6 [4/5]

#define AIPS_PACRP_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP6 [5/5]

#define AIPS_PACRP_WP6 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)

WP6 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP7 [1/5]

#define AIPS_PACRP_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP7 [2/5]

#define AIPS_PACRP_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP7 [3/5]

#define AIPS_PACRP_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP7 [4/5]

#define AIPS_PACRP_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRP_WP7 [5/5]

#define AIPS_PACRP_WP7 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)

WP7 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRU_SP0

#define AIPS_PACRU_SP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP0_SHIFT)) & AIPS_PACRU_SP0_MASK)

SP0 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRU_SP1

#define AIPS_PACRU_SP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP1_SHIFT)) & AIPS_PACRU_SP1_MASK)

SP1 - Supervisor Protect 0b0..This peripheral does not require supervisor privilege level for accesses. 0b1..This peripheral requires supervisor privilege level for accesses.

◆ AIPS_PACRU_TP0

#define AIPS_PACRU_TP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP0_SHIFT)) & AIPS_PACRU_TP0_MASK)

TP0 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRU_TP1

#define AIPS_PACRU_TP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP1_SHIFT)) & AIPS_PACRU_TP1_MASK)

TP1 - Trusted Protect 0b0..Accesses from an untrusted master are allowed. 0b1..Accesses from an untrusted master are not allowed.

◆ AIPS_PACRU_WP0

#define AIPS_PACRU_WP0 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP0_SHIFT)) & AIPS_PACRU_WP0_MASK)

WP0 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.

◆ AIPS_PACRU_WP1

#define AIPS_PACRU_WP1 ( x)    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP1_SHIFT)) & AIPS_PACRU_WP1_MASK)

WP1 - Write Protect 0b0..This peripheral allows write accesses. 0b1..This peripheral is write protected.