mikroSDK Reference Manual
Macros
AXBS Register Masks
Mapping Information » Device Peripheral Access Layer » ADC Peripheral Access Layer » AIPS Peripheral Access Layer » AXBS Peripheral Access Layer

Macros

#define AXBS_BASE   (0x40004000u)
 
#define AXBS   ((AXBS_Type *)AXBS_BASE)
 
#define AXBS_BASE_ADDRS   { AXBS_BASE }
 
#define AXBS_BASE_PTRS   { AXBS }
 
#define AXBS_PRS_COUNT   (5U)
 
#define AXBS_CRS_COUNT   (5U)
 
#define AXBS_PRS_COUNT   (5U)
 
#define AXBS_CRS_COUNT   (5U)
 
#define AXBS_PRS_COUNT   (5U)
 
#define AXBS_CRS_COUNT   (5U)
 
#define AXBS_PRS_COUNT   (7U)
 
#define AXBS_CRS_COUNT   (7U)
 

PRS - Priority Registers Slave

#define AXBS_PRS_M0_MASK   (0x7U)
 
#define AXBS_PRS_M0_SHIFT   (0U)
 
#define AXBS_PRS_M0(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
 
#define AXBS_PRS_M1_MASK   (0x70U)
 
#define AXBS_PRS_M1_SHIFT   (4U)
 
#define AXBS_PRS_M1(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
 
#define AXBS_PRS_M2_MASK   (0x700U)
 
#define AXBS_PRS_M2_SHIFT   (8U)
 
#define AXBS_PRS_M2(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
 
#define AXBS_PRS_M3_MASK   (0x7000U)
 
#define AXBS_PRS_M3_SHIFT   (12U)
 
#define AXBS_PRS_M3(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
 
#define AXBS_PRS_M0_MASK   0x7u
 
#define AXBS_PRS_M0_SHIFT   0
 
#define AXBS_PRS_M0(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
 
#define AXBS_PRS_M1_MASK   0x70u
 
#define AXBS_PRS_M1_SHIFT   4
 
#define AXBS_PRS_M1(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
 
#define AXBS_PRS_M2_MASK   0x700u
 
#define AXBS_PRS_M2_SHIFT   8
 
#define AXBS_PRS_M2(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
 
#define AXBS_PRS_M3_MASK   0x7000u
 
#define AXBS_PRS_M3_SHIFT   12
 
#define AXBS_PRS_M3(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
 
#define AXBS_PRS_M0_MASK   (0x7U)
 
#define AXBS_PRS_M0_SHIFT   (0U)
 
#define AXBS_PRS_M0(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
 
#define AXBS_PRS_M1_MASK   (0x70U)
 
#define AXBS_PRS_M1_SHIFT   (4U)
 
#define AXBS_PRS_M1(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
 
#define AXBS_PRS_M2_MASK   (0x700U)
 
#define AXBS_PRS_M2_SHIFT   (8U)
 
#define AXBS_PRS_M2(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
 
#define AXBS_PRS_M3_MASK   (0x7000U)
 
#define AXBS_PRS_M3_SHIFT   (12U)
 
#define AXBS_PRS_M3(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
 
#define AXBS_PRS_M0_MASK   (0x7U)
 
#define AXBS_PRS_M0_SHIFT   (0U)
 
#define AXBS_PRS_M0(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
 
#define AXBS_PRS_M1_MASK   (0x70U)
 
#define AXBS_PRS_M1_SHIFT   (4U)
 
#define AXBS_PRS_M1(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
 
#define AXBS_PRS_M2_MASK   (0x700U)
 
#define AXBS_PRS_M2_SHIFT   (8U)
 
#define AXBS_PRS_M2(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
 
#define AXBS_PRS_M3_MASK   (0x7000U)
 
#define AXBS_PRS_M3_SHIFT   (12U)
 
#define AXBS_PRS_M3(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
 
#define AXBS_PRS_M0_MASK   (0x7U)
 
#define AXBS_PRS_M0_SHIFT   (0U)
 
#define AXBS_PRS_M0(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
 
#define AXBS_PRS_M1_MASK   (0x70U)
 
#define AXBS_PRS_M1_SHIFT   (4U)
 
#define AXBS_PRS_M1(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
 
#define AXBS_PRS_M2_MASK   (0x700U)
 
#define AXBS_PRS_M2_SHIFT   (8U)
 
#define AXBS_PRS_M2(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
 
#define AXBS_PRS_M3_MASK   (0x7000U)
 
#define AXBS_PRS_M3_SHIFT   (12U)
 
#define AXBS_PRS_M3(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
 
#define AXBS_PRS_M0_MASK   (0x7U)
 
#define AXBS_PRS_M0_SHIFT   (0U)
 
#define AXBS_PRS_M0(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
 
#define AXBS_PRS_M1_MASK   (0x70U)
 
#define AXBS_PRS_M1_SHIFT   (4U)
 
#define AXBS_PRS_M1(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
 
#define AXBS_PRS_M2_MASK   (0x700U)
 
#define AXBS_PRS_M2_SHIFT   (8U)
 
#define AXBS_PRS_M2(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
 
#define AXBS_PRS_M3_MASK   (0x7000U)
 
#define AXBS_PRS_M3_SHIFT   (12U)
 
#define AXBS_PRS_M3(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
 

PRS - Priority Registers Slave

#define AXBS_PRS_M4_MASK   (0x70000U)
 
#define AXBS_PRS_M4_SHIFT   (16U)
 
#define AXBS_PRS_M4(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
 
#define AXBS_PRS_M5_MASK   (0x700000U)
 
#define AXBS_PRS_M5_SHIFT   (20U)
 
#define AXBS_PRS_M5(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
 
#define AXBS_PRS_M4_MASK   0x70000u
 
#define AXBS_PRS_M4_SHIFT   16
 
#define AXBS_PRS_M4(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
 
#define AXBS_PRS_M5_MASK   0x700000u
 
#define AXBS_PRS_M5_SHIFT   20
 
#define AXBS_PRS_M5(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
 
#define AXBS_PRS_M4_MASK   (0x70000U)
 
#define AXBS_PRS_M4_SHIFT   (16U)
 
#define AXBS_PRS_M4(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
 
#define AXBS_PRS_M5_MASK   (0x700000U)
 
#define AXBS_PRS_M5_SHIFT   (20U)
 
#define AXBS_PRS_M5(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
 
#define AXBS_PRS_M4_MASK   (0x70000U)
 
#define AXBS_PRS_M4_SHIFT   (16U)
 
#define AXBS_PRS_M4(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
 
#define AXBS_PRS_M5_MASK   (0x700000U)
 
#define AXBS_PRS_M5_SHIFT   (20U)
 
#define AXBS_PRS_M5(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
 
#define AXBS_PRS_M6_MASK   (0x7000000U)
 
#define AXBS_PRS_M6_SHIFT   (24U)
 
#define AXBS_PRS_M6(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)
 
#define AXBS_PRS_M4_MASK   (0x70000U)
 
#define AXBS_PRS_M4_SHIFT   (16U)
 
#define AXBS_PRS_M4(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
 
#define AXBS_PRS_M5_MASK   (0x700000U)
 
#define AXBS_PRS_M5_SHIFT   (20U)
 
#define AXBS_PRS_M5(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
 
#define AXBS_PRS_M6_MASK   (0x7000000U)
 
#define AXBS_PRS_M6_SHIFT   (24U)
 
#define AXBS_PRS_M6(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)
 

PRS - Priority Registers Slave

#define AXBS_PRS_COUNT   (5U)
 

CRS - Control Register

#define AXBS_CRS_PARK_MASK   (0x7U)
 
#define AXBS_CRS_PARK_SHIFT   (0U)
 
#define AXBS_CRS_PARK(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
 
#define AXBS_CRS_PCTL_MASK   (0x30U)
 
#define AXBS_CRS_PCTL_SHIFT   (4U)
 
#define AXBS_CRS_PCTL(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
 
#define AXBS_CRS_ARB_MASK   (0x300U)
 
#define AXBS_CRS_ARB_SHIFT   (8U)
 
#define AXBS_CRS_ARB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
 
#define AXBS_CRS_HLP_MASK   (0x40000000U)
 
#define AXBS_CRS_HLP_SHIFT   (30U)
 
#define AXBS_CRS_HLP(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
 
#define AXBS_CRS_RO_MASK   (0x80000000U)
 
#define AXBS_CRS_RO_SHIFT   (31U)
 
#define AXBS_CRS_RO(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
 
#define AXBS_CRS_PARK_MASK   0x7u
 
#define AXBS_CRS_PARK_SHIFT   0
 
#define AXBS_CRS_PARK(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
 
#define AXBS_CRS_PCTL_MASK   0x30u
 
#define AXBS_CRS_PCTL_SHIFT   4
 
#define AXBS_CRS_PCTL(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
 
#define AXBS_CRS_ARB_MASK   0x300u
 
#define AXBS_CRS_ARB_SHIFT   8
 
#define AXBS_CRS_ARB(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
 
#define AXBS_CRS_HLP_MASK   0x40000000u
 
#define AXBS_CRS_HLP_SHIFT   30
 
#define AXBS_CRS_RO_MASK   0x80000000u
 
#define AXBS_CRS_RO_SHIFT   31
 
#define AXBS_CRS_PARK_MASK   (0x7U)
 
#define AXBS_CRS_PARK_SHIFT   (0U)
 
#define AXBS_CRS_PARK(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
 
#define AXBS_CRS_PCTL_MASK   (0x30U)
 
#define AXBS_CRS_PCTL_SHIFT   (4U)
 
#define AXBS_CRS_PCTL(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
 
#define AXBS_CRS_ARB_MASK   (0x300U)
 
#define AXBS_CRS_ARB_SHIFT   (8U)
 
#define AXBS_CRS_ARB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
 
#define AXBS_CRS_HLP_MASK   (0x40000000U)
 
#define AXBS_CRS_HLP_SHIFT   (30U)
 
#define AXBS_CRS_HLP(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
 
#define AXBS_CRS_RO_MASK   (0x80000000U)
 
#define AXBS_CRS_RO_SHIFT   (31U)
 
#define AXBS_CRS_RO(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
 
#define AXBS_CRS_PARK_MASK   (0x7U)
 
#define AXBS_CRS_PARK_SHIFT   (0U)
 
#define AXBS_CRS_PARK(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
 
#define AXBS_CRS_PCTL_MASK   (0x30U)
 
#define AXBS_CRS_PCTL_SHIFT   (4U)
 
#define AXBS_CRS_PCTL(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
 
#define AXBS_CRS_ARB_MASK   (0x300U)
 
#define AXBS_CRS_ARB_SHIFT   (8U)
 
#define AXBS_CRS_ARB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
 
#define AXBS_CRS_HLP_MASK   (0x40000000U)
 
#define AXBS_CRS_HLP_SHIFT   (30U)
 
#define AXBS_CRS_HLP(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
 
#define AXBS_CRS_RO_MASK   (0x80000000U)
 
#define AXBS_CRS_RO_SHIFT   (31U)
 
#define AXBS_CRS_RO(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
 
#define AXBS_CRS_PARK_MASK   (0x7U)
 
#define AXBS_CRS_PARK_SHIFT   (0U)
 
#define AXBS_CRS_PARK(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
 
#define AXBS_CRS_PCTL_MASK   (0x30U)
 
#define AXBS_CRS_PCTL_SHIFT   (4U)
 
#define AXBS_CRS_PCTL(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
 
#define AXBS_CRS_ARB_MASK   (0x300U)
 
#define AXBS_CRS_ARB_SHIFT   (8U)
 
#define AXBS_CRS_ARB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
 
#define AXBS_CRS_HLP_MASK   (0x40000000U)
 
#define AXBS_CRS_HLP_SHIFT   (30U)
 
#define AXBS_CRS_HLP(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
 
#define AXBS_CRS_RO_MASK   (0x80000000U)
 
#define AXBS_CRS_RO_SHIFT   (31U)
 
#define AXBS_CRS_RO(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
 
#define AXBS_CRS_PARK_MASK   (0x7U)
 
#define AXBS_CRS_PARK_SHIFT   (0U)
 
#define AXBS_CRS_PARK(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
 
#define AXBS_CRS_PCTL_MASK   (0x30U)
 
#define AXBS_CRS_PCTL_SHIFT   (4U)
 
#define AXBS_CRS_PCTL(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
 
#define AXBS_CRS_ARB_MASK   (0x300U)
 
#define AXBS_CRS_ARB_SHIFT   (8U)
 
#define AXBS_CRS_ARB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
 
#define AXBS_CRS_HLP_MASK   (0x40000000U)
 
#define AXBS_CRS_HLP_SHIFT   (30U)
 
#define AXBS_CRS_HLP(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
 
#define AXBS_CRS_RO_MASK   (0x80000000U)
 
#define AXBS_CRS_RO_SHIFT   (31U)
 
#define AXBS_CRS_RO(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
 

CRS - Control Register

#define AXBS_CRS_COUNT   (5U)
 

MGPCR0 - Master General Purpose Control Register

#define AXBS_MGPCR0_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR0_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR0_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
 
#define AXBS_MGPCR0_AULB_MASK   0x7u
 
#define AXBS_MGPCR0_AULB_SHIFT   0
 
#define AXBS_MGPCR0_AULB(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
 
#define AXBS_MGPCR0_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR0_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR0_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
 
#define AXBS_MGPCR0_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR0_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR0_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
 
#define AXBS_MGPCR0_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR0_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR0_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
 
#define AXBS_MGPCR0_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR0_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR0_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
 

MGPCR1 - Master General Purpose Control Register

#define AXBS_MGPCR1_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR1_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR1_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
 
#define AXBS_MGPCR1_AULB_MASK   0x7u
 
#define AXBS_MGPCR1_AULB_SHIFT   0
 
#define AXBS_MGPCR1_AULB(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
 
#define AXBS_MGPCR1_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR1_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR1_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
 
#define AXBS_MGPCR1_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR1_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR1_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
 
#define AXBS_MGPCR1_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR1_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR1_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
 
#define AXBS_MGPCR1_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR1_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR1_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
 

MGPCR2 - Master General Purpose Control Register

#define AXBS_MGPCR2_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR2_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR2_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
 
#define AXBS_MGPCR2_AULB_MASK   0x7u
 
#define AXBS_MGPCR2_AULB_SHIFT   0
 
#define AXBS_MGPCR2_AULB(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
 
#define AXBS_MGPCR2_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR2_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR2_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
 
#define AXBS_MGPCR2_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR2_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR2_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
 
#define AXBS_MGPCR2_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR2_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR2_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
 
#define AXBS_MGPCR2_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR2_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR2_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
 

MGPCR3 - Master General Purpose Control Register

#define AXBS_MGPCR3_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR3_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR3_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
 
#define AXBS_MGPCR3_AULB_MASK   0x7u
 
#define AXBS_MGPCR3_AULB_SHIFT   0
 
#define AXBS_MGPCR3_AULB(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
 
#define AXBS_MGPCR3_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR3_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR3_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
 
#define AXBS_MGPCR3_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR3_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR3_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
 
#define AXBS_MGPCR3_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR3_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR3_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
 
#define AXBS_MGPCR3_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR3_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR3_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
 

MGPCR4 - Master General Purpose Control Register

#define AXBS_MGPCR4_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR4_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR4_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
 
#define AXBS_MGPCR4_AULB_MASK   0x7u
 
#define AXBS_MGPCR4_AULB_SHIFT   0
 
#define AXBS_MGPCR4_AULB(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
 
#define AXBS_MGPCR4_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR4_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR4_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
 
#define AXBS_MGPCR4_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR4_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR4_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
 
#define AXBS_MGPCR4_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR4_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR4_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
 

MGPCR5 - Master General Purpose Control Register

#define AXBS_MGPCR5_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR5_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR5_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
 
#define AXBS_MGPCR5_AULB_MASK   0x7u
 
#define AXBS_MGPCR5_AULB_SHIFT   0
 
#define AXBS_MGPCR5_AULB(x)   (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
 
#define AXBS_MGPCR5_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR5_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR5_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
 
#define AXBS_MGPCR5_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR5_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR5_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
 
#define AXBS_MGPCR5_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR5_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR5_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
 

MGPCR6 - Master General Purpose Control Register

#define AXBS_MGPCR6_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR6_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR6_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
 
#define AXBS_MGPCR6_AULB_MASK   (0x7U)
 
#define AXBS_MGPCR6_AULB_SHIFT   (0U)
 
#define AXBS_MGPCR6_AULB(x)   (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
 

Macro Definition Documentation

◆ AXBS

#define AXBS   ((AXBS_Type *)AXBS_BASE)

Peripheral AXBS base pointer

◆ AXBS_BASE

#define AXBS_BASE   (0x40004000u)

Peripheral AXBS base address

◆ AXBS_BASE_ADDRS

#define AXBS_BASE_ADDRS   { AXBS_BASE }

Array initializer of AXBS peripheral base addresses

◆ AXBS_BASE_PTRS

#define AXBS_BASE_PTRS   { AXBS }

Array initializer of AXBS peripheral base pointers

◆ AXBS_CRS_ARB [1/6]

#define AXBS_CRS_ARB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)

ARB - Arbitration Mode 0b00..Fixed priority 0b01..Round-robin, or rotating, priority 0b10..Reserved 0b11..Reserved

◆ AXBS_CRS_ARB [2/6]

#define AXBS_CRS_ARB ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)

ARB - Arbitration Mode 0b00..Fixed priority 0b01..Round-robin, or rotating, priority 0b10..Reserved 0b11..Reserved

◆ AXBS_CRS_ARB [3/6]

#define AXBS_CRS_ARB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)

ARB - Arbitration Mode 0b00..Fixed priority 0b01..Round-robin, or rotating, priority 0b10..Reserved 0b11..Reserved

◆ AXBS_CRS_ARB [4/6]

#define AXBS_CRS_ARB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)

ARB - Arbitration Mode 0b00..Fixed priority 0b01..Round-robin, or rotating, priority 0b10..Reserved 0b11..Reserved

◆ AXBS_CRS_ARB [5/6]

#define AXBS_CRS_ARB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)

ARB - Arbitration Mode 0b00..Fixed priority 0b01..Round-robin, or rotating, priority 0b10..Reserved 0b11..Reserved

◆ AXBS_CRS_ARB [6/6]

#define AXBS_CRS_ARB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)

ARB - Arbitration Mode 0b00..Fixed priority 0b01..Round-robin, or rotating, priority 0b10..Reserved 0b11..Reserved

◆ AXBS_CRS_HLP [1/5]

#define AXBS_CRS_HLP ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)

HLP - Halt Low Priority 0b0..The low power mode request has the highest priority for arbitration on this slave port 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port

◆ AXBS_CRS_HLP [2/5]

#define AXBS_CRS_HLP ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)

HLP - Halt Low Priority 0b0..The low power mode request has the highest priority for arbitration on this slave port 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port

◆ AXBS_CRS_HLP [3/5]

#define AXBS_CRS_HLP ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)

HLP - Halt Low Priority 0b0..The low power mode request has the highest priority for arbitration on this slave port 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port

◆ AXBS_CRS_HLP [4/5]

#define AXBS_CRS_HLP ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)

HLP - Halt Low Priority 0b0..The low power mode request has the highest priority for arbitration on this slave port 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port

◆ AXBS_CRS_HLP [5/5]

#define AXBS_CRS_HLP ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)

HLP - Halt Low Priority 0b0..The low power mode request has the highest priority for arbitration on this slave port 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port

◆ AXBS_CRS_PARK [1/6]

#define AXBS_CRS_PARK ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)

PARK - Park 0b000..Park on master port M0 0b001..Park on master port M1 0b010..Park on master port M2 0b011..Park on master port M3 0b100..Park on master port M4 0b101..Park on master port M5 0b110..Park on master port M6 0b111..Park on master port M7

◆ AXBS_CRS_PARK [2/6]

#define AXBS_CRS_PARK ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)

PARK - Park 0b000..Park on master port M0 0b001..Park on master port M1 0b010..Park on master port M2 0b011..Park on master port M3 0b100..Park on master port M4 0b101..Park on master port M5 0b110..Park on master port M6 0b111..Park on master port M7

◆ AXBS_CRS_PARK [3/6]

#define AXBS_CRS_PARK ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)

PARK - Park 0b000..Park on master port M0 0b001..Park on master port M1 0b010..Park on master port M2 0b011..Park on master port M3 0b100..Park on master port M4 0b101..Park on master port M5 0b110..Park on master port M6 0b111..Park on master port M7

◆ AXBS_CRS_PARK [4/6]

#define AXBS_CRS_PARK ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)

PARK - Park 0b000..Park on master port M0 0b001..Park on master port M1 0b010..Park on master port M2 0b011..Park on master port M3 0b100..Park on master port M4 0b101..Park on master port M5 0b110..Park on master port M6 0b111..Park on master port M7

◆ AXBS_CRS_PARK [5/6]

#define AXBS_CRS_PARK ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)

PARK - Park 0b000..Park on master port M0 0b001..Park on master port M1 0b010..Park on master port M2 0b011..Park on master port M3 0b100..Park on master port M4 0b101..Park on master port M5 0b110..Park on master port M6 0b111..Park on master port M7

◆ AXBS_CRS_PARK [6/6]

#define AXBS_CRS_PARK ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)

PARK - Park 0b000..Park on master port M0 0b001..Park on master port M1 0b010..Park on master port M2 0b011..Park on master port M3 0b100..Park on master port M4 0b101..Park on master port M5 0b110..Park on master port M6 0b111..Park on master port M7

◆ AXBS_CRS_PCTL [1/6]

#define AXBS_CRS_PCTL ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)

PCTL - Parking Control 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 0b11..Reserved

◆ AXBS_CRS_PCTL [2/6]

#define AXBS_CRS_PCTL ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)

PCTL - Parking Control 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 0b11..Reserved

◆ AXBS_CRS_PCTL [3/6]

#define AXBS_CRS_PCTL ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)

PCTL - Parking Control 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 0b11..Reserved

◆ AXBS_CRS_PCTL [4/6]

#define AXBS_CRS_PCTL ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)

PCTL - Parking Control 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 0b11..Reserved

◆ AXBS_CRS_PCTL [5/6]

#define AXBS_CRS_PCTL ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)

PCTL - Parking Control 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 0b11..Reserved

◆ AXBS_CRS_PCTL [6/6]

#define AXBS_CRS_PCTL ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)

PCTL - Parking Control 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 0b11..Reserved

◆ AXBS_CRS_RO [1/5]

#define AXBS_CRS_RO ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)

RO - Read Only 0b0..The slave port's registers are writeable 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.

◆ AXBS_CRS_RO [2/5]

#define AXBS_CRS_RO ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)

RO - Read Only 0b0..The slave port's registers are writeable 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.

◆ AXBS_CRS_RO [3/5]

#define AXBS_CRS_RO ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)

RO - Read Only 0b0..The slave port's registers are writeable 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.

◆ AXBS_CRS_RO [4/5]

#define AXBS_CRS_RO ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)

RO - Read Only 0b0..The slave port's registers are writeable 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.

◆ AXBS_CRS_RO [5/5]

#define AXBS_CRS_RO ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)

RO - Read Only 0b0..The slave port's registers are writeable 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.

◆ AXBS_MGPCR0_AULB [1/6]

#define AXBS_MGPCR0_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR0_AULB [2/6]

#define AXBS_MGPCR0_AULB ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR0_AULB [3/6]

#define AXBS_MGPCR0_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR0_AULB [4/6]

#define AXBS_MGPCR0_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR0_AULB [5/6]

#define AXBS_MGPCR0_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR0_AULB [6/6]

#define AXBS_MGPCR0_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR1_AULB [1/6]

#define AXBS_MGPCR1_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR1_AULB [2/6]

#define AXBS_MGPCR1_AULB ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR1_AULB [3/6]

#define AXBS_MGPCR1_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR1_AULB [4/6]

#define AXBS_MGPCR1_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR1_AULB [5/6]

#define AXBS_MGPCR1_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR1_AULB [6/6]

#define AXBS_MGPCR1_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR2_AULB [1/6]

#define AXBS_MGPCR2_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR2_AULB [2/6]

#define AXBS_MGPCR2_AULB ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR2_AULB [3/6]

#define AXBS_MGPCR2_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR2_AULB [4/6]

#define AXBS_MGPCR2_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR2_AULB [5/6]

#define AXBS_MGPCR2_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR2_AULB [6/6]

#define AXBS_MGPCR2_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR3_AULB [1/6]

#define AXBS_MGPCR3_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR3_AULB [2/6]

#define AXBS_MGPCR3_AULB ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR3_AULB [3/6]

#define AXBS_MGPCR3_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR3_AULB [4/6]

#define AXBS_MGPCR3_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR3_AULB [5/6]

#define AXBS_MGPCR3_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR3_AULB [6/6]

#define AXBS_MGPCR3_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR4_AULB [1/5]

#define AXBS_MGPCR4_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR4_AULB [2/5]

#define AXBS_MGPCR4_AULB ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR4_AULB [3/5]

#define AXBS_MGPCR4_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR4_AULB [4/5]

#define AXBS_MGPCR4_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR4_AULB [5/5]

#define AXBS_MGPCR4_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR5_AULB [1/5]

#define AXBS_MGPCR5_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR5_AULB [2/5]

#define AXBS_MGPCR5_AULB ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR5_AULB [3/5]

#define AXBS_MGPCR5_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR5_AULB [4/5]

#define AXBS_MGPCR5_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR5_AULB [5/5]

#define AXBS_MGPCR5_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR6_AULB [1/2]

#define AXBS_MGPCR6_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_MGPCR6_AULB [2/2]

#define AXBS_MGPCR6_AULB ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)

AULB - Arbitrates On Undefined Length Bursts 0b000..No arbitration is allowed during an undefined length burst 0b001..Arbitration is allowed at any time during an undefined length burst 0b010..Arbitration is allowed after four beats of an undefined length burst 0b011..Arbitration is allowed after eight beats of an undefined length burst 0b100..Arbitration is allowed after 16 beats of an undefined length burst 0b101..Reserved 0b110..Reserved 0b111..Reserved

◆ AXBS_PRS_M0 [1/6]

#define AXBS_PRS_M0 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)

M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M0 [2/6]

#define AXBS_PRS_M0 ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)

M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M0 [3/6]

#define AXBS_PRS_M0 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)

M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M0 [4/6]

#define AXBS_PRS_M0 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)

M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M0 [5/6]

#define AXBS_PRS_M0 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)

M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M0 [6/6]

#define AXBS_PRS_M0 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)

M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M1 [1/6]

#define AXBS_PRS_M1 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)

M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M1 [2/6]

#define AXBS_PRS_M1 ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)

M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M1 [3/6]

#define AXBS_PRS_M1 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)

M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M1 [4/6]

#define AXBS_PRS_M1 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)

M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M1 [5/6]

#define AXBS_PRS_M1 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)

M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M1 [6/6]

#define AXBS_PRS_M1 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)

M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M2 [1/6]

#define AXBS_PRS_M2 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)

M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M2 [2/6]

#define AXBS_PRS_M2 ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)

M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M2 [3/6]

#define AXBS_PRS_M2 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)

M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M2 [4/6]

#define AXBS_PRS_M2 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)

M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M2 [5/6]

#define AXBS_PRS_M2 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)

M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M2 [6/6]

#define AXBS_PRS_M2 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)

M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M3 [1/6]

#define AXBS_PRS_M3 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)

M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M3 [2/6]

#define AXBS_PRS_M3 ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)

M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M3 [3/6]

#define AXBS_PRS_M3 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)

M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M3 [4/6]

#define AXBS_PRS_M3 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)

M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M3 [5/6]

#define AXBS_PRS_M3 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)

M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M3 [6/6]

#define AXBS_PRS_M3 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)

M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M4 [1/5]

#define AXBS_PRS_M4 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)

M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M4 [2/5]

#define AXBS_PRS_M4 ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)

M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M4 [3/5]

#define AXBS_PRS_M4 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)

M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M4 [4/5]

#define AXBS_PRS_M4 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)

M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M4 [5/5]

#define AXBS_PRS_M4 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)

M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M5 [1/5]

#define AXBS_PRS_M5 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)

M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M5 [2/5]

#define AXBS_PRS_M5 ( x)    (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)

M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M5 [3/5]

#define AXBS_PRS_M5 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)

M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M5 [4/5]

#define AXBS_PRS_M5 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)

M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M5 [5/5]

#define AXBS_PRS_M5 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)

M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M6 [1/2]

#define AXBS_PRS_M6 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)

M6 - Master 6 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.

◆ AXBS_PRS_M6 [2/2]

#define AXBS_PRS_M6 ( x)    (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)

M6 - Master 6 Priority. Sets the arbitration priority for this port on the associated slave port. 0b000..This master has level 1, or highest, priority when accessing the slave port. 0b001..This master has level 2 priority when accessing the slave port. 0b010..This master has level 3 priority when accessing the slave port. 0b011..This master has level 4 priority when accessing the slave port. 0b100..This master has level 5 priority when accessing the slave port. 0b101..This master has level 6 priority when accessing the slave port. 0b110..This master has level 7 priority when accessing the slave port. 0b111..This master has level 8, or lowest, priority when accessing the slave port.